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1 | 7d13299d | bellard | /*
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2 | 7d13299d | bellard | * i386 emulator main execution loop
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3 | 7d13299d | bellard | *
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4 | 7d13299d | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 7d13299d | bellard | *
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6 | 3ef693a0 | bellard | * This library is free software; you can redistribute it and/or
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7 | 3ef693a0 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 3ef693a0 | bellard | * License as published by the Free Software Foundation; either
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9 | 3ef693a0 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 7d13299d | bellard | *
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11 | 3ef693a0 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 3ef693a0 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 3ef693a0 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 3ef693a0 | bellard | * Lesser General Public License for more details.
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15 | 7d13299d | bellard | *
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16 | 3ef693a0 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 3ef693a0 | bellard | * License along with this library; if not, write to the Free Software
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18 | 3ef693a0 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 7d13299d | bellard | */
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20 | e4533c7a | bellard | #include "config.h" |
21 | 93ac68bc | bellard | #include "exec.h" |
22 | 956034d7 | bellard | #include "disas.h" |
23 | 7d13299d | bellard | |
24 | fbf9eeb3 | bellard | #if !defined(CONFIG_SOFTMMU)
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25 | fbf9eeb3 | bellard | #undef EAX
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26 | fbf9eeb3 | bellard | #undef ECX
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27 | fbf9eeb3 | bellard | #undef EDX
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28 | fbf9eeb3 | bellard | #undef EBX
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29 | fbf9eeb3 | bellard | #undef ESP
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30 | fbf9eeb3 | bellard | #undef EBP
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31 | fbf9eeb3 | bellard | #undef ESI
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32 | fbf9eeb3 | bellard | #undef EDI
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33 | fbf9eeb3 | bellard | #undef EIP
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34 | fbf9eeb3 | bellard | #include <signal.h> |
35 | fbf9eeb3 | bellard | #include <sys/ucontext.h> |
36 | fbf9eeb3 | bellard | #endif
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37 | fbf9eeb3 | bellard | |
38 | 36bdbe54 | bellard | int tb_invalidated_flag;
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39 | 36bdbe54 | bellard | |
40 | dc99065b | bellard | //#define DEBUG_EXEC
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41 | 9de5e440 | bellard | //#define DEBUG_SIGNAL
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42 | 7d13299d | bellard | |
43 | 93ac68bc | bellard | #if defined(TARGET_ARM) || defined(TARGET_SPARC)
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44 | e4533c7a | bellard | /* XXX: unify with i386 target */
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45 | e4533c7a | bellard | void cpu_loop_exit(void) |
46 | e4533c7a | bellard | { |
47 | e4533c7a | bellard | longjmp(env->jmp_env, 1);
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48 | e4533c7a | bellard | } |
49 | e4533c7a | bellard | #endif
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50 | e4533c7a | bellard | |
51 | fbf9eeb3 | bellard | /* exit the current TB from a signal handler. The host registers are
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52 | fbf9eeb3 | bellard | restored in a state compatible with the CPU emulator
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53 | fbf9eeb3 | bellard | */
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54 | fbf9eeb3 | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc) |
55 | fbf9eeb3 | bellard | { |
56 | fbf9eeb3 | bellard | #if !defined(CONFIG_SOFTMMU)
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57 | fbf9eeb3 | bellard | struct ucontext *uc = puc;
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58 | fbf9eeb3 | bellard | #endif
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59 | fbf9eeb3 | bellard | |
60 | fbf9eeb3 | bellard | env = env1; |
61 | fbf9eeb3 | bellard | |
62 | fbf9eeb3 | bellard | /* XXX: restore cpu registers saved in host registers */
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63 | fbf9eeb3 | bellard | |
64 | fbf9eeb3 | bellard | #if !defined(CONFIG_SOFTMMU)
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65 | fbf9eeb3 | bellard | if (puc) {
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66 | fbf9eeb3 | bellard | /* XXX: use siglongjmp ? */
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67 | fbf9eeb3 | bellard | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
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68 | fbf9eeb3 | bellard | } |
69 | fbf9eeb3 | bellard | #endif
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70 | fbf9eeb3 | bellard | longjmp(env->jmp_env, 1);
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71 | fbf9eeb3 | bellard | } |
72 | fbf9eeb3 | bellard | |
73 | 7d13299d | bellard | /* main execution loop */
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74 | 7d13299d | bellard | |
75 | e4533c7a | bellard | int cpu_exec(CPUState *env1)
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76 | 7d13299d | bellard | { |
77 | e4533c7a | bellard | int saved_T0, saved_T1, saved_T2;
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78 | e4533c7a | bellard | CPUState *saved_env; |
79 | 04369ff2 | bellard | #ifdef reg_EAX
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80 | 04369ff2 | bellard | int saved_EAX;
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81 | 04369ff2 | bellard | #endif
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82 | 04369ff2 | bellard | #ifdef reg_ECX
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83 | 04369ff2 | bellard | int saved_ECX;
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84 | 04369ff2 | bellard | #endif
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85 | 04369ff2 | bellard | #ifdef reg_EDX
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86 | 04369ff2 | bellard | int saved_EDX;
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87 | 04369ff2 | bellard | #endif
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88 | 04369ff2 | bellard | #ifdef reg_EBX
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89 | 04369ff2 | bellard | int saved_EBX;
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90 | 04369ff2 | bellard | #endif
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91 | 04369ff2 | bellard | #ifdef reg_ESP
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92 | 04369ff2 | bellard | int saved_ESP;
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93 | 04369ff2 | bellard | #endif
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94 | 04369ff2 | bellard | #ifdef reg_EBP
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95 | 04369ff2 | bellard | int saved_EBP;
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96 | 04369ff2 | bellard | #endif
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97 | 04369ff2 | bellard | #ifdef reg_ESI
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98 | 04369ff2 | bellard | int saved_ESI;
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99 | 04369ff2 | bellard | #endif
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100 | 04369ff2 | bellard | #ifdef reg_EDI
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101 | 04369ff2 | bellard | int saved_EDI;
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102 | 04369ff2 | bellard | #endif
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103 | 8c6939c0 | bellard | #ifdef __sparc__
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104 | 8c6939c0 | bellard | int saved_i7, tmp_T0;
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105 | 8c6939c0 | bellard | #endif
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106 | 68a79315 | bellard | int code_gen_size, ret, interrupt_request;
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107 | 7d13299d | bellard | void (*gen_func)(void); |
108 | 9de5e440 | bellard | TranslationBlock *tb, **ptb; |
109 | c27004ec | bellard | target_ulong cs_base, pc; |
110 | c27004ec | bellard | uint8_t *tc_ptr; |
111 | 6dbad63e | bellard | unsigned int flags; |
112 | 8c6939c0 | bellard | |
113 | 7d13299d | bellard | /* first we save global registers */
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114 | c27004ec | bellard | saved_env = env; |
115 | c27004ec | bellard | env = env1; |
116 | 7d13299d | bellard | saved_T0 = T0; |
117 | 7d13299d | bellard | saved_T1 = T1; |
118 | e4533c7a | bellard | saved_T2 = T2; |
119 | e4533c7a | bellard | #ifdef __sparc__
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120 | e4533c7a | bellard | /* we also save i7 because longjmp may not restore it */
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121 | e4533c7a | bellard | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); |
122 | e4533c7a | bellard | #endif
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123 | e4533c7a | bellard | |
124 | e4533c7a | bellard | #if defined(TARGET_I386)
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125 | 04369ff2 | bellard | #ifdef reg_EAX
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126 | 04369ff2 | bellard | saved_EAX = EAX; |
127 | 04369ff2 | bellard | #endif
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128 | 04369ff2 | bellard | #ifdef reg_ECX
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129 | 04369ff2 | bellard | saved_ECX = ECX; |
130 | 04369ff2 | bellard | #endif
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131 | 04369ff2 | bellard | #ifdef reg_EDX
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132 | 04369ff2 | bellard | saved_EDX = EDX; |
133 | 04369ff2 | bellard | #endif
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134 | 04369ff2 | bellard | #ifdef reg_EBX
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135 | 04369ff2 | bellard | saved_EBX = EBX; |
136 | 04369ff2 | bellard | #endif
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137 | 04369ff2 | bellard | #ifdef reg_ESP
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138 | 04369ff2 | bellard | saved_ESP = ESP; |
139 | 04369ff2 | bellard | #endif
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140 | 04369ff2 | bellard | #ifdef reg_EBP
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141 | 04369ff2 | bellard | saved_EBP = EBP; |
142 | 04369ff2 | bellard | #endif
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143 | 04369ff2 | bellard | #ifdef reg_ESI
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144 | 04369ff2 | bellard | saved_ESI = ESI; |
145 | 04369ff2 | bellard | #endif
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146 | 04369ff2 | bellard | #ifdef reg_EDI
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147 | 04369ff2 | bellard | saved_EDI = EDI; |
148 | 04369ff2 | bellard | #endif
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149 | 0d1a29f9 | bellard | |
150 | 0d1a29f9 | bellard | env_to_regs(); |
151 | 9de5e440 | bellard | /* put eflags in CPU temporary format */
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152 | fc2b4c48 | bellard | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
153 | fc2b4c48 | bellard | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
154 | 9de5e440 | bellard | CC_OP = CC_OP_EFLAGS; |
155 | fc2b4c48 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
156 | e4533c7a | bellard | #elif defined(TARGET_ARM)
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157 | e4533c7a | bellard | { |
158 | e4533c7a | bellard | unsigned int psr; |
159 | e4533c7a | bellard | psr = env->cpsr; |
160 | e4533c7a | bellard | env->CF = (psr >> 29) & 1; |
161 | e4533c7a | bellard | env->NZF = (psr & 0xc0000000) ^ 0x40000000; |
162 | e4533c7a | bellard | env->VF = (psr << 3) & 0x80000000; |
163 | e4533c7a | bellard | env->cpsr = psr & ~0xf0000000;
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164 | e4533c7a | bellard | } |
165 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
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166 | 67867308 | bellard | #elif defined(TARGET_PPC)
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167 | e4533c7a | bellard | #else
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168 | e4533c7a | bellard | #error unsupported target CPU
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169 | e4533c7a | bellard | #endif
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170 | 3fb2ded1 | bellard | env->exception_index = -1;
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171 | 9d27abd9 | bellard | |
172 | 7d13299d | bellard | /* prepare setjmp context for exception handling */
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173 | 3fb2ded1 | bellard | for(;;) {
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174 | 3fb2ded1 | bellard | if (setjmp(env->jmp_env) == 0) { |
175 | ee8b7021 | bellard | env->current_tb = NULL;
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176 | 3fb2ded1 | bellard | /* if an exception is pending, we execute it here */
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177 | 3fb2ded1 | bellard | if (env->exception_index >= 0) { |
178 | 3fb2ded1 | bellard | if (env->exception_index >= EXCP_INTERRUPT) {
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179 | 3fb2ded1 | bellard | /* exit request from the cpu execution loop */
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180 | 3fb2ded1 | bellard | ret = env->exception_index; |
181 | 3fb2ded1 | bellard | break;
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182 | 3fb2ded1 | bellard | } else if (env->user_mode_only) { |
183 | 3fb2ded1 | bellard | /* if user mode only, we simulate a fake exception
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184 | 3fb2ded1 | bellard | which will be hanlded outside the cpu execution
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185 | 3fb2ded1 | bellard | loop */
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186 | 83479e77 | bellard | #if defined(TARGET_I386)
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187 | 3fb2ded1 | bellard | do_interrupt_user(env->exception_index, |
188 | 3fb2ded1 | bellard | env->exception_is_int, |
189 | 3fb2ded1 | bellard | env->error_code, |
190 | 3fb2ded1 | bellard | env->exception_next_eip); |
191 | 83479e77 | bellard | #endif
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192 | 3fb2ded1 | bellard | ret = env->exception_index; |
193 | 3fb2ded1 | bellard | break;
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194 | 3fb2ded1 | bellard | } else {
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195 | 83479e77 | bellard | #if defined(TARGET_I386)
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196 | 3fb2ded1 | bellard | /* simulate a real cpu exception. On i386, it can
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197 | 3fb2ded1 | bellard | trigger new exceptions, but we do not handle
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198 | 3fb2ded1 | bellard | double or triple faults yet. */
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199 | 3fb2ded1 | bellard | do_interrupt(env->exception_index, |
200 | 3fb2ded1 | bellard | env->exception_is_int, |
201 | 3fb2ded1 | bellard | env->error_code, |
202 | d05e66d2 | bellard | env->exception_next_eip, 0);
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203 | ce09776b | bellard | #elif defined(TARGET_PPC)
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204 | ce09776b | bellard | do_interrupt(env); |
205 | e95c8d51 | bellard | #elif defined(TARGET_SPARC)
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206 | e95c8d51 | bellard | do_interrupt(env->exception_index, |
207 | e95c8d51 | bellard | 0,
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208 | e95c8d51 | bellard | env->error_code, |
209 | e95c8d51 | bellard | env->exception_next_pc, 0);
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210 | 83479e77 | bellard | #endif
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211 | 3fb2ded1 | bellard | } |
212 | 3fb2ded1 | bellard | env->exception_index = -1;
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213 | 3fb2ded1 | bellard | } |
214 | 3fb2ded1 | bellard | T0 = 0; /* force lookup of first TB */ |
215 | 3fb2ded1 | bellard | for(;;) {
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216 | 8c6939c0 | bellard | #ifdef __sparc__
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217 | 3fb2ded1 | bellard | /* g1 can be modified by some libc? functions */
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218 | 3fb2ded1 | bellard | tmp_T0 = T0; |
219 | 8c6939c0 | bellard | #endif
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220 | 68a79315 | bellard | interrupt_request = env->interrupt_request; |
221 | 2e255c6b | bellard | if (__builtin_expect(interrupt_request, 0)) { |
222 | 68a79315 | bellard | #if defined(TARGET_I386)
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223 | 68a79315 | bellard | /* if hardware interrupt pending, we execute it */
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224 | 68a79315 | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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225 | 3f337316 | bellard | (env->eflags & IF_MASK) && |
226 | 3f337316 | bellard | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { |
227 | 68a79315 | bellard | int intno;
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228 | fbf9eeb3 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
229 | a541f297 | bellard | intno = cpu_get_pic_interrupt(env); |
230 | f193c797 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
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231 | 68a79315 | bellard | fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
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232 | 68a79315 | bellard | } |
233 | d05e66d2 | bellard | do_interrupt(intno, 0, 0, 0, 1); |
234 | 907a5b26 | bellard | /* ensure that no TB jump will be modified as
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235 | 907a5b26 | bellard | the program flow was changed */
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236 | 907a5b26 | bellard | #ifdef __sparc__
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237 | 907a5b26 | bellard | tmp_T0 = 0;
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238 | 907a5b26 | bellard | #else
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239 | 907a5b26 | bellard | T0 = 0;
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240 | 907a5b26 | bellard | #endif
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241 | 68a79315 | bellard | } |
242 | ce09776b | bellard | #elif defined(TARGET_PPC)
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243 | 9fddaa0c | bellard | #if 0
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244 | 9fddaa0c | bellard | if ((interrupt_request & CPU_INTERRUPT_RESET)) {
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245 | 9fddaa0c | bellard | cpu_ppc_reset(env);
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246 | 9fddaa0c | bellard | }
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247 | 9fddaa0c | bellard | #endif
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248 | 9fddaa0c | bellard | if (msr_ee != 0) { |
249 | ce09776b | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD)) {
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250 | 9fddaa0c | bellard | /* Raise it */
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251 | 9fddaa0c | bellard | env->exception_index = EXCP_EXTERNAL; |
252 | 9fddaa0c | bellard | env->error_code = 0;
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253 | ce09776b | bellard | do_interrupt(env); |
254 | ce09776b | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
255 | 9fddaa0c | bellard | } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) { |
256 | 9fddaa0c | bellard | /* Raise it */
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257 | 9fddaa0c | bellard | env->exception_index = EXCP_DECR; |
258 | 9fddaa0c | bellard | env->error_code = 0;
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259 | 9fddaa0c | bellard | do_interrupt(env); |
260 | 9fddaa0c | bellard | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
261 | 9fddaa0c | bellard | } |
262 | ce09776b | bellard | } |
263 | e95c8d51 | bellard | #elif defined(TARGET_SPARC)
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264 | e95c8d51 | bellard | if (interrupt_request & CPU_INTERRUPT_HARD) {
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265 | e80cfcfc | bellard | do_interrupt(env->interrupt_index, 0, 0, 0, 0); |
266 | e95c8d51 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
267 | e95c8d51 | bellard | } else if (interrupt_request & CPU_INTERRUPT_TIMER) { |
268 | e95c8d51 | bellard | //do_interrupt(0, 0, 0, 0, 0);
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269 | e95c8d51 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
270 | e95c8d51 | bellard | } |
271 | 68a79315 | bellard | #endif
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272 | bf3e8bf1 | bellard | if (interrupt_request & CPU_INTERRUPT_EXITTB) {
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273 | bf3e8bf1 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
274 | bf3e8bf1 | bellard | /* ensure that no TB jump will be modified as
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275 | bf3e8bf1 | bellard | the program flow was changed */
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276 | bf3e8bf1 | bellard | #ifdef __sparc__
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277 | bf3e8bf1 | bellard | tmp_T0 = 0;
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278 | bf3e8bf1 | bellard | #else
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279 | bf3e8bf1 | bellard | T0 = 0;
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280 | bf3e8bf1 | bellard | #endif
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281 | bf3e8bf1 | bellard | } |
282 | 68a79315 | bellard | if (interrupt_request & CPU_INTERRUPT_EXIT) {
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283 | 68a79315 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_EXIT; |
284 | 68a79315 | bellard | env->exception_index = EXCP_INTERRUPT; |
285 | 68a79315 | bellard | cpu_loop_exit(); |
286 | 68a79315 | bellard | } |
287 | 3fb2ded1 | bellard | } |
288 | 7d13299d | bellard | #ifdef DEBUG_EXEC
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289 | c27004ec | bellard | if ((loglevel & CPU_LOG_EXEC)) {
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290 | e4533c7a | bellard | #if defined(TARGET_I386)
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291 | 3fb2ded1 | bellard | /* restore flags in standard format */
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292 | 3fb2ded1 | bellard | env->regs[R_EAX] = EAX; |
293 | 3fb2ded1 | bellard | env->regs[R_EBX] = EBX; |
294 | 3fb2ded1 | bellard | env->regs[R_ECX] = ECX; |
295 | 3fb2ded1 | bellard | env->regs[R_EDX] = EDX; |
296 | 3fb2ded1 | bellard | env->regs[R_ESI] = ESI; |
297 | 3fb2ded1 | bellard | env->regs[R_EDI] = EDI; |
298 | 3fb2ded1 | bellard | env->regs[R_EBP] = EBP; |
299 | 3fb2ded1 | bellard | env->regs[R_ESP] = ESP; |
300 | 3fb2ded1 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
301 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
302 | 3fb2ded1 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
303 | e4533c7a | bellard | #elif defined(TARGET_ARM)
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304 | 1b21b62a | bellard | env->cpsr = compute_cpsr(); |
305 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
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306 | 1b21b62a | bellard | env->cpsr &= ~0xf0000000;
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307 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
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308 | 7fe48483 | bellard | cpu_dump_state (env, logfile, fprintf, 0);
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309 | 67867308 | bellard | #elif defined(TARGET_PPC)
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310 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
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311 | e4533c7a | bellard | #else
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312 | e4533c7a | bellard | #error unsupported target CPU
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313 | e4533c7a | bellard | #endif
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314 | 3fb2ded1 | bellard | } |
315 | 7d13299d | bellard | #endif
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316 | 3f337316 | bellard | /* we record a subset of the CPU state. It will
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317 | 3f337316 | bellard | always be the same before a given translated block
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318 | 3f337316 | bellard | is executed. */
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319 | e4533c7a | bellard | #if defined(TARGET_I386)
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320 | 2e255c6b | bellard | flags = env->hflags; |
321 | 3f337316 | bellard | flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
322 | 3fb2ded1 | bellard | cs_base = env->segs[R_CS].base; |
323 | 3fb2ded1 | bellard | pc = cs_base + env->eip; |
324 | e4533c7a | bellard | #elif defined(TARGET_ARM)
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325 | 3fb2ded1 | bellard | flags = 0;
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326 | 3fb2ded1 | bellard | cs_base = 0;
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327 | c27004ec | bellard | pc = env->regs[15];
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328 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
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329 | 67867308 | bellard | flags = 0;
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330 | c27004ec | bellard | cs_base = env->npc; |
331 | c27004ec | bellard | pc = env->pc; |
332 | 67867308 | bellard | #elif defined(TARGET_PPC)
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333 | 67867308 | bellard | flags = 0;
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334 | 67867308 | bellard | cs_base = 0;
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335 | c27004ec | bellard | pc = env->nip; |
336 | e4533c7a | bellard | #else
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337 | e4533c7a | bellard | #error unsupported CPU
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338 | e4533c7a | bellard | #endif
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339 | c27004ec | bellard | tb = tb_find(&ptb, pc, cs_base, |
340 | 3fb2ded1 | bellard | flags); |
341 | d4e8164f | bellard | if (!tb) {
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342 | 1376847f | bellard | TranslationBlock **ptb1; |
343 | 1376847f | bellard | unsigned int h; |
344 | 1376847f | bellard | target_ulong phys_pc, phys_page1, phys_page2, virt_page2; |
345 | 1376847f | bellard | |
346 | 1376847f | bellard | |
347 | 3fb2ded1 | bellard | spin_lock(&tb_lock); |
348 | 1376847f | bellard | |
349 | 1376847f | bellard | tb_invalidated_flag = 0;
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350 | 0d1a29f9 | bellard | |
351 | 0d1a29f9 | bellard | regs_to_env(); /* XXX: do it just before cpu_gen_code() */
|
352 | 1376847f | bellard | |
353 | 1376847f | bellard | /* find translated block using physical mappings */
|
354 | c27004ec | bellard | phys_pc = get_phys_addr_code(env, pc); |
355 | 1376847f | bellard | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
356 | 1376847f | bellard | phys_page2 = -1;
|
357 | 1376847f | bellard | h = tb_phys_hash_func(phys_pc); |
358 | 1376847f | bellard | ptb1 = &tb_phys_hash[h]; |
359 | 1376847f | bellard | for(;;) {
|
360 | 1376847f | bellard | tb = *ptb1; |
361 | 1376847f | bellard | if (!tb)
|
362 | 1376847f | bellard | goto not_found;
|
363 | c27004ec | bellard | if (tb->pc == pc &&
|
364 | 1376847f | bellard | tb->page_addr[0] == phys_page1 &&
|
365 | c27004ec | bellard | tb->cs_base == cs_base && |
366 | 1376847f | bellard | tb->flags == flags) { |
367 | 1376847f | bellard | /* check next page if needed */
|
368 | b516f85c | bellard | if (tb->page_addr[1] != -1) { |
369 | c27004ec | bellard | virt_page2 = (pc & TARGET_PAGE_MASK) + |
370 | b516f85c | bellard | TARGET_PAGE_SIZE; |
371 | 1376847f | bellard | phys_page2 = get_phys_addr_code(env, virt_page2); |
372 | 1376847f | bellard | if (tb->page_addr[1] == phys_page2) |
373 | 1376847f | bellard | goto found;
|
374 | 1376847f | bellard | } else {
|
375 | 1376847f | bellard | goto found;
|
376 | 1376847f | bellard | } |
377 | 1376847f | bellard | } |
378 | 1376847f | bellard | ptb1 = &tb->phys_hash_next; |
379 | 1376847f | bellard | } |
380 | 1376847f | bellard | not_found:
|
381 | 3fb2ded1 | bellard | /* if no translated code available, then translate it now */
|
382 | c27004ec | bellard | tb = tb_alloc(pc); |
383 | 3fb2ded1 | bellard | if (!tb) {
|
384 | 3fb2ded1 | bellard | /* flush must be done */
|
385 | b453b70b | bellard | tb_flush(env); |
386 | 3fb2ded1 | bellard | /* cannot fail at this point */
|
387 | c27004ec | bellard | tb = tb_alloc(pc); |
388 | 3fb2ded1 | bellard | /* don't forget to invalidate previous TB info */
|
389 | c27004ec | bellard | ptb = &tb_hash[tb_hash_func(pc)]; |
390 | 3fb2ded1 | bellard | T0 = 0;
|
391 | 3fb2ded1 | bellard | } |
392 | 3fb2ded1 | bellard | tc_ptr = code_gen_ptr; |
393 | 3fb2ded1 | bellard | tb->tc_ptr = tc_ptr; |
394 | c27004ec | bellard | tb->cs_base = cs_base; |
395 | 3fb2ded1 | bellard | tb->flags = flags; |
396 | facc68be | bellard | cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
397 | 1376847f | bellard | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
398 | 1376847f | bellard | |
399 | 1376847f | bellard | /* check next page if needed */
|
400 | c27004ec | bellard | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
|
401 | 1376847f | bellard | phys_page2 = -1;
|
402 | c27004ec | bellard | if ((pc & TARGET_PAGE_MASK) != virt_page2) {
|
403 | 1376847f | bellard | phys_page2 = get_phys_addr_code(env, virt_page2); |
404 | 1376847f | bellard | } |
405 | 1376847f | bellard | tb_link_phys(tb, phys_pc, phys_page2); |
406 | 1376847f | bellard | |
407 | 1376847f | bellard | found:
|
408 | 36bdbe54 | bellard | if (tb_invalidated_flag) {
|
409 | 36bdbe54 | bellard | /* as some TB could have been invalidated because
|
410 | 36bdbe54 | bellard | of memory exceptions while generating the code, we
|
411 | 36bdbe54 | bellard | must recompute the hash index here */
|
412 | c27004ec | bellard | ptb = &tb_hash[tb_hash_func(pc)]; |
413 | 36bdbe54 | bellard | while (*ptb != NULL) |
414 | 36bdbe54 | bellard | ptb = &(*ptb)->hash_next; |
415 | 36bdbe54 | bellard | T0 = 0;
|
416 | 36bdbe54 | bellard | } |
417 | 1376847f | bellard | /* we add the TB in the virtual pc hash table */
|
418 | 3fb2ded1 | bellard | *ptb = tb; |
419 | 3fb2ded1 | bellard | tb->hash_next = NULL;
|
420 | 3fb2ded1 | bellard | tb_link(tb); |
421 | 25eb4484 | bellard | spin_unlock(&tb_lock); |
422 | 9de5e440 | bellard | } |
423 | 9d27abd9 | bellard | #ifdef DEBUG_EXEC
|
424 | c1135f61 | bellard | if ((loglevel & CPU_LOG_EXEC)) {
|
425 | c27004ec | bellard | fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", |
426 | c27004ec | bellard | (long)tb->tc_ptr, tb->pc,
|
427 | c27004ec | bellard | lookup_symbol(tb->pc)); |
428 | 3fb2ded1 | bellard | } |
429 | 9d27abd9 | bellard | #endif
|
430 | 8c6939c0 | bellard | #ifdef __sparc__
|
431 | 3fb2ded1 | bellard | T0 = tmp_T0; |
432 | 8c6939c0 | bellard | #endif
|
433 | facc68be | bellard | /* see if we can patch the calling TB. */
|
434 | c27004ec | bellard | { |
435 | c27004ec | bellard | if (T0 != 0 |
436 | bf3e8bf1 | bellard | #if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
437 | bf3e8bf1 | bellard | && (tb->cflags & CF_CODE_COPY) == |
438 | bf3e8bf1 | bellard | (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
|
439 | bf3e8bf1 | bellard | #endif
|
440 | bf3e8bf1 | bellard | ) { |
441 | 3fb2ded1 | bellard | spin_lock(&tb_lock); |
442 | c27004ec | bellard | tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb); |
443 | 97eb5b14 | bellard | #if defined(USE_CODE_COPY)
|
444 | 97eb5b14 | bellard | /* propagates the FP use info */
|
445 | 97eb5b14 | bellard | ((TranslationBlock *)(T0 & ~3))->cflags |=
|
446 | 97eb5b14 | bellard | (tb->cflags & CF_FP_USED); |
447 | 97eb5b14 | bellard | #endif
|
448 | 3fb2ded1 | bellard | spin_unlock(&tb_lock); |
449 | 3fb2ded1 | bellard | } |
450 | c27004ec | bellard | } |
451 | 3fb2ded1 | bellard | tc_ptr = tb->tc_ptr; |
452 | 83479e77 | bellard | env->current_tb = tb; |
453 | 3fb2ded1 | bellard | /* execute the generated code */
|
454 | 3fb2ded1 | bellard | gen_func = (void *)tc_ptr;
|
455 | 8c6939c0 | bellard | #if defined(__sparc__)
|
456 | 3fb2ded1 | bellard | __asm__ __volatile__("call %0\n\t"
|
457 | 3fb2ded1 | bellard | "mov %%o7,%%i0"
|
458 | 3fb2ded1 | bellard | : /* no outputs */
|
459 | 3fb2ded1 | bellard | : "r" (gen_func)
|
460 | 3fb2ded1 | bellard | : "i0", "i1", "i2", "i3", "i4", "i5"); |
461 | 8c6939c0 | bellard | #elif defined(__arm__)
|
462 | 3fb2ded1 | bellard | asm volatile ("mov pc, %0\n\t" |
463 | 3fb2ded1 | bellard | ".global exec_loop\n\t"
|
464 | 3fb2ded1 | bellard | "exec_loop:\n\t"
|
465 | 3fb2ded1 | bellard | : /* no outputs */
|
466 | 3fb2ded1 | bellard | : "r" (gen_func)
|
467 | 3fb2ded1 | bellard | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); |
468 | bf3e8bf1 | bellard | #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
|
469 | bf3e8bf1 | bellard | { |
470 | bf3e8bf1 | bellard | if (!(tb->cflags & CF_CODE_COPY)) {
|
471 | 97eb5b14 | bellard | if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
|
472 | 97eb5b14 | bellard | save_native_fp_state(env); |
473 | 97eb5b14 | bellard | } |
474 | bf3e8bf1 | bellard | gen_func(); |
475 | bf3e8bf1 | bellard | } else {
|
476 | 97eb5b14 | bellard | if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
|
477 | 97eb5b14 | bellard | restore_native_fp_state(env); |
478 | 97eb5b14 | bellard | } |
479 | bf3e8bf1 | bellard | /* we work with native eflags */
|
480 | bf3e8bf1 | bellard | CC_SRC = cc_table[CC_OP].compute_all(); |
481 | bf3e8bf1 | bellard | CC_OP = CC_OP_EFLAGS; |
482 | bf3e8bf1 | bellard | asm(".globl exec_loop\n" |
483 | bf3e8bf1 | bellard | "\n"
|
484 | bf3e8bf1 | bellard | "debug1:\n"
|
485 | bf3e8bf1 | bellard | " pushl %%ebp\n"
|
486 | bf3e8bf1 | bellard | " fs movl %10, %9\n"
|
487 | bf3e8bf1 | bellard | " fs movl %11, %%eax\n"
|
488 | bf3e8bf1 | bellard | " andl $0x400, %%eax\n"
|
489 | bf3e8bf1 | bellard | " fs orl %8, %%eax\n"
|
490 | bf3e8bf1 | bellard | " pushl %%eax\n"
|
491 | bf3e8bf1 | bellard | " popf\n"
|
492 | bf3e8bf1 | bellard | " fs movl %%esp, %12\n"
|
493 | bf3e8bf1 | bellard | " fs movl %0, %%eax\n"
|
494 | bf3e8bf1 | bellard | " fs movl %1, %%ecx\n"
|
495 | bf3e8bf1 | bellard | " fs movl %2, %%edx\n"
|
496 | bf3e8bf1 | bellard | " fs movl %3, %%ebx\n"
|
497 | bf3e8bf1 | bellard | " fs movl %4, %%esp\n"
|
498 | bf3e8bf1 | bellard | " fs movl %5, %%ebp\n"
|
499 | bf3e8bf1 | bellard | " fs movl %6, %%esi\n"
|
500 | bf3e8bf1 | bellard | " fs movl %7, %%edi\n"
|
501 | bf3e8bf1 | bellard | " fs jmp *%9\n"
|
502 | bf3e8bf1 | bellard | "exec_loop:\n"
|
503 | bf3e8bf1 | bellard | " fs movl %%esp, %4\n"
|
504 | bf3e8bf1 | bellard | " fs movl %12, %%esp\n"
|
505 | bf3e8bf1 | bellard | " fs movl %%eax, %0\n"
|
506 | bf3e8bf1 | bellard | " fs movl %%ecx, %1\n"
|
507 | bf3e8bf1 | bellard | " fs movl %%edx, %2\n"
|
508 | bf3e8bf1 | bellard | " fs movl %%ebx, %3\n"
|
509 | bf3e8bf1 | bellard | " fs movl %%ebp, %5\n"
|
510 | bf3e8bf1 | bellard | " fs movl %%esi, %6\n"
|
511 | bf3e8bf1 | bellard | " fs movl %%edi, %7\n"
|
512 | bf3e8bf1 | bellard | " pushf\n"
|
513 | bf3e8bf1 | bellard | " popl %%eax\n"
|
514 | bf3e8bf1 | bellard | " movl %%eax, %%ecx\n"
|
515 | bf3e8bf1 | bellard | " andl $0x400, %%ecx\n"
|
516 | bf3e8bf1 | bellard | " shrl $9, %%ecx\n"
|
517 | bf3e8bf1 | bellard | " andl $0x8d5, %%eax\n"
|
518 | bf3e8bf1 | bellard | " fs movl %%eax, %8\n"
|
519 | bf3e8bf1 | bellard | " movl $1, %%eax\n"
|
520 | bf3e8bf1 | bellard | " subl %%ecx, %%eax\n"
|
521 | bf3e8bf1 | bellard | " fs movl %%eax, %11\n"
|
522 | bf3e8bf1 | bellard | " fs movl %9, %%ebx\n" /* get T0 value */ |
523 | bf3e8bf1 | bellard | " popl %%ebp\n"
|
524 | bf3e8bf1 | bellard | : |
525 | bf3e8bf1 | bellard | : "m" (*(uint8_t *)offsetof(CPUState, regs[0])), |
526 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[1])), |
527 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[2])), |
528 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[3])), |
529 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[4])), |
530 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[5])), |
531 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[6])), |
532 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[7])), |
533 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
|
534 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
|
535 | bf3e8bf1 | bellard | "a" (gen_func),
|
536 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, df)),
|
537 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
|
538 | bf3e8bf1 | bellard | : "%ecx", "%edx" |
539 | bf3e8bf1 | bellard | ); |
540 | bf3e8bf1 | bellard | } |
541 | bf3e8bf1 | bellard | } |
542 | ae228531 | bellard | #else
|
543 | 3fb2ded1 | bellard | gen_func(); |
544 | ae228531 | bellard | #endif
|
545 | 83479e77 | bellard | env->current_tb = NULL;
|
546 | 4cbf74b6 | bellard | /* reset soft MMU for next block (it can currently
|
547 | 4cbf74b6 | bellard | only be set by a memory fault) */
|
548 | 4cbf74b6 | bellard | #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
|
549 | 3f337316 | bellard | if (env->hflags & HF_SOFTMMU_MASK) {
|
550 | 3f337316 | bellard | env->hflags &= ~HF_SOFTMMU_MASK; |
551 | 4cbf74b6 | bellard | /* do not allow linking to another block */
|
552 | 4cbf74b6 | bellard | T0 = 0;
|
553 | 4cbf74b6 | bellard | } |
554 | 4cbf74b6 | bellard | #endif
|
555 | 3fb2ded1 | bellard | } |
556 | 3fb2ded1 | bellard | } else {
|
557 | 0d1a29f9 | bellard | env_to_regs(); |
558 | 7d13299d | bellard | } |
559 | 3fb2ded1 | bellard | } /* for(;;) */
|
560 | 3fb2ded1 | bellard | |
561 | 7d13299d | bellard | |
562 | e4533c7a | bellard | #if defined(TARGET_I386)
|
563 | 97eb5b14 | bellard | #if defined(USE_CODE_COPY)
|
564 | 97eb5b14 | bellard | if (env->native_fp_regs) {
|
565 | 97eb5b14 | bellard | save_native_fp_state(env); |
566 | 97eb5b14 | bellard | } |
567 | 97eb5b14 | bellard | #endif
|
568 | 9de5e440 | bellard | /* restore flags in standard format */
|
569 | fc2b4c48 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
570 | 9de5e440 | bellard | |
571 | 7d13299d | bellard | /* restore global registers */
|
572 | 04369ff2 | bellard | #ifdef reg_EAX
|
573 | 04369ff2 | bellard | EAX = saved_EAX; |
574 | 04369ff2 | bellard | #endif
|
575 | 04369ff2 | bellard | #ifdef reg_ECX
|
576 | 04369ff2 | bellard | ECX = saved_ECX; |
577 | 04369ff2 | bellard | #endif
|
578 | 04369ff2 | bellard | #ifdef reg_EDX
|
579 | 04369ff2 | bellard | EDX = saved_EDX; |
580 | 04369ff2 | bellard | #endif
|
581 | 04369ff2 | bellard | #ifdef reg_EBX
|
582 | 04369ff2 | bellard | EBX = saved_EBX; |
583 | 04369ff2 | bellard | #endif
|
584 | 04369ff2 | bellard | #ifdef reg_ESP
|
585 | 04369ff2 | bellard | ESP = saved_ESP; |
586 | 04369ff2 | bellard | #endif
|
587 | 04369ff2 | bellard | #ifdef reg_EBP
|
588 | 04369ff2 | bellard | EBP = saved_EBP; |
589 | 04369ff2 | bellard | #endif
|
590 | 04369ff2 | bellard | #ifdef reg_ESI
|
591 | 04369ff2 | bellard | ESI = saved_ESI; |
592 | 04369ff2 | bellard | #endif
|
593 | 04369ff2 | bellard | #ifdef reg_EDI
|
594 | 04369ff2 | bellard | EDI = saved_EDI; |
595 | 04369ff2 | bellard | #endif
|
596 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
597 | 1b21b62a | bellard | env->cpsr = compute_cpsr(); |
598 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
599 | 67867308 | bellard | #elif defined(TARGET_PPC)
|
600 | e4533c7a | bellard | #else
|
601 | e4533c7a | bellard | #error unsupported target CPU
|
602 | e4533c7a | bellard | #endif
|
603 | 8c6939c0 | bellard | #ifdef __sparc__
|
604 | 8c6939c0 | bellard | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); |
605 | 8c6939c0 | bellard | #endif
|
606 | 7d13299d | bellard | T0 = saved_T0; |
607 | 7d13299d | bellard | T1 = saved_T1; |
608 | e4533c7a | bellard | T2 = saved_T2; |
609 | 7d13299d | bellard | env = saved_env; |
610 | 7d13299d | bellard | return ret;
|
611 | 7d13299d | bellard | } |
612 | 6dbad63e | bellard | |
613 | fbf9eeb3 | bellard | /* must only be called from the generated code as an exception can be
|
614 | fbf9eeb3 | bellard | generated */
|
615 | fbf9eeb3 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end)
|
616 | fbf9eeb3 | bellard | { |
617 | dc5d0b3d | bellard | /* XXX: cannot enable it yet because it yields to MMU exception
|
618 | dc5d0b3d | bellard | where NIP != read address on PowerPC */
|
619 | dc5d0b3d | bellard | #if 0
|
620 | fbf9eeb3 | bellard | target_ulong phys_addr;
|
621 | fbf9eeb3 | bellard | phys_addr = get_phys_addr_code(env, start);
|
622 | fbf9eeb3 | bellard | tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
|
623 | dc5d0b3d | bellard | #endif
|
624 | fbf9eeb3 | bellard | } |
625 | fbf9eeb3 | bellard | |
626 | 1a18c71b | bellard | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
|
627 | e4533c7a | bellard | |
628 | 6dbad63e | bellard | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
629 | 6dbad63e | bellard | { |
630 | 6dbad63e | bellard | CPUX86State *saved_env; |
631 | 6dbad63e | bellard | |
632 | 6dbad63e | bellard | saved_env = env; |
633 | 6dbad63e | bellard | env = s; |
634 | a412ac57 | bellard | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
635 | a513fe19 | bellard | selector &= 0xffff;
|
636 | 2e255c6b | bellard | cpu_x86_load_seg_cache(env, seg_reg, selector, |
637 | c27004ec | bellard | (selector << 4), 0xffff, 0); |
638 | a513fe19 | bellard | } else {
|
639 | b453b70b | bellard | load_seg(seg_reg, selector); |
640 | a513fe19 | bellard | } |
641 | 6dbad63e | bellard | env = saved_env; |
642 | 6dbad63e | bellard | } |
643 | 9de5e440 | bellard | |
644 | d0a1ffc9 | bellard | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
645 | d0a1ffc9 | bellard | { |
646 | d0a1ffc9 | bellard | CPUX86State *saved_env; |
647 | d0a1ffc9 | bellard | |
648 | d0a1ffc9 | bellard | saved_env = env; |
649 | d0a1ffc9 | bellard | env = s; |
650 | d0a1ffc9 | bellard | |
651 | c27004ec | bellard | helper_fsave((target_ulong)ptr, data32); |
652 | d0a1ffc9 | bellard | |
653 | d0a1ffc9 | bellard | env = saved_env; |
654 | d0a1ffc9 | bellard | } |
655 | d0a1ffc9 | bellard | |
656 | d0a1ffc9 | bellard | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) |
657 | d0a1ffc9 | bellard | { |
658 | d0a1ffc9 | bellard | CPUX86State *saved_env; |
659 | d0a1ffc9 | bellard | |
660 | d0a1ffc9 | bellard | saved_env = env; |
661 | d0a1ffc9 | bellard | env = s; |
662 | d0a1ffc9 | bellard | |
663 | c27004ec | bellard | helper_frstor((target_ulong)ptr, data32); |
664 | d0a1ffc9 | bellard | |
665 | d0a1ffc9 | bellard | env = saved_env; |
666 | d0a1ffc9 | bellard | } |
667 | d0a1ffc9 | bellard | |
668 | e4533c7a | bellard | #endif /* TARGET_I386 */ |
669 | e4533c7a | bellard | |
670 | 67b915a5 | bellard | #if !defined(CONFIG_SOFTMMU)
|
671 | 67b915a5 | bellard | |
672 | 3fb2ded1 | bellard | #if defined(TARGET_I386)
|
673 | 3fb2ded1 | bellard | |
674 | b56dad1c | bellard | /* 'pc' is the host PC at which the exception was raised. 'address' is
|
675 | fd6ce8f6 | bellard | the effective address of the memory exception. 'is_write' is 1 if a
|
676 | fd6ce8f6 | bellard | write caused the exception and otherwise 0'. 'old_set' is the
|
677 | fd6ce8f6 | bellard | signal set which should be restored */
|
678 | 2b413144 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
679 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
680 | bf3e8bf1 | bellard | void *puc)
|
681 | 9de5e440 | bellard | { |
682 | a513fe19 | bellard | TranslationBlock *tb; |
683 | a513fe19 | bellard | int ret;
|
684 | 68a79315 | bellard | |
685 | 83479e77 | bellard | if (cpu_single_env)
|
686 | 83479e77 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
687 | fd6ce8f6 | bellard | #if defined(DEBUG_SIGNAL)
|
688 | bf3e8bf1 | bellard | qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
689 | bf3e8bf1 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
690 | 9de5e440 | bellard | #endif
|
691 | 25eb4484 | bellard | /* XXX: locking issue */
|
692 | fbf9eeb3 | bellard | if (is_write && page_unprotect(address, pc, puc)) {
|
693 | fd6ce8f6 | bellard | return 1; |
694 | fd6ce8f6 | bellard | } |
695 | fbf9eeb3 | bellard | |
696 | 3fb2ded1 | bellard | /* see if it is an MMU fault */
|
697 | 93a40ea9 | bellard | ret = cpu_x86_handle_mmu_fault(env, address, is_write, |
698 | 93a40ea9 | bellard | ((env->hflags & HF_CPL_MASK) == 3), 0); |
699 | 3fb2ded1 | bellard | if (ret < 0) |
700 | 3fb2ded1 | bellard | return 0; /* not an MMU fault */ |
701 | 3fb2ded1 | bellard | if (ret == 0) |
702 | 3fb2ded1 | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
703 | 3fb2ded1 | bellard | /* now we have a real cpu fault */
|
704 | a513fe19 | bellard | tb = tb_find_pc(pc); |
705 | a513fe19 | bellard | if (tb) {
|
706 | 9de5e440 | bellard | /* the PC is inside the translated code. It means that we have
|
707 | 9de5e440 | bellard | a virtual CPU fault */
|
708 | bf3e8bf1 | bellard | cpu_restore_state(tb, env, pc, puc); |
709 | 3fb2ded1 | bellard | } |
710 | 4cbf74b6 | bellard | if (ret == 1) { |
711 | 3fb2ded1 | bellard | #if 0
|
712 | 4cbf74b6 | bellard | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
|
713 | 4cbf74b6 | bellard | env->eip, env->cr[2], env->error_code);
|
714 | 3fb2ded1 | bellard | #endif
|
715 | 4cbf74b6 | bellard | /* we restore the process signal mask as the sigreturn should
|
716 | 4cbf74b6 | bellard | do it (XXX: use sigsetjmp) */
|
717 | 4cbf74b6 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
718 | 4cbf74b6 | bellard | raise_exception_err(EXCP0E_PAGE, env->error_code); |
719 | 4cbf74b6 | bellard | } else {
|
720 | 4cbf74b6 | bellard | /* activate soft MMU for this block */
|
721 | 3f337316 | bellard | env->hflags |= HF_SOFTMMU_MASK; |
722 | fbf9eeb3 | bellard | cpu_resume_from_signal(env, puc); |
723 | 4cbf74b6 | bellard | } |
724 | 3fb2ded1 | bellard | /* never comes here */
|
725 | 3fb2ded1 | bellard | return 1; |
726 | 3fb2ded1 | bellard | } |
727 | 3fb2ded1 | bellard | |
728 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
729 | 3fb2ded1 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
730 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
731 | bf3e8bf1 | bellard | void *puc)
|
732 | 3fb2ded1 | bellard | { |
733 | 3fb2ded1 | bellard | /* XXX: do more */
|
734 | 3fb2ded1 | bellard | return 0; |
735 | 3fb2ded1 | bellard | } |
736 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
737 | 93ac68bc | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
738 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
739 | bf3e8bf1 | bellard | void *puc)
|
740 | 93ac68bc | bellard | { |
741 | b453b70b | bellard | /* XXX: locking issue */
|
742 | fbf9eeb3 | bellard | if (is_write && page_unprotect(address, pc, puc)) {
|
743 | b453b70b | bellard | return 1; |
744 | b453b70b | bellard | } |
745 | b453b70b | bellard | return 0; |
746 | 93ac68bc | bellard | } |
747 | 67867308 | bellard | #elif defined (TARGET_PPC)
|
748 | 67867308 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
749 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
750 | bf3e8bf1 | bellard | void *puc)
|
751 | 67867308 | bellard | { |
752 | 67867308 | bellard | TranslationBlock *tb; |
753 | ce09776b | bellard | int ret;
|
754 | 67867308 | bellard | |
755 | ce09776b | bellard | #if 1 |
756 | 67867308 | bellard | if (cpu_single_env)
|
757 | 67867308 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
758 | 67867308 | bellard | #endif
|
759 | 67867308 | bellard | #if defined(DEBUG_SIGNAL)
|
760 | 67867308 | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
761 | 67867308 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
762 | 67867308 | bellard | #endif
|
763 | 67867308 | bellard | /* XXX: locking issue */
|
764 | fbf9eeb3 | bellard | if (is_write && page_unprotect(address, pc, puc)) {
|
765 | 67867308 | bellard | return 1; |
766 | 67867308 | bellard | } |
767 | 67867308 | bellard | |
768 | ce09776b | bellard | /* see if it is an MMU fault */
|
769 | 7f957d28 | bellard | ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
|
770 | ce09776b | bellard | if (ret < 0) |
771 | ce09776b | bellard | return 0; /* not an MMU fault */ |
772 | ce09776b | bellard | if (ret == 0) |
773 | ce09776b | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
774 | ce09776b | bellard | |
775 | 67867308 | bellard | /* now we have a real cpu fault */
|
776 | 67867308 | bellard | tb = tb_find_pc(pc); |
777 | 67867308 | bellard | if (tb) {
|
778 | 67867308 | bellard | /* the PC is inside the translated code. It means that we have
|
779 | 67867308 | bellard | a virtual CPU fault */
|
780 | bf3e8bf1 | bellard | cpu_restore_state(tb, env, pc, puc); |
781 | 67867308 | bellard | } |
782 | ce09776b | bellard | if (ret == 1) { |
783 | 67867308 | bellard | #if 0
|
784 | ce09776b | bellard | printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
785 | ce09776b | bellard | env->nip, env->error_code, tb);
|
786 | 67867308 | bellard | #endif
|
787 | 67867308 | bellard | /* we restore the process signal mask as the sigreturn should
|
788 | 67867308 | bellard | do it (XXX: use sigsetjmp) */
|
789 | bf3e8bf1 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
790 | 9fddaa0c | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
791 | ce09776b | bellard | } else {
|
792 | ce09776b | bellard | /* activate soft MMU for this block */
|
793 | fbf9eeb3 | bellard | cpu_resume_from_signal(env, puc); |
794 | ce09776b | bellard | } |
795 | 67867308 | bellard | /* never comes here */
|
796 | 67867308 | bellard | return 1; |
797 | 67867308 | bellard | } |
798 | e4533c7a | bellard | #else
|
799 | e4533c7a | bellard | #error unsupported target CPU
|
800 | e4533c7a | bellard | #endif
|
801 | 9de5e440 | bellard | |
802 | 2b413144 | bellard | #if defined(__i386__)
|
803 | 2b413144 | bellard | |
804 | bf3e8bf1 | bellard | #if defined(USE_CODE_COPY)
|
805 | bf3e8bf1 | bellard | static void cpu_send_trap(unsigned long pc, int trap, |
806 | bf3e8bf1 | bellard | struct ucontext *uc)
|
807 | bf3e8bf1 | bellard | { |
808 | bf3e8bf1 | bellard | TranslationBlock *tb; |
809 | bf3e8bf1 | bellard | |
810 | bf3e8bf1 | bellard | if (cpu_single_env)
|
811 | bf3e8bf1 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
812 | bf3e8bf1 | bellard | /* now we have a real cpu fault */
|
813 | bf3e8bf1 | bellard | tb = tb_find_pc(pc); |
814 | bf3e8bf1 | bellard | if (tb) {
|
815 | bf3e8bf1 | bellard | /* the PC is inside the translated code. It means that we have
|
816 | bf3e8bf1 | bellard | a virtual CPU fault */
|
817 | bf3e8bf1 | bellard | cpu_restore_state(tb, env, pc, uc); |
818 | bf3e8bf1 | bellard | } |
819 | bf3e8bf1 | bellard | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
|
820 | bf3e8bf1 | bellard | raise_exception_err(trap, env->error_code); |
821 | bf3e8bf1 | bellard | } |
822 | bf3e8bf1 | bellard | #endif
|
823 | bf3e8bf1 | bellard | |
824 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
825 | e4533c7a | bellard | void *puc)
|
826 | 9de5e440 | bellard | { |
827 | 9de5e440 | bellard | struct ucontext *uc = puc;
|
828 | 9de5e440 | bellard | unsigned long pc; |
829 | bf3e8bf1 | bellard | int trapno;
|
830 | 97eb5b14 | bellard | |
831 | d691f669 | bellard | #ifndef REG_EIP
|
832 | d691f669 | bellard | /* for glibc 2.1 */
|
833 | fd6ce8f6 | bellard | #define REG_EIP EIP
|
834 | fd6ce8f6 | bellard | #define REG_ERR ERR
|
835 | fd6ce8f6 | bellard | #define REG_TRAPNO TRAPNO
|
836 | d691f669 | bellard | #endif
|
837 | fc2b4c48 | bellard | pc = uc->uc_mcontext.gregs[REG_EIP]; |
838 | bf3e8bf1 | bellard | trapno = uc->uc_mcontext.gregs[REG_TRAPNO]; |
839 | bf3e8bf1 | bellard | #if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
840 | bf3e8bf1 | bellard | if (trapno == 0x00 || trapno == 0x05) { |
841 | bf3e8bf1 | bellard | /* send division by zero or bound exception */
|
842 | bf3e8bf1 | bellard | cpu_send_trap(pc, trapno, uc); |
843 | bf3e8bf1 | bellard | return 1; |
844 | bf3e8bf1 | bellard | } else
|
845 | bf3e8bf1 | bellard | #endif
|
846 | bf3e8bf1 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
847 | bf3e8bf1 | bellard | trapno == 0xe ?
|
848 | bf3e8bf1 | bellard | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
849 | bf3e8bf1 | bellard | &uc->uc_sigmask, puc); |
850 | 2b413144 | bellard | } |
851 | 2b413144 | bellard | |
852 | bc51c5c9 | bellard | #elif defined(__x86_64__)
|
853 | bc51c5c9 | bellard | |
854 | bc51c5c9 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
855 | bc51c5c9 | bellard | void *puc)
|
856 | bc51c5c9 | bellard | { |
857 | bc51c5c9 | bellard | struct ucontext *uc = puc;
|
858 | bc51c5c9 | bellard | unsigned long pc; |
859 | bc51c5c9 | bellard | |
860 | bc51c5c9 | bellard | pc = uc->uc_mcontext.gregs[REG_RIP]; |
861 | bc51c5c9 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
862 | bc51c5c9 | bellard | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
|
863 | bc51c5c9 | bellard | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
864 | bc51c5c9 | bellard | &uc->uc_sigmask, puc); |
865 | bc51c5c9 | bellard | } |
866 | bc51c5c9 | bellard | |
867 | 83fb7adf | bellard | #elif defined(__powerpc__)
|
868 | 2b413144 | bellard | |
869 | 83fb7adf | bellard | /***********************************************************************
|
870 | 83fb7adf | bellard | * signal context platform-specific definitions
|
871 | 83fb7adf | bellard | * From Wine
|
872 | 83fb7adf | bellard | */
|
873 | 83fb7adf | bellard | #ifdef linux
|
874 | 83fb7adf | bellard | /* All Registers access - only for local access */
|
875 | 83fb7adf | bellard | # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
|
876 | 83fb7adf | bellard | /* Gpr Registers access */
|
877 | 83fb7adf | bellard | # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
|
878 | 83fb7adf | bellard | # define IAR_sig(context) REG_sig(nip, context) /* Program counter */ |
879 | 83fb7adf | bellard | # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ |
880 | 83fb7adf | bellard | # define CTR_sig(context) REG_sig(ctr, context) /* Count register */ |
881 | 83fb7adf | bellard | # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ |
882 | 83fb7adf | bellard | # define LR_sig(context) REG_sig(link, context) /* Link register */ |
883 | 83fb7adf | bellard | # define CR_sig(context) REG_sig(ccr, context) /* Condition register */ |
884 | 83fb7adf | bellard | /* Float Registers access */
|
885 | 83fb7adf | bellard | # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) |
886 | 83fb7adf | bellard | # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) |
887 | 83fb7adf | bellard | /* Exception Registers access */
|
888 | 83fb7adf | bellard | # define DAR_sig(context) REG_sig(dar, context)
|
889 | 83fb7adf | bellard | # define DSISR_sig(context) REG_sig(dsisr, context)
|
890 | 83fb7adf | bellard | # define TRAP_sig(context) REG_sig(trap, context)
|
891 | 83fb7adf | bellard | #endif /* linux */ |
892 | 83fb7adf | bellard | |
893 | 83fb7adf | bellard | #ifdef __APPLE__
|
894 | 83fb7adf | bellard | # include <sys/ucontext.h> |
895 | 83fb7adf | bellard | typedef struct ucontext SIGCONTEXT; |
896 | 83fb7adf | bellard | /* All Registers access - only for local access */
|
897 | 83fb7adf | bellard | # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
|
898 | 83fb7adf | bellard | # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
|
899 | 83fb7adf | bellard | # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
|
900 | 83fb7adf | bellard | # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
|
901 | 83fb7adf | bellard | /* Gpr Registers access */
|
902 | 83fb7adf | bellard | # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) |
903 | 83fb7adf | bellard | # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ |
904 | 83fb7adf | bellard | # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ |
905 | 83fb7adf | bellard | # define CTR_sig(context) REG_sig(ctr, context)
|
906 | 83fb7adf | bellard | # define XER_sig(context) REG_sig(xer, context) /* Link register */ |
907 | 83fb7adf | bellard | # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ |
908 | 83fb7adf | bellard | # define CR_sig(context) REG_sig(cr, context) /* Condition register */ |
909 | 83fb7adf | bellard | /* Float Registers access */
|
910 | 83fb7adf | bellard | # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
|
911 | 83fb7adf | bellard | # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) |
912 | 83fb7adf | bellard | /* Exception Registers access */
|
913 | 83fb7adf | bellard | # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ |
914 | 83fb7adf | bellard | # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
|
915 | 83fb7adf | bellard | # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ |
916 | 83fb7adf | bellard | #endif /* __APPLE__ */ |
917 | 83fb7adf | bellard | |
918 | d1d9f421 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
919 | e4533c7a | bellard | void *puc)
|
920 | 2b413144 | bellard | { |
921 | 25eb4484 | bellard | struct ucontext *uc = puc;
|
922 | 25eb4484 | bellard | unsigned long pc; |
923 | 25eb4484 | bellard | int is_write;
|
924 | 25eb4484 | bellard | |
925 | 83fb7adf | bellard | pc = IAR_sig(uc); |
926 | 25eb4484 | bellard | is_write = 0;
|
927 | 25eb4484 | bellard | #if 0
|
928 | 25eb4484 | bellard | /* ppc 4xx case */
|
929 | 83fb7adf | bellard | if (DSISR_sig(uc) & 0x00800000)
|
930 | 25eb4484 | bellard | is_write = 1;
|
931 | 25eb4484 | bellard | #else
|
932 | 83fb7adf | bellard | if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
933 | 25eb4484 | bellard | is_write = 1;
|
934 | 25eb4484 | bellard | #endif
|
935 | 25eb4484 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
936 | bf3e8bf1 | bellard | is_write, &uc->uc_sigmask, puc); |
937 | 2b413144 | bellard | } |
938 | 2b413144 | bellard | |
939 | 2f87c607 | bellard | #elif defined(__alpha__)
|
940 | 2f87c607 | bellard | |
941 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
942 | 2f87c607 | bellard | void *puc)
|
943 | 2f87c607 | bellard | { |
944 | 2f87c607 | bellard | struct ucontext *uc = puc;
|
945 | 2f87c607 | bellard | uint32_t *pc = uc->uc_mcontext.sc_pc; |
946 | 2f87c607 | bellard | uint32_t insn = *pc; |
947 | 2f87c607 | bellard | int is_write = 0; |
948 | 2f87c607 | bellard | |
949 | 8c6939c0 | bellard | /* XXX: need kernel patch to get write flag faster */
|
950 | 2f87c607 | bellard | switch (insn >> 26) { |
951 | 2f87c607 | bellard | case 0x0d: // stw |
952 | 2f87c607 | bellard | case 0x0e: // stb |
953 | 2f87c607 | bellard | case 0x0f: // stq_u |
954 | 2f87c607 | bellard | case 0x24: // stf |
955 | 2f87c607 | bellard | case 0x25: // stg |
956 | 2f87c607 | bellard | case 0x26: // sts |
957 | 2f87c607 | bellard | case 0x27: // stt |
958 | 2f87c607 | bellard | case 0x2c: // stl |
959 | 2f87c607 | bellard | case 0x2d: // stq |
960 | 2f87c607 | bellard | case 0x2e: // stl_c |
961 | 2f87c607 | bellard | case 0x2f: // stq_c |
962 | 2f87c607 | bellard | is_write = 1;
|
963 | 2f87c607 | bellard | } |
964 | 2f87c607 | bellard | |
965 | 2f87c607 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
966 | bf3e8bf1 | bellard | is_write, &uc->uc_sigmask, puc); |
967 | 2f87c607 | bellard | } |
968 | 8c6939c0 | bellard | #elif defined(__sparc__)
|
969 | 8c6939c0 | bellard | |
970 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
971 | e4533c7a | bellard | void *puc)
|
972 | 8c6939c0 | bellard | { |
973 | 8c6939c0 | bellard | uint32_t *regs = (uint32_t *)(info + 1);
|
974 | 8c6939c0 | bellard | void *sigmask = (regs + 20); |
975 | 8c6939c0 | bellard | unsigned long pc; |
976 | 8c6939c0 | bellard | int is_write;
|
977 | 8c6939c0 | bellard | uint32_t insn; |
978 | 8c6939c0 | bellard | |
979 | 8c6939c0 | bellard | /* XXX: is there a standard glibc define ? */
|
980 | 8c6939c0 | bellard | pc = regs[1];
|
981 | 8c6939c0 | bellard | /* XXX: need kernel patch to get write flag faster */
|
982 | 8c6939c0 | bellard | is_write = 0;
|
983 | 8c6939c0 | bellard | insn = *(uint32_t *)pc; |
984 | 8c6939c0 | bellard | if ((insn >> 30) == 3) { |
985 | 8c6939c0 | bellard | switch((insn >> 19) & 0x3f) { |
986 | 8c6939c0 | bellard | case 0x05: // stb |
987 | 8c6939c0 | bellard | case 0x06: // sth |
988 | 8c6939c0 | bellard | case 0x04: // st |
989 | 8c6939c0 | bellard | case 0x07: // std |
990 | 8c6939c0 | bellard | case 0x24: // stf |
991 | 8c6939c0 | bellard | case 0x27: // stdf |
992 | 8c6939c0 | bellard | case 0x25: // stfsr |
993 | 8c6939c0 | bellard | is_write = 1;
|
994 | 8c6939c0 | bellard | break;
|
995 | 8c6939c0 | bellard | } |
996 | 8c6939c0 | bellard | } |
997 | 8c6939c0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
998 | bf3e8bf1 | bellard | is_write, sigmask, NULL);
|
999 | 8c6939c0 | bellard | } |
1000 | 8c6939c0 | bellard | |
1001 | 8c6939c0 | bellard | #elif defined(__arm__)
|
1002 | 8c6939c0 | bellard | |
1003 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1004 | e4533c7a | bellard | void *puc)
|
1005 | 8c6939c0 | bellard | { |
1006 | 8c6939c0 | bellard | struct ucontext *uc = puc;
|
1007 | 8c6939c0 | bellard | unsigned long pc; |
1008 | 8c6939c0 | bellard | int is_write;
|
1009 | 8c6939c0 | bellard | |
1010 | 8c6939c0 | bellard | pc = uc->uc_mcontext.gregs[R15]; |
1011 | 8c6939c0 | bellard | /* XXX: compute is_write */
|
1012 | 8c6939c0 | bellard | is_write = 0;
|
1013 | 8c6939c0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1014 | 8c6939c0 | bellard | is_write, |
1015 | 8c6939c0 | bellard | &uc->uc_sigmask); |
1016 | 8c6939c0 | bellard | } |
1017 | 8c6939c0 | bellard | |
1018 | 38e584a0 | bellard | #elif defined(__mc68000)
|
1019 | 38e584a0 | bellard | |
1020 | 38e584a0 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1021 | 38e584a0 | bellard | void *puc)
|
1022 | 38e584a0 | bellard | { |
1023 | 38e584a0 | bellard | struct ucontext *uc = puc;
|
1024 | 38e584a0 | bellard | unsigned long pc; |
1025 | 38e584a0 | bellard | int is_write;
|
1026 | 38e584a0 | bellard | |
1027 | 38e584a0 | bellard | pc = uc->uc_mcontext.gregs[16];
|
1028 | 38e584a0 | bellard | /* XXX: compute is_write */
|
1029 | 38e584a0 | bellard | is_write = 0;
|
1030 | 38e584a0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1031 | 38e584a0 | bellard | is_write, |
1032 | bf3e8bf1 | bellard | &uc->uc_sigmask, puc); |
1033 | 38e584a0 | bellard | } |
1034 | 38e584a0 | bellard | |
1035 | 9de5e440 | bellard | #else
|
1036 | 2b413144 | bellard | |
1037 | 3fb2ded1 | bellard | #error host CPU specific signal handler needed
|
1038 | 2b413144 | bellard | |
1039 | 9de5e440 | bellard | #endif
|
1040 | 67b915a5 | bellard | |
1041 | 67b915a5 | bellard | #endif /* !defined(CONFIG_SOFTMMU) */ |