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1 | dc99065b | bellard | /* Interface between the opcode library and its callers.
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2 | dc99065b | bellard | Written by Cygnus Support, 1993.
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3 | dc99065b | bellard | |
4 | dc99065b | bellard | The opcode library (libopcodes.a) provides instruction decoders for
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5 | dc99065b | bellard | a large variety of instruction sets, callable with an identical
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6 | dc99065b | bellard | interface, for making instruction-processing programs more independent
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7 | dc99065b | bellard | of the instruction set being processed. */
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8 | dc99065b | bellard | |
9 | dc99065b | bellard | #ifndef DIS_ASM_H
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10 | dc99065b | bellard | #define DIS_ASM_H
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11 | dc99065b | bellard | |
12 | c27004ec | bellard | #include <stdlib.h> |
13 | dc99065b | bellard | #include <stdio.h> |
14 | 04369ff2 | bellard | #include <string.h> |
15 | 43d4145a | bellard | #include <inttypes.h> |
16 | 43d4145a | bellard | |
17 | 43d4145a | bellard | #define PARAMS(x) x
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18 | 43d4145a | bellard | typedef void *PTR; |
19 | 43d4145a | bellard | typedef uint64_t bfd_vma;
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20 | bc51c5c9 | bellard | typedef int64_t bfd_signed_vma;
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21 | 43d4145a | bellard | typedef uint8_t bfd_byte;
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22 | bc51c5c9 | bellard | #define sprintf_vma(s,x) sprintf (s, "%0" PRIx64, x) |
23 | 43d4145a | bellard | |
24 | c27004ec | bellard | #define BFD64
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25 | c27004ec | bellard | |
26 | 43d4145a | bellard | enum bfd_flavour {
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27 | 43d4145a | bellard | bfd_target_unknown_flavour, |
28 | 43d4145a | bellard | bfd_target_aout_flavour, |
29 | 43d4145a | bellard | bfd_target_coff_flavour, |
30 | 43d4145a | bellard | bfd_target_ecoff_flavour, |
31 | 43d4145a | bellard | bfd_target_elf_flavour, |
32 | 43d4145a | bellard | bfd_target_ieee_flavour, |
33 | 43d4145a | bellard | bfd_target_nlm_flavour, |
34 | 43d4145a | bellard | bfd_target_oasys_flavour, |
35 | 43d4145a | bellard | bfd_target_tekhex_flavour, |
36 | 43d4145a | bellard | bfd_target_srec_flavour, |
37 | 43d4145a | bellard | bfd_target_ihex_flavour, |
38 | 43d4145a | bellard | bfd_target_som_flavour, |
39 | 43d4145a | bellard | bfd_target_os9k_flavour, |
40 | 43d4145a | bellard | bfd_target_versados_flavour, |
41 | 43d4145a | bellard | bfd_target_msdos_flavour, |
42 | 43d4145a | bellard | bfd_target_evax_flavour |
43 | 43d4145a | bellard | }; |
44 | 43d4145a | bellard | |
45 | 43d4145a | bellard | enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN };
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46 | 43d4145a | bellard | |
47 | 5fafdf24 | ths | enum bfd_architecture
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48 | 43d4145a | bellard | { |
49 | 43d4145a | bellard | bfd_arch_unknown, /* File arch not known */
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50 | 43d4145a | bellard | bfd_arch_obscure, /* Arch known, not one of these */
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51 | 43d4145a | bellard | bfd_arch_m68k, /* Motorola 68xxx */
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52 | 43d4145a | bellard | #define bfd_mach_m68000 1 |
53 | 43d4145a | bellard | #define bfd_mach_m68008 2 |
54 | 43d4145a | bellard | #define bfd_mach_m68010 3 |
55 | 43d4145a | bellard | #define bfd_mach_m68020 4 |
56 | 43d4145a | bellard | #define bfd_mach_m68030 5 |
57 | 43d4145a | bellard | #define bfd_mach_m68040 6 |
58 | 43d4145a | bellard | #define bfd_mach_m68060 7 |
59 | 48024e4a | bellard | #define bfd_mach_cpu32 8 |
60 | 48024e4a | bellard | #define bfd_mach_mcf5200 9 |
61 | 48024e4a | bellard | #define bfd_mach_mcf5206e 10 |
62 | 48024e4a | bellard | #define bfd_mach_mcf5307 11 |
63 | 48024e4a | bellard | #define bfd_mach_mcf5407 12 |
64 | 48024e4a | bellard | #define bfd_mach_mcf528x 13 |
65 | 48024e4a | bellard | #define bfd_mach_mcfv4e 14 |
66 | 48024e4a | bellard | #define bfd_mach_mcf521x 15 |
67 | 48024e4a | bellard | #define bfd_mach_mcf5249 16 |
68 | 48024e4a | bellard | #define bfd_mach_mcf547x 17 |
69 | 48024e4a | bellard | #define bfd_mach_mcf548x 18 |
70 | 3b46e624 | ths | bfd_arch_vax, /* DEC Vax */
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71 | 43d4145a | bellard | bfd_arch_i960, /* Intel 960 */
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72 | 43d4145a | bellard | /* The order of the following is important.
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73 | 5fafdf24 | ths | lower number indicates a machine type that
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74 | 43d4145a | bellard | only accepts a subset of the instructions
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75 | 43d4145a | bellard | available to machines with higher numbers.
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76 | 43d4145a | bellard | The exception is the "ca", which is
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77 | 5fafdf24 | ths | incompatible with all other machines except
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78 | 43d4145a | bellard | "core". */
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79 | 43d4145a | bellard | |
80 | 43d4145a | bellard | #define bfd_mach_i960_core 1 |
81 | 43d4145a | bellard | #define bfd_mach_i960_ka_sa 2 |
82 | 43d4145a | bellard | #define bfd_mach_i960_kb_sb 3 |
83 | 43d4145a | bellard | #define bfd_mach_i960_mc 4 |
84 | 43d4145a | bellard | #define bfd_mach_i960_xa 5 |
85 | 43d4145a | bellard | #define bfd_mach_i960_ca 6 |
86 | 43d4145a | bellard | #define bfd_mach_i960_jx 7 |
87 | 43d4145a | bellard | #define bfd_mach_i960_hx 8 |
88 | 43d4145a | bellard | |
89 | 43d4145a | bellard | bfd_arch_a29k, /* AMD 29000 */
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90 | 43d4145a | bellard | bfd_arch_sparc, /* SPARC */
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91 | 43d4145a | bellard | #define bfd_mach_sparc 1 |
92 | aa0aa4fa | bellard | /* The difference between v8plus and v9 is that v9 is a true 64 bit env. */
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93 | 43d4145a | bellard | #define bfd_mach_sparc_sparclet 2 |
94 | 43d4145a | bellard | #define bfd_mach_sparc_sparclite 3 |
95 | 43d4145a | bellard | #define bfd_mach_sparc_v8plus 4 |
96 | aa0aa4fa | bellard | #define bfd_mach_sparc_v8plusa 5 /* with ultrasparc add'ns. */ |
97 | aa0aa4fa | bellard | #define bfd_mach_sparc_sparclite_le 6 |
98 | aa0aa4fa | bellard | #define bfd_mach_sparc_v9 7 |
99 | aa0aa4fa | bellard | #define bfd_mach_sparc_v9a 8 /* with ultrasparc add'ns. */ |
100 | aa0aa4fa | bellard | #define bfd_mach_sparc_v8plusb 9 /* with cheetah add'ns. */ |
101 | aa0aa4fa | bellard | #define bfd_mach_sparc_v9b 10 /* with cheetah add'ns. */ |
102 | aa0aa4fa | bellard | /* Nonzero if MACH has the v9 instruction set. */
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103 | 43d4145a | bellard | #define bfd_mach_sparc_v9_p(mach) \
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104 | aa0aa4fa | bellard | ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \ |
105 | aa0aa4fa | bellard | && (mach) != bfd_mach_sparc_sparclite_le) |
106 | 43d4145a | bellard | bfd_arch_mips, /* MIPS Rxxxx */
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107 | 43d4145a | bellard | #define bfd_mach_mips3000 3000 |
108 | 43d4145a | bellard | #define bfd_mach_mips3900 3900 |
109 | 43d4145a | bellard | #define bfd_mach_mips4000 4000 |
110 | 43d4145a | bellard | #define bfd_mach_mips4010 4010 |
111 | 43d4145a | bellard | #define bfd_mach_mips4100 4100 |
112 | 43d4145a | bellard | #define bfd_mach_mips4300 4300 |
113 | 43d4145a | bellard | #define bfd_mach_mips4400 4400 |
114 | 43d4145a | bellard | #define bfd_mach_mips4600 4600 |
115 | 43d4145a | bellard | #define bfd_mach_mips4650 4650 |
116 | 43d4145a | bellard | #define bfd_mach_mips5000 5000 |
117 | 43d4145a | bellard | #define bfd_mach_mips6000 6000 |
118 | 43d4145a | bellard | #define bfd_mach_mips8000 8000 |
119 | 43d4145a | bellard | #define bfd_mach_mips10000 10000 |
120 | 43d4145a | bellard | #define bfd_mach_mips16 16 |
121 | 43d4145a | bellard | bfd_arch_i386, /* Intel 386 */
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122 | 43d4145a | bellard | #define bfd_mach_i386_i386 0 |
123 | 43d4145a | bellard | #define bfd_mach_i386_i8086 1 |
124 | bc51c5c9 | bellard | #define bfd_mach_i386_i386_intel_syntax 2 |
125 | bc51c5c9 | bellard | #define bfd_mach_x86_64 3 |
126 | bc51c5c9 | bellard | #define bfd_mach_x86_64_intel_syntax 4 |
127 | 43d4145a | bellard | bfd_arch_we32k, /* AT&T WE32xxx */
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128 | 43d4145a | bellard | bfd_arch_tahoe, /* CCI/Harris Tahoe */
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129 | 43d4145a | bellard | bfd_arch_i860, /* Intel 860 */
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130 | 43d4145a | bellard | bfd_arch_romp, /* IBM ROMP PC/RT */
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131 | 43d4145a | bellard | bfd_arch_alliant, /* Alliant */
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132 | 43d4145a | bellard | bfd_arch_convex, /* Convex */
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133 | 43d4145a | bellard | bfd_arch_m88k, /* Motorola 88xxx */
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134 | 43d4145a | bellard | bfd_arch_pyramid, /* Pyramid Technology */
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135 | 43d4145a | bellard | bfd_arch_h8300, /* Hitachi H8/300 */
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136 | 43d4145a | bellard | #define bfd_mach_h8300 1 |
137 | 43d4145a | bellard | #define bfd_mach_h8300h 2 |
138 | 43d4145a | bellard | #define bfd_mach_h8300s 3 |
139 | 43d4145a | bellard | bfd_arch_powerpc, /* PowerPC */
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140 | a2458627 | bellard | #define bfd_mach_ppc 0 |
141 | a2458627 | bellard | #define bfd_mach_ppc64 1 |
142 | a2458627 | bellard | #define bfd_mach_ppc_403 403 |
143 | a2458627 | bellard | #define bfd_mach_ppc_403gc 4030 |
144 | a2458627 | bellard | #define bfd_mach_ppc_505 505 |
145 | a2458627 | bellard | #define bfd_mach_ppc_601 601 |
146 | a2458627 | bellard | #define bfd_mach_ppc_602 602 |
147 | a2458627 | bellard | #define bfd_mach_ppc_603 603 |
148 | a2458627 | bellard | #define bfd_mach_ppc_ec603e 6031 |
149 | a2458627 | bellard | #define bfd_mach_ppc_604 604 |
150 | a2458627 | bellard | #define bfd_mach_ppc_620 620 |
151 | a2458627 | bellard | #define bfd_mach_ppc_630 630 |
152 | a2458627 | bellard | #define bfd_mach_ppc_750 750 |
153 | a2458627 | bellard | #define bfd_mach_ppc_860 860 |
154 | a2458627 | bellard | #define bfd_mach_ppc_a35 35 |
155 | a2458627 | bellard | #define bfd_mach_ppc_rs64ii 642 |
156 | a2458627 | bellard | #define bfd_mach_ppc_rs64iii 643 |
157 | a2458627 | bellard | #define bfd_mach_ppc_7400 7400 |
158 | 43d4145a | bellard | bfd_arch_rs6000, /* IBM RS/6000 */
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159 | 43d4145a | bellard | bfd_arch_hppa, /* HP PA RISC */
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160 | 43d4145a | bellard | bfd_arch_d10v, /* Mitsubishi D10V */
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161 | 43d4145a | bellard | bfd_arch_z8k, /* Zilog Z8000 */
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162 | 43d4145a | bellard | #define bfd_mach_z8001 1 |
163 | 43d4145a | bellard | #define bfd_mach_z8002 2 |
164 | 43d4145a | bellard | bfd_arch_h8500, /* Hitachi H8/500 */
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165 | 43d4145a | bellard | bfd_arch_sh, /* Hitachi SH */
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166 | fdf9b3e8 | bellard | #define bfd_mach_sh 1 |
167 | fdf9b3e8 | bellard | #define bfd_mach_sh2 0x20 |
168 | fdf9b3e8 | bellard | #define bfd_mach_sh_dsp 0x2d |
169 | fdf9b3e8 | bellard | #define bfd_mach_sh2a 0x2a |
170 | fdf9b3e8 | bellard | #define bfd_mach_sh2a_nofpu 0x2b |
171 | fdf9b3e8 | bellard | #define bfd_mach_sh2e 0x2e |
172 | 43d4145a | bellard | #define bfd_mach_sh3 0x30 |
173 | fdf9b3e8 | bellard | #define bfd_mach_sh3_nommu 0x31 |
174 | fdf9b3e8 | bellard | #define bfd_mach_sh3_dsp 0x3d |
175 | 43d4145a | bellard | #define bfd_mach_sh3e 0x3e |
176 | 43d4145a | bellard | #define bfd_mach_sh4 0x40 |
177 | fdf9b3e8 | bellard | #define bfd_mach_sh4_nofpu 0x41 |
178 | fdf9b3e8 | bellard | #define bfd_mach_sh4_nommu_nofpu 0x42 |
179 | fdf9b3e8 | bellard | #define bfd_mach_sh4a 0x4a |
180 | fdf9b3e8 | bellard | #define bfd_mach_sh4a_nofpu 0x4b |
181 | fdf9b3e8 | bellard | #define bfd_mach_sh4al_dsp 0x4d |
182 | fdf9b3e8 | bellard | #define bfd_mach_sh5 0x50 |
183 | 43d4145a | bellard | bfd_arch_alpha, /* Dec Alpha */
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184 | eddf68a6 | j_mayer | #define bfd_mach_alpha 1 |
185 | 43d4145a | bellard | bfd_arch_arm, /* Advanced Risc Machines ARM */
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186 | 4b0f1a8b | pbrook | #define bfd_mach_arm_unknown 0 |
187 | 4b0f1a8b | pbrook | #define bfd_mach_arm_2 1 |
188 | 4b0f1a8b | pbrook | #define bfd_mach_arm_2a 2 |
189 | 4b0f1a8b | pbrook | #define bfd_mach_arm_3 3 |
190 | 4b0f1a8b | pbrook | #define bfd_mach_arm_3M 4 |
191 | 4b0f1a8b | pbrook | #define bfd_mach_arm_4 5 |
192 | 4b0f1a8b | pbrook | #define bfd_mach_arm_4T 6 |
193 | 4b0f1a8b | pbrook | #define bfd_mach_arm_5 7 |
194 | 4b0f1a8b | pbrook | #define bfd_mach_arm_5T 8 |
195 | 4b0f1a8b | pbrook | #define bfd_mach_arm_5TE 9 |
196 | 4b0f1a8b | pbrook | #define bfd_mach_arm_XScale 10 |
197 | 4b0f1a8b | pbrook | #define bfd_mach_arm_ep9312 11 |
198 | 4b0f1a8b | pbrook | #define bfd_mach_arm_iWMMXt 12 |
199 | 4b0f1a8b | pbrook | #define bfd_mach_arm_iWMMXt2 13 |
200 | 43d4145a | bellard | bfd_arch_ns32k, /* National Semiconductors ns32000 */
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201 | 43d4145a | bellard | bfd_arch_w65, /* WDC 65816 */
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202 | 43d4145a | bellard | bfd_arch_tic30, /* Texas Instruments TMS320C30 */
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203 | 43d4145a | bellard | bfd_arch_v850, /* NEC V850 */
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204 | 43d4145a | bellard | #define bfd_mach_v850 0 |
205 | 43d4145a | bellard | bfd_arch_arc, /* Argonaut RISC Core */
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206 | 43d4145a | bellard | #define bfd_mach_arc_base 0 |
207 | 43d4145a | bellard | bfd_arch_m32r, /* Mitsubishi M32R/D */
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208 | 43d4145a | bellard | #define bfd_mach_m32r 0 /* backwards compatibility */ |
209 | 43d4145a | bellard | bfd_arch_mn10200, /* Matsushita MN10200 */
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210 | 43d4145a | bellard | bfd_arch_mn10300, /* Matsushita MN10300 */
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211 | a25fd137 | ths | bfd_arch_cris, /* Axis CRIS */
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212 | a25fd137 | ths | #define bfd_mach_cris_v0_v10 255 |
213 | a25fd137 | ths | #define bfd_mach_cris_v32 32 |
214 | a25fd137 | ths | #define bfd_mach_cris_v10_v32 1032 |
215 | 43d4145a | bellard | bfd_arch_last |
216 | 43d4145a | bellard | }; |
217 | 8f860bb8 | ths | #define bfd_mach_s390_31 31 |
218 | 8f860bb8 | ths | #define bfd_mach_s390_64 64 |
219 | 43d4145a | bellard | |
220 | 43d4145a | bellard | typedef struct symbol_cache_entry |
221 | 43d4145a | bellard | { |
222 | 43d4145a | bellard | const char *name; |
223 | 43d4145a | bellard | union
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224 | 43d4145a | bellard | { |
225 | 43d4145a | bellard | PTR p; |
226 | 43d4145a | bellard | bfd_vma i; |
227 | 43d4145a | bellard | } udata; |
228 | 43d4145a | bellard | } asymbol; |
229 | dc99065b | bellard | |
230 | dc99065b | bellard | typedef int (*fprintf_ftype) PARAMS((FILE*, const char*, ...)); |
231 | dc99065b | bellard | |
232 | dc99065b | bellard | enum dis_insn_type {
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233 | dc99065b | bellard | dis_noninsn, /* Not a valid instruction */
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234 | dc99065b | bellard | dis_nonbranch, /* Not a branch instruction */
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235 | dc99065b | bellard | dis_branch, /* Unconditional branch */
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236 | dc99065b | bellard | dis_condbranch, /* Conditional branch */
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237 | dc99065b | bellard | dis_jsr, /* Jump to subroutine */
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238 | dc99065b | bellard | dis_condjsr, /* Conditional jump to subroutine */
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239 | dc99065b | bellard | dis_dref, /* Data reference instruction */
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240 | dc99065b | bellard | dis_dref2 /* Two data references in instruction */
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241 | dc99065b | bellard | }; |
242 | dc99065b | bellard | |
243 | 5fafdf24 | ths | /* This struct is passed into the instruction decoding routine,
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244 | dc99065b | bellard | and is passed back out into each callback. The various fields are used
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245 | dc99065b | bellard | for conveying information from your main routine into your callbacks,
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246 | dc99065b | bellard | for passing information into the instruction decoders (such as the
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247 | dc99065b | bellard | addresses of the callback functions), or for passing information
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248 | dc99065b | bellard | back from the instruction decoders to their callers.
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249 | dc99065b | bellard | |
250 | dc99065b | bellard | It must be initialized before it is first passed; this can be done
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251 | dc99065b | bellard | by hand, or using one of the initialization macros below. */
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252 | dc99065b | bellard | |
253 | dc99065b | bellard | typedef struct disassemble_info { |
254 | dc99065b | bellard | fprintf_ftype fprintf_func; |
255 | dc99065b | bellard | FILE *stream; |
256 | dc99065b | bellard | PTR application_data; |
257 | dc99065b | bellard | |
258 | dc99065b | bellard | /* Target description. We could replace this with a pointer to the bfd,
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259 | dc99065b | bellard | but that would require one. There currently isn't any such requirement
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260 | dc99065b | bellard | so to avoid introducing one we record these explicitly. */
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261 | dc99065b | bellard | /* The bfd_flavour. This can be bfd_target_unknown_flavour. */
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262 | dc99065b | bellard | enum bfd_flavour flavour;
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263 | dc99065b | bellard | /* The bfd_arch value. */
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264 | dc99065b | bellard | enum bfd_architecture arch;
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265 | dc99065b | bellard | /* The bfd_mach value. */
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266 | dc99065b | bellard | unsigned long mach; |
267 | dc99065b | bellard | /* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */
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268 | dc99065b | bellard | enum bfd_endian endian;
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269 | dc99065b | bellard | |
270 | dc99065b | bellard | /* An array of pointers to symbols either at the location being disassembled
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271 | dc99065b | bellard | or at the start of the function being disassembled. The array is sorted
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272 | dc99065b | bellard | so that the first symbol is intended to be the one used. The others are
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273 | dc99065b | bellard | present for any misc. purposes. This is not set reliably, but if it is
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274 | dc99065b | bellard | not NULL, it is correct. */
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275 | dc99065b | bellard | asymbol **symbols; |
276 | dc99065b | bellard | /* Number of symbols in array. */
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277 | dc99065b | bellard | int num_symbols;
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278 | dc99065b | bellard | |
279 | dc99065b | bellard | /* For use by the disassembler.
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280 | dc99065b | bellard | The top 16 bits are reserved for public use (and are documented here).
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281 | dc99065b | bellard | The bottom 16 bits are for the internal use of the disassembler. */
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282 | dc99065b | bellard | unsigned long flags; |
283 | dc99065b | bellard | #define INSN_HAS_RELOC 0x80000000 |
284 | dc99065b | bellard | PTR private_data; |
285 | dc99065b | bellard | |
286 | dc99065b | bellard | /* Function used to get bytes to disassemble. MEMADDR is the
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287 | dc99065b | bellard | address of the stuff to be disassembled, MYADDR is the address to
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288 | dc99065b | bellard | put the bytes in, and LENGTH is the number of bytes to read.
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289 | dc99065b | bellard | INFO is a pointer to this struct.
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290 | dc99065b | bellard | Returns an errno value or 0 for success. */
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291 | dc99065b | bellard | int (*read_memory_func)
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292 | dc99065b | bellard | PARAMS ((bfd_vma memaddr, bfd_byte *myaddr, int length,
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293 | dc99065b | bellard | struct disassemble_info *info));
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294 | dc99065b | bellard | |
295 | dc99065b | bellard | /* Function which should be called if we get an error that we can't
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296 | dc99065b | bellard | recover from. STATUS is the errno value from read_memory_func and
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297 | dc99065b | bellard | MEMADDR is the address that we were trying to read. INFO is a
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298 | dc99065b | bellard | pointer to this struct. */
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299 | dc99065b | bellard | void (*memory_error_func)
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300 | dc99065b | bellard | PARAMS ((int status, bfd_vma memaddr, struct disassemble_info *info)); |
301 | dc99065b | bellard | |
302 | dc99065b | bellard | /* Function called to print ADDR. */
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303 | dc99065b | bellard | void (*print_address_func)
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304 | dc99065b | bellard | PARAMS ((bfd_vma addr, struct disassemble_info *info));
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305 | dc99065b | bellard | |
306 | dc99065b | bellard | /* Function called to determine if there is a symbol at the given ADDR.
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307 | dc99065b | bellard | If there is, the function returns 1, otherwise it returns 0.
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308 | dc99065b | bellard | This is used by ports which support an overlay manager where
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309 | dc99065b | bellard | the overlay number is held in the top part of an address. In
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310 | dc99065b | bellard | some circumstances we want to include the overlay number in the
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311 | dc99065b | bellard | address, (normally because there is a symbol associated with
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312 | dc99065b | bellard | that address), but sometimes we want to mask out the overlay bits. */
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313 | dc99065b | bellard | int (* symbol_at_address_func)
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314 | dc99065b | bellard | PARAMS ((bfd_vma addr, struct disassemble_info * info));
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315 | dc99065b | bellard | |
316 | dc99065b | bellard | /* These are for buffer_read_memory. */
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317 | dc99065b | bellard | bfd_byte *buffer; |
318 | dc99065b | bellard | bfd_vma buffer_vma; |
319 | dc99065b | bellard | int buffer_length;
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320 | dc99065b | bellard | |
321 | dc99065b | bellard | /* This variable may be set by the instruction decoder. It suggests
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322 | dc99065b | bellard | the number of bytes objdump should display on a single line. If
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323 | dc99065b | bellard | the instruction decoder sets this, it should always set it to
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324 | dc99065b | bellard | the same value in order to get reasonable looking output. */
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325 | dc99065b | bellard | int bytes_per_line;
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326 | dc99065b | bellard | |
327 | dc99065b | bellard | /* the next two variables control the way objdump displays the raw data */
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328 | dc99065b | bellard | /* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */
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329 | dc99065b | bellard | /* output will look like this:
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330 | dc99065b | bellard | 00: 00000000 00000000
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331 | dc99065b | bellard | with the chunks displayed according to "display_endian". */
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332 | dc99065b | bellard | int bytes_per_chunk;
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333 | dc99065b | bellard | enum bfd_endian display_endian;
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334 | dc99065b | bellard | |
335 | dc99065b | bellard | /* Results from instruction decoders. Not all decoders yet support
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336 | dc99065b | bellard | this information. This info is set each time an instruction is
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337 | dc99065b | bellard | decoded, and is only valid for the last such instruction.
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338 | dc99065b | bellard | |
339 | dc99065b | bellard | To determine whether this decoder supports this information, set
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340 | dc99065b | bellard | insn_info_valid to 0, decode an instruction, then check it. */
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341 | dc99065b | bellard | |
342 | dc99065b | bellard | char insn_info_valid; /* Branch info has been set. */ |
343 | dc99065b | bellard | char branch_delay_insns; /* How many sequential insn's will run before |
344 | dc99065b | bellard | a branch takes effect. (0 = normal) */
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345 | dc99065b | bellard | char data_size; /* Size of data reference in insn, in bytes */ |
346 | dc99065b | bellard | enum dis_insn_type insn_type; /* Type of instruction */ |
347 | dc99065b | bellard | bfd_vma target; /* Target address of branch or dref, if known;
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348 | dc99065b | bellard | zero if unknown. */
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349 | dc99065b | bellard | bfd_vma target2; /* Second target address for dref2 */
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350 | dc99065b | bellard | |
351 | aa0aa4fa | bellard | /* Command line options specific to the target disassembler. */
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352 | aa0aa4fa | bellard | char * disassembler_options;
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353 | aa0aa4fa | bellard | |
354 | dc99065b | bellard | } disassemble_info; |
355 | dc99065b | bellard | |
356 | dc99065b | bellard | |
357 | dc99065b | bellard | /* Standard disassemblers. Disassemble one instruction at the given
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358 | dc99065b | bellard | target address. Return number of bytes processed. */
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359 | dc99065b | bellard | typedef int (*disassembler_ftype) |
360 | dc99065b | bellard | PARAMS((bfd_vma, disassemble_info *)); |
361 | dc99065b | bellard | |
362 | dc99065b | bellard | extern int print_insn_big_mips PARAMS ((bfd_vma, disassemble_info*)); |
363 | dc99065b | bellard | extern int print_insn_little_mips PARAMS ((bfd_vma, disassemble_info*)); |
364 | dc99065b | bellard | extern int print_insn_i386 PARAMS ((bfd_vma, disassemble_info*)); |
365 | dc99065b | bellard | extern int print_insn_m68k PARAMS ((bfd_vma, disassemble_info*)); |
366 | dc99065b | bellard | extern int print_insn_z8001 PARAMS ((bfd_vma, disassemble_info*)); |
367 | dc99065b | bellard | extern int print_insn_z8002 PARAMS ((bfd_vma, disassemble_info*)); |
368 | dc99065b | bellard | extern int print_insn_h8300 PARAMS ((bfd_vma, disassemble_info*)); |
369 | dc99065b | bellard | extern int print_insn_h8300h PARAMS ((bfd_vma, disassemble_info*)); |
370 | dc99065b | bellard | extern int print_insn_h8300s PARAMS ((bfd_vma, disassemble_info*)); |
371 | dc99065b | bellard | extern int print_insn_h8500 PARAMS ((bfd_vma, disassemble_info*)); |
372 | dc99065b | bellard | extern int print_insn_alpha PARAMS ((bfd_vma, disassemble_info*)); |
373 | dc99065b | bellard | extern disassembler_ftype arc_get_disassembler PARAMS ((int, int)); |
374 | aa0aa4fa | bellard | extern int print_insn_arm PARAMS ((bfd_vma, disassemble_info*)); |
375 | dc99065b | bellard | extern int print_insn_sparc PARAMS ((bfd_vma, disassemble_info*)); |
376 | dc99065b | bellard | extern int print_insn_big_a29k PARAMS ((bfd_vma, disassemble_info*)); |
377 | dc99065b | bellard | extern int print_insn_little_a29k PARAMS ((bfd_vma, disassemble_info*)); |
378 | dc99065b | bellard | extern int print_insn_i960 PARAMS ((bfd_vma, disassemble_info*)); |
379 | dc99065b | bellard | extern int print_insn_sh PARAMS ((bfd_vma, disassemble_info*)); |
380 | dc99065b | bellard | extern int print_insn_shl PARAMS ((bfd_vma, disassemble_info*)); |
381 | dc99065b | bellard | extern int print_insn_hppa PARAMS ((bfd_vma, disassemble_info*)); |
382 | dc99065b | bellard | extern int print_insn_m32r PARAMS ((bfd_vma, disassemble_info*)); |
383 | dc99065b | bellard | extern int print_insn_m88k PARAMS ((bfd_vma, disassemble_info*)); |
384 | dc99065b | bellard | extern int print_insn_mn10200 PARAMS ((bfd_vma, disassemble_info*)); |
385 | dc99065b | bellard | extern int print_insn_mn10300 PARAMS ((bfd_vma, disassemble_info*)); |
386 | dc99065b | bellard | extern int print_insn_ns32k PARAMS ((bfd_vma, disassemble_info*)); |
387 | dc99065b | bellard | extern int print_insn_big_powerpc PARAMS ((bfd_vma, disassemble_info*)); |
388 | dc99065b | bellard | extern int print_insn_little_powerpc PARAMS ((bfd_vma, disassemble_info*)); |
389 | dc99065b | bellard | extern int print_insn_rs6000 PARAMS ((bfd_vma, disassemble_info*)); |
390 | dc99065b | bellard | extern int print_insn_w65 PARAMS ((bfd_vma, disassemble_info*)); |
391 | dc99065b | bellard | extern int print_insn_d10v PARAMS ((bfd_vma, disassemble_info*)); |
392 | dc99065b | bellard | extern int print_insn_v850 PARAMS ((bfd_vma, disassemble_info*)); |
393 | dc99065b | bellard | extern int print_insn_tic30 PARAMS ((bfd_vma, disassemble_info*)); |
394 | b9adb4a6 | bellard | extern int print_insn_ppc PARAMS ((bfd_vma, disassemble_info*)); |
395 | eddf68a6 | j_mayer | extern int print_insn_alpha PARAMS ((bfd_vma, disassemble_info*)); |
396 | 8f860bb8 | ths | extern int print_insn_s390 PARAMS ((bfd_vma, disassemble_info*)); |
397 | a25fd137 | ths | extern int print_insn_crisv32 PARAMS ((bfd_vma, disassemble_info*)); |
398 | dc99065b | bellard | |
399 | 43d4145a | bellard | #if 0
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400 | dc99065b | bellard | /* Fetch the disassembler for a given BFD, if that support is available. */
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401 | dc99065b | bellard | extern disassembler_ftype disassembler PARAMS ((bfd *));
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402 | 43d4145a | bellard | #endif
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403 | dc99065b | bellard | |
404 | dc99065b | bellard | |
405 | dc99065b | bellard | /* This block of definitions is for particular callers who read instructions
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406 | dc99065b | bellard | into a buffer before calling the instruction decoder. */
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407 | dc99065b | bellard | |
408 | dc99065b | bellard | /* Here is a function which callers may wish to use for read_memory_func.
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409 | dc99065b | bellard | It gets bytes from a buffer. */
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410 | dc99065b | bellard | extern int buffer_read_memory |
411 | dc99065b | bellard | PARAMS ((bfd_vma, bfd_byte *, int, struct disassemble_info *)); |
412 | dc99065b | bellard | |
413 | dc99065b | bellard | /* This function goes with buffer_read_memory.
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414 | dc99065b | bellard | It prints a message using info->fprintf_func and info->stream. */
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415 | dc99065b | bellard | extern void perror_memory PARAMS ((int, bfd_vma, struct disassemble_info *)); |
416 | dc99065b | bellard | |
417 | dc99065b | bellard | |
418 | dc99065b | bellard | /* Just print the address in hex. This is included for completeness even
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419 | dc99065b | bellard | though both GDB and objdump provide their own (to print symbolic
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420 | dc99065b | bellard | addresses). */
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421 | dc99065b | bellard | extern void generic_print_address |
422 | dc99065b | bellard | PARAMS ((bfd_vma, struct disassemble_info *));
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423 | dc99065b | bellard | |
424 | dc99065b | bellard | /* Always true. */
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425 | dc99065b | bellard | extern int generic_symbol_at_address |
426 | dc99065b | bellard | PARAMS ((bfd_vma, struct disassemble_info *));
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427 | dc99065b | bellard | |
428 | dc99065b | bellard | /* Macro to initialize a disassemble_info struct. This should be called
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429 | dc99065b | bellard | by all applications creating such a struct. */
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430 | dc99065b | bellard | #define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \
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431 | dc99065b | bellard | (INFO).flavour = bfd_target_unknown_flavour, \ |
432 | dc99065b | bellard | (INFO).arch = bfd_arch_unknown, \ |
433 | dc99065b | bellard | (INFO).mach = 0, \
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434 | dc99065b | bellard | (INFO).endian = BFD_ENDIAN_UNKNOWN, \ |
435 | dc99065b | bellard | INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) |
436 | dc99065b | bellard | |
437 | dc99065b | bellard | /* Call this macro to initialize only the internal variables for the
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438 | dc99065b | bellard | disassembler. Architecture dependent things such as byte order, or machine
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439 | dc99065b | bellard | variant are not touched by this macro. This makes things much easier for
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440 | aa1f17c1 | ths | GDB which must initialize these things separately. */
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441 | dc99065b | bellard | |
442 | dc99065b | bellard | #define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \
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443 | dc99065b | bellard | (INFO).fprintf_func = (FPRINTF_FUNC), \ |
444 | dc99065b | bellard | (INFO).stream = (STREAM), \ |
445 | dc99065b | bellard | (INFO).symbols = NULL, \
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446 | dc99065b | bellard | (INFO).num_symbols = 0, \
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447 | 77b087cd | edgar_igl | (INFO).private_data = NULL, \
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448 | dc99065b | bellard | (INFO).buffer = NULL, \
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449 | dc99065b | bellard | (INFO).buffer_vma = 0, \
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450 | dc99065b | bellard | (INFO).buffer_length = 0, \
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451 | dc99065b | bellard | (INFO).read_memory_func = buffer_read_memory, \ |
452 | dc99065b | bellard | (INFO).memory_error_func = perror_memory, \ |
453 | dc99065b | bellard | (INFO).print_address_func = generic_print_address, \ |
454 | dc99065b | bellard | (INFO).symbol_at_address_func = generic_symbol_at_address, \ |
455 | dc99065b | bellard | (INFO).flags = 0, \
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456 | dc99065b | bellard | (INFO).bytes_per_line = 0, \
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457 | dc99065b | bellard | (INFO).bytes_per_chunk = 0, \
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458 | dc99065b | bellard | (INFO).display_endian = BFD_ENDIAN_UNKNOWN, \ |
459 | aa0aa4fa | bellard | (INFO).disassembler_options = NULL, \
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460 | dc99065b | bellard | (INFO).insn_info_valid = 0
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461 | dc99065b | bellard | |
462 | aa0aa4fa | bellard | #define _(x) x
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463 | 48024e4a | bellard | #define ATTRIBUTE_UNUSED __attribute__((unused))
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464 | aa0aa4fa | bellard | |
465 | aa0aa4fa | bellard | /* from libbfd */
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466 | aa0aa4fa | bellard | |
467 | aa0aa4fa | bellard | bfd_vma bfd_getl32 (const bfd_byte *addr);
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468 | aa0aa4fa | bellard | bfd_vma bfd_getb32 (const bfd_byte *addr);
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469 | 6af0bf9c | bellard | bfd_vma bfd_getl16 (const bfd_byte *addr);
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470 | 6af0bf9c | bellard | bfd_vma bfd_getb16 (const bfd_byte *addr);
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471 | aa0aa4fa | bellard | typedef enum bfd_boolean {false, true} boolean; |
472 | 48024e4a | bellard | typedef boolean bfd_boolean;
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473 | aa0aa4fa | bellard | |
474 | dc99065b | bellard | #endif /* ! defined (DIS_ASM_H) */ |