root / hw / etraxfs.c @ c171148c
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1 | 83fa1010 | ths | /*
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2 | 83fa1010 | ths | * QEMU ETRAX System Emulator
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3 | 83fa1010 | ths | *
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4 | 83fa1010 | ths | * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
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5 | 83fa1010 | ths | *
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6 | 83fa1010 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 83fa1010 | ths | * of this software and associated documentation files (the "Software"), to deal
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8 | 83fa1010 | ths | * in the Software without restriction, including without limitation the rights
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9 | 83fa1010 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 83fa1010 | ths | * copies of the Software, and to permit persons to whom the Software is
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11 | 83fa1010 | ths | * furnished to do so, subject to the following conditions:
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12 | 83fa1010 | ths | *
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13 | 83fa1010 | ths | * The above copyright notice and this permission notice shall be included in
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14 | 83fa1010 | ths | * all copies or substantial portions of the Software.
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15 | 83fa1010 | ths | *
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16 | 83fa1010 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 83fa1010 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 83fa1010 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 83fa1010 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 83fa1010 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 83fa1010 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 83fa1010 | ths | * THE SOFTWARE.
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23 | 83fa1010 | ths | */
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24 | 83fa1010 | ths | #include <time.h> |
25 | 83fa1010 | ths | #include <sys/time.h> |
26 | 87ecb68b | pbrook | #include "hw.h" |
27 | 87ecb68b | pbrook | #include "sysemu.h" |
28 | e62b5b13 | edgar_igl | #include "flash.h" |
29 | 87ecb68b | pbrook | #include "boards.h" |
30 | 83fa1010 | ths | |
31 | 83fa1010 | ths | static void main_cpu_reset(void *opaque) |
32 | 83fa1010 | ths | { |
33 | 83fa1010 | ths | CPUState *env = opaque; |
34 | 83fa1010 | ths | cpu_reset(env); |
35 | 83fa1010 | ths | } |
36 | 83fa1010 | ths | |
37 | 83fa1010 | ths | /* Init functions for different blocks. */
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38 | ca87d03b | edgar_igl | extern qemu_irq *etraxfs_pic_init(CPUState *env, target_phys_addr_t base);
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39 | ca87d03b | edgar_igl | void etraxfs_timer_init(CPUState *env, qemu_irq *irqs,
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40 | ca87d03b | edgar_igl | target_phys_addr_t base); |
41 | ca87d03b | edgar_igl | void etraxfs_ser_init(CPUState *env, qemu_irq *irqs, target_phys_addr_t base);
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42 | 83fa1010 | ths | |
43 | 83fa1010 | ths | static
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44 | b881c2c6 | blueswir1 | void bareetraxfs_init (int ram_size, int vga_ram_size, |
45 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState *ds, |
46 | 83fa1010 | ths | const char *kernel_filename, const char *kernel_cmdline, |
47 | 83fa1010 | ths | const char *initrd_filename, const char *cpu_model) |
48 | 83fa1010 | ths | { |
49 | 83fa1010 | ths | CPUState *env; |
50 | e62b5b13 | edgar_igl | qemu_irq *pic; |
51 | 83fa1010 | ths | int kernel_size;
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52 | e62b5b13 | edgar_igl | int flash_size = 0x800000; |
53 | e62b5b13 | edgar_igl | int index;
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54 | e62b5b13 | edgar_igl | ram_addr_t phys_flash; |
55 | e62b5b13 | edgar_igl | ram_addr_t phys_ram; |
56 | 83fa1010 | ths | |
57 | 83fa1010 | ths | /* init CPUs */
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58 | 83fa1010 | ths | if (cpu_model == NULL) { |
59 | 83fa1010 | ths | cpu_model = "crisv32";
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60 | 83fa1010 | ths | } |
61 | aaed909a | bellard | env = cpu_init(cpu_model); |
62 | 83fa1010 | ths | /* register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); */
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63 | 83fa1010 | ths | qemu_register_reset(main_cpu_reset, env); |
64 | 83fa1010 | ths | |
65 | 83fa1010 | ths | /* allocate RAM */
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66 | e62b5b13 | edgar_igl | phys_ram = qemu_ram_alloc(ram_size); |
67 | e62b5b13 | edgar_igl | cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM);
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68 | e62b5b13 | edgar_igl | /* Unached mapping. */
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69 | e62b5b13 | edgar_igl | cpu_register_physical_memory(0xc0000000, ram_size, phys_ram | IO_MEM_RAM);
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70 | e62b5b13 | edgar_igl | |
71 | e62b5b13 | edgar_igl | phys_flash = qemu_ram_alloc(flash_size); |
72 | e62b5b13 | edgar_igl | cpu_register_physical_memory(0,flash_size, IO_MEM_ROM);
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73 | e62b5b13 | edgar_igl | cpu_register_physical_memory(0x80000000, flash_size, IO_MEM_ROM);
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74 | e62b5b13 | edgar_igl | cpu_register_physical_memory(0x04000000, flash_size, IO_MEM_ROM);
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75 | e62b5b13 | edgar_igl | cpu_register_physical_memory(0x84000000, flash_size,
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76 | e62b5b13 | edgar_igl | 0x04000000 | IO_MEM_ROM);
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77 | e62b5b13 | edgar_igl | index = drive_get_index(IF_PFLASH, 0, 0); |
78 | e62b5b13 | edgar_igl | pflash_cfi01_register(0x80000000, flash_size,
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79 | e62b5b13 | edgar_igl | drives_table[index].bdrv, 65536, flash_size >> 16, |
80 | e62b5b13 | edgar_igl | 4, 0x0000, 0x0000, 0x0000, 0x0000); |
81 | e62b5b13 | edgar_igl | index = drive_get_index(IF_PFLASH, 0, 1); |
82 | e62b5b13 | edgar_igl | pflash_cfi01_register(0x84000000, flash_size,
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83 | e62b5b13 | edgar_igl | drives_table[index].bdrv, 65536, flash_size >> 16, |
84 | e62b5b13 | edgar_igl | 4, 0x0000, 0x0000, 0x0000, 0x0000); |
85 | e62b5b13 | edgar_igl | |
86 | e62b5b13 | edgar_igl | pic = etraxfs_pic_init(env, 0xb001c000);
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87 | ca87d03b | edgar_igl | /* 2 timers. */
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88 | ca87d03b | edgar_igl | etraxfs_timer_init(env, pic, 0xb001e000);
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89 | ca87d03b | edgar_igl | etraxfs_timer_init(env, pic, 0xb005e000);
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90 | ca87d03b | edgar_igl | /* 4 serial ports. */
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91 | ca87d03b | edgar_igl | etraxfs_ser_init(env, pic, 0xb0026000);
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92 | ca87d03b | edgar_igl | etraxfs_ser_init(env, pic, 0xb0028000);
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93 | ca87d03b | edgar_igl | etraxfs_ser_init(env, pic, 0xb002a000);
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94 | ca87d03b | edgar_igl | etraxfs_ser_init(env, pic, 0xb002c000);
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95 | 83fa1010 | ths | |
96 | 83fa1010 | ths | kernel_size = load_image(kernel_filename, phys_ram_base + 0x4000);
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97 | 83fa1010 | ths | /* magic for boot. */
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98 | 83fa1010 | ths | env->regs[8] = 0x56902387; |
99 | 83fa1010 | ths | env->regs[9] = 0x40004000 + kernel_size; |
100 | 83fa1010 | ths | env->pc = 0x40004000;
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101 | 83fa1010 | ths | |
102 | 83fa1010 | ths | { |
103 | 83fa1010 | ths | unsigned char *ptr = phys_ram_base + 0x4000; |
104 | 83fa1010 | ths | int i;
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105 | 83fa1010 | ths | for (i = 0; i < 8; i++) |
106 | 83fa1010 | ths | { |
107 | 83fa1010 | ths | printf ("%2.2x ", ptr[i]);
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108 | 83fa1010 | ths | } |
109 | 83fa1010 | ths | printf("\n");
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110 | 83fa1010 | ths | } |
111 | 83fa1010 | ths | |
112 | 83fa1010 | ths | printf ("pc =%x\n", env->pc);
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113 | 83fa1010 | ths | printf ("ram size =%d\n", ram_size);
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114 | 83fa1010 | ths | printf ("kernel name =%s\n", kernel_filename);
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115 | 83fa1010 | ths | printf ("kernel size =%d\n", kernel_size);
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116 | 83fa1010 | ths | printf ("cpu haltd =%d\n", env->halted);
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117 | 83fa1010 | ths | } |
118 | 83fa1010 | ths | |
119 | 83fa1010 | ths | void DMA_run(void) |
120 | 83fa1010 | ths | { |
121 | 83fa1010 | ths | } |
122 | 83fa1010 | ths | |
123 | 83fa1010 | ths | QEMUMachine bareetraxfs_machine = { |
124 | 83fa1010 | ths | "bareetraxfs",
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125 | 83fa1010 | ths | "Bare ETRAX FS board",
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126 | 83fa1010 | ths | bareetraxfs_init, |
127 | 83fa1010 | ths | }; |