root / hw / pxa2xx_gpio.c @ c171148c
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1 | c1713132 | balrog | /*
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2 | c1713132 | balrog | * Intel XScale PXA255/270 GPIO controller emulation.
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3 | c1713132 | balrog | *
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4 | c1713132 | balrog | * Copyright (c) 2006 Openedhand Ltd.
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5 | c1713132 | balrog | * Written by Andrzej Zaborowski <balrog@zabor.org>
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6 | c1713132 | balrog | *
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7 | c1713132 | balrog | * This code is licensed under the GPL.
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8 | c1713132 | balrog | */
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9 | c1713132 | balrog | |
10 | 87ecb68b | pbrook | #include "hw.h" |
11 | 87ecb68b | pbrook | #include "pxa.h" |
12 | c1713132 | balrog | |
13 | c1713132 | balrog | #define PXA2XX_GPIO_BANKS 4 |
14 | c1713132 | balrog | |
15 | c1713132 | balrog | struct pxa2xx_gpio_info_s {
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16 | c1713132 | balrog | target_phys_addr_t base; |
17 | c1713132 | balrog | qemu_irq *pic; |
18 | c1713132 | balrog | int lines;
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19 | c1713132 | balrog | CPUState *cpu_env; |
20 | 38641a52 | balrog | qemu_irq *in; |
21 | c1713132 | balrog | |
22 | c1713132 | balrog | /* XXX: GNU C vectors are more suitable */
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23 | c1713132 | balrog | uint32_t ilevel[PXA2XX_GPIO_BANKS]; |
24 | c1713132 | balrog | uint32_t olevel[PXA2XX_GPIO_BANKS]; |
25 | c1713132 | balrog | uint32_t dir[PXA2XX_GPIO_BANKS]; |
26 | c1713132 | balrog | uint32_t rising[PXA2XX_GPIO_BANKS]; |
27 | c1713132 | balrog | uint32_t falling[PXA2XX_GPIO_BANKS]; |
28 | c1713132 | balrog | uint32_t status[PXA2XX_GPIO_BANKS]; |
29 | 2b76bdc9 | balrog | uint32_t gpsr[PXA2XX_GPIO_BANKS]; |
30 | c1713132 | balrog | uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
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31 | c1713132 | balrog | |
32 | c1713132 | balrog | uint32_t prev_level[PXA2XX_GPIO_BANKS]; |
33 | 38641a52 | balrog | qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
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34 | 38641a52 | balrog | qemu_irq read_notify; |
35 | c1713132 | balrog | }; |
36 | c1713132 | balrog | |
37 | c1713132 | balrog | static struct { |
38 | c1713132 | balrog | enum {
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39 | c1713132 | balrog | GPIO_NONE, |
40 | c1713132 | balrog | GPLR, |
41 | c1713132 | balrog | GPSR, |
42 | c1713132 | balrog | GPCR, |
43 | c1713132 | balrog | GPDR, |
44 | c1713132 | balrog | GRER, |
45 | c1713132 | balrog | GFER, |
46 | c1713132 | balrog | GEDR, |
47 | c1713132 | balrog | GAFR_L, |
48 | c1713132 | balrog | GAFR_U, |
49 | c1713132 | balrog | } reg; |
50 | c1713132 | balrog | int bank;
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51 | c1713132 | balrog | } pxa2xx_gpio_regs[0x200] = {
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52 | c1713132 | balrog | [0 ... 0x1ff] = { GPIO_NONE, 0 }, |
53 | c1713132 | balrog | #define PXA2XX_REG(reg, a0, a1, a2, a3) \
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54 | 5fafdf24 | ths | [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 }, |
55 | c1713132 | balrog | |
56 | c1713132 | balrog | PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100) |
57 | c1713132 | balrog | PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118) |
58 | c1713132 | balrog | PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124) |
59 | c1713132 | balrog | PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c) |
60 | c1713132 | balrog | PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130) |
61 | c1713132 | balrog | PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c) |
62 | c1713132 | balrog | PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148) |
63 | c1713132 | balrog | PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c) |
64 | c1713132 | balrog | PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070) |
65 | c1713132 | balrog | }; |
66 | c1713132 | balrog | |
67 | c1713132 | balrog | static void pxa2xx_gpio_irq_update(struct pxa2xx_gpio_info_s *s) |
68 | c1713132 | balrog | { |
69 | c1713132 | balrog | if (s->status[0] & (1 << 0)) |
70 | c1713132 | balrog | qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_0]); |
71 | c1713132 | balrog | else
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72 | c1713132 | balrog | qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_0]); |
73 | c1713132 | balrog | |
74 | c1713132 | balrog | if (s->status[0] & (1 << 1)) |
75 | c1713132 | balrog | qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_1]); |
76 | c1713132 | balrog | else
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77 | c1713132 | balrog | qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_1]); |
78 | c1713132 | balrog | |
79 | c1713132 | balrog | if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3]) |
80 | c1713132 | balrog | qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_X]); |
81 | c1713132 | balrog | else
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82 | c1713132 | balrog | qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_X]); |
83 | c1713132 | balrog | } |
84 | c1713132 | balrog | |
85 | c1713132 | balrog | /* Bitmap of pins used as standby and sleep wake-up sources. */
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86 | 38641a52 | balrog | static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = { |
87 | c1713132 | balrog | 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f, |
88 | c1713132 | balrog | }; |
89 | c1713132 | balrog | |
90 | 38641a52 | balrog | static void pxa2xx_gpio_set(void *opaque, int line, int level) |
91 | c1713132 | balrog | { |
92 | 38641a52 | balrog | struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque; |
93 | c1713132 | balrog | int bank;
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94 | c1713132 | balrog | uint32_t mask; |
95 | c1713132 | balrog | |
96 | c1713132 | balrog | if (line >= s->lines) {
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97 | c1713132 | balrog | printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
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98 | c1713132 | balrog | return;
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99 | c1713132 | balrog | } |
100 | c1713132 | balrog | |
101 | c1713132 | balrog | bank = line >> 5;
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102 | c1713132 | balrog | mask = 1 << (line & 31); |
103 | c1713132 | balrog | |
104 | c1713132 | balrog | if (level) {
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105 | c1713132 | balrog | s->status[bank] |= s->rising[bank] & mask & |
106 | c1713132 | balrog | ~s->ilevel[bank] & ~s->dir[bank]; |
107 | c1713132 | balrog | s->ilevel[bank] |= mask; |
108 | c1713132 | balrog | } else {
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109 | c1713132 | balrog | s->status[bank] |= s->falling[bank] & mask & |
110 | c1713132 | balrog | s->ilevel[bank] & ~s->dir[bank]; |
111 | c1713132 | balrog | s->ilevel[bank] &= ~mask; |
112 | c1713132 | balrog | } |
113 | c1713132 | balrog | |
114 | c1713132 | balrog | if (s->status[bank] & mask)
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115 | c1713132 | balrog | pxa2xx_gpio_irq_update(s); |
116 | c1713132 | balrog | |
117 | c1713132 | balrog | /* Wake-up GPIOs */
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118 | c1713132 | balrog | if (s->cpu_env->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank]))
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119 | c1713132 | balrog | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB); |
120 | c1713132 | balrog | } |
121 | c1713132 | balrog | |
122 | c1713132 | balrog | static void pxa2xx_gpio_handler_update(struct pxa2xx_gpio_info_s *s) { |
123 | c1713132 | balrog | uint32_t level, diff; |
124 | c1713132 | balrog | int i, bit, line;
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125 | c1713132 | balrog | for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) { |
126 | c1713132 | balrog | level = s->olevel[i] & s->dir[i]; |
127 | c1713132 | balrog | |
128 | c1713132 | balrog | for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) { |
129 | c1713132 | balrog | bit = ffs(diff) - 1;
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130 | c1713132 | balrog | line = bit + 32 * i;
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131 | 38641a52 | balrog | qemu_set_irq(s->handler[line], (level >> bit) & 1);
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132 | c1713132 | balrog | } |
133 | c1713132 | balrog | |
134 | c1713132 | balrog | s->prev_level[i] = level; |
135 | c1713132 | balrog | } |
136 | c1713132 | balrog | } |
137 | c1713132 | balrog | |
138 | c1713132 | balrog | static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset) |
139 | c1713132 | balrog | { |
140 | c1713132 | balrog | struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque; |
141 | c1713132 | balrog | uint32_t ret; |
142 | c1713132 | balrog | int bank;
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143 | c1713132 | balrog | offset -= s->base; |
144 | c1713132 | balrog | if (offset >= 0x200) |
145 | c1713132 | balrog | return 0; |
146 | c1713132 | balrog | |
147 | c1713132 | balrog | bank = pxa2xx_gpio_regs[offset].bank; |
148 | c1713132 | balrog | switch (pxa2xx_gpio_regs[offset].reg) {
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149 | c1713132 | balrog | case GPDR: /* GPIO Pin-Direction registers */ |
150 | c1713132 | balrog | return s->dir[bank];
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151 | c1713132 | balrog | |
152 | 2b76bdc9 | balrog | case GPSR: /* GPIO Pin-Output Set registers */ |
153 | 2b76bdc9 | balrog | printf("%s: Read from a write-only register " REG_FMT "\n", |
154 | 2b76bdc9 | balrog | __FUNCTION__, offset); |
155 | 2b76bdc9 | balrog | return s->gpsr[bank]; /* Return last written value. */ |
156 | 2b76bdc9 | balrog | |
157 | e1dad5a6 | balrog | case GPCR: /* GPIO Pin-Output Clear registers */ |
158 | e1dad5a6 | balrog | printf("%s: Read from a write-only register " REG_FMT "\n", |
159 | e1dad5a6 | balrog | __FUNCTION__, offset); |
160 | e1dad5a6 | balrog | return 31337; /* Specified as unpredictable in the docs. */ |
161 | e1dad5a6 | balrog | |
162 | c1713132 | balrog | case GRER: /* GPIO Rising-Edge Detect Enable registers */ |
163 | c1713132 | balrog | return s->rising[bank];
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164 | c1713132 | balrog | |
165 | c1713132 | balrog | case GFER: /* GPIO Falling-Edge Detect Enable registers */ |
166 | c1713132 | balrog | return s->falling[bank];
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167 | c1713132 | balrog | |
168 | c1713132 | balrog | case GAFR_L: /* GPIO Alternate Function registers */ |
169 | c1713132 | balrog | return s->gafr[bank * 2]; |
170 | c1713132 | balrog | |
171 | c1713132 | balrog | case GAFR_U: /* GPIO Alternate Function registers */ |
172 | c1713132 | balrog | return s->gafr[bank * 2 + 1]; |
173 | c1713132 | balrog | |
174 | c1713132 | balrog | case GPLR: /* GPIO Pin-Level registers */ |
175 | c1713132 | balrog | ret = (s->olevel[bank] & s->dir[bank]) | |
176 | c1713132 | balrog | (s->ilevel[bank] & ~s->dir[bank]); |
177 | 38641a52 | balrog | qemu_irq_raise(s->read_notify); |
178 | c1713132 | balrog | return ret;
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179 | c1713132 | balrog | |
180 | c1713132 | balrog | case GEDR: /* GPIO Edge Detect Status registers */ |
181 | c1713132 | balrog | return s->status[bank];
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182 | c1713132 | balrog | |
183 | c1713132 | balrog | default:
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184 | c1713132 | balrog | cpu_abort(cpu_single_env, |
185 | c1713132 | balrog | "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); |
186 | c1713132 | balrog | } |
187 | c1713132 | balrog | |
188 | c1713132 | balrog | return 0; |
189 | c1713132 | balrog | } |
190 | c1713132 | balrog | |
191 | c1713132 | balrog | static void pxa2xx_gpio_write(void *opaque, |
192 | c1713132 | balrog | target_phys_addr_t offset, uint32_t value) |
193 | c1713132 | balrog | { |
194 | c1713132 | balrog | struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque; |
195 | c1713132 | balrog | int bank;
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196 | c1713132 | balrog | offset -= s->base; |
197 | c1713132 | balrog | if (offset >= 0x200) |
198 | c1713132 | balrog | return;
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199 | c1713132 | balrog | |
200 | c1713132 | balrog | bank = pxa2xx_gpio_regs[offset].bank; |
201 | c1713132 | balrog | switch (pxa2xx_gpio_regs[offset].reg) {
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202 | c1713132 | balrog | case GPDR: /* GPIO Pin-Direction registers */ |
203 | c1713132 | balrog | s->dir[bank] = value; |
204 | c1713132 | balrog | pxa2xx_gpio_handler_update(s); |
205 | c1713132 | balrog | break;
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206 | c1713132 | balrog | |
207 | c1713132 | balrog | case GPSR: /* GPIO Pin-Output Set registers */ |
208 | c1713132 | balrog | s->olevel[bank] |= value; |
209 | c1713132 | balrog | pxa2xx_gpio_handler_update(s); |
210 | 2b76bdc9 | balrog | s->gpsr[bank] = value; |
211 | c1713132 | balrog | break;
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212 | c1713132 | balrog | |
213 | c1713132 | balrog | case GPCR: /* GPIO Pin-Output Clear registers */ |
214 | c1713132 | balrog | s->olevel[bank] &= ~value; |
215 | c1713132 | balrog | pxa2xx_gpio_handler_update(s); |
216 | c1713132 | balrog | break;
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217 | c1713132 | balrog | |
218 | c1713132 | balrog | case GRER: /* GPIO Rising-Edge Detect Enable registers */ |
219 | c1713132 | balrog | s->rising[bank] = value; |
220 | c1713132 | balrog | break;
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221 | c1713132 | balrog | |
222 | c1713132 | balrog | case GFER: /* GPIO Falling-Edge Detect Enable registers */ |
223 | c1713132 | balrog | s->falling[bank] = value; |
224 | c1713132 | balrog | break;
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225 | c1713132 | balrog | |
226 | c1713132 | balrog | case GAFR_L: /* GPIO Alternate Function registers */ |
227 | c1713132 | balrog | s->gafr[bank * 2] = value;
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228 | c1713132 | balrog | break;
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229 | c1713132 | balrog | |
230 | c1713132 | balrog | case GAFR_U: /* GPIO Alternate Function registers */ |
231 | c1713132 | balrog | s->gafr[bank * 2 + 1] = value; |
232 | c1713132 | balrog | break;
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233 | c1713132 | balrog | |
234 | c1713132 | balrog | case GEDR: /* GPIO Edge Detect Status registers */ |
235 | c1713132 | balrog | s->status[bank] &= ~value; |
236 | c1713132 | balrog | pxa2xx_gpio_irq_update(s); |
237 | c1713132 | balrog | break;
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238 | c1713132 | balrog | |
239 | c1713132 | balrog | default:
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240 | c1713132 | balrog | cpu_abort(cpu_single_env, |
241 | c1713132 | balrog | "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); |
242 | c1713132 | balrog | } |
243 | c1713132 | balrog | } |
244 | c1713132 | balrog | |
245 | c1713132 | balrog | static CPUReadMemoryFunc *pxa2xx_gpio_readfn[] = {
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246 | c1713132 | balrog | pxa2xx_gpio_read, |
247 | c1713132 | balrog | pxa2xx_gpio_read, |
248 | c1713132 | balrog | pxa2xx_gpio_read |
249 | c1713132 | balrog | }; |
250 | c1713132 | balrog | |
251 | c1713132 | balrog | static CPUWriteMemoryFunc *pxa2xx_gpio_writefn[] = {
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252 | c1713132 | balrog | pxa2xx_gpio_write, |
253 | c1713132 | balrog | pxa2xx_gpio_write, |
254 | c1713132 | balrog | pxa2xx_gpio_write |
255 | c1713132 | balrog | }; |
256 | c1713132 | balrog | |
257 | aa941b94 | balrog | static void pxa2xx_gpio_save(QEMUFile *f, void *opaque) |
258 | aa941b94 | balrog | { |
259 | aa941b94 | balrog | struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque; |
260 | aa941b94 | balrog | int i;
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261 | aa941b94 | balrog | |
262 | aa941b94 | balrog | qemu_put_be32(f, s->lines); |
263 | aa941b94 | balrog | |
264 | aa941b94 | balrog | for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) { |
265 | aa941b94 | balrog | qemu_put_be32s(f, &s->ilevel[i]); |
266 | aa941b94 | balrog | qemu_put_be32s(f, &s->olevel[i]); |
267 | aa941b94 | balrog | qemu_put_be32s(f, &s->dir[i]); |
268 | aa941b94 | balrog | qemu_put_be32s(f, &s->rising[i]); |
269 | aa941b94 | balrog | qemu_put_be32s(f, &s->falling[i]); |
270 | aa941b94 | balrog | qemu_put_be32s(f, &s->status[i]); |
271 | aa941b94 | balrog | qemu_put_be32s(f, &s->gafr[i * 2 + 0]); |
272 | aa941b94 | balrog | qemu_put_be32s(f, &s->gafr[i * 2 + 1]); |
273 | aa941b94 | balrog | |
274 | aa941b94 | balrog | qemu_put_be32s(f, &s->prev_level[i]); |
275 | aa941b94 | balrog | } |
276 | aa941b94 | balrog | } |
277 | aa941b94 | balrog | |
278 | aa941b94 | balrog | static int pxa2xx_gpio_load(QEMUFile *f, void *opaque, int version_id) |
279 | aa941b94 | balrog | { |
280 | aa941b94 | balrog | struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque; |
281 | aa941b94 | balrog | int i;
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282 | aa941b94 | balrog | |
283 | aa941b94 | balrog | if (qemu_get_be32(f) != s->lines)
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284 | aa941b94 | balrog | return -EINVAL;
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285 | aa941b94 | balrog | |
286 | aa941b94 | balrog | for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) { |
287 | aa941b94 | balrog | qemu_get_be32s(f, &s->ilevel[i]); |
288 | aa941b94 | balrog | qemu_get_be32s(f, &s->olevel[i]); |
289 | aa941b94 | balrog | qemu_get_be32s(f, &s->dir[i]); |
290 | aa941b94 | balrog | qemu_get_be32s(f, &s->rising[i]); |
291 | aa941b94 | balrog | qemu_get_be32s(f, &s->falling[i]); |
292 | aa941b94 | balrog | qemu_get_be32s(f, &s->status[i]); |
293 | aa941b94 | balrog | qemu_get_be32s(f, &s->gafr[i * 2 + 0]); |
294 | aa941b94 | balrog | qemu_get_be32s(f, &s->gafr[i * 2 + 1]); |
295 | aa941b94 | balrog | |
296 | aa941b94 | balrog | qemu_get_be32s(f, &s->prev_level[i]); |
297 | aa941b94 | balrog | } |
298 | aa941b94 | balrog | |
299 | aa941b94 | balrog | return 0; |
300 | aa941b94 | balrog | } |
301 | aa941b94 | balrog | |
302 | c1713132 | balrog | struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
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303 | c1713132 | balrog | CPUState *env, qemu_irq *pic, int lines)
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304 | c1713132 | balrog | { |
305 | c1713132 | balrog | int iomemtype;
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306 | c1713132 | balrog | struct pxa2xx_gpio_info_s *s;
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307 | c1713132 | balrog | |
308 | c1713132 | balrog | s = (struct pxa2xx_gpio_info_s *)
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309 | c1713132 | balrog | qemu_mallocz(sizeof(struct pxa2xx_gpio_info_s)); |
310 | c1713132 | balrog | memset(s, 0, sizeof(struct pxa2xx_gpio_info_s)); |
311 | c1713132 | balrog | s->base = base; |
312 | c1713132 | balrog | s->pic = pic; |
313 | c1713132 | balrog | s->lines = lines; |
314 | c1713132 | balrog | s->cpu_env = env; |
315 | 38641a52 | balrog | s->in = qemu_allocate_irqs(pxa2xx_gpio_set, s, lines); |
316 | c1713132 | balrog | |
317 | c1713132 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_gpio_readfn,
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318 | c1713132 | balrog | pxa2xx_gpio_writefn, s); |
319 | 187337f8 | pbrook | cpu_register_physical_memory(base, 0x00001000, iomemtype);
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320 | c1713132 | balrog | |
321 | aa941b94 | balrog | register_savevm("pxa2xx_gpio", 0, 0, |
322 | aa941b94 | balrog | pxa2xx_gpio_save, pxa2xx_gpio_load, s); |
323 | aa941b94 | balrog | |
324 | c1713132 | balrog | return s;
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325 | c1713132 | balrog | } |
326 | c1713132 | balrog | |
327 | 38641a52 | balrog | qemu_irq *pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s *s)
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328 | 38641a52 | balrog | { |
329 | 38641a52 | balrog | return s->in;
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330 | 38641a52 | balrog | } |
331 | 38641a52 | balrog | |
332 | 38641a52 | balrog | void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s, |
333 | 38641a52 | balrog | int line, qemu_irq handler)
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334 | 38641a52 | balrog | { |
335 | c1713132 | balrog | if (line >= s->lines) {
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336 | c1713132 | balrog | printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
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337 | c1713132 | balrog | return;
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338 | c1713132 | balrog | } |
339 | c1713132 | balrog | |
340 | 38641a52 | balrog | s->handler[line] = handler; |
341 | c1713132 | balrog | } |
342 | c1713132 | balrog | |
343 | c1713132 | balrog | /*
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344 | c1713132 | balrog | * Registers a callback to notify on GPLR reads. This normally
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345 | c1713132 | balrog | * shouldn't be needed but it is used for the hack on Spitz machines.
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346 | c1713132 | balrog | */
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347 | 38641a52 | balrog | void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, qemu_irq handler) |
348 | 38641a52 | balrog | { |
349 | c1713132 | balrog | s->read_notify = handler; |
350 | c1713132 | balrog | } |