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/*
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* Software MMU support
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#if DATA_SIZE == 8 |
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#define SUFFIX q
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#define USUFFIX q
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#define DATA_TYPE uint64_t
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#elif DATA_SIZE == 4 |
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#define SUFFIX l
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#define USUFFIX l
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#define DATA_TYPE uint32_t
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#elif DATA_SIZE == 2 |
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#define SUFFIX w
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#define USUFFIX uw
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#define DATA_TYPE uint16_t
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#define DATA_STYPE int16_t
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#elif DATA_SIZE == 1 |
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#define SUFFIX b
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#define USUFFIX ub
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#define DATA_TYPE uint8_t
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#define DATA_STYPE int8_t
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#else
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#error unsupported data size
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#endif
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#if ACCESS_TYPE == 0 |
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#define CPU_MEM_INDEX 0 |
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#define MMUSUFFIX _mmu
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#elif ACCESS_TYPE == 1 |
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#define CPU_MEM_INDEX 1 |
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#define MMUSUFFIX _mmu
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#elif ACCESS_TYPE == 2 |
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#ifdef TARGET_I386
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#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3) |
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#elif defined (TARGET_PPC)
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#define CPU_MEM_INDEX (msr_pr)
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#elif defined (TARGET_MIPS)
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#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
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#elif defined (TARGET_SPARC)
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#define CPU_MEM_INDEX ((env->psrs) == 0) |
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#elif defined (TARGET_ARM)
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#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
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#elif defined (TARGET_SH4)
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#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0) |
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#elif defined (TARGET_ALPHA)
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#define CPU_MEM_INDEX ((env->ps >> 3) & 3) |
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#else
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#error unsupported CPU
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#endif
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#define MMUSUFFIX _mmu
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#elif ACCESS_TYPE == 3 |
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#ifdef TARGET_I386
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#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3) |
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#elif defined (TARGET_PPC)
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#define CPU_MEM_INDEX (msr_pr)
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#elif defined (TARGET_MIPS)
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#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
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#elif defined (TARGET_SPARC)
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#define CPU_MEM_INDEX ((env->psrs) == 0) |
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#elif defined (TARGET_ARM)
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#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
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#elif defined (TARGET_SH4)
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#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0) |
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#elif defined (TARGET_ALPHA)
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#define CPU_MEM_INDEX ((env->ps >> 3) & 3) |
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#else
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#error unsupported CPU
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#endif
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#define MMUSUFFIX _cmmu
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#else
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#error invalid ACCESS_TYPE
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#endif
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#if DATA_SIZE == 8 |
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#define RES_TYPE uint64_t
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#else
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#define RES_TYPE int |
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#endif
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#if ACCESS_TYPE == 3 |
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#define ADDR_READ addr_code
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#else
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#define ADDR_READ addr_read
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#endif
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DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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int is_user);
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void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int is_user); |
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#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \ |
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(ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU)
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#define CPU_TLB_ENTRY_BITS 4 |
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static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr) |
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{
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int res;
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asm volatile ("movl %1, %%edx\n" |
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"movl %1, %%eax\n"
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"shrl %3, %%edx\n"
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"andl %4, %%eax\n"
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"andl %2, %%edx\n"
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"leal %5(%%edx, %%ebp), %%edx\n"
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"cmpl (%%edx), %%eax\n"
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"movl %1, %%eax\n"
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"je 1f\n"
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"pushl %6\n"
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"call %7\n"
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"popl %%edx\n"
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"movl %%eax, %0\n"
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"jmp 2f\n"
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"1:\n"
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"addl 12(%%edx), %%eax\n"
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#if DATA_SIZE == 1 |
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"movzbl (%%eax), %0\n"
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#elif DATA_SIZE == 2 |
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"movzwl (%%eax), %0\n"
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#elif DATA_SIZE == 4 |
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"movl (%%eax), %0\n"
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#else
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#error unsupported size
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#endif
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"2:\n"
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: "=r" (res)
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: "r" (ptr),
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"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS), |
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"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
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"i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)), |
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"m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)), |
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"i" (CPU_MEM_INDEX),
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"m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
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: "%eax", "%ecx", "%edx", "memory", "cc"); |
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return res;
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} |
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#if DATA_SIZE <= 2 |
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static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr) |
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{
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int res;
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asm volatile ("movl %1, %%edx\n" |
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"movl %1, %%eax\n"
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"shrl %3, %%edx\n"
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"andl %4, %%eax\n"
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"andl %2, %%edx\n"
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"leal %5(%%edx, %%ebp), %%edx\n"
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"cmpl (%%edx), %%eax\n"
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"movl %1, %%eax\n"
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"je 1f\n"
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"pushl %6\n"
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"call %7\n"
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"popl %%edx\n"
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#if DATA_SIZE == 1 |
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"movsbl %%al, %0\n"
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#elif DATA_SIZE == 2 |
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"movswl %%ax, %0\n"
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#else
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#error unsupported size
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#endif
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"jmp 2f\n"
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"1:\n"
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"addl 12(%%edx), %%eax\n"
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#if DATA_SIZE == 1 |
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"movsbl (%%eax), %0\n"
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#elif DATA_SIZE == 2 |
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"movswl (%%eax), %0\n"
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#else
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#error unsupported size
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#endif
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"2:\n"
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: "=r" (res)
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: "r" (ptr),
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"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS), |
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"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
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"i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)), |
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"m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)), |
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"i" (CPU_MEM_INDEX),
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"m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
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: "%eax", "%ecx", "%edx", "memory", "cc"); |
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return res;
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} |
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#endif
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static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v) |
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{
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asm volatile ("movl %0, %%edx\n" |
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"movl %0, %%eax\n"
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"shrl %3, %%edx\n"
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"andl %4, %%eax\n"
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"andl %2, %%edx\n"
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"leal %5(%%edx, %%ebp), %%edx\n"
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"cmpl (%%edx), %%eax\n"
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"movl %0, %%eax\n"
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"je 1f\n"
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#if DATA_SIZE == 1 |
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"movzbl %b1, %%edx\n"
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#elif DATA_SIZE == 2 |
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"movzwl %w1, %%edx\n"
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#elif DATA_SIZE == 4 |
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"movl %1, %%edx\n"
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#else
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#error unsupported size
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#endif
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"pushl %6\n"
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"call %7\n"
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"popl %%eax\n"
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"jmp 2f\n"
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"1:\n"
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"addl 8(%%edx), %%eax\n"
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#if DATA_SIZE == 1 |
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"movb %b1, (%%eax)\n"
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#elif DATA_SIZE == 2 |
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"movw %w1, (%%eax)\n"
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#elif DATA_SIZE == 4 |
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"movl %1, (%%eax)\n"
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#else
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#error unsupported size
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#endif
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"2:\n"
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: |
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: "r" (ptr),
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/* NOTE: 'q' would be needed as constraint, but we could not use it
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with T1 ! */
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"r" (v),
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"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS), |
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"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
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"i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)), |
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"m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_write)), |
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"i" (CPU_MEM_INDEX),
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"m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
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: "%eax", "%ecx", "%edx", "memory", "cc"); |
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} |
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#else
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/* generic load/store macros */
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static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr) |
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{
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int index;
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RES_TYPE res; |
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target_ulong addr; |
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unsigned long physaddr; |
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int is_user;
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addr = ptr; |
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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is_user = CPU_MEM_INDEX; |
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if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ !=
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(addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) { |
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res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user); |
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} else {
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physaddr = addr + env->tlb_table[is_user][index].addend; |
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res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr); |
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} |
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return res;
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} |
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#if DATA_SIZE <= 2 |
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static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr) |
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{
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int res, index;
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target_ulong addr; |
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unsigned long physaddr; |
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int is_user;
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addr = ptr; |
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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is_user = CPU_MEM_INDEX; |
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if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ !=
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(addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) { |
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res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user); |
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} else {
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physaddr = addr + env->tlb_table[is_user][index].addend; |
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res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr); |
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} |
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return res;
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} |
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#endif
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|
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#if ACCESS_TYPE != 3 |
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/* generic store macro */
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static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v) |
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{
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int index;
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target_ulong addr; |
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unsigned long physaddr; |
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int is_user;
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addr = ptr; |
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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is_user = CPU_MEM_INDEX; |
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if (__builtin_expect(env->tlb_table[is_user][index].addr_write !=
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(addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) { |
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glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user); |
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} else {
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physaddr = addr + env->tlb_table[is_user][index].addend; |
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glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v); |
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} |
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} |
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#endif /* ACCESS_TYPE != 3 */ |
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#endif /* !asm */ |
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#if ACCESS_TYPE != 3 |
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#if DATA_SIZE == 8 |
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static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr) |
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{
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union {
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float64 d; |
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uint64_t i; |
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} u; |
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u.i = glue(ldq, MEMSUFFIX)(ptr); |
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return u.d;
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} |
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static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v) |
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{
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union {
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float64 d; |
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uint64_t i; |
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} u; |
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u.d = v; |
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glue(stq, MEMSUFFIX)(ptr, u.i); |
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} |
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#endif /* DATA_SIZE == 8 */ |
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|
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#if DATA_SIZE == 4 |
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static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr) |
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{
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union {
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float32 f; |
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uint32_t i; |
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} u; |
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u.i = glue(ldl, MEMSUFFIX)(ptr); |
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return u.f;
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} |
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static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v) |
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{
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union {
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float32 f; |
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uint32_t i; |
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} u; |
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u.f = v; |
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glue(stl, MEMSUFFIX)(ptr, u.i); |
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} |
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#endif /* DATA_SIZE == 4 */ |
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|
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#endif /* ACCESS_TYPE != 3 */ |
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#undef RES_TYPE
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#undef DATA_TYPE
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#undef DATA_STYPE
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#undef SUFFIX
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#undef USUFFIX
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#undef DATA_SIZE
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#undef CPU_MEM_INDEX
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#undef MMUSUFFIX
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#undef ADDR_READ
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