Revision c190ea07 hw/apb_pci.c
| b/hw/apb_pci.c | ||
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PCIBus *pci_apb_init(target_phys_addr_t special_base, |
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target_phys_addr_t mem_base, |
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qemu_irq *pic) |
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qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
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{
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APBState *s; |
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PCIDevice *d; |
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int pci_mem_config, pci_mem_data, apb_config, pci_ioport; |
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PCIBus *secondary; |
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s = qemu_mallocz(sizeof(APBState)); |
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/* Ultrasparc PBM main bus */ |
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d->config[0x0E] = 0x00; // header_type |
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/* APB secondary busses */ |
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secondary = pci_bridge_init(s->bus, 8, 0x108e5000, pci_apb_map_irq,
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"Advanced PCI Bus secondary bridge 1");
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pci_bridge_init(s->bus, 9, 0x108e5000, pci_apb_map_irq, |
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"Advanced PCI Bus secondary bridge 2"); |
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*bus2 = pci_bridge_init(s->bus, 8, 0x108e5000, pci_apb_map_irq,
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"Advanced PCI Bus secondary bridge 1"); |
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*bus3 = pci_bridge_init(s->bus, 9, 0x108e5000, pci_apb_map_irq,
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"Advanced PCI Bus secondary bridge 2");
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return s->bus; |
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} |
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