Revision c190ea07 hw/sun4u.c
| b/hw/sun4u.c | ||
|---|---|---|
| 344 | 344 |
|
| 345 | 345 |
static fdctrl_t *floppy_controller; |
| 346 | 346 |
|
| 347 |
static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num, |
|
| 348 |
uint32_t addr, uint32_t size, int type) |
|
| 349 |
{
|
|
| 350 |
DPRINTF("Mapping region %d registers at %08x\n", region_num, addr);
|
|
| 351 |
switch (region_num) {
|
|
| 352 |
case 0: |
|
| 353 |
isa_mmio_init(addr, 0x1000000); |
|
| 354 |
break; |
|
| 355 |
case 1: |
|
| 356 |
isa_mmio_init(addr, 0x800000); |
|
| 357 |
break; |
|
| 358 |
} |
|
| 359 |
} |
|
| 360 |
|
|
| 361 |
/* EBUS (Eight bit bus) bridge */ |
|
| 362 |
static void |
|
| 363 |
pci_ebus_init(PCIBus *bus, int devfn) |
|
| 364 |
{
|
|
| 365 |
PCIDevice *s; |
|
| 366 |
|
|
| 367 |
s = pci_register_device(bus, "EBUS", sizeof(*s), devfn, NULL, NULL); |
|
| 368 |
s->config[0x00] = 0x8e; // vendor_id : Sun |
|
| 369 |
s->config[0x01] = 0x10; |
|
| 370 |
s->config[0x02] = 0x00; // device_id |
|
| 371 |
s->config[0x03] = 0x10; |
|
| 372 |
s->config[0x04] = 0x06; // command = bus master, pci mem |
|
| 373 |
s->config[0x05] = 0x00; |
|
| 374 |
s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
|
| 375 |
s->config[0x07] = 0x03; // status = medium devsel |
|
| 376 |
s->config[0x08] = 0x01; // revision |
|
| 377 |
s->config[0x09] = 0x00; // programming i/f |
|
| 378 |
s->config[0x0A] = 0x80; // class_sub = misc bridge |
|
| 379 |
s->config[0x0B] = 0x06; // class_base = PCI_bridge |
|
| 380 |
s->config[0x0D] = 0x0a; // latency_timer |
|
| 381 |
s->config[0x0E] = 0x00; // header_type |
|
| 382 |
|
|
| 383 |
pci_register_io_region(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM, |
|
| 384 |
ebus_mmio_mapfunc); |
|
| 385 |
pci_register_io_region(s, 1, 0x800000, PCI_ADDRESS_SPACE_MEM, |
|
| 386 |
ebus_mmio_mapfunc); |
|
| 387 |
} |
|
| 388 |
|
|
| 347 | 389 |
static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size, |
| 348 | 390 |
const char *boot_devices, DisplayState *ds, |
| 349 | 391 |
const char *kernel_filename, const char *kernel_cmdline, |
| ... | ... | |
| 357 | 399 |
unsigned int i; |
| 358 | 400 |
ram_addr_t ram_offset, prom_offset, vga_ram_offset; |
| 359 | 401 |
long initrd_size, kernel_size; |
| 360 |
PCIBus *pci_bus; |
|
| 402 |
PCIBus *pci_bus, *pci_bus2, *pci_bus3;
|
|
| 361 | 403 |
QEMUBH *bh; |
| 362 | 404 |
qemu_irq *irq; |
| 363 | 405 |
int drive_index; |
| ... | ... | |
| 462 | 504 |
} |
| 463 | 505 |
} |
| 464 | 506 |
} |
| 465 |
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL); |
|
| 507 |
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL, &pci_bus2, |
|
| 508 |
&pci_bus3); |
|
| 466 | 509 |
isa_mem_base = VGA_BASE; |
| 467 | 510 |
vga_ram_offset = qemu_ram_alloc(vga_ram_size); |
| 468 | 511 |
pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_offset, |
| 469 | 512 |
vga_ram_offset, vga_ram_size, |
| 470 | 513 |
0, 0); |
| 471 | 514 |
|
| 515 |
// XXX Should be pci_bus3 |
|
| 516 |
pci_ebus_init(pci_bus, -1); |
|
| 517 |
|
|
| 472 | 518 |
i = 0; |
| 473 | 519 |
if (hwdef->console_serial_base) {
|
| 474 | 520 |
serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200, |
Also available in: Unified diff