Revision c190ea07 hw/sun4u.c
b/hw/sun4u.c | ||
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344 | 344 |
|
345 | 345 |
static fdctrl_t *floppy_controller; |
346 | 346 |
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347 |
static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num, |
|
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uint32_t addr, uint32_t size, int type) |
|
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{ |
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DPRINTF("Mapping region %d registers at %08x\n", region_num, addr); |
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switch (region_num) { |
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case 0: |
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isa_mmio_init(addr, 0x1000000); |
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break; |
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case 1: |
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isa_mmio_init(addr, 0x800000); |
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break; |
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} |
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} |
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|
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361 |
/* EBUS (Eight bit bus) bridge */ |
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static void |
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pci_ebus_init(PCIBus *bus, int devfn) |
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{ |
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PCIDevice *s; |
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|
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s = pci_register_device(bus, "EBUS", sizeof(*s), devfn, NULL, NULL); |
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s->config[0x00] = 0x8e; // vendor_id : Sun |
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s->config[0x01] = 0x10; |
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s->config[0x02] = 0x00; // device_id |
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s->config[0x03] = 0x10; |
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s->config[0x04] = 0x06; // command = bus master, pci mem |
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s->config[0x05] = 0x00; |
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s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
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s->config[0x07] = 0x03; // status = medium devsel |
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s->config[0x08] = 0x01; // revision |
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s->config[0x09] = 0x00; // programming i/f |
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s->config[0x0A] = 0x80; // class_sub = misc bridge |
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s->config[0x0B] = 0x06; // class_base = PCI_bridge |
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s->config[0x0D] = 0x0a; // latency_timer |
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s->config[0x0E] = 0x00; // header_type |
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|
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pci_register_io_region(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM, |
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ebus_mmio_mapfunc); |
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pci_register_io_region(s, 1, 0x800000, PCI_ADDRESS_SPACE_MEM, |
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ebus_mmio_mapfunc); |
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} |
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|
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347 | 389 |
static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size, |
348 | 390 |
const char *boot_devices, DisplayState *ds, |
349 | 391 |
const char *kernel_filename, const char *kernel_cmdline, |
... | ... | |
357 | 399 |
unsigned int i; |
358 | 400 |
ram_addr_t ram_offset, prom_offset, vga_ram_offset; |
359 | 401 |
long initrd_size, kernel_size; |
360 |
PCIBus *pci_bus; |
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PCIBus *pci_bus, *pci_bus2, *pci_bus3;
|
|
361 | 403 |
QEMUBH *bh; |
362 | 404 |
qemu_irq *irq; |
363 | 405 |
int drive_index; |
... | ... | |
462 | 504 |
} |
463 | 505 |
} |
464 | 506 |
} |
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pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL); |
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pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL, &pci_bus2, |
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&pci_bus3); |
|
466 | 509 |
isa_mem_base = VGA_BASE; |
467 | 510 |
vga_ram_offset = qemu_ram_alloc(vga_ram_size); |
468 | 511 |
pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_offset, |
469 | 512 |
vga_ram_offset, vga_ram_size, |
470 | 513 |
0, 0); |
471 | 514 |
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// XXX Should be pci_bus3 |
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pci_ebus_init(pci_bus, -1); |
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|
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472 | 518 |
i = 0; |
473 | 519 |
if (hwdef->console_serial_base) { |
474 | 520 |
serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200, |
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