Revision c1c37968
| b/target-i386/translate.c | ||
|---|---|---|
| 1432 | 1432 |
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
| 1433 | 1433 |
} |
| 1434 | 1434 |
|
| 1435 |
/* XXX: add faster immediate case */ |
|
| 1436 | 1435 |
static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, |
| 1437 | 1436 |
int is_right, int is_arith) |
| 1438 | 1437 |
{
|
| ... | ... | |
| 1493 | 1492 |
s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ |
| 1494 | 1493 |
} |
| 1495 | 1494 |
|
| 1495 |
static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2, |
|
| 1496 |
int is_right, int is_arith) |
|
| 1497 |
{
|
|
| 1498 |
int mask; |
|
| 1499 |
|
|
| 1500 |
if (ot == OT_QUAD) |
|
| 1501 |
mask = 0x3f; |
|
| 1502 |
else |
|
| 1503 |
mask = 0x1f; |
|
| 1504 |
|
|
| 1505 |
/* load */ |
|
| 1506 |
if (op1 == OR_TMP0) |
|
| 1507 |
gen_op_ld_T0_A0(ot + s->mem_index); |
|
| 1508 |
else |
|
| 1509 |
gen_op_mov_TN_reg(ot, 0, op1); |
|
| 1510 |
|
|
| 1511 |
op2 &= mask; |
|
| 1512 |
if (op2 != 0) {
|
|
| 1513 |
if (is_right) {
|
|
| 1514 |
if (is_arith) {
|
|
| 1515 |
gen_exts(ot, cpu_T[0]); |
|
| 1516 |
tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], op2 - 1); |
|
| 1517 |
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2); |
|
| 1518 |
} else {
|
|
| 1519 |
gen_extu(ot, cpu_T[0]); |
|
| 1520 |
tcg_gen_shri_tl(cpu_tmp0, cpu_T[0], op2 - 1); |
|
| 1521 |
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2); |
|
| 1522 |
} |
|
| 1523 |
} else {
|
|
| 1524 |
tcg_gen_shli_tl(cpu_tmp0, cpu_T[0], op2 - 1); |
|
| 1525 |
tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2); |
|
| 1526 |
} |
|
| 1527 |
} |
|
| 1528 |
|
|
| 1529 |
/* store */ |
|
| 1530 |
if (op1 == OR_TMP0) |
|
| 1531 |
gen_op_st_T0_A0(ot + s->mem_index); |
|
| 1532 |
else |
|
| 1533 |
gen_op_mov_reg_T0(ot, op1); |
|
| 1534 |
|
|
| 1535 |
/* update eflags if non zero shift */ |
|
| 1536 |
if (op2 != 0) {
|
|
| 1537 |
tcg_gen_mov_tl(cpu_cc_src, cpu_tmp0); |
|
| 1538 |
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
|
| 1539 |
if (is_right) |
|
| 1540 |
s->cc_op = CC_OP_SARB + ot; |
|
| 1541 |
else |
|
| 1542 |
s->cc_op = CC_OP_SHLB + ot; |
|
| 1543 |
} |
|
| 1544 |
} |
|
| 1545 |
|
|
| 1496 | 1546 |
static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2) |
| 1497 | 1547 |
{
|
| 1498 | 1548 |
if (arg2 >= 0) |
| ... | ... | |
| 1770 | 1820 |
|
| 1771 | 1821 |
static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c) |
| 1772 | 1822 |
{
|
| 1773 |
/* currently not optimized */ |
|
| 1774 |
gen_op_movl_T1_im(c); |
|
| 1775 |
gen_shift(s1, op, ot, d, OR_TMP1); |
|
| 1823 |
switch(op) {
|
|
| 1824 |
case OP_SHL: |
|
| 1825 |
case OP_SHL1: |
|
| 1826 |
gen_shift_rm_im(s1, ot, d, c, 0, 0); |
|
| 1827 |
break; |
|
| 1828 |
case OP_SHR: |
|
| 1829 |
gen_shift_rm_im(s1, ot, d, c, 1, 0); |
|
| 1830 |
break; |
|
| 1831 |
case OP_SAR: |
|
| 1832 |
gen_shift_rm_im(s1, ot, d, c, 1, 1); |
|
| 1833 |
break; |
|
| 1834 |
default: |
|
| 1835 |
/* currently not optimized */ |
|
| 1836 |
gen_op_movl_T1_im(c); |
|
| 1837 |
gen_shift(s1, op, ot, d, OR_TMP1); |
|
| 1838 |
break; |
|
| 1839 |
} |
|
| 1776 | 1840 |
} |
| 1777 | 1841 |
|
| 1778 | 1842 |
static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr) |
Also available in: Unified diff