Revision c326b979 target-arm/translate.c
| b/target-arm/translate.c | ||
|---|---|---|
| 6355 | 6355 |
return 0; |
| 6356 | 6356 |
} |
| 6357 | 6357 |
|
| 6358 |
static int disas_cp14_read(CPUARMState * env, DisasContext *s, uint32_t insn) |
|
| 6359 |
{
|
|
| 6360 |
int crn = (insn >> 16) & 0xf; |
|
| 6361 |
int crm = insn & 0xf; |
|
| 6362 |
int op1 = (insn >> 21) & 7; |
|
| 6363 |
int op2 = (insn >> 5) & 7; |
|
| 6364 |
int rt = (insn >> 12) & 0xf; |
|
| 6365 |
TCGv tmp; |
|
| 6366 |
|
|
| 6367 |
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
|
|
| 6368 |
if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
|
|
| 6369 |
/* TEECR */ |
|
| 6370 |
if (IS_USER(s)) |
|
| 6371 |
return 1; |
|
| 6372 |
tmp = load_cpu_field(teecr); |
|
| 6373 |
store_reg(s, rt, tmp); |
|
| 6374 |
return 0; |
|
| 6375 |
} |
|
| 6376 |
if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
|
|
| 6377 |
/* TEEHBR */ |
|
| 6378 |
if (IS_USER(s) && (env->teecr & 1)) |
|
| 6379 |
return 1; |
|
| 6380 |
tmp = load_cpu_field(teehbr); |
|
| 6381 |
store_reg(s, rt, tmp); |
|
| 6382 |
return 0; |
|
| 6383 |
} |
|
| 6384 |
} |
|
| 6385 |
return 1; |
|
| 6386 |
} |
|
| 6387 |
|
|
| 6388 |
static int disas_cp14_write(CPUARMState * env, DisasContext *s, uint32_t insn) |
|
| 6389 |
{
|
|
| 6390 |
int crn = (insn >> 16) & 0xf; |
|
| 6391 |
int crm = insn & 0xf; |
|
| 6392 |
int op1 = (insn >> 21) & 7; |
|
| 6393 |
int op2 = (insn >> 5) & 7; |
|
| 6394 |
int rt = (insn >> 12) & 0xf; |
|
| 6395 |
TCGv tmp; |
|
| 6396 |
|
|
| 6397 |
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
|
|
| 6398 |
if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
|
|
| 6399 |
/* TEECR */ |
|
| 6400 |
if (IS_USER(s)) |
|
| 6401 |
return 1; |
|
| 6402 |
tmp = load_reg(s, rt); |
|
| 6403 |
gen_helper_set_teecr(cpu_env, tmp); |
|
| 6404 |
tcg_temp_free_i32(tmp); |
|
| 6405 |
return 0; |
|
| 6406 |
} |
|
| 6407 |
if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
|
|
| 6408 |
/* TEEHBR */ |
|
| 6409 |
if (IS_USER(s) && (env->teecr & 1)) |
|
| 6410 |
return 1; |
|
| 6411 |
tmp = load_reg(s, rt); |
|
| 6412 |
store_cpu_field(tmp, teehbr); |
|
| 6413 |
return 0; |
|
| 6414 |
} |
|
| 6415 |
} |
|
| 6416 |
return 1; |
|
| 6417 |
} |
|
| 6418 |
|
|
| 6419 | 6358 |
static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) |
| 6420 | 6359 |
{
|
| 6421 | 6360 |
int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; |
| ... | ... | |
| 6591 | 6530 |
* to ARMCPRegInfo. |
| 6592 | 6531 |
*/ |
| 6593 | 6532 |
switch (cpnum) {
|
| 6594 |
case 14: |
|
| 6595 |
if (insn & (1 << 20)) |
|
| 6596 |
return disas_cp14_read(env, s, insn); |
|
| 6597 |
else |
|
| 6598 |
return disas_cp14_write(env, s, insn); |
|
| 6599 | 6533 |
case 15: |
| 6600 | 6534 |
return disas_cp15_insn (env, s, insn); |
| 6601 | 6535 |
default: |
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