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/*
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 * QEMU IDE disk and CD-ROM Emulator
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 * 
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 * Copyright (c) 2003 Fabrice Bellard
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 * 
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "vl.h"
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/* debug IDE devices */
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//#define DEBUG_IDE
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//#define DEBUG_IDE_ATAPI
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//#define DEBUG_AIO
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#define USE_DMA_CDROM
31

    
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/* Bits of HD_STATUS */
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#define ERR_STAT                0x01
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#define INDEX_STAT                0x02
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#define ECC_STAT                0x04        /* Corrected error */
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#define DRQ_STAT                0x08
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#define SEEK_STAT                0x10
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#define SRV_STAT                0x10
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#define WRERR_STAT                0x20
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#define READY_STAT                0x40
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#define BUSY_STAT                0x80
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/* Bits for HD_ERROR */
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#define MARK_ERR                0x01        /* Bad address mark */
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#define TRK0_ERR                0x02        /* couldn't find track 0 */
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#define ABRT_ERR                0x04        /* Command aborted */
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#define MCR_ERR                        0x08        /* media change request */
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#define ID_ERR                        0x10        /* ID field not found */
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#define MC_ERR                        0x20        /* media changed */
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#define ECC_ERR                        0x40        /* Uncorrectable ECC error */
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#define BBD_ERR                        0x80        /* pre-EIDE meaning:  block marked bad */
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#define ICRC_ERR                0x80        /* new meaning:  CRC error during transfer */
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54
/* Bits of HD_NSECTOR */
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#define CD                        0x01
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#define IO                        0x02
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#define REL                        0x04
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#define TAG_MASK                0xf8
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#define IDE_CMD_RESET           0x04
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#define IDE_CMD_DISABLE_IRQ     0x02
62

    
63
/* ATA/ATAPI Commands pre T13 Spec */
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#define WIN_NOP                                0x00
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/*
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 *        0x01->0x02 Reserved
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 */
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#define CFA_REQ_EXT_ERROR_CODE                0x03 /* CFA Request Extended Error Code */
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/*
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 *        0x04->0x07 Reserved
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 */
72
#define WIN_SRST                        0x08 /* ATAPI soft reset command */
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#define WIN_DEVICE_RESET                0x08
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/*
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 *        0x09->0x0F Reserved
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 */
77
#define WIN_RECAL                        0x10
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#define WIN_RESTORE                        WIN_RECAL
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/*
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 *        0x10->0x1F Reserved
81
 */
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#define WIN_READ                        0x20 /* 28-Bit */
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#define WIN_READ_ONCE                        0x21 /* 28-Bit without retries */
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#define WIN_READ_LONG                        0x22 /* 28-Bit */
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#define WIN_READ_LONG_ONCE                0x23 /* 28-Bit without retries */
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#define WIN_READ_EXT                        0x24 /* 48-Bit */
87
#define WIN_READDMA_EXT                        0x25 /* 48-Bit */
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#define WIN_READDMA_QUEUED_EXT                0x26 /* 48-Bit */
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#define WIN_READ_NATIVE_MAX_EXT                0x27 /* 48-Bit */
90
/*
91
 *        0x28
92
 */
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#define WIN_MULTREAD_EXT                0x29 /* 48-Bit */
94
/*
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 *        0x2A->0x2F Reserved
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 */
97
#define WIN_WRITE                        0x30 /* 28-Bit */
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#define WIN_WRITE_ONCE                        0x31 /* 28-Bit without retries */
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#define WIN_WRITE_LONG                        0x32 /* 28-Bit */
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#define WIN_WRITE_LONG_ONCE                0x33 /* 28-Bit without retries */
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#define WIN_WRITE_EXT                        0x34 /* 48-Bit */
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#define WIN_WRITEDMA_EXT                0x35 /* 48-Bit */
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#define WIN_WRITEDMA_QUEUED_EXT                0x36 /* 48-Bit */
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#define WIN_SET_MAX_EXT                        0x37 /* 48-Bit */
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#define CFA_WRITE_SECT_WO_ERASE                0x38 /* CFA Write Sectors without erase */
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#define WIN_MULTWRITE_EXT                0x39 /* 48-Bit */
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/*
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 *        0x3A->0x3B Reserved
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 */
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#define WIN_WRITE_VERIFY                0x3C /* 28-Bit */
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/*
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 *        0x3D->0x3F Reserved
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 */
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#define WIN_VERIFY                        0x40 /* 28-Bit - Read Verify Sectors */
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#define WIN_VERIFY_ONCE                        0x41 /* 28-Bit - without retries */
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#define WIN_VERIFY_EXT                        0x42 /* 48-Bit */
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/*
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 *        0x43->0x4F Reserved
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 */
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#define WIN_FORMAT                        0x50
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/*
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 *        0x51->0x5F Reserved
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 */
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#define WIN_INIT                        0x60
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/*
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 *        0x61->0x5F Reserved
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 */
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#define WIN_SEEK                        0x70 /* 0x70-0x7F Reserved */
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#define CFA_TRANSLATE_SECTOR                0x87 /* CFA Translate Sector */
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#define WIN_DIAGNOSE                        0x90
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#define WIN_SPECIFY                        0x91 /* set drive geometry translation */
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#define WIN_DOWNLOAD_MICROCODE                0x92
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#define WIN_STANDBYNOW2                        0x94
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#define WIN_STANDBY2                        0x96
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#define WIN_SETIDLE2                        0x97
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#define WIN_CHECKPOWERMODE2                0x98
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#define WIN_SLEEPNOW2                        0x99
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/*
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 *        0x9A VENDOR
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 */
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#define WIN_PACKETCMD                        0xA0 /* Send a packet command. */
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#define WIN_PIDENTIFY                        0xA1 /* identify ATAPI device        */
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#define WIN_QUEUED_SERVICE                0xA2
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#define WIN_SMART                        0xB0 /* self-monitoring and reporting */
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#define CFA_ERASE_SECTORS               0xC0
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#define WIN_MULTREAD                        0xC4 /* read sectors using multiple mode*/
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#define WIN_MULTWRITE                        0xC5 /* write sectors using multiple mode */
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#define WIN_SETMULT                        0xC6 /* enable/disable multiple mode */
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#define WIN_READDMA_QUEUED                0xC7 /* read sectors using Queued DMA transfers */
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#define WIN_READDMA                        0xC8 /* read sectors using DMA transfers */
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#define WIN_READDMA_ONCE                0xC9 /* 28-Bit - without retries */
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#define WIN_WRITEDMA                        0xCA /* write sectors using DMA transfers */
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#define WIN_WRITEDMA_ONCE                0xCB /* 28-Bit - without retries */
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#define WIN_WRITEDMA_QUEUED                0xCC /* write sectors using Queued DMA transfers */
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#define CFA_WRITE_MULTI_WO_ERASE        0xCD /* CFA Write multiple without erase */
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#define WIN_GETMEDIASTATUS                0xDA        
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#define WIN_ACKMEDIACHANGE                0xDB /* ATA-1, ATA-2 vendor */
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#define WIN_POSTBOOT                        0xDC
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#define WIN_PREBOOT                        0xDD
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#define WIN_DOORLOCK                        0xDE /* lock door on removable drives */
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#define WIN_DOORUNLOCK                        0xDF /* unlock door on removable drives */
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#define WIN_STANDBYNOW1                        0xE0
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#define WIN_IDLEIMMEDIATE                0xE1 /* force drive to become "ready" */
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#define WIN_STANDBY                     0xE2 /* Set device in Standby Mode */
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#define WIN_SETIDLE1                        0xE3
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#define WIN_READ_BUFFER                        0xE4 /* force read only 1 sector */
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#define WIN_CHECKPOWERMODE1                0xE5
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#define WIN_SLEEPNOW1                        0xE6
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#define WIN_FLUSH_CACHE                        0xE7
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#define WIN_WRITE_BUFFER                0xE8 /* force write only 1 sector */
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#define WIN_WRITE_SAME                        0xE9 /* read ata-2 to use */
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        /* SET_FEATURES 0x22 or 0xDD */
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#define WIN_FLUSH_CACHE_EXT                0xEA /* 48-Bit */
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#define WIN_IDENTIFY                        0xEC /* ask drive to identify itself        */
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#define WIN_MEDIAEJECT                        0xED
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#define WIN_IDENTIFY_DMA                0xEE /* same as WIN_IDENTIFY, but DMA */
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#define WIN_SETFEATURES                        0xEF /* set special drive features */
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#define EXABYTE_ENABLE_NEST                0xF0
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#define WIN_SECURITY_SET_PASS                0xF1
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#define WIN_SECURITY_UNLOCK                0xF2
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#define WIN_SECURITY_ERASE_PREPARE        0xF3
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#define WIN_SECURITY_ERASE_UNIT                0xF4
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#define WIN_SECURITY_FREEZE_LOCK        0xF5
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#define WIN_SECURITY_DISABLE                0xF6
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#define WIN_READ_NATIVE_MAX                0xF8 /* return the native maximum address */
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#define WIN_SET_MAX                        0xF9
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#define DISABLE_SEAGATE                        0xFB
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/* set to 1 set disable mult support */
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#define MAX_MULT_SECTORS 16
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/* ATAPI defines */
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#define ATAPI_PACKET_SIZE 12
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/* The generic packet command opcodes for CD/DVD Logical Units,
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 * From Table 57 of the SFF8090 Ver. 3 (Mt. Fuji) draft standard. */
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#define GPCMD_BLANK                            0xa1
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#define GPCMD_CLOSE_TRACK                    0x5b
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#define GPCMD_FLUSH_CACHE                    0x35
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#define GPCMD_FORMAT_UNIT                    0x04
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#define GPCMD_GET_CONFIGURATION                    0x46
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#define GPCMD_GET_EVENT_STATUS_NOTIFICATION 0x4a
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#define GPCMD_GET_PERFORMANCE                    0xac
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#define GPCMD_INQUIRY                            0x12
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#define GPCMD_LOAD_UNLOAD                    0xa6
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#define GPCMD_MECHANISM_STATUS                    0xbd
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#define GPCMD_MODE_SELECT_10                    0x55
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#define GPCMD_MODE_SENSE_10                    0x5a
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#define GPCMD_PAUSE_RESUME                    0x4b
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#define GPCMD_PLAY_AUDIO_10                    0x45
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#define GPCMD_PLAY_AUDIO_MSF                    0x47
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#define GPCMD_PLAY_AUDIO_TI                    0x48
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#define GPCMD_PLAY_CD                            0xbc
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#define GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL  0x1e
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#define GPCMD_READ_10                            0x28
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#define GPCMD_READ_12                            0xa8
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#define GPCMD_READ_CDVD_CAPACITY            0x25
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#define GPCMD_READ_CD                            0xbe
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#define GPCMD_READ_CD_MSF                    0xb9
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#define GPCMD_READ_DISC_INFO                    0x51
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#define GPCMD_READ_DVD_STRUCTURE            0xad
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#define GPCMD_READ_FORMAT_CAPACITIES            0x23
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#define GPCMD_READ_HEADER                    0x44
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#define GPCMD_READ_TRACK_RZONE_INFO            0x52
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#define GPCMD_READ_SUBCHANNEL                    0x42
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#define GPCMD_READ_TOC_PMA_ATIP                    0x43
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#define GPCMD_REPAIR_RZONE_TRACK            0x58
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#define GPCMD_REPORT_KEY                    0xa4
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#define GPCMD_REQUEST_SENSE                    0x03
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#define GPCMD_RESERVE_RZONE_TRACK            0x53
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#define GPCMD_SCAN                            0xba
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#define GPCMD_SEEK                            0x2b
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#define GPCMD_SEND_DVD_STRUCTURE            0xad
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#define GPCMD_SEND_EVENT                    0xa2
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#define GPCMD_SEND_KEY                            0xa3
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#define GPCMD_SEND_OPC                            0x54
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#define GPCMD_SET_READ_AHEAD                    0xa7
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#define GPCMD_SET_STREAMING                    0xb6
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#define GPCMD_START_STOP_UNIT                    0x1b
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#define GPCMD_STOP_PLAY_SCAN                    0x4e
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#define GPCMD_TEST_UNIT_READY                    0x00
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#define GPCMD_VERIFY_10                            0x2f
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#define GPCMD_WRITE_10                            0x2a
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#define GPCMD_WRITE_AND_VERIFY_10            0x2e
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/* This is listed as optional in ATAPI 2.6, but is (curiously) 
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 * missing from Mt. Fuji, Table 57.  It _is_ mentioned in Mt. Fuji
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 * Table 377 as an MMC command for SCSi devices though...  Most ATAPI
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 * drives support it. */
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#define GPCMD_SET_SPEED                            0xbb
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/* This seems to be a SCSI specific CD-ROM opcode 
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 * to play data at track/index */
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#define GPCMD_PLAYAUDIO_TI                    0x48
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/*
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 * From MS Media Status Notification Support Specification. For
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 * older drives only.
257
 */
258
#define GPCMD_GET_MEDIA_STATUS                    0xda
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/* Mode page codes for mode sense/set */
261
#define GPMODE_R_W_ERROR_PAGE                0x01
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#define GPMODE_WRITE_PARMS_PAGE                0x05
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#define GPMODE_AUDIO_CTL_PAGE                0x0e
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#define GPMODE_POWER_PAGE                0x1a
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#define GPMODE_FAULT_FAIL_PAGE                0x1c
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#define GPMODE_TO_PROTECT_PAGE                0x1d
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#define GPMODE_CAPABILITIES_PAGE        0x2a
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#define GPMODE_ALL_PAGES                0x3f
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/* Not in Mt. Fuji, but in ATAPI 2.6 -- depricated now in favor
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 * of MODE_SENSE_POWER_PAGE */
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#define GPMODE_CDROM_PAGE                0x0d
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#define ATAPI_INT_REASON_CD             0x01 /* 0 = data transfer */
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#define ATAPI_INT_REASON_IO             0x02 /* 1 = transfer to the host */
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#define ATAPI_INT_REASON_REL            0x04
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#define ATAPI_INT_REASON_TAG            0xf8
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/* same constants as bochs */
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#define ASC_ILLEGAL_OPCODE                   0x20
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#define ASC_LOGICAL_BLOCK_OOR                0x21
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#define ASC_INV_FIELD_IN_CMD_PACKET          0x24
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#define ASC_MEDIUM_NOT_PRESENT               0x3a
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#define ASC_SAVING_PARAMETERS_NOT_SUPPORTED  0x39
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#define SENSE_NONE            0
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#define SENSE_NOT_READY       2
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#define SENSE_ILLEGAL_REQUEST 5
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#define SENSE_UNIT_ATTENTION  6
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struct IDEState;
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typedef void EndTransferFunc(struct IDEState *);
293

    
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/* NOTE: IDEState represents in fact one drive */
295
typedef struct IDEState {
296
    /* ide config */
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    int is_cdrom;
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    int cylinders, heads, sectors;
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    int64_t nb_sectors;
300
    int mult_sectors;
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    int identify_set;
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    uint16_t identify_data[256];
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    SetIRQFunc *set_irq;
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    void *irq_opaque;
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    int irq;
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    PCIDevice *pci_dev;
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    struct BMDMAState *bmdma;
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    int drive_serial;
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    /* ide regs */
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    uint8_t feature;
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    uint8_t error;
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    uint32_t nsector;
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    uint8_t sector;
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    uint8_t lcyl;
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    uint8_t hcyl;
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    /* other part of tf for lba48 support */
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    uint8_t hob_feature;
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    uint8_t hob_nsector;
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    uint8_t hob_sector;
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    uint8_t hob_lcyl;
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    uint8_t hob_hcyl;
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    uint8_t select;
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    uint8_t status;
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    /* 0x3f6 command, only meaningful for drive 0 */
327
    uint8_t cmd;
328
    /* set for lba48 access */
329
    uint8_t lba48;
330
    /* depends on bit 4 in select, only meaningful for drive 0 */
331
    struct IDEState *cur_drive; 
332
    BlockDriverState *bs;
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    /* ATAPI specific */
334
    uint8_t sense_key;
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    uint8_t asc;
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    int packet_transfer_size;
337
    int elementary_transfer_size;
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    int io_buffer_index;
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    int lba;
340
    int cd_sector_size;
341
    int atapi_dma; /* true if dma is requested for the packet cmd */
342
    /* ATA DMA state */
343
    int io_buffer_size;
344
    /* PIO transfer handling */
345
    int req_nb_sectors; /* number of sectors per interrupt */
346
    EndTransferFunc *end_transfer_func;
347
    uint8_t *data_ptr;
348
    uint8_t *data_end;
349
    uint8_t io_buffer[MAX_MULT_SECTORS*512 + 4];
350
    QEMUTimer *sector_write_timer; /* only used for win2k instal hack */
351
    uint32_t irq_count; /* counts IRQs when using win2k install hack */
352
} IDEState;
353

    
354
#define BM_STATUS_DMAING 0x01
355
#define BM_STATUS_ERROR  0x02
356
#define BM_STATUS_INT    0x04
357

    
358
#define BM_CMD_START     0x01
359
#define BM_CMD_READ      0x08
360

    
361
#define IDE_TYPE_PIIX3   0
362
#define IDE_TYPE_CMD646  1
363

    
364
/* CMD646 specific */
365
#define MRDMODE                0x71
366
#define   MRDMODE_INTR_CH0        0x04
367
#define   MRDMODE_INTR_CH1        0x08
368
#define   MRDMODE_BLK_CH0        0x10
369
#define   MRDMODE_BLK_CH1        0x20
370
#define UDIDETCR0        0x73
371
#define UDIDETCR1        0x7B
372

    
373
typedef struct BMDMAState {
374
    uint8_t cmd;
375
    uint8_t status;
376
    uint32_t addr;
377
    
378
    struct PCIIDEState *pci_dev;
379
    /* current transfer state */
380
    uint32_t cur_addr;
381
    uint32_t cur_prd_last;
382
    uint32_t cur_prd_addr;
383
    uint32_t cur_prd_len;
384
    IDEState *ide_if;
385
    BlockDriverCompletionFunc *dma_cb;
386
    BlockDriverAIOCB *aiocb;
387
} BMDMAState;
388

    
389
typedef struct PCIIDEState {
390
    PCIDevice dev;
391
    IDEState ide_if[4];
392
    BMDMAState bmdma[2];
393
    int type; /* see IDE_TYPE_xxx */
394
} PCIIDEState;
395

    
396
static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb);
397

    
398
static void padstr(char *str, const char *src, int len)
399
{
400
    int i, v;
401
    for(i = 0; i < len; i++) {
402
        if (*src)
403
            v = *src++;
404
        else
405
            v = ' ';
406
        *(char *)((long)str ^ 1) = v;
407
        str++;
408
    }
409
}
410

    
411
static void padstr8(uint8_t *buf, int buf_size, const char *src)
412
{
413
    int i;
414
    for(i = 0; i < buf_size; i++) {
415
        if (*src)
416
            buf[i] = *src++;
417
        else
418
            buf[i] = ' ';
419
    }
420
}
421

    
422
static void put_le16(uint16_t *p, unsigned int v)
423
{
424
    *p = cpu_to_le16(v);
425
}
426

    
427
static void ide_identify(IDEState *s)
428
{
429
    uint16_t *p;
430
    unsigned int oldsize;
431
    char buf[20];
432

    
433
    if (s->identify_set) {
434
        memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
435
        return;
436
    }
437

    
438
    memset(s->io_buffer, 0, 512);
439
    p = (uint16_t *)s->io_buffer;
440
    put_le16(p + 0, 0x0040);
441
    put_le16(p + 1, s->cylinders); 
442
    put_le16(p + 3, s->heads);
443
    put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
444
    put_le16(p + 5, 512); /* XXX: retired, remove ? */
445
    put_le16(p + 6, s->sectors); 
446
    snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial);
447
    padstr((uint8_t *)(p + 10), buf, 20); /* serial number */
448
    put_le16(p + 20, 3); /* XXX: retired, remove ? */
449
    put_le16(p + 21, 512); /* cache size in sectors */
450
    put_le16(p + 22, 4); /* ecc bytes */
451
    padstr((uint8_t *)(p + 23), QEMU_VERSION, 8); /* firmware version */
452
    padstr((uint8_t *)(p + 27), "QEMU HARDDISK", 40); /* model */
453
#if MAX_MULT_SECTORS > 1    
454
    put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
455
#endif
456
    put_le16(p + 48, 1); /* dword I/O */
457
    put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
458
    put_le16(p + 51, 0x200); /* PIO transfer cycle */
459
    put_le16(p + 52, 0x200); /* DMA transfer cycle */
460
    put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
461
    put_le16(p + 54, s->cylinders);
462
    put_le16(p + 55, s->heads);
463
    put_le16(p + 56, s->sectors);
464
    oldsize = s->cylinders * s->heads * s->sectors;
465
    put_le16(p + 57, oldsize);
466
    put_le16(p + 58, oldsize >> 16);
467
    if (s->mult_sectors)
468
        put_le16(p + 59, 0x100 | s->mult_sectors);
469
    put_le16(p + 60, s->nb_sectors);
470
    put_le16(p + 61, s->nb_sectors >> 16);
471
    put_le16(p + 63, 0x07); /* mdma0-2 supported */
472
    put_le16(p + 65, 120);
473
    put_le16(p + 66, 120);
474
    put_le16(p + 67, 120);
475
    put_le16(p + 68, 120);
476
    put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
477
    put_le16(p + 81, 0x16); /* conforms to ata5 */
478
    put_le16(p + 82, (1 << 14));
479
    /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
480
    put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
481
    put_le16(p + 84, (1 << 14));
482
    put_le16(p + 85, (1 << 14));
483
    /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
484
    put_le16(p + 86, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
485
    put_le16(p + 87, (1 << 14));
486
    put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
487
    put_le16(p + 93, 1 | (1 << 14) | 0x2000);
488
    put_le16(p + 100, s->nb_sectors);
489
    put_le16(p + 101, s->nb_sectors >> 16);
490
    put_le16(p + 102, s->nb_sectors >> 32);
491
    put_le16(p + 103, s->nb_sectors >> 48);
492

    
493
    memcpy(s->identify_data, p, sizeof(s->identify_data));
494
    s->identify_set = 1;
495
}
496

    
497
static void ide_atapi_identify(IDEState *s)
498
{
499
    uint16_t *p;
500
    char buf[20];
501

    
502
    if (s->identify_set) {
503
        memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
504
        return;
505
    }
506

    
507
    memset(s->io_buffer, 0, 512);
508
    p = (uint16_t *)s->io_buffer;
509
    /* Removable CDROM, 50us response, 12 byte packets */
510
    put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
511
    snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial);
512
    padstr((uint8_t *)(p + 10), buf, 20); /* serial number */
513
    put_le16(p + 20, 3); /* buffer type */
514
    put_le16(p + 21, 512); /* cache size in sectors */
515
    put_le16(p + 22, 4); /* ecc bytes */
516
    padstr((uint8_t *)(p + 23), QEMU_VERSION, 8); /* firmware version */
517
    padstr((uint8_t *)(p + 27), "QEMU CD-ROM", 40); /* model */
518
    put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
519
#ifdef USE_DMA_CDROM
520
    put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
521
    put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
522
    put_le16(p + 63, 7);  /* mdma0-2 supported */
523
    put_le16(p + 64, 0x3f); /* PIO modes supported */
524
#else
525
    put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
526
    put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
527
    put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
528
    put_le16(p + 64, 1); /* PIO modes */
529
#endif
530
    put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
531
    put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
532
    put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
533
    put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
534

    
535
    put_le16(p + 71, 30); /* in ns */
536
    put_le16(p + 72, 30); /* in ns */
537

    
538
    put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
539
#ifdef USE_DMA_CDROM
540
    put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
541
#endif
542
    memcpy(s->identify_data, p, sizeof(s->identify_data));
543
    s->identify_set = 1;
544
}
545

    
546
static void ide_set_signature(IDEState *s)
547
{
548
    s->select &= 0xf0; /* clear head */
549
    /* put signature */
550
    s->nsector = 1;
551
    s->sector = 1;
552
    if (s->is_cdrom) {
553
        s->lcyl = 0x14;
554
        s->hcyl = 0xeb;
555
    } else if (s->bs) {
556
        s->lcyl = 0;
557
        s->hcyl = 0;
558
    } else {
559
        s->lcyl = 0xff;
560
        s->hcyl = 0xff;
561
    }
562
}
563

    
564
static inline void ide_abort_command(IDEState *s)
565
{
566
    s->status = READY_STAT | ERR_STAT;
567
    s->error = ABRT_ERR;
568
}
569

    
570
static inline void ide_set_irq(IDEState *s)
571
{
572
    BMDMAState *bm = s->bmdma;
573
    if (!(s->cmd & IDE_CMD_DISABLE_IRQ)) {
574
        if (bm) {
575
            bm->status |= BM_STATUS_INT;
576
        }
577
        s->set_irq(s->irq_opaque, s->irq, 1);
578
    }
579
}
580

    
581
/* prepare data transfer and tell what to do after */
582
static void ide_transfer_start(IDEState *s, uint8_t *buf, int size, 
583
                               EndTransferFunc *end_transfer_func)
584
{
585
    s->end_transfer_func = end_transfer_func;
586
    s->data_ptr = buf;
587
    s->data_end = buf + size;
588
    s->status |= DRQ_STAT;
589
}
590

    
591
static void ide_transfer_stop(IDEState *s)
592
{
593
    s->end_transfer_func = ide_transfer_stop;
594
    s->data_ptr = s->io_buffer;
595
    s->data_end = s->io_buffer;
596
    s->status &= ~DRQ_STAT;
597
}
598

    
599
static int64_t ide_get_sector(IDEState *s)
600
{
601
    int64_t sector_num;
602
    if (s->select & 0x40) {
603
        /* lba */
604
        if (!s->lba48) {
605
            sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
606
                (s->lcyl << 8) | s->sector;
607
        } else {
608
            sector_num = ((int64_t)s->hob_hcyl << 40) |
609
                ((int64_t) s->hob_lcyl << 32) |
610
                ((int64_t) s->hob_sector << 24) |
611
                ((int64_t) s->hcyl << 16) |
612
                ((int64_t) s->lcyl << 8) | s->sector;
613
        }
614
    } else {
615
        sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
616
            (s->select & 0x0f) * s->sectors + (s->sector - 1);
617
    }
618
    return sector_num;
619
}
620

    
621
static void ide_set_sector(IDEState *s, int64_t sector_num)
622
{
623
    unsigned int cyl, r;
624
    if (s->select & 0x40) {
625
        if (!s->lba48) {
626
            s->select = (s->select & 0xf0) | (sector_num >> 24);
627
            s->hcyl = (sector_num >> 16);
628
            s->lcyl = (sector_num >> 8);
629
            s->sector = (sector_num);
630
        } else {
631
            s->sector = sector_num;
632
            s->lcyl = sector_num >> 8;
633
            s->hcyl = sector_num >> 16;
634
            s->hob_sector = sector_num >> 24;
635
            s->hob_lcyl = sector_num >> 32;
636
            s->hob_hcyl = sector_num >> 40;
637
        }
638
    } else {
639
        cyl = sector_num / (s->heads * s->sectors);
640
        r = sector_num % (s->heads * s->sectors);
641
        s->hcyl = cyl >> 8;
642
        s->lcyl = cyl;
643
        s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
644
        s->sector = (r % s->sectors) + 1;
645
    }
646
}
647

    
648
static void ide_sector_read(IDEState *s)
649
{
650
    int64_t sector_num;
651
    int ret, n;
652

    
653
    s->status = READY_STAT | SEEK_STAT;
654
    s->error = 0; /* not needed by IDE spec, but needed by Windows */
655
    sector_num = ide_get_sector(s);
656
    n = s->nsector;
657
    if (n == 0) {
658
        /* no more sector to read from disk */
659
        ide_transfer_stop(s);
660
    } else {
661
#if defined(DEBUG_IDE)
662
        printf("read sector=%Ld\n", sector_num);
663
#endif
664
        if (n > s->req_nb_sectors)
665
            n = s->req_nb_sectors;
666
        ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
667
        ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_read);
668
        ide_set_irq(s);
669
        ide_set_sector(s, sector_num + n);
670
        s->nsector -= n;
671
    }
672
}
673

    
674
/* return 0 if buffer completed */
675
static int dma_buf_rw(BMDMAState *bm, int is_write)
676
{
677
    IDEState *s = bm->ide_if;
678
    struct {
679
        uint32_t addr;
680
        uint32_t size;
681
    } prd;
682
    int l, len;
683

    
684
    for(;;) {
685
        l = s->io_buffer_size - s->io_buffer_index;
686
        if (l <= 0) 
687
            break;
688
        if (bm->cur_prd_len == 0) {
689
            /* end of table (with a fail safe of one page) */
690
            if (bm->cur_prd_last ||
691
                (bm->cur_addr - bm->addr) >= 4096)
692
                return 0;
693
            cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
694
            bm->cur_addr += 8;
695
            prd.addr = le32_to_cpu(prd.addr);
696
            prd.size = le32_to_cpu(prd.size);
697
            len = prd.size & 0xfffe;
698
            if (len == 0)
699
                len = 0x10000;
700
            bm->cur_prd_len = len;
701
            bm->cur_prd_addr = prd.addr;
702
            bm->cur_prd_last = (prd.size & 0x80000000);
703
        }
704
        if (l > bm->cur_prd_len)
705
            l = bm->cur_prd_len;
706
        if (l > 0) {
707
            if (is_write) {
708
                cpu_physical_memory_write(bm->cur_prd_addr, 
709
                                          s->io_buffer + s->io_buffer_index, l);
710
            } else {
711
                cpu_physical_memory_read(bm->cur_prd_addr, 
712
                                          s->io_buffer + s->io_buffer_index, l);
713
            }
714
            bm->cur_prd_addr += l;
715
            bm->cur_prd_len -= l;
716
            s->io_buffer_index += l;
717
        }
718
    }
719
    return 1;
720
}
721

    
722
/* XXX: handle errors */
723
static void ide_read_dma_cb(void *opaque, int ret)
724
{
725
    BMDMAState *bm = opaque;
726
    IDEState *s = bm->ide_if;
727
    int n;
728
    int64_t sector_num;
729

    
730
    n = s->io_buffer_size >> 9;
731
    sector_num = ide_get_sector(s);
732
    if (n > 0) {
733
        sector_num += n;
734
        ide_set_sector(s, sector_num);
735
        s->nsector -= n;
736
        if (dma_buf_rw(bm, 1) == 0)
737
            goto eot;
738
    }
739

    
740
    /* end of transfer ? */
741
    if (s->nsector == 0) {
742
        s->status = READY_STAT | SEEK_STAT;
743
        ide_set_irq(s);
744
    eot:
745
        bm->status &= ~BM_STATUS_DMAING;
746
        bm->status |= BM_STATUS_INT;
747
        bm->dma_cb = NULL;
748
        bm->ide_if = NULL;
749
        bm->aiocb = NULL;
750
        return;
751
    }
752

    
753
    /* launch next transfer */
754
    n = s->nsector;
755
    if (n > MAX_MULT_SECTORS)
756
        n = MAX_MULT_SECTORS;
757
    s->io_buffer_index = 0;
758
    s->io_buffer_size = n * 512;
759
#ifdef DEBUG_AIO
760
    printf("aio_read: sector_num=%lld n=%d\n", sector_num, n);
761
#endif
762
    bm->aiocb = bdrv_aio_read(s->bs, sector_num, s->io_buffer, n, 
763
                              ide_read_dma_cb, bm);
764
}
765

    
766
static void ide_sector_read_dma(IDEState *s)
767
{
768
    s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
769
    s->io_buffer_index = 0;
770
    s->io_buffer_size = 0;
771
    ide_dma_start(s, ide_read_dma_cb);
772
}
773

    
774
static void ide_sector_write_timer_cb(void *opaque)
775
{
776
    IDEState *s = opaque;
777
    ide_set_irq(s);
778
}
779

    
780
static void ide_sector_write(IDEState *s)
781
{
782
    int64_t sector_num;
783
    int ret, n, n1;
784

    
785
    s->status = READY_STAT | SEEK_STAT;
786
    sector_num = ide_get_sector(s);
787
#if defined(DEBUG_IDE)
788
    printf("write sector=%Ld\n", sector_num);
789
#endif
790
    n = s->nsector;
791
    if (n > s->req_nb_sectors)
792
        n = s->req_nb_sectors;
793
    ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
794
    s->nsector -= n;
795
    if (s->nsector == 0) {
796
        /* no more sector to write */
797
        ide_transfer_stop(s);
798
    } else {
799
        n1 = s->nsector;
800
        if (n1 > s->req_nb_sectors)
801
            n1 = s->req_nb_sectors;
802
        ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write);
803
    }
804
    ide_set_sector(s, sector_num + n);
805
    
806
#ifdef TARGET_I386
807
    if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
808
        /* It seems there is a bug in the Windows 2000 installer HDD
809
           IDE driver which fills the disk with empty logs when the
810
           IDE write IRQ comes too early. This hack tries to correct
811
           that at the expense of slower write performances. Use this
812
           option _only_ to install Windows 2000. You must disable it
813
           for normal use. */
814
        qemu_mod_timer(s->sector_write_timer, 
815
                       qemu_get_clock(vm_clock) + (ticks_per_sec / 1000));
816
    } else 
817
#endif
818
    {
819
        ide_set_irq(s);
820
    }
821
}
822

    
823
/* XXX: handle errors */
824
static void ide_write_dma_cb(void *opaque, int ret)
825
{
826
    BMDMAState *bm = opaque;
827
    IDEState *s = bm->ide_if;
828
    int n;
829
    int64_t sector_num;
830

    
831
    n = s->io_buffer_size >> 9;
832
    sector_num = ide_get_sector(s);
833
    if (n > 0) {
834
        sector_num += n;
835
        ide_set_sector(s, sector_num);
836
        s->nsector -= n;
837
    }
838

    
839
    /* end of transfer ? */
840
    if (s->nsector == 0) {
841
        s->status = READY_STAT | SEEK_STAT;
842
        ide_set_irq(s);
843
    eot:
844
        bm->status &= ~BM_STATUS_DMAING;
845
        bm->status |= BM_STATUS_INT;
846
        bm->dma_cb = NULL;
847
        bm->ide_if = NULL;
848
        bm->aiocb = NULL;
849
        return;
850
    }
851

    
852
    /* launch next transfer */
853
    n = s->nsector;
854
    if (n > MAX_MULT_SECTORS)
855
        n = MAX_MULT_SECTORS;
856
    s->io_buffer_index = 0;
857
    s->io_buffer_size = n * 512;
858

    
859
    if (dma_buf_rw(bm, 0) == 0)
860
        goto eot;
861
#ifdef DEBUG_AIO
862
    printf("aio_write: sector_num=%lld n=%d\n", sector_num, n);
863
#endif
864
    bm->aiocb = bdrv_aio_write(s->bs, sector_num, s->io_buffer, n, 
865
                               ide_write_dma_cb, bm);
866
}
867

    
868
static void ide_sector_write_dma(IDEState *s)
869
{
870
    s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
871
    s->io_buffer_index = 0;
872
    s->io_buffer_size = 0;
873
    ide_dma_start(s, ide_write_dma_cb);
874
}
875

    
876
static void ide_atapi_cmd_ok(IDEState *s)
877
{
878
    s->error = 0;
879
    s->status = READY_STAT;
880
    s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
881
    ide_set_irq(s);
882
}
883

    
884
static void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc)
885
{
886
#ifdef DEBUG_IDE_ATAPI
887
    printf("atapi_cmd_error: sense=0x%x asc=0x%x\n", sense_key, asc);
888
#endif
889
    s->error = sense_key << 4;
890
    s->status = READY_STAT | ERR_STAT;
891
    s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
892
    s->sense_key = sense_key;
893
    s->asc = asc;
894
    ide_set_irq(s);
895
}
896

    
897
static inline void cpu_to_ube16(uint8_t *buf, int val)
898
{
899
    buf[0] = val >> 8;
900
    buf[1] = val;
901
}
902

    
903
static inline void cpu_to_ube32(uint8_t *buf, unsigned int val)
904
{
905
    buf[0] = val >> 24;
906
    buf[1] = val >> 16;
907
    buf[2] = val >> 8;
908
    buf[3] = val;
909
}
910

    
911
static inline int ube16_to_cpu(const uint8_t *buf)
912
{
913
    return (buf[0] << 8) | buf[1];
914
}
915

    
916
static inline int ube32_to_cpu(const uint8_t *buf)
917
{
918
    return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
919
}
920

    
921
static void lba_to_msf(uint8_t *buf, int lba)
922
{
923
    lba += 150;
924
    buf[0] = (lba / 75) / 60;
925
    buf[1] = (lba / 75) % 60;
926
    buf[2] = lba % 75;
927
}
928

    
929
static void cd_data_to_raw(uint8_t *buf, int lba)
930
{
931
    /* sync bytes */
932
    buf[0] = 0x00;
933
    memset(buf + 1, 0xff, 10);
934
    buf[11] = 0x00;
935
    buf += 12;
936
    /* MSF */
937
    lba_to_msf(buf, lba);
938
    buf[3] = 0x01; /* mode 1 data */
939
    buf += 4;
940
    /* data */
941
    buf += 2048;
942
    /* XXX: ECC not computed */
943
    memset(buf, 0, 288);
944
}
945

    
946
static void cd_read_sector(BlockDriverState *bs, int lba, uint8_t *buf, 
947
                           int sector_size)
948
{
949
    switch(sector_size) {
950
    case 2048:
951
        bdrv_read(bs, (int64_t)lba << 2, buf, 4);
952
        break;
953
    case 2352:
954
        bdrv_read(bs, (int64_t)lba << 2, buf + 16, 4);
955
        cd_data_to_raw(buf, lba);
956
        break;
957
    default:
958
        break;
959
    }
960
}
961

    
962
/* The whole ATAPI transfer logic is handled in this function */
963
static void ide_atapi_cmd_reply_end(IDEState *s)
964
{
965
    int byte_count_limit, size;
966
#ifdef DEBUG_IDE_ATAPI
967
    printf("reply: tx_size=%d elem_tx_size=%d index=%d\n", 
968
           s->packet_transfer_size,
969
           s->elementary_transfer_size,
970
           s->io_buffer_index);
971
#endif
972
    if (s->packet_transfer_size <= 0) {
973
        /* end of transfer */
974
        ide_transfer_stop(s);
975
        s->status = READY_STAT;
976
        s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
977
        ide_set_irq(s);
978
#ifdef DEBUG_IDE_ATAPI
979
        printf("status=0x%x\n", s->status);
980
#endif
981
    } else {
982
        /* see if a new sector must be read */
983
        if (s->lba != -1 && s->io_buffer_index >= s->cd_sector_size) {
984
            cd_read_sector(s->bs, s->lba, s->io_buffer, s->cd_sector_size);
985
            s->lba++;
986
            s->io_buffer_index = 0;
987
        }
988
        if (s->elementary_transfer_size > 0) {
989
            /* there are some data left to transmit in this elementary
990
               transfer */
991
            size = s->cd_sector_size - s->io_buffer_index;
992
            if (size > s->elementary_transfer_size)
993
                size = s->elementary_transfer_size;
994
            ide_transfer_start(s, s->io_buffer + s->io_buffer_index, 
995
                               size, ide_atapi_cmd_reply_end);
996
            s->packet_transfer_size -= size;
997
            s->elementary_transfer_size -= size;
998
            s->io_buffer_index += size;
999
        } else {
1000
            /* a new transfer is needed */
1001
            s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO;
1002
            byte_count_limit = s->lcyl | (s->hcyl << 8);
1003
#ifdef DEBUG_IDE_ATAPI
1004
            printf("byte_count_limit=%d\n", byte_count_limit);
1005
#endif
1006
            if (byte_count_limit == 0xffff)
1007
                byte_count_limit--;
1008
            size = s->packet_transfer_size;
1009
            if (size > byte_count_limit) {
1010
                /* byte count limit must be even if this case */
1011
                if (byte_count_limit & 1)
1012
                    byte_count_limit--;
1013
                size = byte_count_limit;
1014
            }
1015
            s->lcyl = size;
1016
            s->hcyl = size >> 8;
1017
            s->elementary_transfer_size = size;
1018
            /* we cannot transmit more than one sector at a time */
1019
            if (s->lba != -1) {
1020
                if (size > (s->cd_sector_size - s->io_buffer_index))
1021
                    size = (s->cd_sector_size - s->io_buffer_index);
1022
            }
1023
            ide_transfer_start(s, s->io_buffer + s->io_buffer_index, 
1024
                               size, ide_atapi_cmd_reply_end);
1025
            s->packet_transfer_size -= size;
1026
            s->elementary_transfer_size -= size;
1027
            s->io_buffer_index += size;
1028
            ide_set_irq(s);
1029
#ifdef DEBUG_IDE_ATAPI
1030
            printf("status=0x%x\n", s->status);
1031
#endif
1032
        }
1033
    }
1034
}
1035

    
1036
/* send a reply of 'size' bytes in s->io_buffer to an ATAPI command */
1037
static void ide_atapi_cmd_reply(IDEState *s, int size, int max_size)
1038
{
1039
    if (size > max_size)
1040
        size = max_size;
1041
    s->lba = -1; /* no sector read */
1042
    s->packet_transfer_size = size;
1043
    s->elementary_transfer_size = 0;
1044
    s->io_buffer_index = 0;
1045

    
1046
    s->status = READY_STAT;
1047
    ide_atapi_cmd_reply_end(s);
1048
}
1049

    
1050
/* start a CD-CDROM read command */
1051
static void ide_atapi_cmd_read_pio(IDEState *s, int lba, int nb_sectors,
1052
                                   int sector_size)
1053
{
1054
    s->lba = lba;
1055
    s->packet_transfer_size = nb_sectors * sector_size;
1056
    s->elementary_transfer_size = 0;
1057
    s->io_buffer_index = sector_size;
1058
    s->cd_sector_size = sector_size;
1059

    
1060
    s->status = READY_STAT;
1061
    ide_atapi_cmd_reply_end(s);
1062
}
1063

    
1064
/* ATAPI DMA support */
1065

    
1066
/* XXX: handle read errors */
1067
static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret)
1068
{
1069
    BMDMAState *bm = opaque;
1070
    IDEState *s = bm->ide_if;
1071
    int data_offset, n;
1072

    
1073
    if (s->io_buffer_size > 0) {
1074
        if (s->cd_sector_size == 2352) {
1075
            n = 1;
1076
            cd_data_to_raw(s->io_buffer, s->lba);
1077
        } else {
1078
            n = s->io_buffer_size >> 11;
1079
        }
1080
        s->packet_transfer_size -= s->io_buffer_size;
1081
        s->lba += n;
1082
        if (dma_buf_rw(bm, 1) == 0)
1083
            goto eot;
1084
    }
1085

    
1086
    if (s->packet_transfer_size <= 0) {
1087
        s->status = READY_STAT;
1088
        s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
1089
        ide_set_irq(s);
1090
    eot:
1091
        bm->status &= ~BM_STATUS_DMAING;
1092
        bm->status |= BM_STATUS_INT;
1093
        bm->dma_cb = NULL;
1094
        bm->ide_if = NULL;
1095
        bm->aiocb = NULL;
1096
        return;
1097
    }
1098
    
1099
    s->io_buffer_index = 0;
1100
    if (s->cd_sector_size == 2352) {
1101
        n = 1;
1102
        s->io_buffer_size = s->cd_sector_size;
1103
        data_offset = 16;
1104
    } else {
1105
        n = s->packet_transfer_size >> 11;
1106
        if (n > (MAX_MULT_SECTORS / 4))
1107
            n = (MAX_MULT_SECTORS / 4);
1108
        s->io_buffer_size = n * 2048;
1109
        data_offset = 0;
1110
    }
1111
#ifdef DEBUG_AIO
1112
    printf("aio_read_cd: lba=%u n=%d\n", s->lba, n);
1113
#endif
1114
    bm->aiocb = bdrv_aio_read(s->bs, (int64_t)s->lba << 2, 
1115
                              s->io_buffer + data_offset, n * 4, 
1116
                              ide_atapi_cmd_read_dma_cb, bm);
1117
}
1118

    
1119
/* start a CD-CDROM read command with DMA */
1120
/* XXX: test if DMA is available */
1121
static void ide_atapi_cmd_read_dma(IDEState *s, int lba, int nb_sectors,
1122
                                   int sector_size)
1123
{
1124
    s->lba = lba;
1125
    s->packet_transfer_size = nb_sectors * sector_size;
1126
    s->io_buffer_index = 0;
1127
    s->io_buffer_size = 0;
1128
    s->cd_sector_size = sector_size;
1129

    
1130
    /* XXX: check if BUSY_STAT should be set */
1131
    s->status = READY_STAT | DRQ_STAT | BUSY_STAT;
1132
    ide_dma_start(s, ide_atapi_cmd_read_dma_cb);
1133
}
1134

    
1135
static void ide_atapi_cmd_read(IDEState *s, int lba, int nb_sectors, 
1136
                               int sector_size)
1137
{
1138
#ifdef DEBUG_IDE_ATAPI
1139
    printf("read: LBA=%d nb_sectors=%d\n", lba, nb_sectors);
1140
#endif
1141
    if (s->atapi_dma) {
1142
        ide_atapi_cmd_read_dma(s, lba, nb_sectors, sector_size);
1143
    } else {
1144
        ide_atapi_cmd_read_pio(s, lba, nb_sectors, sector_size);
1145
    }
1146
}
1147

    
1148
static void ide_atapi_cmd(IDEState *s)
1149
{
1150
    const uint8_t *packet;
1151
    uint8_t *buf;
1152
    int max_len;
1153

    
1154
    packet = s->io_buffer;
1155
    buf = s->io_buffer;
1156
#ifdef DEBUG_IDE_ATAPI
1157
    {
1158
        int i;
1159
        printf("ATAPI limit=0x%x packet:", s->lcyl | (s->hcyl << 8));
1160
        for(i = 0; i < ATAPI_PACKET_SIZE; i++) {
1161
            printf(" %02x", packet[i]);
1162
        }
1163
        printf("\n");
1164
    }
1165
#endif
1166
    switch(s->io_buffer[0]) {
1167
    case GPCMD_TEST_UNIT_READY:
1168
        if (bdrv_is_inserted(s->bs)) {
1169
            ide_atapi_cmd_ok(s);
1170
        } else {
1171
            ide_atapi_cmd_error(s, SENSE_NOT_READY, 
1172
                                ASC_MEDIUM_NOT_PRESENT);
1173
        }
1174
        break;
1175
    case GPCMD_MODE_SENSE_10:
1176
        {
1177
            int action, code;
1178
            max_len = ube16_to_cpu(packet + 7);
1179
            action = packet[2] >> 6;
1180
            code = packet[2] & 0x3f;
1181
            switch(action) {
1182
            case 0: /* current values */
1183
                switch(code) {
1184
                case 0x01: /* error recovery */
1185
                    cpu_to_ube16(&buf[0], 16 + 6);
1186
                    buf[2] = 0x70;
1187
                    buf[3] = 0;
1188
                    buf[4] = 0;
1189
                    buf[5] = 0;
1190
                    buf[6] = 0;
1191
                    buf[7] = 0;
1192

    
1193
                    buf[8] = 0x01;
1194
                    buf[9] = 0x06;
1195
                    buf[10] = 0x00;
1196
                    buf[11] = 0x05;
1197
                    buf[12] = 0x00;
1198
                    buf[13] = 0x00;
1199
                    buf[14] = 0x00;
1200
                    buf[15] = 0x00;
1201
                    ide_atapi_cmd_reply(s, 16, max_len);
1202
                    break;
1203
                case 0x2a:
1204
                    cpu_to_ube16(&buf[0], 28 + 6);
1205
                    buf[2] = 0x70;
1206
                    buf[3] = 0;
1207
                    buf[4] = 0;
1208
                    buf[5] = 0;
1209
                    buf[6] = 0;
1210
                    buf[7] = 0;
1211

    
1212
                    buf[8] = 0x2a;
1213
                    buf[9] = 0x12;
1214
                    buf[10] = 0x00;
1215
                    buf[11] = 0x00;
1216
                    
1217
                    buf[12] = 0x70;
1218
                    buf[13] = 3 << 5;
1219
                    buf[14] = (1 << 0) | (1 << 3) | (1 << 5);
1220
                    if (bdrv_is_locked(s->bs))
1221
                        buf[6] |= 1 << 1;
1222
                    buf[15] = 0x00;
1223
                    cpu_to_ube16(&buf[16], 706);
1224
                    buf[18] = 0;
1225
                    buf[19] = 2;
1226
                    cpu_to_ube16(&buf[20], 512);
1227
                    cpu_to_ube16(&buf[22], 706);
1228
                    buf[24] = 0;
1229
                    buf[25] = 0;
1230
                    buf[26] = 0;
1231
                    buf[27] = 0;
1232
                    ide_atapi_cmd_reply(s, 28, max_len);
1233
                    break;
1234
                default:
1235
                    goto error_cmd;
1236
                }
1237
                break;
1238
            case 1: /* changeable values */
1239
                goto error_cmd;
1240
            case 2: /* default values */
1241
                goto error_cmd;
1242
            default:
1243
            case 3: /* saved values */
1244
                ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, 
1245
                                    ASC_SAVING_PARAMETERS_NOT_SUPPORTED);
1246
                break;
1247
            }
1248
        }
1249
        break;
1250
    case GPCMD_REQUEST_SENSE:
1251
        max_len = packet[4];
1252
        memset(buf, 0, 18);
1253
        buf[0] = 0x70 | (1 << 7);
1254
        buf[2] = s->sense_key;
1255
        buf[7] = 10;
1256
        buf[12] = s->asc;
1257
        ide_atapi_cmd_reply(s, 18, max_len);
1258
        break;
1259
    case GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
1260
        if (bdrv_is_inserted(s->bs)) {
1261
            bdrv_set_locked(s->bs, packet[4] & 1);
1262
            ide_atapi_cmd_ok(s);
1263
        } else {
1264
            ide_atapi_cmd_error(s, SENSE_NOT_READY, 
1265
                                ASC_MEDIUM_NOT_PRESENT);
1266
        }
1267
        break;
1268
    case GPCMD_READ_10:
1269
    case GPCMD_READ_12:
1270
        {
1271
            int nb_sectors, lba;
1272

    
1273
            if (!bdrv_is_inserted(s->bs)) {
1274
                ide_atapi_cmd_error(s, SENSE_NOT_READY, 
1275
                                    ASC_MEDIUM_NOT_PRESENT);
1276
                break;
1277
            }
1278
            if (packet[0] == GPCMD_READ_10)
1279
                nb_sectors = ube16_to_cpu(packet + 7);
1280
            else
1281
                nb_sectors = ube32_to_cpu(packet + 6);
1282
            lba = ube32_to_cpu(packet + 2);
1283
            if (nb_sectors == 0) {
1284
                ide_atapi_cmd_ok(s);
1285
                break;
1286
            }
1287
            if (((int64_t)(lba + nb_sectors) << 2) > s->nb_sectors) {
1288
                ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, 
1289
                                    ASC_LOGICAL_BLOCK_OOR);
1290
                break;
1291
            }
1292
            ide_atapi_cmd_read(s, lba, nb_sectors, 2048);
1293
        }
1294
        break;
1295
    case GPCMD_READ_CD:
1296
        {
1297
            int nb_sectors, lba, transfer_request;
1298

    
1299
            if (!bdrv_is_inserted(s->bs)) {
1300
                ide_atapi_cmd_error(s, SENSE_NOT_READY, 
1301
                                    ASC_MEDIUM_NOT_PRESENT);
1302
                break;
1303
            }
1304
            nb_sectors = (packet[6] << 16) | (packet[7] << 8) | packet[8];
1305
            lba = ube32_to_cpu(packet + 2);
1306
            if (nb_sectors == 0) {
1307
                ide_atapi_cmd_ok(s);
1308
                break;
1309
            }
1310
            if (((int64_t)(lba + nb_sectors) << 2) > s->nb_sectors) {
1311
                ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, 
1312
                                    ASC_LOGICAL_BLOCK_OOR);
1313
                break;
1314
            }
1315
            transfer_request = packet[9];
1316
            switch(transfer_request & 0xf8) {
1317
            case 0x00:
1318
                /* nothing */
1319
                ide_atapi_cmd_ok(s);
1320
                break;
1321
            case 0x10:
1322
                /* normal read */
1323
                ide_atapi_cmd_read(s, lba, nb_sectors, 2048);
1324
                break;
1325
            case 0xf8:
1326
                /* read all data */
1327
                ide_atapi_cmd_read(s, lba, nb_sectors, 2352);
1328
                break;
1329
            default:
1330
                ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, 
1331
                                    ASC_INV_FIELD_IN_CMD_PACKET);
1332
                break;
1333
            }
1334
        }
1335
        break;
1336
    case GPCMD_SEEK:
1337
        {
1338
            int lba;
1339
            if (!bdrv_is_inserted(s->bs)) {
1340
                ide_atapi_cmd_error(s, SENSE_NOT_READY, 
1341
                                    ASC_MEDIUM_NOT_PRESENT);
1342
                break;
1343
            }
1344
            lba = ube32_to_cpu(packet + 2);
1345
            if (((int64_t)lba << 2) > s->nb_sectors) {
1346
                ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, 
1347
                                    ASC_LOGICAL_BLOCK_OOR);
1348
                break;
1349
            }
1350
            ide_atapi_cmd_ok(s);
1351
        }
1352
        break;
1353
    case GPCMD_START_STOP_UNIT:
1354
        {
1355
            int start, eject;
1356
            start = packet[4] & 1;
1357
            eject = (packet[4] >> 1) & 1;
1358
            
1359
            if (eject && !start) {
1360
                /* eject the disk */
1361
                bdrv_close(s->bs);
1362
            }
1363
            ide_atapi_cmd_ok(s);
1364
        }
1365
        break;
1366
    case GPCMD_MECHANISM_STATUS:
1367
        {
1368
            max_len = ube16_to_cpu(packet + 8);
1369
            cpu_to_ube16(buf, 0);
1370
            /* no current LBA */
1371
            buf[2] = 0;
1372
            buf[3] = 0;
1373
            buf[4] = 0;
1374
            buf[5] = 1;
1375
            cpu_to_ube16(buf + 6, 0);
1376
            ide_atapi_cmd_reply(s, 8, max_len);
1377
        }
1378
        break;
1379
    case GPCMD_READ_TOC_PMA_ATIP:
1380
        {
1381
            int format, msf, start_track, len;
1382

    
1383
            if (!bdrv_is_inserted(s->bs)) {
1384
                ide_atapi_cmd_error(s, SENSE_NOT_READY, 
1385
                                    ASC_MEDIUM_NOT_PRESENT);
1386
                break;
1387
            }
1388
            max_len = ube16_to_cpu(packet + 7);
1389
            format = packet[9] >> 6;
1390
            msf = (packet[1] >> 1) & 1;
1391
            start_track = packet[6];
1392
            switch(format) {
1393
            case 0:
1394
                len = cdrom_read_toc(s->nb_sectors >> 2, buf, msf, start_track);
1395
                if (len < 0)
1396
                    goto error_cmd;
1397
                ide_atapi_cmd_reply(s, len, max_len);
1398
                break;
1399
            case 1:
1400
                /* multi session : only a single session defined */
1401
                memset(buf, 0, 12);
1402
                buf[1] = 0x0a;
1403
                buf[2] = 0x01;
1404
                buf[3] = 0x01;
1405
                ide_atapi_cmd_reply(s, 12, max_len);
1406
                break;
1407
            case 2:
1408
                len = cdrom_read_toc_raw(s->nb_sectors >> 2, buf, msf, start_track);
1409
                if (len < 0)
1410
                    goto error_cmd;
1411
                ide_atapi_cmd_reply(s, len, max_len);
1412
                break;
1413
            default:
1414
            error_cmd:
1415
                ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, 
1416
                                    ASC_INV_FIELD_IN_CMD_PACKET);
1417
                break;
1418
            }
1419
        }
1420
        break;
1421
    case GPCMD_READ_CDVD_CAPACITY:
1422
        if (!bdrv_is_inserted(s->bs)) {
1423
            ide_atapi_cmd_error(s, SENSE_NOT_READY, 
1424
                                ASC_MEDIUM_NOT_PRESENT);
1425
            break;
1426
        }
1427
        /* NOTE: it is really the number of sectors minus 1 */
1428
        cpu_to_ube32(buf, (s->nb_sectors >> 2) - 1);
1429
        cpu_to_ube32(buf + 4, 2048);
1430
        ide_atapi_cmd_reply(s, 8, 8);
1431
        break;
1432
    case GPCMD_INQUIRY:
1433
        max_len = packet[4];
1434
        buf[0] = 0x05; /* CD-ROM */
1435
        buf[1] = 0x80; /* removable */
1436
        buf[2] = 0x00; /* ISO */
1437
        buf[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */
1438
        buf[4] = 31; /* additionnal length */
1439
        buf[5] = 0; /* reserved */
1440
        buf[6] = 0; /* reserved */
1441
        buf[7] = 0; /* reserved */
1442
        padstr8(buf + 8, 8, "QEMU");
1443
        padstr8(buf + 16, 16, "QEMU CD-ROM");
1444
        padstr8(buf + 32, 4, QEMU_VERSION);
1445
        ide_atapi_cmd_reply(s, 36, max_len);
1446
        break;
1447
    default:
1448
        ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, 
1449
                            ASC_ILLEGAL_OPCODE);
1450
        break;
1451
    }
1452
}
1453

    
1454
/* called when the inserted state of the media has changed */
1455
static void cdrom_change_cb(void *opaque)
1456
{
1457
    IDEState *s = opaque;
1458
    int64_t nb_sectors;
1459

    
1460
    /* XXX: send interrupt too */
1461
    bdrv_get_geometry(s->bs, &nb_sectors);
1462
    s->nb_sectors = nb_sectors;
1463
}
1464

    
1465
static void ide_cmd_lba48_transform(IDEState *s, int lba48)
1466
{
1467
    s->lba48 = lba48;
1468

    
1469
    /* handle the 'magic' 0 nsector count conversion here. to avoid
1470
     * fiddling with the rest of the read logic, we just store the
1471
     * full sector count in ->nsector and ignore ->hob_nsector from now
1472
     */
1473
    if (!s->lba48) {
1474
        if (!s->nsector)
1475
            s->nsector = 256;
1476
    } else {
1477
        if (!s->nsector && !s->hob_nsector)
1478
            s->nsector = 65536;
1479
        else {
1480
            int lo = s->nsector;
1481
            int hi = s->hob_nsector;
1482

    
1483
            s->nsector = (hi << 8) | lo;
1484
        }
1485
    }
1486
}
1487

    
1488
static void ide_clear_hob(IDEState *ide_if)
1489
{
1490
    /* any write clears HOB high bit of device control register */
1491
    ide_if[0].select &= ~(1 << 7);
1492
    ide_if[1].select &= ~(1 << 7);
1493
}
1494

    
1495
static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1496
{
1497
    IDEState *ide_if = opaque;
1498
    IDEState *s;
1499
    int unit, n;
1500
    int lba48 = 0;
1501

    
1502
#ifdef DEBUG_IDE
1503
    printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
1504
#endif
1505

    
1506
    addr &= 7;
1507
    switch(addr) {
1508
    case 0:
1509
        break;
1510
    case 1:
1511
        ide_clear_hob(ide_if);
1512
        /* NOTE: data is written to the two drives */
1513
        ide_if[0].hob_feature = ide_if[0].feature;
1514
        ide_if[1].hob_feature = ide_if[1].feature;
1515
        ide_if[0].feature = val;
1516
        ide_if[1].feature = val;
1517
        break;
1518
    case 2:
1519
        ide_clear_hob(ide_if);
1520
        ide_if[0].hob_nsector = ide_if[0].nsector;
1521
        ide_if[1].hob_nsector = ide_if[1].nsector;
1522
        ide_if[0].nsector = val;
1523
        ide_if[1].nsector = val;
1524
        break;
1525
    case 3:
1526
        ide_clear_hob(ide_if);
1527
        ide_if[0].hob_sector = ide_if[0].sector;
1528
        ide_if[1].hob_sector = ide_if[1].sector;
1529
        ide_if[0].sector = val;
1530
        ide_if[1].sector = val;
1531
        break;
1532
    case 4:
1533
        ide_clear_hob(ide_if);
1534
        ide_if[0].hob_lcyl = ide_if[0].lcyl;
1535
        ide_if[1].hob_lcyl = ide_if[1].lcyl;
1536
        ide_if[0].lcyl = val;
1537
        ide_if[1].lcyl = val;
1538
        break;
1539
    case 5:
1540
        ide_clear_hob(ide_if);
1541
        ide_if[0].hob_hcyl = ide_if[0].hcyl;
1542
        ide_if[1].hob_hcyl = ide_if[1].hcyl;
1543
        ide_if[0].hcyl = val;
1544
        ide_if[1].hcyl = val;
1545
        break;
1546
    case 6:
1547
        /* FIXME: HOB readback uses bit 7 */
1548
        ide_if[0].select = (val & ~0x10) | 0xa0;
1549
        ide_if[1].select = (val | 0x10) | 0xa0;
1550
        /* select drive */
1551
        unit = (val >> 4) & 1;
1552
        s = ide_if + unit;
1553
        ide_if->cur_drive = s;
1554
        break;
1555
    default:
1556
    case 7:
1557
        /* command */
1558
#if defined(DEBUG_IDE)
1559
        printf("ide: CMD=%02x\n", val);
1560
#endif
1561
        s = ide_if->cur_drive;
1562
        /* ignore commands to non existant slave */
1563
        if (s != ide_if && !s->bs) 
1564
            break;
1565

    
1566
        switch(val) {
1567
        case WIN_IDENTIFY:
1568
            if (s->bs && !s->is_cdrom) {
1569
                ide_identify(s);
1570
                s->status = READY_STAT | SEEK_STAT;
1571
                ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1572
            } else {
1573
                if (s->is_cdrom) {
1574
                    ide_set_signature(s);
1575
                }
1576
                ide_abort_command(s);
1577
            }
1578
            ide_set_irq(s);
1579
            break;
1580
        case WIN_SPECIFY:
1581
        case WIN_RECAL:
1582
            s->error = 0;
1583
            s->status = READY_STAT | SEEK_STAT;
1584
            ide_set_irq(s);
1585
            break;
1586
        case WIN_SETMULT:
1587
            if (s->nsector > MAX_MULT_SECTORS || 
1588
                s->nsector == 0 ||
1589
                (s->nsector & (s->nsector - 1)) != 0) {
1590
                ide_abort_command(s);
1591
            } else {
1592
                s->mult_sectors = s->nsector;
1593
                s->status = READY_STAT;
1594
            }
1595
            ide_set_irq(s);
1596
            break;
1597
        case WIN_VERIFY_EXT:
1598
            lba48 = 1;
1599
        case WIN_VERIFY:
1600
        case WIN_VERIFY_ONCE:
1601
            /* do sector number check ? */
1602
            ide_cmd_lba48_transform(s, lba48);
1603
            s->status = READY_STAT;
1604
            ide_set_irq(s);
1605
            break;
1606
        case WIN_READ_EXT:
1607
            lba48 = 1;
1608
        case WIN_READ:
1609
        case WIN_READ_ONCE:
1610
            if (!s->bs) 
1611
                goto abort_cmd;
1612
            ide_cmd_lba48_transform(s, lba48);
1613
            s->req_nb_sectors = 1;
1614
            ide_sector_read(s);
1615
            break;
1616
        case WIN_WRITE_EXT:
1617
            lba48 = 1;
1618
        case WIN_WRITE:
1619
        case WIN_WRITE_ONCE:
1620
            ide_cmd_lba48_transform(s, lba48);
1621
            s->error = 0;
1622
            s->status = SEEK_STAT | READY_STAT;
1623
            s->req_nb_sectors = 1;
1624
            ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1625
            break;
1626
        case WIN_MULTREAD_EXT:
1627
            lba48 = 1;
1628
        case WIN_MULTREAD:
1629
            if (!s->mult_sectors)
1630
                goto abort_cmd;
1631
            ide_cmd_lba48_transform(s, lba48);
1632
            s->req_nb_sectors = s->mult_sectors;
1633
            ide_sector_read(s);
1634
            break;
1635
        case WIN_MULTWRITE_EXT:
1636
            lba48 = 1;
1637
        case WIN_MULTWRITE:
1638
            if (!s->mult_sectors)
1639
                goto abort_cmd;
1640
            ide_cmd_lba48_transform(s, lba48);
1641
            s->error = 0;
1642
            s->status = SEEK_STAT | READY_STAT;
1643
            s->req_nb_sectors = s->mult_sectors;
1644
            n = s->nsector;
1645
            if (n > s->req_nb_sectors)
1646
                n = s->req_nb_sectors;
1647
            ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1648
            break;
1649
        case WIN_READDMA_EXT:
1650
            lba48 = 1;
1651
        case WIN_READDMA:
1652
        case WIN_READDMA_ONCE:
1653
            if (!s->bs) 
1654
                goto abort_cmd;
1655
            ide_cmd_lba48_transform(s, lba48);
1656
            ide_sector_read_dma(s);
1657
            break;
1658
        case WIN_WRITEDMA_EXT:
1659
            lba48 = 1;
1660
        case WIN_WRITEDMA:
1661
        case WIN_WRITEDMA_ONCE:
1662
            if (!s->bs) 
1663
                goto abort_cmd;
1664
            ide_cmd_lba48_transform(s, lba48);
1665
            ide_sector_write_dma(s);
1666
            break;
1667
        case WIN_READ_NATIVE_MAX_EXT:
1668
            lba48 = 1;
1669
        case WIN_READ_NATIVE_MAX:
1670
            ide_cmd_lba48_transform(s, lba48);
1671
            ide_set_sector(s, s->nb_sectors - 1);
1672
            s->status = READY_STAT;
1673
            ide_set_irq(s);
1674
            break;
1675
        case WIN_CHECKPOWERMODE1:
1676
            s->nsector = 0xff; /* device active or idle */
1677
            s->status = READY_STAT;
1678
            ide_set_irq(s);
1679
            break;
1680
        case WIN_SETFEATURES:
1681
            if (!s->bs)
1682
                goto abort_cmd;
1683
            /* XXX: valid for CDROM ? */
1684
            switch(s->feature) {
1685
            case 0x02: /* write cache enable */
1686
            case 0x82: /* write cache disable */
1687
            case 0xaa: /* read look-ahead enable */
1688
            case 0x55: /* read look-ahead disable */
1689
                s->status = READY_STAT | SEEK_STAT;
1690
                ide_set_irq(s);
1691
                break;
1692
            case 0x03: { /* set transfer mode */
1693
                uint8_t val = s->nsector & 0x07;
1694

    
1695
                switch (s->nsector >> 3) {
1696
                    case 0x00: /* pio default */
1697
                    case 0x01: /* pio mode */
1698
                        put_le16(s->identify_data + 63,0x07);
1699
                        put_le16(s->identify_data + 88,0x3f);
1700
                        break;
1701
                    case 0x04: /* mdma mode */
1702
                        put_le16(s->identify_data + 63,0x07 | (1 << (val + 8)));
1703
                        put_le16(s->identify_data + 88,0x3f);
1704
                        break;
1705
                    case 0x08: /* udma mode */
1706
                        put_le16(s->identify_data + 63,0x07);
1707
                        put_le16(s->identify_data + 88,0x3f | (1 << (val + 8)));
1708
                        break;
1709
                    default:
1710
                        goto abort_cmd;
1711
                }
1712
                s->status = READY_STAT | SEEK_STAT;
1713
                ide_set_irq(s);
1714
                break;
1715
            }
1716
            default:
1717
                goto abort_cmd;
1718
            }
1719
            break;
1720
        case WIN_FLUSH_CACHE:
1721
        case WIN_FLUSH_CACHE_EXT:
1722
            if (s->bs)
1723
                bdrv_flush(s->bs);
1724
            s->status = READY_STAT;
1725
            ide_set_irq(s);
1726
            break;
1727
        case WIN_STANDBYNOW1:
1728
        case WIN_IDLEIMMEDIATE:
1729
            s->status = READY_STAT;
1730
            ide_set_irq(s);
1731
            break;
1732
            /* ATAPI commands */
1733
        case WIN_PIDENTIFY:
1734
            if (s->is_cdrom) {
1735
                ide_atapi_identify(s);
1736
                s->status = READY_STAT | SEEK_STAT;
1737
                ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1738
            } else {
1739
                ide_abort_command(s);
1740
            }
1741
            ide_set_irq(s);
1742
            break;
1743
        case WIN_DIAGNOSE:
1744
            ide_set_signature(s);
1745
            s->status = 0x00; /* NOTE: READY is _not_ set */
1746
            s->error = 0x01;
1747
            break;
1748
        case WIN_SRST:
1749
            if (!s->is_cdrom)
1750
                goto abort_cmd;
1751
            ide_set_signature(s);
1752
            s->status = 0x00; /* NOTE: READY is _not_ set */
1753
            s->error = 0x01;
1754
            break;
1755
        case WIN_PACKETCMD:
1756
            if (!s->is_cdrom)
1757
                goto abort_cmd;
1758
            /* overlapping commands not supported */
1759
            if (s->feature & 0x02)
1760
                goto abort_cmd;
1761
            s->atapi_dma = s->feature & 1;
1762
            s->nsector = 1;
1763
            ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE, 
1764
                               ide_atapi_cmd);
1765
            break;
1766
        default:
1767
        abort_cmd:
1768
            ide_abort_command(s);
1769
            ide_set_irq(s);
1770
            break;
1771
        }
1772
    }
1773
}
1774

    
1775
static uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
1776
{
1777
    IDEState *ide_if = opaque;
1778
    IDEState *s = ide_if->cur_drive;
1779
    uint32_t addr;
1780
    int ret, hob;
1781

    
1782
    addr = addr1 & 7;
1783
    /* FIXME: HOB readback uses bit 7, but it's always set right now */
1784
    //hob = s->select & (1 << 7);
1785
    hob = 0;
1786
    switch(addr) {
1787
    case 0:
1788
        ret = 0xff;
1789
        break;
1790
    case 1:
1791
        if (!ide_if[0].bs && !ide_if[1].bs)
1792
            ret = 0;
1793
        else if (!hob)
1794
            ret = s->error;
1795
        else
1796
            ret = s->hob_feature;
1797
        break;
1798
    case 2:
1799
        if (!ide_if[0].bs && !ide_if[1].bs)
1800
            ret = 0;
1801
        else if (!hob)
1802
            ret = s->nsector & 0xff;
1803
        else
1804
            ret = s->hob_nsector;
1805
        break;
1806
    case 3:
1807
        if (!ide_if[0].bs && !ide_if[1].bs)
1808
            ret = 0;
1809
        else if (!hob)
1810
            ret = s->sector;
1811
        else
1812
            ret = s->hob_sector;
1813
        break;
1814
    case 4:
1815
        if (!ide_if[0].bs && !ide_if[1].bs)
1816
            ret = 0;
1817
        else if (!hob)
1818
            ret = s->lcyl;
1819
        else
1820
            ret = s->hob_lcyl;
1821
        break;
1822
    case 5:
1823
        if (!ide_if[0].bs && !ide_if[1].bs)
1824
            ret = 0;
1825
        else if (!hob)
1826
            ret = s->hcyl;
1827
        else
1828
            ret = s->hob_hcyl;
1829
        break;
1830
    case 6:
1831
        if (!ide_if[0].bs && !ide_if[1].bs)
1832
            ret = 0;
1833
        else
1834
            ret = s->select;
1835
        break;
1836
    default:
1837
    case 7:
1838
        if ((!ide_if[0].bs && !ide_if[1].bs) ||
1839
            (s != ide_if && !s->bs))
1840
            ret = 0;
1841
        else
1842
            ret = s->status;
1843
        s->set_irq(s->irq_opaque, s->irq, 0);
1844
        break;
1845
    }
1846
#ifdef DEBUG_IDE
1847
    printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1848
#endif
1849
    return ret;
1850
}
1851

    
1852
static uint32_t ide_status_read(void *opaque, uint32_t addr)
1853
{
1854
    IDEState *ide_if = opaque;
1855
    IDEState *s = ide_if->cur_drive;
1856
    int ret;
1857

    
1858
    if ((!ide_if[0].bs && !ide_if[1].bs) ||
1859
        (s != ide_if && !s->bs))
1860
        ret = 0;
1861
    else
1862
        ret = s->status;
1863
#ifdef DEBUG_IDE
1864
    printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1865
#endif
1866
    return ret;
1867
}
1868

    
1869
static void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
1870
{
1871
    IDEState *ide_if = opaque;
1872
    IDEState *s;
1873
    int i;
1874

    
1875
#ifdef DEBUG_IDE
1876
    printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1877
#endif
1878
    /* common for both drives */
1879
    if (!(ide_if[0].cmd & IDE_CMD_RESET) &&
1880
        (val & IDE_CMD_RESET)) {
1881
        /* reset low to high */
1882
        for(i = 0;i < 2; i++) {
1883
            s = &ide_if[i];
1884
            s->status = BUSY_STAT | SEEK_STAT;
1885
            s->error = 0x01;
1886
        }
1887
    } else if ((ide_if[0].cmd & IDE_CMD_RESET) &&
1888
               !(val & IDE_CMD_RESET)) {
1889
        /* high to low */
1890
        for(i = 0;i < 2; i++) {
1891
            s = &ide_if[i];
1892
            if (s->is_cdrom)
1893
                s->status = 0x00; /* NOTE: READY is _not_ set */
1894
            else
1895
                s->status = READY_STAT | SEEK_STAT;
1896
            ide_set_signature(s);
1897
        }
1898
    }
1899

    
1900
    ide_if[0].cmd = val;
1901
    ide_if[1].cmd = val;
1902
}
1903

    
1904
static void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
1905
{
1906
    IDEState *s = ((IDEState *)opaque)->cur_drive;
1907
    uint8_t *p;
1908

    
1909
    p = s->data_ptr;
1910
    *(uint16_t *)p = le16_to_cpu(val);
1911
    p += 2;
1912
    s->data_ptr = p;
1913
    if (p >= s->data_end)
1914
        s->end_transfer_func(s);
1915
}
1916

    
1917
static uint32_t ide_data_readw(void *opaque, uint32_t addr)
1918
{
1919
    IDEState *s = ((IDEState *)opaque)->cur_drive;
1920
    uint8_t *p;
1921
    int ret;
1922
    p = s->data_ptr;
1923
    ret = cpu_to_le16(*(uint16_t *)p);
1924
    p += 2;
1925
    s->data_ptr = p;
1926
    if (p >= s->data_end)
1927
        s->end_transfer_func(s);
1928
    return ret;
1929
}
1930

    
1931
static void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
1932
{
1933
    IDEState *s = ((IDEState *)opaque)->cur_drive;
1934
    uint8_t *p;
1935

    
1936
    p = s->data_ptr;
1937
    *(uint32_t *)p = le32_to_cpu(val);
1938
    p += 4;
1939
    s->data_ptr = p;
1940
    if (p >= s->data_end)
1941
        s->end_transfer_func(s);
1942
}
1943

    
1944
static uint32_t ide_data_readl(void *opaque, uint32_t addr)
1945
{
1946
    IDEState *s = ((IDEState *)opaque)->cur_drive;
1947
    uint8_t *p;
1948
    int ret;
1949
    
1950
    p = s->data_ptr;
1951
    ret = cpu_to_le32(*(uint32_t *)p);
1952
    p += 4;
1953
    s->data_ptr = p;
1954
    if (p >= s->data_end)
1955
        s->end_transfer_func(s);
1956
    return ret;
1957
}
1958

    
1959
static void ide_dummy_transfer_stop(IDEState *s)
1960
{
1961
    s->data_ptr = s->io_buffer;
1962
    s->data_end = s->io_buffer;
1963
    s->io_buffer[0] = 0xff;
1964
    s->io_buffer[1] = 0xff;
1965
    s->io_buffer[2] = 0xff;
1966
    s->io_buffer[3] = 0xff;
1967
}
1968

    
1969
static void ide_reset(IDEState *s)
1970
{
1971
    s->mult_sectors = MAX_MULT_SECTORS;
1972
    s->cur_drive = s;
1973
    s->select = 0xa0;
1974
    s->status = READY_STAT;
1975
    ide_set_signature(s);
1976
    /* init the transfer handler so that 0xffff is returned on data
1977
       accesses */
1978
    s->end_transfer_func = ide_dummy_transfer_stop;
1979
    ide_dummy_transfer_stop(s);
1980
}
1981

    
1982
struct partition {
1983
        uint8_t boot_ind;                /* 0x80 - active */
1984
        uint8_t head;                /* starting head */
1985
        uint8_t sector;                /* starting sector */
1986
        uint8_t cyl;                /* starting cylinder */
1987
        uint8_t sys_ind;                /* What partition type */
1988
        uint8_t end_head;                /* end head */
1989
        uint8_t end_sector;        /* end sector */
1990
        uint8_t end_cyl;                /* end cylinder */
1991
        uint32_t start_sect;        /* starting sector counting from 0 */
1992
        uint32_t nr_sects;                /* nr of sectors in partition */
1993
} __attribute__((packed));
1994

    
1995
/* try to guess the disk logical geometry from the MSDOS partition table. Return 0 if OK, -1 if could not guess */
1996
static int guess_disk_lchs(IDEState *s, 
1997
                           int *pcylinders, int *pheads, int *psectors)
1998
{
1999
    uint8_t buf[512];
2000
    int ret, i, heads, sectors, cylinders;
2001
    struct partition *p;
2002
    uint32_t nr_sects;
2003

    
2004
    ret = bdrv_read(s->bs, 0, buf, 1);
2005
    if (ret < 0)
2006
        return -1;
2007
    /* test msdos magic */
2008
    if (buf[510] != 0x55 || buf[511] != 0xaa)
2009
        return -1;
2010
    for(i = 0; i < 4; i++) {
2011
        p = ((struct partition *)(buf + 0x1be)) + i;
2012
        nr_sects = le32_to_cpu(p->nr_sects);
2013
        if (nr_sects && p->end_head) {
2014
            /* We make the assumption that the partition terminates on
2015
               a cylinder boundary */
2016
            heads = p->end_head + 1;
2017
            sectors = p->end_sector & 63;
2018
            if (sectors == 0)
2019
                continue;
2020
            cylinders = s->nb_sectors / (heads * sectors);
2021
            if (cylinders < 1 || cylinders > 16383)
2022
                continue;
2023
            *pheads = heads;
2024
            *psectors = sectors;
2025
            *pcylinders = cylinders;
2026
#if 0
2027
            printf("guessed geometry: LCHS=%d %d %d\n", 
2028
                   cylinders, heads, sectors);
2029
#endif
2030
            return 0;
2031
        }
2032
    }
2033
    return -1;
2034
}
2035

    
2036
static void ide_init2(IDEState *ide_state,
2037
                      BlockDriverState *hd0, BlockDriverState *hd1,
2038
                      SetIRQFunc *set_irq, void *irq_opaque, int irq)
2039
{
2040
    IDEState *s;
2041
    static int drive_serial = 1;
2042
    int i, cylinders, heads, secs, translation;
2043
    int64_t nb_sectors;
2044

    
2045
    for(i = 0; i < 2; i++) {
2046
        s = ide_state + i;
2047
        if (i == 0)
2048
            s->bs = hd0;
2049
        else
2050
            s->bs = hd1;
2051
        if (s->bs) {
2052
            bdrv_get_geometry(s->bs, &nb_sectors);
2053
            s->nb_sectors = nb_sectors;
2054
            /* if a geometry hint is available, use it */
2055
            bdrv_get_geometry_hint(s->bs, &cylinders, &heads, &secs);
2056
            if (cylinders != 0) {
2057
                s->cylinders = cylinders;
2058
                s->heads = heads;
2059
                s->sectors = secs;
2060
            } else {
2061
                if (guess_disk_lchs(s, &cylinders, &heads, &secs) == 0) {
2062
                    if (heads > 16) {
2063
                        /* if heads > 16, it means that a BIOS LBA
2064
                           translation was active, so the default
2065
                           hardware geometry is OK */
2066
                        goto default_geometry;
2067
                    } else {
2068
                        s->cylinders = cylinders;
2069
                        s->heads = heads;
2070
                        s->sectors = secs;
2071
                        /* disable any translation to be in sync with
2072
                           the logical geometry */
2073
                        translation = bdrv_get_translation_hint(s->bs);
2074
                        if (translation == BIOS_ATA_TRANSLATION_AUTO) {
2075
                            bdrv_set_translation_hint(s->bs,
2076
                                                      BIOS_ATA_TRANSLATION_NONE);
2077
                        }
2078
                    }
2079
                } else {
2080
                default_geometry:
2081
                    /* if no geometry, use a standard physical disk geometry */
2082
                    cylinders = nb_sectors / (16 * 63);
2083
                    if (cylinders > 16383)
2084
                        cylinders = 16383;
2085
                    else if (cylinders < 2)
2086
                        cylinders = 2;
2087
                    s->cylinders = cylinders;
2088
                    s->heads = 16;
2089
                    s->sectors = 63;
2090
                }
2091
                bdrv_set_geometry_hint(s->bs, s->cylinders, s->heads, s->sectors);
2092
            }
2093
            if (bdrv_get_type_hint(s->bs) == BDRV_TYPE_CDROM) {
2094
                s->is_cdrom = 1;
2095
                bdrv_set_change_cb(s->bs, cdrom_change_cb, s);
2096
            }
2097
        }
2098
        s->drive_serial = drive_serial++;
2099
        s->set_irq = set_irq;
2100
        s->irq_opaque = irq_opaque;
2101
        s->irq = irq;
2102
        s->sector_write_timer = qemu_new_timer(vm_clock, 
2103
                                               ide_sector_write_timer_cb, s);
2104
        ide_reset(s);
2105
    }
2106
}
2107

    
2108
static void ide_init_ioport(IDEState *ide_state, int iobase, int iobase2)
2109
{
2110
    register_ioport_write(iobase, 8, 1, ide_ioport_write, ide_state);
2111
    register_ioport_read(iobase, 8, 1, ide_ioport_read, ide_state);
2112
    if (iobase2) {
2113
        register_ioport_read(iobase2, 1, 1, ide_status_read, ide_state);
2114
        register_ioport_write(iobase2, 1, 1, ide_cmd_write, ide_state);
2115
    }
2116
    
2117
    /* data ports */
2118
    register_ioport_write(iobase, 2, 2, ide_data_writew, ide_state);
2119
    register_ioport_read(iobase, 2, 2, ide_data_readw, ide_state);
2120
    register_ioport_write(iobase, 4, 4, ide_data_writel, ide_state);
2121
    register_ioport_read(iobase, 4, 4, ide_data_readl, ide_state);
2122
}
2123

    
2124
/***********************************************************/
2125
/* ISA IDE definitions */
2126

    
2127
void isa_ide_init(int iobase, int iobase2, int irq,
2128
                  BlockDriverState *hd0, BlockDriverState *hd1)
2129
{
2130
    IDEState *ide_state;
2131

    
2132
    ide_state = qemu_mallocz(sizeof(IDEState) * 2);
2133
    if (!ide_state)
2134
        return;
2135
    
2136
    ide_init2(ide_state, hd0, hd1, pic_set_irq_new, isa_pic, irq);
2137
    ide_init_ioport(ide_state, iobase, iobase2);
2138
}
2139

    
2140
/***********************************************************/
2141
/* PCI IDE definitions */
2142

    
2143
static void cmd646_update_irq(PCIIDEState *d);
2144

    
2145
static void ide_map(PCIDevice *pci_dev, int region_num, 
2146
                    uint32_t addr, uint32_t size, int type)
2147
{
2148
    PCIIDEState *d = (PCIIDEState *)pci_dev;
2149
    IDEState *ide_state;
2150

    
2151
    if (region_num <= 3) {
2152
        ide_state = &d->ide_if[(region_num >> 1) * 2];
2153
        if (region_num & 1) {
2154
            register_ioport_read(addr + 2, 1, 1, ide_status_read, ide_state);
2155
            register_ioport_write(addr + 2, 1, 1, ide_cmd_write, ide_state);
2156
        } else {
2157
            register_ioport_write(addr, 8, 1, ide_ioport_write, ide_state);
2158
            register_ioport_read(addr, 8, 1, ide_ioport_read, ide_state);
2159

    
2160
            /* data ports */
2161
            register_ioport_write(addr, 2, 2, ide_data_writew, ide_state);
2162
            register_ioport_read(addr, 2, 2, ide_data_readw, ide_state);
2163
            register_ioport_write(addr, 4, 4, ide_data_writel, ide_state);
2164
            register_ioport_read(addr, 4, 4, ide_data_readl, ide_state);
2165
        }
2166
    }
2167
}
2168

    
2169
static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb)
2170
{
2171
    BMDMAState *bm = s->bmdma;
2172
    if(!bm)
2173
        return;
2174
    bm->ide_if = s;
2175
    bm->dma_cb = dma_cb;
2176
    bm->cur_addr = bm->addr;
2177
    bm->cur_prd_last = 0;
2178
    bm->cur_prd_addr = 0;
2179
    bm->cur_prd_len = 0;
2180
    if (bm->status & BM_STATUS_DMAING) {
2181
        bm->dma_cb(bm, 0);
2182
    }
2183
}
2184

    
2185
static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
2186
{
2187
    BMDMAState *bm = opaque;
2188
#ifdef DEBUG_IDE
2189
    printf("%s: 0x%08x\n", __func__, val);
2190
#endif
2191
    if (!(val & BM_CMD_START)) {
2192
        /* XXX: do it better */
2193
        if (bm->status & BM_STATUS_DMAING) {
2194
            bm->status &= ~BM_STATUS_DMAING;
2195
            /* cancel DMA request */
2196
            bm->ide_if = NULL;
2197
            bm->dma_cb = NULL;
2198
            if (bm->aiocb) {
2199
#ifdef DEBUG_AIO
2200
                printf("aio_cancel\n");
2201
#endif
2202
                bdrv_aio_cancel(bm->aiocb);
2203
                bm->aiocb = NULL;
2204
            }
2205
        }
2206
        bm->cmd = val & 0x09;
2207
    } else {
2208
        if (!(bm->status & BM_STATUS_DMAING)) {
2209
            bm->status |= BM_STATUS_DMAING;
2210
            /* start dma transfer if possible */
2211
            if (bm->dma_cb)
2212
                bm->dma_cb(bm, 0);
2213
        }
2214
        bm->cmd = val & 0x09;
2215
    }
2216
}
2217

    
2218
static uint32_t bmdma_readb(void *opaque, uint32_t addr)
2219
{
2220
    BMDMAState *bm = opaque;
2221
    PCIIDEState *pci_dev;
2222
    uint32_t val;
2223
    
2224
    switch(addr & 3) {
2225
    case 0: 
2226
        val = bm->cmd;
2227
        break;
2228
    case 1:
2229
        pci_dev = bm->pci_dev;
2230
        if (pci_dev->type == IDE_TYPE_CMD646) {
2231
            val = pci_dev->dev.config[MRDMODE];
2232
        } else {
2233
            val = 0xff;
2234
        }
2235
        break;
2236
    case 2:
2237
        val = bm->status;
2238
        break;
2239
    case 3:
2240
        pci_dev = bm->pci_dev;
2241
        if (pci_dev->type == IDE_TYPE_CMD646) {
2242
            if (bm == &pci_dev->bmdma[0])
2243
                val = pci_dev->dev.config[UDIDETCR0];
2244
            else
2245
                val = pci_dev->dev.config[UDIDETCR1];
2246
        } else {
2247
            val = 0xff;
2248
        }
2249
        break;
2250
    default:
2251
        val = 0xff;
2252
        break;
2253
    }
2254
#ifdef DEBUG_IDE
2255
    printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
2256
#endif
2257
    return val;
2258
}
2259

    
2260
static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
2261
{
2262
    BMDMAState *bm = opaque;
2263
    PCIIDEState *pci_dev;
2264
#ifdef DEBUG_IDE
2265
    printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
2266
#endif
2267
    switch(addr & 3) {
2268
    case 1:
2269
        pci_dev = bm->pci_dev;
2270
        if (pci_dev->type == IDE_TYPE_CMD646) {
2271
            pci_dev->dev.config[MRDMODE] = 
2272
                (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
2273
            cmd646_update_irq(pci_dev);
2274
        }
2275
        break;
2276
    case 2:
2277
        bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
2278
        break;
2279
    case 3:
2280
        pci_dev = bm->pci_dev;
2281
        if (pci_dev->type == IDE_TYPE_CMD646) {
2282
            if (bm == &pci_dev->bmdma[0])
2283
                pci_dev->dev.config[UDIDETCR0] = val;
2284
            else
2285
                pci_dev->dev.config[UDIDETCR1] = val;
2286
        }
2287
        break;
2288
    }
2289
}
2290

    
2291
static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr)
2292
{
2293
    BMDMAState *bm = opaque;
2294
    uint32_t val;
2295
    val = bm->addr;
2296
#ifdef DEBUG_IDE
2297
    printf("%s: 0x%08x\n", __func__, val);
2298
#endif
2299
    return val;
2300
}
2301

    
2302
static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val)
2303
{
2304
    BMDMAState *bm = opaque;
2305
#ifdef DEBUG_IDE
2306
    printf("%s: 0x%08x\n", __func__, val);
2307
#endif
2308
    bm->addr = val & ~3;
2309
}
2310

    
2311
static void bmdma_map(PCIDevice *pci_dev, int region_num, 
2312
                    uint32_t addr, uint32_t size, int type)
2313
{
2314
    PCIIDEState *d = (PCIIDEState *)pci_dev;
2315
    int i;
2316

    
2317
    for(i = 0;i < 2; i++) {
2318
        BMDMAState *bm = &d->bmdma[i];
2319
        d->ide_if[2 * i].bmdma = bm;
2320
        d->ide_if[2 * i + 1].bmdma = bm;
2321
        bm->pci_dev = (PCIIDEState *)pci_dev;
2322

    
2323
        register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
2324

    
2325
        register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
2326
        register_ioport_read(addr, 4, 1, bmdma_readb, bm);
2327

    
2328
        register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
2329
        register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
2330
        addr += 8;
2331
    }
2332
}
2333

    
2334
/* XXX: call it also when the MRDMODE is changed from the PCI config
2335
   registers */
2336
static void cmd646_update_irq(PCIIDEState *d)
2337
{
2338
    int pci_level;
2339
    pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) &&
2340
                 !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) ||
2341
        ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) &&
2342
         !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1));
2343
    pci_set_irq((PCIDevice *)d, 0, pci_level);
2344
}
2345

    
2346
/* the PCI irq level is the logical OR of the two channels */
2347
static void cmd646_set_irq(void *opaque, int channel, int level)
2348
{
2349
    PCIIDEState *d = opaque;
2350
    int irq_mask;
2351

    
2352
    irq_mask = MRDMODE_INTR_CH0 << channel;
2353
    if (level)
2354
        d->dev.config[MRDMODE] |= irq_mask;
2355
    else
2356
        d->dev.config[MRDMODE] &= ~irq_mask;
2357
    cmd646_update_irq(d);
2358
}
2359

    
2360
/* CMD646 PCI IDE controller */
2361
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
2362
                         int secondary_ide_enabled)
2363
{
2364
    PCIIDEState *d;
2365
    uint8_t *pci_conf;
2366
    int i;
2367

    
2368
    d = (PCIIDEState *)pci_register_device(bus, "CMD646 IDE", 
2369
                                           sizeof(PCIIDEState),
2370
                                           -1, 
2371
                                           NULL, NULL);
2372
    d->type = IDE_TYPE_CMD646;
2373
    pci_conf = d->dev.config;
2374
    pci_conf[0x00] = 0x95; // CMD646
2375
    pci_conf[0x01] = 0x10;
2376
    pci_conf[0x02] = 0x46;
2377
    pci_conf[0x03] = 0x06;
2378

    
2379
    pci_conf[0x08] = 0x07; // IDE controller revision
2380
    pci_conf[0x09] = 0x8f; 
2381

    
2382
    pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
2383
    pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
2384
    pci_conf[0x0e] = 0x00; // header_type
2385
    
2386
    if (secondary_ide_enabled) {
2387
        /* XXX: if not enabled, really disable the seconday IDE controller */
2388
        pci_conf[0x51] = 0x80; /* enable IDE1 */
2389
    }
2390

    
2391
    pci_register_io_region((PCIDevice *)d, 0, 0x8, 
2392
                           PCI_ADDRESS_SPACE_IO, ide_map);
2393
    pci_register_io_region((PCIDevice *)d, 1, 0x4, 
2394
                           PCI_ADDRESS_SPACE_IO, ide_map);
2395
    pci_register_io_region((PCIDevice *)d, 2, 0x8, 
2396
                           PCI_ADDRESS_SPACE_IO, ide_map);
2397
    pci_register_io_region((PCIDevice *)d, 3, 0x4, 
2398
                           PCI_ADDRESS_SPACE_IO, ide_map);
2399
    pci_register_io_region((PCIDevice *)d, 4, 0x10, 
2400
                           PCI_ADDRESS_SPACE_IO, bmdma_map);
2401

    
2402
    pci_conf[0x3d] = 0x01; // interrupt on pin 1
2403
    
2404
    for(i = 0; i < 4; i++)
2405
        d->ide_if[i].pci_dev = (PCIDevice *)d;
2406
    ide_init2(&d->ide_if[0], hd_table[0], hd_table[1],
2407
              cmd646_set_irq, d, 0);
2408
    ide_init2(&d->ide_if[2], hd_table[2], hd_table[3],
2409
              cmd646_set_irq, d, 1);
2410
}
2411

    
2412
static void pci_ide_save(QEMUFile* f, void *opaque)
2413
{
2414
    PCIIDEState *d = opaque;
2415
    int i;
2416

    
2417
    pci_device_save(&d->dev, f);
2418

    
2419
    for(i = 0; i < 2; i++) {
2420
        BMDMAState *bm = &d->bmdma[i];
2421
        qemu_put_8s(f, &bm->cmd);
2422
        qemu_put_8s(f, &bm->status);
2423
        qemu_put_be32s(f, &bm->addr);
2424
        /* XXX: if a transfer is pending, we do not save it yet */
2425
    }
2426

    
2427
    /* per IDE interface data */
2428
    for(i = 0; i < 2; i++) {
2429
        IDEState *s = &d->ide_if[i * 2];
2430
        uint8_t drive1_selected;
2431
        qemu_put_8s(f, &s->cmd);
2432
        drive1_selected = (s->cur_drive != s);
2433
        qemu_put_8s(f, &drive1_selected);
2434
    }
2435

    
2436
    /* per IDE drive data */
2437
    for(i = 0; i < 4; i++) {
2438
        IDEState *s = &d->ide_if[i];
2439
        qemu_put_be32s(f, &s->mult_sectors);
2440
        qemu_put_be32s(f, &s->identify_set);
2441
        if (s->identify_set) {
2442
            qemu_put_buffer(f, (const uint8_t *)s->identify_data, 512);
2443
        }
2444
        qemu_put_8s(f, &s->feature);
2445
        qemu_put_8s(f, &s->error);
2446
        qemu_put_be32s(f, &s->nsector);
2447
        qemu_put_8s(f, &s->sector);
2448
        qemu_put_8s(f, &s->lcyl);
2449
        qemu_put_8s(f, &s->hcyl);
2450
        qemu_put_8s(f, &s->hob_feature);
2451
        qemu_put_8s(f, &s->hob_nsector);
2452
        qemu_put_8s(f, &s->hob_sector);
2453
        qemu_put_8s(f, &s->hob_lcyl);
2454
        qemu_put_8s(f, &s->hob_hcyl);
2455
        qemu_put_8s(f, &s->select);
2456
        qemu_put_8s(f, &s->status);
2457
        qemu_put_8s(f, &s->lba48);
2458

    
2459
        qemu_put_8s(f, &s->sense_key);
2460
        qemu_put_8s(f, &s->asc);
2461
        /* XXX: if a transfer is pending, we do not save it yet */
2462
    }
2463
}
2464

    
2465
static int pci_ide_load(QEMUFile* f, void *opaque, int version_id)
2466
{
2467
    PCIIDEState *d = opaque;
2468
    int ret, i;
2469

    
2470
    if (version_id != 1)
2471
        return -EINVAL;
2472
    ret = pci_device_load(&d->dev, f);
2473
    if (ret < 0)
2474
        return ret;
2475

    
2476
    for(i = 0; i < 2; i++) {
2477
        BMDMAState *bm = &d->bmdma[i];
2478
        qemu_get_8s(f, &bm->cmd);
2479
        qemu_get_8s(f, &bm->status);
2480
        qemu_get_be32s(f, &bm->addr);
2481
        /* XXX: if a transfer is pending, we do not save it yet */
2482
    }
2483

    
2484
    /* per IDE interface data */
2485
    for(i = 0; i < 2; i++) {
2486
        IDEState *s = &d->ide_if[i * 2];
2487
        uint8_t drive1_selected;
2488
        qemu_get_8s(f, &s->cmd);
2489
        qemu_get_8s(f, &drive1_selected);
2490
        s->cur_drive = &d->ide_if[i * 2 + (drive1_selected != 0)];
2491
    }
2492

    
2493
    /* per IDE drive data */
2494
    for(i = 0; i < 4; i++) {
2495
        IDEState *s = &d->ide_if[i];
2496
        qemu_get_be32s(f, &s->mult_sectors);
2497
        qemu_get_be32s(f, &s->identify_set);
2498
        if (s->identify_set) {
2499
            qemu_get_buffer(f, (uint8_t *)s->identify_data, 512);
2500
        }
2501
        qemu_get_8s(f, &s->feature);
2502
        qemu_get_8s(f, &s->error);
2503
        qemu_get_be32s(f, &s->nsector);
2504
        qemu_get_8s(f, &s->sector);
2505
        qemu_get_8s(f, &s->lcyl);
2506
        qemu_get_8s(f, &s->hcyl);
2507
        qemu_get_8s(f, &s->hob_feature);
2508
        qemu_get_8s(f, &s->hob_nsector);
2509
        qemu_get_8s(f, &s->hob_sector);
2510
        qemu_get_8s(f, &s->hob_lcyl);
2511
        qemu_get_8s(f, &s->hob_hcyl);
2512
        qemu_get_8s(f, &s->select);
2513
        qemu_get_8s(f, &s->status);
2514
        qemu_get_8s(f, &s->lba48);
2515

    
2516
        qemu_get_8s(f, &s->sense_key);
2517
        qemu_get_8s(f, &s->asc);
2518
        /* XXX: if a transfer is pending, we do not save it yet */
2519
    }
2520
    return 0;
2521
}
2522

    
2523
/* hd_table must contain 4 block drivers */
2524
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
2525
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn)
2526
{
2527
    PCIIDEState *d;
2528
    uint8_t *pci_conf;
2529
    
2530
    /* register a function 1 of PIIX3 */
2531
    d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE", 
2532
                                           sizeof(PCIIDEState),
2533
                                           devfn,
2534
                                           NULL, NULL);
2535
    d->type = IDE_TYPE_PIIX3;
2536

    
2537
    pci_conf = d->dev.config;
2538
    pci_conf[0x00] = 0x86; // Intel
2539
    pci_conf[0x01] = 0x80;
2540
    pci_conf[0x02] = 0x10;
2541
    pci_conf[0x03] = 0x70;
2542
    pci_conf[0x09] = 0x80; // legacy ATA mode
2543
    pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
2544
    pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
2545
    pci_conf[0x0e] = 0x00; // header_type
2546

    
2547
    pci_register_io_region((PCIDevice *)d, 4, 0x10, 
2548
                           PCI_ADDRESS_SPACE_IO, bmdma_map);
2549

    
2550
    ide_init2(&d->ide_if[0], hd_table[0], hd_table[1],
2551
              pic_set_irq_new, isa_pic, 14);
2552
    ide_init2(&d->ide_if[2], hd_table[2], hd_table[3],
2553
              pic_set_irq_new, isa_pic, 15);
2554
    ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
2555
    ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
2556

    
2557
    register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d);
2558
}
2559

    
2560
/***********************************************************/
2561
/* MacIO based PowerPC IDE */
2562

    
2563
/* PowerMac IDE memory IO */
2564
static void pmac_ide_writeb (void *opaque,
2565
                             target_phys_addr_t addr, uint32_t val)
2566
{
2567
    addr = (addr & 0xFFF) >> 4; 
2568
    switch (addr) {
2569
    case 1 ... 7:
2570
        ide_ioport_write(opaque, addr, val);
2571
        break;
2572
    case 8:
2573
    case 22:
2574
        ide_cmd_write(opaque, 0, val);
2575
        break;
2576
    default:
2577
        break;
2578
    }
2579
}
2580

    
2581
static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
2582
{
2583
    uint8_t retval;
2584

    
2585
    addr = (addr & 0xFFF) >> 4;
2586
    switch (addr) {
2587
    case 1 ... 7:
2588
        retval = ide_ioport_read(opaque, addr);
2589
        break;
2590
    case 8:
2591
    case 22:
2592
        retval = ide_status_read(opaque, 0);
2593
        break;
2594
    default:
2595
        retval = 0xFF;
2596
        break;
2597
    }
2598
    return retval;
2599
}
2600

    
2601
static void pmac_ide_writew (void *opaque,
2602
                             target_phys_addr_t addr, uint32_t val)
2603
{
2604
    addr = (addr & 0xFFF) >> 4; 
2605
#ifdef TARGET_WORDS_BIGENDIAN
2606
    val = bswap16(val);
2607
#endif
2608
    if (addr == 0) {
2609
        ide_data_writew(opaque, 0, val);
2610
    }
2611
}
2612

    
2613
static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
2614
{
2615
    uint16_t retval;
2616

    
2617
    addr = (addr & 0xFFF) >> 4; 
2618
    if (addr == 0) {
2619
        retval = ide_data_readw(opaque, 0);
2620
    } else {
2621
        retval = 0xFFFF;
2622
    }
2623
#ifdef TARGET_WORDS_BIGENDIAN
2624
    retval = bswap16(retval);
2625
#endif
2626
    return retval;
2627
}
2628

    
2629
static void pmac_ide_writel (void *opaque,
2630
                             target_phys_addr_t addr, uint32_t val)
2631
{
2632
    addr = (addr & 0xFFF) >> 4; 
2633
#ifdef TARGET_WORDS_BIGENDIAN
2634
    val = bswap32(val);
2635
#endif
2636
    if (addr == 0) {
2637
        ide_data_writel(opaque, 0, val);
2638
    }
2639
}
2640

    
2641
static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
2642
{
2643
    uint32_t retval;
2644

    
2645
    addr = (addr & 0xFFF) >> 4; 
2646
    if (addr == 0) {
2647
        retval = ide_data_readl(opaque, 0);
2648
    } else {
2649
        retval = 0xFFFFFFFF;
2650
    }
2651
#ifdef TARGET_WORDS_BIGENDIAN
2652
    retval = bswap32(retval);
2653
#endif
2654
    return retval;
2655
}
2656

    
2657
static CPUWriteMemoryFunc *pmac_ide_write[] = {
2658
    pmac_ide_writeb,
2659
    pmac_ide_writew,
2660
    pmac_ide_writel,
2661
};
2662

    
2663
static CPUReadMemoryFunc *pmac_ide_read[] = {
2664
    pmac_ide_readb,
2665
    pmac_ide_readw,
2666
    pmac_ide_readl,
2667
};
2668

    
2669
/* hd_table must contain 4 block drivers */
2670
/* PowerMac uses memory mapped registers, not I/O. Return the memory
2671
   I/O index to access the ide. */
2672
int pmac_ide_init (BlockDriverState **hd_table,
2673
                   SetIRQFunc *set_irq, void *irq_opaque, int irq)
2674
{
2675
    IDEState *ide_if;
2676
    int pmac_ide_memory;
2677

    
2678
    ide_if = qemu_mallocz(sizeof(IDEState) * 2);
2679
    ide_init2(&ide_if[0], hd_table[0], hd_table[1],
2680
              set_irq, irq_opaque, irq);
2681
    
2682
    pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
2683
                                             pmac_ide_write, &ide_if[0]);
2684
    return pmac_ide_memory;
2685
}