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1 | 20dcee94 | pbrook | /*
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2 | 20dcee94 | pbrook | * Motorola ColdFire MCF5208 SoC emulation.
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3 | 20dcee94 | pbrook | *
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4 | 20dcee94 | pbrook | * Copyright (c) 2007 CodeSourcery.
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5 | 20dcee94 | pbrook | *
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6 | 20dcee94 | pbrook | * This code is licenced under the GPL
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7 | 20dcee94 | pbrook | */
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8 | 20dcee94 | pbrook | #include "vl.h" |
9 | 20dcee94 | pbrook | |
10 | 20dcee94 | pbrook | #define SYS_FREQ 66000000 |
11 | 20dcee94 | pbrook | |
12 | 20dcee94 | pbrook | #define PCSR_EN 0x0001 |
13 | 20dcee94 | pbrook | #define PCSR_RLD 0x0002 |
14 | 20dcee94 | pbrook | #define PCSR_PIF 0x0004 |
15 | 20dcee94 | pbrook | #define PCSR_PIE 0x0008 |
16 | 20dcee94 | pbrook | #define PCSR_OVW 0x0010 |
17 | 20dcee94 | pbrook | #define PCSR_DBG 0x0020 |
18 | 20dcee94 | pbrook | #define PCSR_DOZE 0x0040 |
19 | 20dcee94 | pbrook | #define PCSR_PRE_SHIFT 8 |
20 | 20dcee94 | pbrook | #define PCSR_PRE_MASK 0x0f00 |
21 | 20dcee94 | pbrook | |
22 | 20dcee94 | pbrook | typedef struct { |
23 | 20dcee94 | pbrook | qemu_irq irq; |
24 | 20dcee94 | pbrook | ptimer_state *timer; |
25 | 20dcee94 | pbrook | uint16_t pcsr; |
26 | 20dcee94 | pbrook | uint16_t pmr; |
27 | 20dcee94 | pbrook | uint16_t pcntr; |
28 | 20dcee94 | pbrook | } m5208_timer_state; |
29 | 20dcee94 | pbrook | |
30 | 20dcee94 | pbrook | static void m5208_timer_update(m5208_timer_state *s) |
31 | 20dcee94 | pbrook | { |
32 | 20dcee94 | pbrook | if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF))
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33 | 20dcee94 | pbrook | qemu_irq_raise(s->irq); |
34 | 20dcee94 | pbrook | else
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35 | 20dcee94 | pbrook | qemu_irq_lower(s->irq); |
36 | 20dcee94 | pbrook | } |
37 | 20dcee94 | pbrook | |
38 | 20dcee94 | pbrook | static void m5208_timer_write(m5208_timer_state *s, int offset, |
39 | 20dcee94 | pbrook | uint32_t value) |
40 | 20dcee94 | pbrook | { |
41 | 20dcee94 | pbrook | int prescale;
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42 | 20dcee94 | pbrook | int limit;
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43 | 20dcee94 | pbrook | switch (offset) {
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44 | 20dcee94 | pbrook | case 0: |
45 | 20dcee94 | pbrook | /* The PIF bit is set-to-clear. */
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46 | 20dcee94 | pbrook | if (value & PCSR_PIF) {
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47 | 20dcee94 | pbrook | s->pcsr &= ~PCSR_PIF; |
48 | 20dcee94 | pbrook | value &= ~PCSR_PIF; |
49 | 20dcee94 | pbrook | } |
50 | 20dcee94 | pbrook | /* Avoid frobbing the timer if we're just twiddling IRQ bits. */
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51 | 20dcee94 | pbrook | if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) { |
52 | 20dcee94 | pbrook | s->pcsr = value; |
53 | 20dcee94 | pbrook | m5208_timer_update(s); |
54 | 20dcee94 | pbrook | return;
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55 | 20dcee94 | pbrook | } |
56 | 20dcee94 | pbrook | |
57 | 20dcee94 | pbrook | if (s->pcsr & PCSR_EN)
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58 | 20dcee94 | pbrook | ptimer_stop(s->timer); |
59 | 20dcee94 | pbrook | |
60 | 20dcee94 | pbrook | s->pcsr = value; |
61 | 20dcee94 | pbrook | |
62 | 20dcee94 | pbrook | prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT);
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63 | 20dcee94 | pbrook | ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale);
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64 | 20dcee94 | pbrook | if (s->pcsr & PCSR_RLD)
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65 | 20dcee94 | pbrook | limit = s->pmr; |
66 | 6d9db39c | pbrook | else
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67 | 6d9db39c | pbrook | limit = 0xffff;
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68 | 20dcee94 | pbrook | ptimer_set_limit(s->timer, limit, 0);
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69 | 20dcee94 | pbrook | |
70 | 20dcee94 | pbrook | if (s->pcsr & PCSR_EN)
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71 | 20dcee94 | pbrook | ptimer_run(s->timer, 0);
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72 | 20dcee94 | pbrook | break;
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73 | 20dcee94 | pbrook | case 2: |
74 | 20dcee94 | pbrook | s->pmr = value; |
75 | 20dcee94 | pbrook | s->pcsr &= ~PCSR_PIF; |
76 | 6d9db39c | pbrook | if ((s->pcsr & PCSR_RLD) == 0) { |
77 | 6d9db39c | pbrook | if (s->pcsr & PCSR_OVW)
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78 | 6d9db39c | pbrook | ptimer_set_count(s->timer, value); |
79 | 6d9db39c | pbrook | } else {
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80 | 6d9db39c | pbrook | ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW); |
81 | 6d9db39c | pbrook | } |
82 | 20dcee94 | pbrook | break;
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83 | 20dcee94 | pbrook | case 4: |
84 | 20dcee94 | pbrook | break;
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85 | 20dcee94 | pbrook | default:
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86 | 20dcee94 | pbrook | /* Should never happen. */
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87 | 20dcee94 | pbrook | abort(); |
88 | 20dcee94 | pbrook | } |
89 | 20dcee94 | pbrook | m5208_timer_update(s); |
90 | 20dcee94 | pbrook | } |
91 | 20dcee94 | pbrook | |
92 | 20dcee94 | pbrook | static void m5208_timer_trigger(void *opaque) |
93 | 20dcee94 | pbrook | { |
94 | 20dcee94 | pbrook | m5208_timer_state *s = (m5208_timer_state *)opaque; |
95 | 20dcee94 | pbrook | s->pcsr |= PCSR_PIF; |
96 | 20dcee94 | pbrook | m5208_timer_update(s); |
97 | 20dcee94 | pbrook | } |
98 | 20dcee94 | pbrook | |
99 | 20dcee94 | pbrook | typedef struct { |
100 | 20dcee94 | pbrook | m5208_timer_state timer[2];
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101 | 20dcee94 | pbrook | } m5208_sys_state; |
102 | 20dcee94 | pbrook | |
103 | 20dcee94 | pbrook | static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr) |
104 | 20dcee94 | pbrook | { |
105 | 20dcee94 | pbrook | m5208_sys_state *s = (m5208_sys_state *)opaque; |
106 | 20dcee94 | pbrook | switch (addr) {
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107 | 20dcee94 | pbrook | /* PIT0 */
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108 | 20dcee94 | pbrook | case 0xfc080000: |
109 | 20dcee94 | pbrook | return s->timer[0].pcsr; |
110 | 20dcee94 | pbrook | case 0xfc080002: |
111 | 20dcee94 | pbrook | return s->timer[0].pmr; |
112 | 20dcee94 | pbrook | case 0xfc080004: |
113 | 20dcee94 | pbrook | return ptimer_get_count(s->timer[0].timer); |
114 | 20dcee94 | pbrook | /* PIT1 */
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115 | 20dcee94 | pbrook | case 0xfc084000: |
116 | 20dcee94 | pbrook | return s->timer[1].pcsr; |
117 | 20dcee94 | pbrook | case 0xfc084002: |
118 | 20dcee94 | pbrook | return s->timer[1].pmr; |
119 | 20dcee94 | pbrook | case 0xfc084004: |
120 | 20dcee94 | pbrook | return ptimer_get_count(s->timer[1].timer); |
121 | 20dcee94 | pbrook | |
122 | 20dcee94 | pbrook | /* SDRAM Controller. */
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123 | 20dcee94 | pbrook | case 0xfc0a8110: /* SDCS0 */ |
124 | 20dcee94 | pbrook | { |
125 | 20dcee94 | pbrook | int n;
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126 | 20dcee94 | pbrook | for (n = 0; n < 32; n++) { |
127 | 20dcee94 | pbrook | if (ram_size < (2u << n)) |
128 | 20dcee94 | pbrook | break;
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129 | 20dcee94 | pbrook | } |
130 | 20dcee94 | pbrook | return (n - 1) | 0x40000000; |
131 | 20dcee94 | pbrook | } |
132 | 20dcee94 | pbrook | case 0xfc0a8114: /* SDCS1 */ |
133 | 20dcee94 | pbrook | return 0; |
134 | 20dcee94 | pbrook | |
135 | 20dcee94 | pbrook | default:
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136 | 20dcee94 | pbrook | cpu_abort(cpu_single_env, "m5208_sys_read: Bad offset 0x%x\n",
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137 | 20dcee94 | pbrook | (int)addr);
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138 | 20dcee94 | pbrook | return 0; |
139 | 20dcee94 | pbrook | } |
140 | 20dcee94 | pbrook | } |
141 | 20dcee94 | pbrook | |
142 | 20dcee94 | pbrook | static void m5208_sys_write(void *opaque, target_phys_addr_t addr, |
143 | 20dcee94 | pbrook | uint32_t value) |
144 | 20dcee94 | pbrook | { |
145 | 20dcee94 | pbrook | m5208_sys_state *s = (m5208_sys_state *)opaque; |
146 | 20dcee94 | pbrook | switch (addr) {
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147 | 20dcee94 | pbrook | /* PIT0 */
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148 | 20dcee94 | pbrook | case 0xfc080000: |
149 | 20dcee94 | pbrook | case 0xfc080002: |
150 | 20dcee94 | pbrook | case 0xfc080004: |
151 | 20dcee94 | pbrook | m5208_timer_write(&s->timer[0], addr & 0xf, value); |
152 | 20dcee94 | pbrook | return;
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153 | 20dcee94 | pbrook | /* PIT1 */
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154 | 20dcee94 | pbrook | case 0xfc084000: |
155 | 20dcee94 | pbrook | case 0xfc084002: |
156 | 20dcee94 | pbrook | case 0xfc084004: |
157 | 20dcee94 | pbrook | m5208_timer_write(&s->timer[1], addr & 0xf, value); |
158 | 20dcee94 | pbrook | return;
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159 | 20dcee94 | pbrook | default:
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160 | 20dcee94 | pbrook | cpu_abort(cpu_single_env, "m5208_sys_write: Bad offset 0x%x\n",
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161 | 20dcee94 | pbrook | (int)addr);
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162 | 20dcee94 | pbrook | break;
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163 | 20dcee94 | pbrook | } |
164 | 20dcee94 | pbrook | } |
165 | 20dcee94 | pbrook | |
166 | 20dcee94 | pbrook | static CPUReadMemoryFunc *m5208_sys_readfn[] = {
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167 | 20dcee94 | pbrook | m5208_sys_read, |
168 | 20dcee94 | pbrook | m5208_sys_read, |
169 | 20dcee94 | pbrook | m5208_sys_read |
170 | 20dcee94 | pbrook | }; |
171 | 20dcee94 | pbrook | |
172 | 20dcee94 | pbrook | static CPUWriteMemoryFunc *m5208_sys_writefn[] = {
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173 | 20dcee94 | pbrook | m5208_sys_write, |
174 | 20dcee94 | pbrook | m5208_sys_write, |
175 | 20dcee94 | pbrook | m5208_sys_write |
176 | 20dcee94 | pbrook | }; |
177 | 20dcee94 | pbrook | |
178 | 20dcee94 | pbrook | static void mcf5208_sys_init(qemu_irq *pic) |
179 | 20dcee94 | pbrook | { |
180 | 20dcee94 | pbrook | int iomemtype;
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181 | 20dcee94 | pbrook | m5208_sys_state *s; |
182 | 20dcee94 | pbrook | QEMUBH *bh; |
183 | 20dcee94 | pbrook | int i;
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184 | 20dcee94 | pbrook | |
185 | 20dcee94 | pbrook | s = (m5208_sys_state *)qemu_mallocz(sizeof(m5208_sys_state));
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186 | 20dcee94 | pbrook | iomemtype = cpu_register_io_memory(0, m5208_sys_readfn,
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187 | 20dcee94 | pbrook | m5208_sys_writefn, s); |
188 | 20dcee94 | pbrook | /* SDRAMC. */
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189 | 20dcee94 | pbrook | cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype); |
190 | 20dcee94 | pbrook | /* Timers. */
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191 | 20dcee94 | pbrook | for (i = 0; i < 2; i++) { |
192 | 20dcee94 | pbrook | bh = qemu_bh_new(m5208_timer_trigger, &s->timer[i]); |
193 | 20dcee94 | pbrook | s->timer[i].timer = ptimer_init(bh); |
194 | 20dcee94 | pbrook | cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000, |
195 | 20dcee94 | pbrook | iomemtype); |
196 | 20dcee94 | pbrook | s->timer[i].irq = pic[4 + i];
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197 | 20dcee94 | pbrook | } |
198 | 20dcee94 | pbrook | } |
199 | 20dcee94 | pbrook | |
200 | 20dcee94 | pbrook | static void mcf5208evb_init(int ram_size, int vga_ram_size, int boot_device, |
201 | 20dcee94 | pbrook | DisplayState *ds, const char **fd_filename, int snapshot, |
202 | 20dcee94 | pbrook | const char *kernel_filename, const char *kernel_cmdline, |
203 | 20dcee94 | pbrook | const char *initrd_filename, const char *cpu_model) |
204 | 20dcee94 | pbrook | { |
205 | 20dcee94 | pbrook | CPUState *env; |
206 | 20dcee94 | pbrook | int kernel_size;
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207 | 20dcee94 | pbrook | uint64_t elf_entry; |
208 | 20dcee94 | pbrook | target_ulong entry; |
209 | 20dcee94 | pbrook | qemu_irq *pic; |
210 | 20dcee94 | pbrook | |
211 | 20dcee94 | pbrook | env = cpu_init(); |
212 | 20dcee94 | pbrook | if (!cpu_model)
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213 | 20dcee94 | pbrook | cpu_model = "m5208";
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214 | 20dcee94 | pbrook | if (cpu_m68k_set_model(env, cpu_model)) {
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215 | 20dcee94 | pbrook | cpu_abort(env, "Unable to find m68k CPU definition\n");
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216 | 20dcee94 | pbrook | } |
217 | 20dcee94 | pbrook | |
218 | 20dcee94 | pbrook | /* Initialize CPU registers. */
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219 | 20dcee94 | pbrook | env->vbr = 0;
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220 | 20dcee94 | pbrook | /* TODO: Configure BARs. */
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221 | 20dcee94 | pbrook | |
222 | 20dcee94 | pbrook | /* DRAM at 0x20000000 */
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223 | 20dcee94 | pbrook | cpu_register_physical_memory(0x40000000, ram_size,
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224 | 20dcee94 | pbrook | qemu_ram_alloc(ram_size) | IO_MEM_RAM); |
225 | 20dcee94 | pbrook | |
226 | 20dcee94 | pbrook | /* Internal SRAM. */
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227 | 20dcee94 | pbrook | cpu_register_physical_memory(0x80000000, 16384, |
228 | 20dcee94 | pbrook | qemu_ram_alloc(16384) | IO_MEM_RAM);
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229 | 20dcee94 | pbrook | |
230 | 20dcee94 | pbrook | /* Internal peripherals. */
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231 | 20dcee94 | pbrook | pic = mcf_intc_init(0xfc048000, env);
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232 | 20dcee94 | pbrook | |
233 | 20dcee94 | pbrook | mcf_uart_mm_init(0xfc060000, pic[26], serial_hds[0]); |
234 | 20dcee94 | pbrook | mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]); |
235 | 20dcee94 | pbrook | mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]); |
236 | 20dcee94 | pbrook | |
237 | 20dcee94 | pbrook | mcf5208_sys_init(pic); |
238 | 20dcee94 | pbrook | |
239 | 7e049b8a | pbrook | if (nb_nics > 1) { |
240 | 7e049b8a | pbrook | fprintf(stderr, "Too many NICs\n");
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241 | 7e049b8a | pbrook | exit(1);
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242 | 7e049b8a | pbrook | } |
243 | 7e049b8a | pbrook | if (nd_table[0].vlan) { |
244 | 7e049b8a | pbrook | if (nd_table[0].model == NULL |
245 | 7e049b8a | pbrook | || strcmp(nd_table[0].model, "mcf_fec") == 0) { |
246 | 7e049b8a | pbrook | mcf_fec_init(&nd_table[0], 0xfc030000, pic + 36); |
247 | 7e049b8a | pbrook | } else if (strcmp(nd_table[0].model, "?") == 0) { |
248 | 7e049b8a | pbrook | fprintf(stderr, "qemu: Supported NICs: mcf_fec\n");
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249 | 7e049b8a | pbrook | exit (1);
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250 | 7e049b8a | pbrook | } else {
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251 | 7e049b8a | pbrook | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
252 | 7e049b8a | pbrook | exit (1);
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253 | 7e049b8a | pbrook | } |
254 | 7e049b8a | pbrook | } |
255 | 7e049b8a | pbrook | |
256 | 20dcee94 | pbrook | /* 0xfc000000 SCM. */
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257 | 20dcee94 | pbrook | /* 0xfc004000 XBS. */
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258 | 20dcee94 | pbrook | /* 0xfc008000 FlexBus CS. */
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259 | 7e049b8a | pbrook | /* 0xfc030000 FEC. */
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260 | 20dcee94 | pbrook | /* 0xfc040000 SCM + Power management. */
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261 | 20dcee94 | pbrook | /* 0xfc044000 eDMA. */
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262 | 20dcee94 | pbrook | /* 0xfc048000 INTC. */
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263 | 20dcee94 | pbrook | /* 0xfc058000 I2C. */
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264 | 20dcee94 | pbrook | /* 0xfc05c000 QSPI. */
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265 | 20dcee94 | pbrook | /* 0xfc060000 UART0. */
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266 | 20dcee94 | pbrook | /* 0xfc064000 UART0. */
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267 | 20dcee94 | pbrook | /* 0xfc068000 UART0. */
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268 | 20dcee94 | pbrook | /* 0xfc070000 DMA timers. */
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269 | 20dcee94 | pbrook | /* 0xfc080000 PIT0. */
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270 | 20dcee94 | pbrook | /* 0xfc084000 PIT1. */
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271 | 20dcee94 | pbrook | /* 0xfc088000 EPORT. */
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272 | 20dcee94 | pbrook | /* 0xfc08c000 Watchdog. */
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273 | 20dcee94 | pbrook | /* 0xfc090000 clock module. */
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274 | 20dcee94 | pbrook | /* 0xfc0a0000 CCM + reset. */
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275 | 20dcee94 | pbrook | /* 0xfc0a4000 GPIO. */
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276 | 20dcee94 | pbrook | /* 0xfc0a8000 SDRAM controller. */
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277 | 20dcee94 | pbrook | |
278 | 20dcee94 | pbrook | /* Load kernel. */
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279 | 20dcee94 | pbrook | if (!kernel_filename) {
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280 | 20dcee94 | pbrook | fprintf(stderr, "Kernel image must be specified\n");
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281 | 20dcee94 | pbrook | exit(1);
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282 | 20dcee94 | pbrook | } |
283 | 20dcee94 | pbrook | |
284 | 20dcee94 | pbrook | kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL); |
285 | 20dcee94 | pbrook | entry = elf_entry; |
286 | 20dcee94 | pbrook | if (kernel_size < 0) { |
287 | 20dcee94 | pbrook | kernel_size = load_uboot(kernel_filename, &entry, NULL);
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288 | 20dcee94 | pbrook | } |
289 | 20dcee94 | pbrook | if (kernel_size < 0) { |
290 | 20dcee94 | pbrook | kernel_size = load_image(kernel_filename, phys_ram_base); |
291 | 20dcee94 | pbrook | entry = 0x20000000;
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292 | 20dcee94 | pbrook | } |
293 | 20dcee94 | pbrook | if (kernel_size < 0) { |
294 | 20dcee94 | pbrook | fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
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295 | 20dcee94 | pbrook | exit(1);
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296 | 20dcee94 | pbrook | } |
297 | 20dcee94 | pbrook | |
298 | 20dcee94 | pbrook | env->pc = entry; |
299 | 20dcee94 | pbrook | } |
300 | 20dcee94 | pbrook | |
301 | 20dcee94 | pbrook | QEMUMachine mcf5208evb_machine = { |
302 | 20dcee94 | pbrook | "mcf5208evb",
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303 | 20dcee94 | pbrook | "MCF5206EVB",
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304 | 20dcee94 | pbrook | mcf5208evb_init, |
305 | 20dcee94 | pbrook | }; |