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1 | 450d4ff5 | ths | /* Disassembler code for CRIS.
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2 | 450d4ff5 | ths | Copyright 2000, 2001, 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
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3 | 450d4ff5 | ths | Contributed by Axis Communications AB, Lund, Sweden.
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4 | 450d4ff5 | ths | Written by Hans-Peter Nilsson.
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5 | 450d4ff5 | ths | |
6 | 450d4ff5 | ths | This file is part of the GNU binutils and GDB, the GNU debugger.
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7 | 450d4ff5 | ths | |
8 | 450d4ff5 | ths | This program is free software; you can redistribute it and/or modify it
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9 | 450d4ff5 | ths | under the terms of the GNU General Public License as published by the
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10 | 450d4ff5 | ths | Free Software Foundation; either version 2, or (at your option) any later
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11 | 450d4ff5 | ths | version.
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12 | 450d4ff5 | ths | |
13 | 450d4ff5 | ths | This program is distributed in the hope that it will be useful, but WITHOUT
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14 | 450d4ff5 | ths | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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15 | 450d4ff5 | ths | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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16 | 450d4ff5 | ths | more details.
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17 | 450d4ff5 | ths | |
18 | 450d4ff5 | ths | You should have received a copy of the GNU General Public License
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19 | 8167ee88 | Blue Swirl | along with this program; if not, see <http://www.gnu.org/licenses/>. */
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20 | 450d4ff5 | ths | |
21 | 450d4ff5 | ths | #include "dis-asm.h" |
22 | 450d4ff5 | ths | //#include "sysdep.h"
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23 | 450d4ff5 | ths | #include "target-cris/opcode-cris.h" |
24 | 450d4ff5 | ths | //#include "libiberty.h"
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25 | 450d4ff5 | ths | |
26 | 450d4ff5 | ths | |
27 | 1eec614b | aliguori | void *qemu_malloc(size_t len); /* can't include qemu-common.h here */ |
28 | 1eec614b | aliguori | |
29 | 450d4ff5 | ths | #define FALSE 0 |
30 | 450d4ff5 | ths | #define TRUE 1 |
31 | 450d4ff5 | ths | #define CONST_STRNEQ(STR1,STR2) (strncmp ((STR1), (STR2), sizeof (STR2) - 1) == 0) |
32 | 450d4ff5 | ths | |
33 | 450d4ff5 | ths | /* cris-opc.c -- Table of opcodes for the CRIS processor.
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34 | 450d4ff5 | ths | Copyright 2000, 2001, 2004 Free Software Foundation, Inc.
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35 | 450d4ff5 | ths | Contributed by Axis Communications AB, Lund, Sweden.
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36 | 450d4ff5 | ths | Originally written for GAS 1.38.1 by Mikael Asker.
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37 | 450d4ff5 | ths | Reorganized by Hans-Peter Nilsson.
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38 | 450d4ff5 | ths | |
39 | 450d4ff5 | ths | This file is part of GAS, GDB and the GNU binutils.
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40 | 450d4ff5 | ths | |
41 | 450d4ff5 | ths | GAS, GDB, and GNU binutils is free software; you can redistribute it
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42 | 450d4ff5 | ths | and/or modify it under the terms of the GNU General Public License as
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43 | 450d4ff5 | ths | published by the Free Software Foundation; either version 2, or (at your
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44 | 450d4ff5 | ths | option) any later version.
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45 | 450d4ff5 | ths | |
46 | 450d4ff5 | ths | GAS, GDB, and GNU binutils are distributed in the hope that they will be
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47 | 450d4ff5 | ths | useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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48 | 450d4ff5 | ths | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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49 | 450d4ff5 | ths | GNU General Public License for more details.
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50 | 450d4ff5 | ths | |
51 | 450d4ff5 | ths | You should have received a copy of the GNU General Public License
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52 | 8167ee88 | Blue Swirl | along with this program; if not, see <http://www.gnu.org/licenses/>. */
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53 | 450d4ff5 | ths | |
54 | 450d4ff5 | ths | #ifndef NULL |
55 | 450d4ff5 | ths | #define NULL (0) |
56 | 450d4ff5 | ths | #endif
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57 | 450d4ff5 | ths | |
58 | 450d4ff5 | ths | /* This table isn't used for CRISv32 and the size of immediate operands. */
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59 | 450d4ff5 | ths | const struct cris_spec_reg |
60 | 450d4ff5 | ths | cris_spec_regs[] = |
61 | 450d4ff5 | ths | { |
62 | 450d4ff5 | ths | {"bz", 0, 1, cris_ver_v32p, NULL}, |
63 | 450d4ff5 | ths | {"p0", 0, 1, 0, NULL}, |
64 | 450d4ff5 | ths | {"vr", 1, 1, 0, NULL}, |
65 | 450d4ff5 | ths | {"p1", 1, 1, 0, NULL}, |
66 | 450d4ff5 | ths | {"pid", 2, 1, cris_ver_v32p, NULL}, |
67 | 450d4ff5 | ths | {"p2", 2, 1, cris_ver_v32p, NULL}, |
68 | 450d4ff5 | ths | {"p2", 2, 1, cris_ver_warning, NULL}, |
69 | 450d4ff5 | ths | {"srs", 3, 1, cris_ver_v32p, NULL}, |
70 | 450d4ff5 | ths | {"p3", 3, 1, cris_ver_v32p, NULL}, |
71 | 450d4ff5 | ths | {"p3", 3, 1, cris_ver_warning, NULL}, |
72 | 450d4ff5 | ths | {"wz", 4, 2, cris_ver_v32p, NULL}, |
73 | 450d4ff5 | ths | {"p4", 4, 2, 0, NULL}, |
74 | 450d4ff5 | ths | {"ccr", 5, 2, cris_ver_v0_10, NULL}, |
75 | 450d4ff5 | ths | {"exs", 5, 4, cris_ver_v32p, NULL}, |
76 | 450d4ff5 | ths | {"p5", 5, 2, cris_ver_v0_10, NULL}, |
77 | 450d4ff5 | ths | {"p5", 5, 4, cris_ver_v32p, NULL}, |
78 | 450d4ff5 | ths | {"dcr0",6, 2, cris_ver_v0_3, NULL}, |
79 | 450d4ff5 | ths | {"eda", 6, 4, cris_ver_v32p, NULL}, |
80 | 450d4ff5 | ths | {"p6", 6, 2, cris_ver_v0_3, NULL}, |
81 | 450d4ff5 | ths | {"p6", 6, 4, cris_ver_v32p, NULL}, |
82 | 450d4ff5 | ths | {"dcr1/mof", 7, 4, cris_ver_v10p, |
83 | 450d4ff5 | ths | "Register `dcr1/mof' with ambiguous size specified. Guessing 4 bytes"},
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84 | 450d4ff5 | ths | {"dcr1/mof", 7, 2, cris_ver_v0_3, |
85 | 450d4ff5 | ths | "Register `dcr1/mof' with ambiguous size specified. Guessing 2 bytes"},
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86 | 450d4ff5 | ths | {"mof", 7, 4, cris_ver_v10p, NULL}, |
87 | 450d4ff5 | ths | {"dcr1",7, 2, cris_ver_v0_3, NULL}, |
88 | 450d4ff5 | ths | {"p7", 7, 4, cris_ver_v10p, NULL}, |
89 | 450d4ff5 | ths | {"p7", 7, 2, cris_ver_v0_3, NULL}, |
90 | 450d4ff5 | ths | {"dz", 8, 4, cris_ver_v32p, NULL}, |
91 | 450d4ff5 | ths | {"p8", 8, 4, 0, NULL}, |
92 | 450d4ff5 | ths | {"ibr", 9, 4, cris_ver_v0_10, NULL}, |
93 | 450d4ff5 | ths | {"ebp", 9, 4, cris_ver_v32p, NULL}, |
94 | 450d4ff5 | ths | {"p9", 9, 4, 0, NULL}, |
95 | 450d4ff5 | ths | {"irp", 10, 4, cris_ver_v0_10, NULL}, |
96 | 450d4ff5 | ths | {"erp", 10, 4, cris_ver_v32p, NULL}, |
97 | 450d4ff5 | ths | {"p10", 10, 4, 0, NULL}, |
98 | 450d4ff5 | ths | {"srp", 11, 4, 0, NULL}, |
99 | 450d4ff5 | ths | {"p11", 11, 4, 0, NULL}, |
100 | 450d4ff5 | ths | /* For disassembly use only. Accept at assembly with a warning. */
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101 | 450d4ff5 | ths | {"bar/dtp0", 12, 4, cris_ver_warning, |
102 | 450d4ff5 | ths | "Ambiguous register `bar/dtp0' specified"},
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103 | 450d4ff5 | ths | {"nrp", 12, 4, cris_ver_v32p, NULL}, |
104 | 450d4ff5 | ths | {"bar", 12, 4, cris_ver_v8_10, NULL}, |
105 | 450d4ff5 | ths | {"dtp0",12, 4, cris_ver_v0_3, NULL}, |
106 | 450d4ff5 | ths | {"p12", 12, 4, 0, NULL}, |
107 | 450d4ff5 | ths | /* For disassembly use only. Accept at assembly with a warning. */
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108 | 450d4ff5 | ths | {"dccr/dtp1",13, 4, cris_ver_warning, |
109 | 450d4ff5 | ths | "Ambiguous register `dccr/dtp1' specified"},
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110 | 450d4ff5 | ths | {"ccs", 13, 4, cris_ver_v32p, NULL}, |
111 | 450d4ff5 | ths | {"dccr",13, 4, cris_ver_v8_10, NULL}, |
112 | 450d4ff5 | ths | {"dtp1",13, 4, cris_ver_v0_3, NULL}, |
113 | 450d4ff5 | ths | {"p13", 13, 4, 0, NULL}, |
114 | 450d4ff5 | ths | {"brp", 14, 4, cris_ver_v3_10, NULL}, |
115 | 450d4ff5 | ths | {"usp", 14, 4, cris_ver_v32p, NULL}, |
116 | 450d4ff5 | ths | {"p14", 14, 4, cris_ver_v3p, NULL}, |
117 | 450d4ff5 | ths | {"usp", 15, 4, cris_ver_v10, NULL}, |
118 | 450d4ff5 | ths | {"spc", 15, 4, cris_ver_v32p, NULL}, |
119 | 450d4ff5 | ths | {"p15", 15, 4, cris_ver_v10p, NULL}, |
120 | 450d4ff5 | ths | {NULL, 0, 0, cris_ver_version_all, NULL} |
121 | 450d4ff5 | ths | }; |
122 | 450d4ff5 | ths | |
123 | 450d4ff5 | ths | /* Add version specifiers to this table when necessary.
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124 | 450d4ff5 | ths | The (now) regular coding of register names suggests a simpler
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125 | 450d4ff5 | ths | implementation. */
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126 | 450d4ff5 | ths | const struct cris_support_reg cris_support_regs[] = |
127 | 450d4ff5 | ths | { |
128 | 450d4ff5 | ths | {"s0", 0}, |
129 | 450d4ff5 | ths | {"s1", 1}, |
130 | 450d4ff5 | ths | {"s2", 2}, |
131 | 450d4ff5 | ths | {"s3", 3}, |
132 | 450d4ff5 | ths | {"s4", 4}, |
133 | 450d4ff5 | ths | {"s5", 5}, |
134 | 450d4ff5 | ths | {"s6", 6}, |
135 | 450d4ff5 | ths | {"s7", 7}, |
136 | 450d4ff5 | ths | {"s8", 8}, |
137 | 450d4ff5 | ths | {"s9", 9}, |
138 | 450d4ff5 | ths | {"s10", 10}, |
139 | 450d4ff5 | ths | {"s11", 11}, |
140 | 450d4ff5 | ths | {"s12", 12}, |
141 | 450d4ff5 | ths | {"s13", 13}, |
142 | 450d4ff5 | ths | {"s14", 14}, |
143 | 450d4ff5 | ths | {"s15", 15}, |
144 | 450d4ff5 | ths | {NULL, 0} |
145 | 450d4ff5 | ths | }; |
146 | 450d4ff5 | ths | |
147 | 450d4ff5 | ths | /* All CRIS opcodes are 16 bits.
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148 | 450d4ff5 | ths | |
149 | 450d4ff5 | ths | - The match component is a mask saying which bits must match a
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150 | 450d4ff5 | ths | particular opcode in order for an instruction to be an instance
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151 | 450d4ff5 | ths | of that opcode.
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152 | 450d4ff5 | ths | |
153 | 450d4ff5 | ths | - The args component is a string containing characters symbolically
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154 | 450d4ff5 | ths | matching the operands of an instruction. Used for both assembly
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155 | 450d4ff5 | ths | and disassembly.
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156 | 450d4ff5 | ths | |
157 | 450d4ff5 | ths | Operand-matching characters:
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158 | 450d4ff5 | ths | [ ] , space
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159 | 450d4ff5 | ths | Verbatim.
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160 | 450d4ff5 | ths | A The string "ACR" (case-insensitive).
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161 | 450d4ff5 | ths | B Not really an operand. It causes a "BDAP -size,SP" prefix to be
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162 | 450d4ff5 | ths | output for the PUSH alias-instructions and recognizes a push-
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163 | 450d4ff5 | ths | prefix at disassembly. This letter isn't recognized for v32.
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164 | 450d4ff5 | ths | Must be followed by a R or P letter.
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165 | 450d4ff5 | ths | ! Non-match pattern, will not match if there's a prefix insn.
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166 | 450d4ff5 | ths | b Non-matching operand, used for branches with 16-bit
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167 | 450d4ff5 | ths | displacement. Only recognized by the disassembler.
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168 | 450d4ff5 | ths | c 5-bit unsigned immediate in bits <4:0>.
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169 | 450d4ff5 | ths | C 4-bit unsigned immediate in bits <3:0>.
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170 | 450d4ff5 | ths | d At assembly, optionally (as in put other cases before this one)
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171 | 450d4ff5 | ths | ".d" or ".D" at the start of the operands, followed by one space
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172 | 450d4ff5 | ths | character. At disassembly, nothing.
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173 | 450d4ff5 | ths | D General register in bits <15:12> and <3:0>.
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174 | 450d4ff5 | ths | f List of flags in bits <15:12> and <3:0>.
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175 | 450d4ff5 | ths | i 6-bit signed immediate in bits <5:0>.
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176 | 450d4ff5 | ths | I 6-bit unsigned immediate in bits <5:0>.
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177 | 450d4ff5 | ths | M Size modifier (B, W or D) for CLEAR instructions.
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178 | 450d4ff5 | ths | m Size modifier (B, W or D) in bits <5:4>
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179 | 450d4ff5 | ths | N A 32-bit dword, like in the difference between s and y.
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180 | 450d4ff5 | ths | This has no effect on bits in the opcode. Can also be expressed
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181 | 450d4ff5 | ths | as "[pc+]" in input.
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182 | 450d4ff5 | ths | n As N, but PC-relative (to the start of the instruction).
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183 | 450d4ff5 | ths | o [-128..127] word offset in bits <7:1> and <0>. Used by 8-bit
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184 | 450d4ff5 | ths | branch instructions.
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185 | 450d4ff5 | ths | O [-128..127] offset in bits <7:0>. Also matches a comma and a
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186 | 450d4ff5 | ths | general register after the expression, in bits <15:12>. Used
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187 | 450d4ff5 | ths | only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode).
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188 | 450d4ff5 | ths | P Special register in bits <15:12>.
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189 | 450d4ff5 | ths | p Indicates that the insn is a prefix insn. Must be first
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190 | 450d4ff5 | ths | character.
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191 | 450d4ff5 | ths | Q As O, but don't relax; force an 8-bit offset.
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192 | 450d4ff5 | ths | R General register in bits <15:12>.
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193 | 450d4ff5 | ths | r General register in bits <3:0>.
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194 | 450d4ff5 | ths | S Source operand in bit <10> and a prefix; a 3-operand prefix
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195 | 450d4ff5 | ths | without side-effect.
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196 | 450d4ff5 | ths | s Source operand in bits <10> and <3:0>, optionally with a
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197 | 450d4ff5 | ths | side-effect prefix, except [pc] (the name, not R15 as in ACR)
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198 | 450d4ff5 | ths | isn't allowed for v32 and higher.
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199 | 450d4ff5 | ths | T Support register in bits <15:12>.
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200 | 450d4ff5 | ths | u 4-bit (PC-relative) unsigned immediate word offset in bits <3:0>.
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201 | 450d4ff5 | ths | U Relaxes to either u or n, instruction is assumed LAPCQ or LAPC.
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202 | 450d4ff5 | ths | Not recognized at disassembly.
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203 | 450d4ff5 | ths | x Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>.
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204 | 450d4ff5 | ths | y Like 's' but do not allow an integer at assembly.
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205 | 450d4ff5 | ths | Y The difference s-y; only an integer is allowed.
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206 | 450d4ff5 | ths | z Size modifier (B or W) in bit <4>. */
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207 | 450d4ff5 | ths | |
208 | 450d4ff5 | ths | |
209 | 450d4ff5 | ths | /* Please note the order of the opcodes in this table is significant.
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210 | 450d4ff5 | ths | The assembler requires that all instances of the same mnemonic must
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211 | 450d4ff5 | ths | be consecutive. If they aren't, the assembler might not recognize
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212 | 450d4ff5 | ths | them, or may indicate an internal error.
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213 | 450d4ff5 | ths | |
214 | 450d4ff5 | ths | The disassembler should not normally care about the order of the
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215 | 450d4ff5 | ths | opcodes, but will prefer an earlier alternative if the "match-score"
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216 | 450d4ff5 | ths | (see cris-dis.c) is computed as equal.
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217 | 450d4ff5 | ths | |
218 | 450d4ff5 | ths | It should not be significant for proper execution that this table is
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219 | 450d4ff5 | ths | in alphabetical order, but please follow that convention for an easy
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220 | 450d4ff5 | ths | overview. */
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221 | 450d4ff5 | ths | |
222 | 450d4ff5 | ths | const struct cris_opcode |
223 | 450d4ff5 | ths | cris_opcodes[] = |
224 | 450d4ff5 | ths | { |
225 | 450d4ff5 | ths | {"abs", 0x06B0, 0x0940, "r,R", 0, SIZE_NONE, 0, |
226 | 450d4ff5 | ths | cris_abs_op}, |
227 | 450d4ff5 | ths | |
228 | 450d4ff5 | ths | {"add", 0x0600, 0x09c0, "m r,R", 0, SIZE_NONE, 0, |
229 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
230 | 450d4ff5 | ths | |
231 | 450d4ff5 | ths | {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 0, |
232 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
233 | 450d4ff5 | ths | |
234 | 450d4ff5 | ths | {"add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE, |
235 | 450d4ff5 | ths | cris_ver_v0_10, |
236 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
237 | 450d4ff5 | ths | |
238 | 450d4ff5 | ths | {"add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE, |
239 | 450d4ff5 | ths | cris_ver_v0_10, |
240 | 450d4ff5 | ths | cris_three_operand_add_sub_cmp_and_or_op}, |
241 | 450d4ff5 | ths | |
242 | 450d4ff5 | ths | {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, |
243 | 450d4ff5 | ths | cris_ver_v32p, |
244 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
245 | 450d4ff5 | ths | |
246 | 450d4ff5 | ths | {"addc", 0x0570, 0x0A80, "r,R", 0, SIZE_FIX_32, |
247 | 450d4ff5 | ths | cris_ver_v32p, |
248 | 450d4ff5 | ths | cris_not_implemented_op}, |
249 | 450d4ff5 | ths | |
250 | 450d4ff5 | ths | {"addc", 0x09A0, 0x0250, "s,R", 0, SIZE_FIX_32, |
251 | 450d4ff5 | ths | cris_ver_v32p, |
252 | 450d4ff5 | ths | cris_not_implemented_op}, |
253 | 450d4ff5 | ths | |
254 | 450d4ff5 | ths | {"addi", 0x0540, 0x0A80, "x,r,A", 0, SIZE_NONE, |
255 | 450d4ff5 | ths | cris_ver_v32p, |
256 | 450d4ff5 | ths | cris_addi_op}, |
257 | 450d4ff5 | ths | |
258 | 450d4ff5 | ths | {"addi", 0x0500, 0x0Ac0, "x,r", 0, SIZE_NONE, 0, |
259 | 450d4ff5 | ths | cris_addi_op}, |
260 | 450d4ff5 | ths | |
261 | 450d4ff5 | ths | /* This collates after "addo", but we want to disassemble as "addoq",
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262 | 450d4ff5 | ths | not "addo". */
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263 | 450d4ff5 | ths | {"addoq", 0x0100, 0x0E00, "Q,A", 0, SIZE_NONE, |
264 | 450d4ff5 | ths | cris_ver_v32p, |
265 | 450d4ff5 | ths | cris_not_implemented_op}, |
266 | 450d4ff5 | ths | |
267 | 450d4ff5 | ths | {"addo", 0x0940, 0x0280, "m s,R,A", 0, SIZE_FIELD_SIGNED, |
268 | 450d4ff5 | ths | cris_ver_v32p, |
269 | 450d4ff5 | ths | cris_not_implemented_op}, |
270 | 450d4ff5 | ths | |
271 | 450d4ff5 | ths | /* This must be located after the insn above, lest we misinterpret
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272 | 450d4ff5 | ths | "addo.b -1,r0,acr" as "addo .b-1,r0,acr". FIXME: Sounds like a
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273 | 450d4ff5 | ths | parser bug. */
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274 | 450d4ff5 | ths | {"addo", 0x0100, 0x0E00, "O,A", 0, SIZE_NONE, |
275 | 450d4ff5 | ths | cris_ver_v32p, |
276 | 450d4ff5 | ths | cris_not_implemented_op}, |
277 | 450d4ff5 | ths | |
278 | 450d4ff5 | ths | {"addq", 0x0200, 0x0Dc0, "I,R", 0, SIZE_NONE, 0, |
279 | 450d4ff5 | ths | cris_quick_mode_add_sub_op}, |
280 | 450d4ff5 | ths | |
281 | 450d4ff5 | ths | {"adds", 0x0420, 0x0Bc0, "z r,R", 0, SIZE_NONE, 0, |
282 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
283 | 450d4ff5 | ths | |
284 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
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285 | 450d4ff5 | ths | {"adds", 0x0820, 0x03c0, "z s,R", 0, SIZE_FIELD, 0, |
286 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
287 | 450d4ff5 | ths | |
288 | 450d4ff5 | ths | {"adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE, |
289 | 450d4ff5 | ths | cris_ver_v0_10, |
290 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
291 | 450d4ff5 | ths | |
292 | 450d4ff5 | ths | {"adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE, |
293 | 450d4ff5 | ths | cris_ver_v0_10, |
294 | 450d4ff5 | ths | cris_three_operand_add_sub_cmp_and_or_op}, |
295 | 450d4ff5 | ths | |
296 | 450d4ff5 | ths | {"addu", 0x0400, 0x0be0, "z r,R", 0, SIZE_NONE, 0, |
297 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
298 | 450d4ff5 | ths | |
299 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
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300 | 450d4ff5 | ths | {"addu", 0x0800, 0x03e0, "z s,R", 0, SIZE_FIELD, 0, |
301 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
302 | 450d4ff5 | ths | |
303 | 450d4ff5 | ths | {"addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE, |
304 | 450d4ff5 | ths | cris_ver_v0_10, |
305 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
306 | 450d4ff5 | ths | |
307 | 450d4ff5 | ths | {"addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE, |
308 | 450d4ff5 | ths | cris_ver_v0_10, |
309 | 450d4ff5 | ths | cris_three_operand_add_sub_cmp_and_or_op}, |
310 | 450d4ff5 | ths | |
311 | 450d4ff5 | ths | {"and", 0x0700, 0x08C0, "m r,R", 0, SIZE_NONE, 0, |
312 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
313 | 450d4ff5 | ths | |
314 | 450d4ff5 | ths | {"and", 0x0B00, 0x00C0, "m s,R", 0, SIZE_FIELD, 0, |
315 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
316 | 450d4ff5 | ths | |
317 | 450d4ff5 | ths | {"and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE, |
318 | 450d4ff5 | ths | cris_ver_v0_10, |
319 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
320 | 450d4ff5 | ths | |
321 | 450d4ff5 | ths | {"and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE, |
322 | 450d4ff5 | ths | cris_ver_v0_10, |
323 | 450d4ff5 | ths | cris_three_operand_add_sub_cmp_and_or_op}, |
324 | 450d4ff5 | ths | |
325 | 450d4ff5 | ths | {"andq", 0x0300, 0x0CC0, "i,R", 0, SIZE_NONE, 0, |
326 | 450d4ff5 | ths | cris_quick_mode_and_cmp_move_or_op}, |
327 | 450d4ff5 | ths | |
328 | 450d4ff5 | ths | {"asr", 0x0780, 0x0840, "m r,R", 0, SIZE_NONE, 0, |
329 | 450d4ff5 | ths | cris_asr_op}, |
330 | 450d4ff5 | ths | |
331 | 450d4ff5 | ths | {"asrq", 0x03a0, 0x0c40, "c,R", 0, SIZE_NONE, 0, |
332 | 450d4ff5 | ths | cris_asrq_op}, |
333 | 450d4ff5 | ths | |
334 | 450d4ff5 | ths | {"ax", 0x15B0, 0xEA4F, "", 0, SIZE_NONE, 0, |
335 | 450d4ff5 | ths | cris_ax_ei_setf_op}, |
336 | 450d4ff5 | ths | |
337 | 450d4ff5 | ths | /* FIXME: Should use branch #defines. */
|
338 | 450d4ff5 | ths | {"b", 0x0dff, 0x0200, "b", 1, SIZE_NONE, 0, |
339 | 450d4ff5 | ths | cris_sixteen_bit_offset_branch_op}, |
340 | 450d4ff5 | ths | |
341 | 450d4ff5 | ths | {"ba",
|
342 | 450d4ff5 | ths | BA_QUICK_OPCODE, |
343 | 450d4ff5 | ths | 0x0F00+(0xF-CC_A)*0x1000, "o", 1, SIZE_NONE, 0, |
344 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
345 | 450d4ff5 | ths | |
346 | 450d4ff5 | ths | /* Needs to come after the usual "ba o", which might be relaxed to
|
347 | 450d4ff5 | ths | this one. */
|
348 | 450d4ff5 | ths | {"ba", BA_DWORD_OPCODE,
|
349 | 450d4ff5 | ths | 0xffff & (~BA_DWORD_OPCODE), "n", 0, SIZE_FIX_32, |
350 | 450d4ff5 | ths | cris_ver_v32p, |
351 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
352 | 450d4ff5 | ths | |
353 | 450d4ff5 | ths | {"bas", 0x0EBF, 0x0140, "n,P", 0, SIZE_FIX_32, |
354 | 450d4ff5 | ths | cris_ver_v32p, |
355 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
356 | 450d4ff5 | ths | |
357 | 450d4ff5 | ths | {"basc", 0x0EFF, 0x0100, "n,P", 0, SIZE_FIX_32, |
358 | 450d4ff5 | ths | cris_ver_v32p, |
359 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
360 | 450d4ff5 | ths | |
361 | 450d4ff5 | ths | {"bcc",
|
362 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_CC*0x1000,
|
363 | 450d4ff5 | ths | 0x0f00+(0xF-CC_CC)*0x1000, "o", 1, SIZE_NONE, 0, |
364 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
365 | 450d4ff5 | ths | |
366 | 450d4ff5 | ths | {"bcs",
|
367 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_CS*0x1000,
|
368 | 450d4ff5 | ths | 0x0f00+(0xF-CC_CS)*0x1000, "o", 1, SIZE_NONE, 0, |
369 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
370 | 450d4ff5 | ths | |
371 | 450d4ff5 | ths | {"bdap",
|
372 | 450d4ff5 | ths | BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS, "pm s,R", 0, SIZE_FIELD_SIGNED, |
373 | 450d4ff5 | ths | cris_ver_v0_10, |
374 | 450d4ff5 | ths | cris_bdap_prefix}, |
375 | 450d4ff5 | ths | |
376 | 450d4ff5 | ths | {"bdap",
|
377 | 450d4ff5 | ths | BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS, "pO", 0, SIZE_NONE, |
378 | 450d4ff5 | ths | cris_ver_v0_10, |
379 | 450d4ff5 | ths | cris_quick_mode_bdap_prefix}, |
380 | 450d4ff5 | ths | |
381 | 450d4ff5 | ths | {"beq",
|
382 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_EQ*0x1000,
|
383 | 450d4ff5 | ths | 0x0f00+(0xF-CC_EQ)*0x1000, "o", 1, SIZE_NONE, 0, |
384 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
385 | 450d4ff5 | ths | |
386 | 450d4ff5 | ths | /* This is deliberately put before "bext" to trump it, even though not
|
387 | 450d4ff5 | ths | in alphabetical order, since we don't do excluding version checks
|
388 | 450d4ff5 | ths | for v0..v10. */
|
389 | 450d4ff5 | ths | {"bwf",
|
390 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
|
391 | 450d4ff5 | ths | 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, |
392 | 450d4ff5 | ths | cris_ver_v10, |
393 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
394 | 450d4ff5 | ths | |
395 | 450d4ff5 | ths | {"bext",
|
396 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
|
397 | 450d4ff5 | ths | 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, |
398 | 450d4ff5 | ths | cris_ver_v0_3, |
399 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
400 | 450d4ff5 | ths | |
401 | 450d4ff5 | ths | {"bge",
|
402 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_GE*0x1000,
|
403 | 450d4ff5 | ths | 0x0f00+(0xF-CC_GE)*0x1000, "o", 1, SIZE_NONE, 0, |
404 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
405 | 450d4ff5 | ths | |
406 | 450d4ff5 | ths | {"bgt",
|
407 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_GT*0x1000,
|
408 | 450d4ff5 | ths | 0x0f00+(0xF-CC_GT)*0x1000, "o", 1, SIZE_NONE, 0, |
409 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
410 | 450d4ff5 | ths | |
411 | 450d4ff5 | ths | {"bhi",
|
412 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_HI*0x1000,
|
413 | 450d4ff5 | ths | 0x0f00+(0xF-CC_HI)*0x1000, "o", 1, SIZE_NONE, 0, |
414 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
415 | 450d4ff5 | ths | |
416 | 450d4ff5 | ths | {"bhs",
|
417 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_HS*0x1000,
|
418 | 450d4ff5 | ths | 0x0f00+(0xF-CC_HS)*0x1000, "o", 1, SIZE_NONE, 0, |
419 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
420 | 450d4ff5 | ths | |
421 | 450d4ff5 | ths | {"biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE, |
422 | 450d4ff5 | ths | cris_ver_v0_10, |
423 | 450d4ff5 | ths | cris_biap_prefix}, |
424 | 450d4ff5 | ths | |
425 | 450d4ff5 | ths | {"ble",
|
426 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_LE*0x1000,
|
427 | 450d4ff5 | ths | 0x0f00+(0xF-CC_LE)*0x1000, "o", 1, SIZE_NONE, 0, |
428 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
429 | 450d4ff5 | ths | |
430 | 450d4ff5 | ths | {"blo",
|
431 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_LO*0x1000,
|
432 | 450d4ff5 | ths | 0x0f00+(0xF-CC_LO)*0x1000, "o", 1, SIZE_NONE, 0, |
433 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
434 | 450d4ff5 | ths | |
435 | 450d4ff5 | ths | {"bls",
|
436 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_LS*0x1000,
|
437 | 450d4ff5 | ths | 0x0f00+(0xF-CC_LS)*0x1000, "o", 1, SIZE_NONE, 0, |
438 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
439 | 450d4ff5 | ths | |
440 | 450d4ff5 | ths | {"blt",
|
441 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_LT*0x1000,
|
442 | 450d4ff5 | ths | 0x0f00+(0xF-CC_LT)*0x1000, "o", 1, SIZE_NONE, 0, |
443 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
444 | 450d4ff5 | ths | |
445 | 450d4ff5 | ths | {"bmi",
|
446 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_MI*0x1000,
|
447 | 450d4ff5 | ths | 0x0f00+(0xF-CC_MI)*0x1000, "o", 1, SIZE_NONE, 0, |
448 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
449 | 450d4ff5 | ths | |
450 | 450d4ff5 | ths | {"bmod", 0x0ab0, 0x0140, "s,R", 0, SIZE_FIX_32, |
451 | 450d4ff5 | ths | cris_ver_sim_v0_10, |
452 | 450d4ff5 | ths | cris_not_implemented_op}, |
453 | 450d4ff5 | ths | |
454 | 450d4ff5 | ths | {"bmod", 0x0ab0, 0x0140, "S,D", 0, SIZE_NONE, |
455 | 450d4ff5 | ths | cris_ver_sim_v0_10, |
456 | 450d4ff5 | ths | cris_not_implemented_op}, |
457 | 450d4ff5 | ths | |
458 | 450d4ff5 | ths | {"bmod", 0x0ab0, 0x0540, "S,R,r", 0, SIZE_NONE, |
459 | 450d4ff5 | ths | cris_ver_sim_v0_10, |
460 | 450d4ff5 | ths | cris_not_implemented_op}, |
461 | 450d4ff5 | ths | |
462 | 450d4ff5 | ths | {"bne",
|
463 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_NE*0x1000,
|
464 | 450d4ff5 | ths | 0x0f00+(0xF-CC_NE)*0x1000, "o", 1, SIZE_NONE, 0, |
465 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
466 | 450d4ff5 | ths | |
467 | 450d4ff5 | ths | {"bound", 0x05c0, 0x0A00, "m r,R", 0, SIZE_NONE, 0, |
468 | 450d4ff5 | ths | cris_two_operand_bound_op}, |
469 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
|
470 | 450d4ff5 | ths | {"bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD, |
471 | 450d4ff5 | ths | cris_ver_v0_10, |
472 | 450d4ff5 | ths | cris_two_operand_bound_op}, |
473 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
|
474 | 450d4ff5 | ths | {"bound", 0x0dcf, 0x0200, "m Y,R", 0, SIZE_FIELD, 0, |
475 | 450d4ff5 | ths | cris_two_operand_bound_op}, |
476 | 450d4ff5 | ths | {"bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE, |
477 | 450d4ff5 | ths | cris_ver_v0_10, |
478 | 450d4ff5 | ths | cris_two_operand_bound_op}, |
479 | 450d4ff5 | ths | {"bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE, |
480 | 450d4ff5 | ths | cris_ver_v0_10, |
481 | 450d4ff5 | ths | cris_three_operand_bound_op}, |
482 | 450d4ff5 | ths | |
483 | 450d4ff5 | ths | {"bpl",
|
484 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_PL*0x1000,
|
485 | 450d4ff5 | ths | 0x0f00+(0xF-CC_PL)*0x1000, "o", 1, SIZE_NONE, 0, |
486 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
487 | 450d4ff5 | ths | |
488 | 450d4ff5 | ths | {"break", 0xe930, 0x16c0, "C", 0, SIZE_NONE, |
489 | 450d4ff5 | ths | cris_ver_v3p, |
490 | 450d4ff5 | ths | cris_break_op}, |
491 | 450d4ff5 | ths | |
492 | 450d4ff5 | ths | {"bsb",
|
493 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
|
494 | 450d4ff5 | ths | 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, |
495 | 450d4ff5 | ths | cris_ver_v32p, |
496 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
497 | 450d4ff5 | ths | |
498 | 450d4ff5 | ths | {"bsr", 0xBEBF, 0x4140, "n", 0, SIZE_FIX_32, |
499 | 450d4ff5 | ths | cris_ver_v32p, |
500 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
501 | 450d4ff5 | ths | |
502 | 450d4ff5 | ths | {"bsrc", 0xBEFF, 0x4100, "n", 0, SIZE_FIX_32, |
503 | 450d4ff5 | ths | cris_ver_v32p, |
504 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
505 | 450d4ff5 | ths | |
506 | 450d4ff5 | ths | {"bstore", 0x0af0, 0x0100, "s,R", 0, SIZE_FIX_32, |
507 | 450d4ff5 | ths | cris_ver_warning, |
508 | 450d4ff5 | ths | cris_not_implemented_op}, |
509 | 450d4ff5 | ths | |
510 | 450d4ff5 | ths | {"bstore", 0x0af0, 0x0100, "S,D", 0, SIZE_NONE, |
511 | 450d4ff5 | ths | cris_ver_warning, |
512 | 450d4ff5 | ths | cris_not_implemented_op}, |
513 | 450d4ff5 | ths | |
514 | 450d4ff5 | ths | {"bstore", 0x0af0, 0x0500, "S,R,r", 0, SIZE_NONE, |
515 | 450d4ff5 | ths | cris_ver_warning, |
516 | 450d4ff5 | ths | cris_not_implemented_op}, |
517 | 450d4ff5 | ths | |
518 | 450d4ff5 | ths | {"btst", 0x04F0, 0x0B00, "r,R", 0, SIZE_NONE, 0, |
519 | 450d4ff5 | ths | cris_btst_nop_op}, |
520 | 450d4ff5 | ths | {"btstq", 0x0380, 0x0C60, "c,R", 0, SIZE_NONE, 0, |
521 | 450d4ff5 | ths | cris_btst_nop_op}, |
522 | 450d4ff5 | ths | |
523 | 450d4ff5 | ths | {"bvc",
|
524 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_VC*0x1000,
|
525 | 450d4ff5 | ths | 0x0f00+(0xF-CC_VC)*0x1000, "o", 1, SIZE_NONE, 0, |
526 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
527 | 450d4ff5 | ths | |
528 | 450d4ff5 | ths | {"bvs",
|
529 | 450d4ff5 | ths | BRANCH_QUICK_OPCODE+CC_VS*0x1000,
|
530 | 450d4ff5 | ths | 0x0f00+(0xF-CC_VS)*0x1000, "o", 1, SIZE_NONE, 0, |
531 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op}, |
532 | 450d4ff5 | ths | |
533 | 450d4ff5 | ths | {"clear", 0x0670, 0x3980, "M r", 0, SIZE_NONE, 0, |
534 | 450d4ff5 | ths | cris_reg_mode_clear_op}, |
535 | 450d4ff5 | ths | |
536 | 450d4ff5 | ths | {"clear", 0x0A70, 0x3180, "M y", 0, SIZE_NONE, 0, |
537 | 450d4ff5 | ths | cris_none_reg_mode_clear_test_op}, |
538 | 450d4ff5 | ths | |
539 | 450d4ff5 | ths | {"clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE, |
540 | 450d4ff5 | ths | cris_ver_v0_10, |
541 | 450d4ff5 | ths | cris_none_reg_mode_clear_test_op}, |
542 | 450d4ff5 | ths | |
543 | 450d4ff5 | ths | {"clearf", 0x05F0, 0x0A00, "f", 0, SIZE_NONE, 0, |
544 | 450d4ff5 | ths | cris_clearf_di_op}, |
545 | 450d4ff5 | ths | |
546 | 450d4ff5 | ths | {"cmp", 0x06C0, 0x0900, "m r,R", 0, SIZE_NONE, 0, |
547 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
548 | 450d4ff5 | ths | |
549 | 450d4ff5 | ths | {"cmp", 0x0Ac0, 0x0100, "m s,R", 0, SIZE_FIELD, 0, |
550 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
551 | 450d4ff5 | ths | |
552 | 450d4ff5 | ths | {"cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE, |
553 | 450d4ff5 | ths | cris_ver_v0_10, |
554 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
555 | 450d4ff5 | ths | |
556 | 450d4ff5 | ths | {"cmpq", 0x02C0, 0x0D00, "i,R", 0, SIZE_NONE, 0, |
557 | 450d4ff5 | ths | cris_quick_mode_and_cmp_move_or_op}, |
558 | 450d4ff5 | ths | |
559 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
|
560 | 450d4ff5 | ths | {"cmps", 0x08e0, 0x0300, "z s,R", 0, SIZE_FIELD, 0, |
561 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
562 | 450d4ff5 | ths | |
563 | 450d4ff5 | ths | {"cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE, |
564 | 450d4ff5 | ths | cris_ver_v0_10, |
565 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
566 | 450d4ff5 | ths | |
567 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
|
568 | 450d4ff5 | ths | {"cmpu", 0x08c0, 0x0320, "z s,R" , 0, SIZE_FIELD, 0, |
569 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
570 | 450d4ff5 | ths | |
571 | 450d4ff5 | ths | {"cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE, |
572 | 450d4ff5 | ths | cris_ver_v0_10, |
573 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
574 | 450d4ff5 | ths | |
575 | 450d4ff5 | ths | {"di", 0x25F0, 0xDA0F, "", 0, SIZE_NONE, 0, |
576 | 450d4ff5 | ths | cris_clearf_di_op}, |
577 | 450d4ff5 | ths | |
578 | 450d4ff5 | ths | {"dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32, |
579 | 450d4ff5 | ths | cris_ver_v0_10, |
580 | 450d4ff5 | ths | cris_dip_prefix}, |
581 | 450d4ff5 | ths | |
582 | 450d4ff5 | ths | {"div", 0x0980, 0x0640, "m R,r", 0, SIZE_FIELD, 0, |
583 | 450d4ff5 | ths | cris_not_implemented_op}, |
584 | 450d4ff5 | ths | |
585 | 450d4ff5 | ths | {"dstep", 0x06f0, 0x0900, "r,R", 0, SIZE_NONE, 0, |
586 | 450d4ff5 | ths | cris_dstep_logshift_mstep_neg_not_op}, |
587 | 450d4ff5 | ths | |
588 | 450d4ff5 | ths | {"ei", 0x25B0, 0xDA4F, "", 0, SIZE_NONE, 0, |
589 | 450d4ff5 | ths | cris_ax_ei_setf_op}, |
590 | 450d4ff5 | ths | |
591 | 450d4ff5 | ths | {"fidxd", 0x0ab0, 0xf540, "[r]", 0, SIZE_NONE, |
592 | 450d4ff5 | ths | cris_ver_v32p, |
593 | 450d4ff5 | ths | cris_not_implemented_op}, |
594 | 450d4ff5 | ths | |
595 | 450d4ff5 | ths | {"fidxi", 0x0d30, 0xF2C0, "[r]", 0, SIZE_NONE, |
596 | 450d4ff5 | ths | cris_ver_v32p, |
597 | 450d4ff5 | ths | cris_not_implemented_op}, |
598 | 450d4ff5 | ths | |
599 | 450d4ff5 | ths | {"ftagd", 0x1AB0, 0xE540, "[r]", 0, SIZE_NONE, |
600 | 450d4ff5 | ths | cris_ver_v32p, |
601 | 450d4ff5 | ths | cris_not_implemented_op}, |
602 | 450d4ff5 | ths | |
603 | 450d4ff5 | ths | {"ftagi", 0x1D30, 0xE2C0, "[r]", 0, SIZE_NONE, |
604 | 450d4ff5 | ths | cris_ver_v32p, |
605 | 450d4ff5 | ths | cris_not_implemented_op}, |
606 | 450d4ff5 | ths | |
607 | 450d4ff5 | ths | {"halt", 0xF930, 0x06CF, "", 0, SIZE_NONE, |
608 | 450d4ff5 | ths | cris_ver_v32p, |
609 | 450d4ff5 | ths | cris_not_implemented_op}, |
610 | 450d4ff5 | ths | |
611 | 450d4ff5 | ths | {"jas", 0x09B0, 0x0640, "r,P", 0, SIZE_NONE, |
612 | 450d4ff5 | ths | cris_ver_v32p, |
613 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
614 | 450d4ff5 | ths | |
615 | 450d4ff5 | ths | {"jas", 0x0DBF, 0x0240, "N,P", 0, SIZE_FIX_32, |
616 | 450d4ff5 | ths | cris_ver_v32p, |
617 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
618 | 450d4ff5 | ths | |
619 | 450d4ff5 | ths | {"jasc", 0x0B30, 0x04C0, "r,P", 0, SIZE_NONE, |
620 | 450d4ff5 | ths | cris_ver_v32p, |
621 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
622 | 450d4ff5 | ths | |
623 | 450d4ff5 | ths | {"jasc", 0x0F3F, 0x00C0, "N,P", 0, SIZE_FIX_32, |
624 | 450d4ff5 | ths | cris_ver_v32p, |
625 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
626 | 450d4ff5 | ths | |
627 | 450d4ff5 | ths | {"jbrc", 0x69b0, 0x9640, "r", 0, SIZE_NONE, |
628 | 450d4ff5 | ths | cris_ver_v8_10, |
629 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
630 | 450d4ff5 | ths | |
631 | 450d4ff5 | ths | {"jbrc", 0x6930, 0x92c0, "s", 0, SIZE_FIX_32, |
632 | 450d4ff5 | ths | cris_ver_v8_10, |
633 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
634 | 450d4ff5 | ths | |
635 | 450d4ff5 | ths | {"jbrc", 0x6930, 0x92c0, "S", 0, SIZE_NONE, |
636 | 450d4ff5 | ths | cris_ver_v8_10, |
637 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
638 | 450d4ff5 | ths | |
639 | 450d4ff5 | ths | {"jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE, |
640 | 450d4ff5 | ths | cris_ver_v8_10, |
641 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
642 | 450d4ff5 | ths | |
643 | 450d4ff5 | ths | {"jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32, |
644 | 450d4ff5 | ths | cris_ver_v8_10, |
645 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
646 | 450d4ff5 | ths | |
647 | 450d4ff5 | ths | {"jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE, |
648 | 450d4ff5 | ths | cris_ver_v8_10, |
649 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
650 | 450d4ff5 | ths | |
651 | 450d4ff5 | ths | {"jirc", 0x29b0, 0xd640, "r", 0, SIZE_NONE, |
652 | 450d4ff5 | ths | cris_ver_v8_10, |
653 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
654 | 450d4ff5 | ths | |
655 | 450d4ff5 | ths | {"jirc", 0x2930, 0xd2c0, "s", 0, SIZE_FIX_32, |
656 | 450d4ff5 | ths | cris_ver_v8_10, |
657 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
658 | 450d4ff5 | ths | |
659 | 450d4ff5 | ths | {"jirc", 0x2930, 0xd2c0, "S", 0, SIZE_NONE, |
660 | 450d4ff5 | ths | cris_ver_v8_10, |
661 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
662 | 450d4ff5 | ths | |
663 | 450d4ff5 | ths | {"jsr", 0xB9b0, 0x4640, "r", 0, SIZE_NONE, 0, |
664 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
665 | 450d4ff5 | ths | |
666 | 450d4ff5 | ths | {"jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32, |
667 | 450d4ff5 | ths | cris_ver_v0_10, |
668 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
669 | 450d4ff5 | ths | |
670 | 450d4ff5 | ths | {"jsr", 0xBDBF, 0x4240, "N", 0, SIZE_FIX_32, |
671 | 450d4ff5 | ths | cris_ver_v32p, |
672 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
673 | 450d4ff5 | ths | |
674 | 450d4ff5 | ths | {"jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE, |
675 | 450d4ff5 | ths | cris_ver_v0_10, |
676 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
677 | 450d4ff5 | ths | |
678 | 450d4ff5 | ths | {"jsrc", 0x39b0, 0xc640, "r", 0, SIZE_NONE, |
679 | 450d4ff5 | ths | cris_ver_v8_10, |
680 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
681 | 450d4ff5 | ths | |
682 | 450d4ff5 | ths | {"jsrc", 0x3930, 0xc2c0, "s", 0, SIZE_FIX_32, |
683 | 450d4ff5 | ths | cris_ver_v8_10, |
684 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
685 | 450d4ff5 | ths | |
686 | 450d4ff5 | ths | {"jsrc", 0x3930, 0xc2c0, "S", 0, SIZE_NONE, |
687 | 450d4ff5 | ths | cris_ver_v8_10, |
688 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
689 | 450d4ff5 | ths | |
690 | 450d4ff5 | ths | {"jsrc", 0xBB30, 0x44C0, "r", 0, SIZE_NONE, |
691 | 450d4ff5 | ths | cris_ver_v32p, |
692 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
693 | 450d4ff5 | ths | |
694 | 450d4ff5 | ths | {"jsrc", 0xBF3F, 0x40C0, "N", 0, SIZE_FIX_32, |
695 | 450d4ff5 | ths | cris_ver_v32p, |
696 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
697 | 450d4ff5 | ths | |
698 | 450d4ff5 | ths | {"jump", 0x09b0, 0xF640, "r", 0, SIZE_NONE, 0, |
699 | 450d4ff5 | ths | cris_reg_mode_jump_op}, |
700 | 450d4ff5 | ths | |
701 | 450d4ff5 | ths | {"jump",
|
702 | 450d4ff5 | ths | JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "s", 0, SIZE_FIX_32, |
703 | 450d4ff5 | ths | cris_ver_v0_10, |
704 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
705 | 450d4ff5 | ths | |
706 | 450d4ff5 | ths | {"jump",
|
707 | 450d4ff5 | ths | JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "S", 0, SIZE_NONE, |
708 | 450d4ff5 | ths | cris_ver_v0_10, |
709 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
710 | 450d4ff5 | ths | |
711 | 450d4ff5 | ths | {"jump", 0x09F0, 0x060F, "P", 0, SIZE_NONE, |
712 | 450d4ff5 | ths | cris_ver_v32p, |
713 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
714 | 450d4ff5 | ths | |
715 | 450d4ff5 | ths | {"jump",
|
716 | 450d4ff5 | ths | JUMP_PC_INCR_OPCODE_V32, |
717 | 450d4ff5 | ths | (0xffff & ~JUMP_PC_INCR_OPCODE_V32), "N", 0, SIZE_FIX_32, |
718 | 450d4ff5 | ths | cris_ver_v32p, |
719 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
720 | 450d4ff5 | ths | |
721 | 450d4ff5 | ths | {"jmpu", 0x8930, 0x72c0, "s", 0, SIZE_FIX_32, |
722 | 450d4ff5 | ths | cris_ver_v10, |
723 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
724 | 450d4ff5 | ths | |
725 | 450d4ff5 | ths | {"jmpu", 0x8930, 0x72c0, "S", 0, SIZE_NONE, |
726 | 450d4ff5 | ths | cris_ver_v10, |
727 | 450d4ff5 | ths | cris_none_reg_mode_jump_op}, |
728 | 450d4ff5 | ths | |
729 | 450d4ff5 | ths | {"lapc", 0x0970, 0x0680, "U,R", 0, SIZE_NONE, |
730 | 450d4ff5 | ths | cris_ver_v32p, |
731 | 450d4ff5 | ths | cris_not_implemented_op}, |
732 | 450d4ff5 | ths | |
733 | 450d4ff5 | ths | {"lapc", 0x0D7F, 0x0280, "dn,R", 0, SIZE_FIX_32, |
734 | 450d4ff5 | ths | cris_ver_v32p, |
735 | 450d4ff5 | ths | cris_not_implemented_op}, |
736 | 450d4ff5 | ths | |
737 | 450d4ff5 | ths | {"lapcq", 0x0970, 0x0680, "u,R", 0, SIZE_NONE, |
738 | 450d4ff5 | ths | cris_ver_v32p, |
739 | 450d4ff5 | ths | cris_addi_op}, |
740 | 450d4ff5 | ths | |
741 | 450d4ff5 | ths | {"lsl", 0x04C0, 0x0B00, "m r,R", 0, SIZE_NONE, 0, |
742 | 450d4ff5 | ths | cris_dstep_logshift_mstep_neg_not_op}, |
743 | 450d4ff5 | ths | |
744 | 450d4ff5 | ths | {"lslq", 0x03c0, 0x0C20, "c,R", 0, SIZE_NONE, 0, |
745 | 450d4ff5 | ths | cris_dstep_logshift_mstep_neg_not_op}, |
746 | 450d4ff5 | ths | |
747 | 450d4ff5 | ths | {"lsr", 0x07C0, 0x0800, "m r,R", 0, SIZE_NONE, 0, |
748 | 450d4ff5 | ths | cris_dstep_logshift_mstep_neg_not_op}, |
749 | 450d4ff5 | ths | |
750 | 450d4ff5 | ths | {"lsrq", 0x03e0, 0x0C00, "c,R", 0, SIZE_NONE, 0, |
751 | 450d4ff5 | ths | cris_dstep_logshift_mstep_neg_not_op}, |
752 | 450d4ff5 | ths | |
753 | 450d4ff5 | ths | {"lz", 0x0730, 0x08C0, "r,R", 0, SIZE_NONE, |
754 | 450d4ff5 | ths | cris_ver_v3p, |
755 | 450d4ff5 | ths | cris_not_implemented_op}, |
756 | 450d4ff5 | ths | |
757 | 450d4ff5 | ths | {"mcp", 0x07f0, 0x0800, "P,r", 0, SIZE_NONE, |
758 | 450d4ff5 | ths | cris_ver_v32p, |
759 | 450d4ff5 | ths | cris_not_implemented_op}, |
760 | 450d4ff5 | ths | |
761 | 450d4ff5 | ths | {"move", 0x0640, 0x0980, "m r,R", 0, SIZE_NONE, 0, |
762 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
763 | 450d4ff5 | ths | |
764 | 450d4ff5 | ths | {"move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0, |
765 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
766 | 450d4ff5 | ths | |
767 | 450d4ff5 | ths | {"move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE, |
768 | 450d4ff5 | ths | cris_ver_v0_10, |
769 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
770 | 450d4ff5 | ths | |
771 | 450d4ff5 | ths | {"move", 0x0630, 0x09c0, "r,P", 0, SIZE_NONE, 0, |
772 | 450d4ff5 | ths | cris_move_to_preg_op}, |
773 | 450d4ff5 | ths | |
774 | 450d4ff5 | ths | {"move", 0x0670, 0x0980, "P,r", 0, SIZE_NONE, 0, |
775 | 450d4ff5 | ths | cris_reg_mode_move_from_preg_op}, |
776 | 450d4ff5 | ths | |
777 | 450d4ff5 | ths | {"move", 0x0BC0, 0x0000, "m R,y", 0, SIZE_FIELD, 0, |
778 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
779 | 450d4ff5 | ths | |
780 | 450d4ff5 | ths | {"move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE, |
781 | 450d4ff5 | ths | cris_ver_v0_10, |
782 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
783 | 450d4ff5 | ths | |
784 | 450d4ff5 | ths | {"move",
|
785 | 450d4ff5 | ths | MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS, |
786 | 450d4ff5 | ths | "s,P", 0, SIZE_SPEC_REG, 0, |
787 | 450d4ff5 | ths | cris_move_to_preg_op}, |
788 | 450d4ff5 | ths | |
789 | 450d4ff5 | ths | {"move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE, |
790 | 450d4ff5 | ths | cris_ver_v0_10, |
791 | 450d4ff5 | ths | cris_move_to_preg_op}, |
792 | 450d4ff5 | ths | |
793 | 450d4ff5 | ths | {"move", 0x0A70, 0x0180, "P,y", 0, SIZE_SPEC_REG, 0, |
794 | 450d4ff5 | ths | cris_none_reg_mode_move_from_preg_op}, |
795 | 450d4ff5 | ths | |
796 | 450d4ff5 | ths | {"move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE, |
797 | 450d4ff5 | ths | cris_ver_v0_10, |
798 | 450d4ff5 | ths | cris_none_reg_mode_move_from_preg_op}, |
799 | 450d4ff5 | ths | |
800 | 450d4ff5 | ths | {"move", 0x0B70, 0x0480, "r,T", 0, SIZE_NONE, |
801 | 450d4ff5 | ths | cris_ver_v32p, |
802 | 450d4ff5 | ths | cris_not_implemented_op}, |
803 | 450d4ff5 | ths | |
804 | 450d4ff5 | ths | {"move", 0x0F70, 0x0080, "T,r", 0, SIZE_NONE, |
805 | 450d4ff5 | ths | cris_ver_v32p, |
806 | 450d4ff5 | ths | cris_not_implemented_op}, |
807 | 450d4ff5 | ths | |
808 | 450d4ff5 | ths | {"movem", 0x0BF0, 0x0000, "R,y", 0, SIZE_FIX_32, 0, |
809 | 450d4ff5 | ths | cris_move_reg_to_mem_movem_op}, |
810 | 450d4ff5 | ths | |
811 | 450d4ff5 | ths | {"movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE, |
812 | 450d4ff5 | ths | cris_ver_v0_10, |
813 | 450d4ff5 | ths | cris_move_reg_to_mem_movem_op}, |
814 | 450d4ff5 | ths | |
815 | 450d4ff5 | ths | {"movem", 0x0BB0, 0x0040, "s,R", 0, SIZE_FIX_32, 0, |
816 | 450d4ff5 | ths | cris_move_mem_to_reg_movem_op}, |
817 | 450d4ff5 | ths | |
818 | 450d4ff5 | ths | {"movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE, |
819 | 450d4ff5 | ths | cris_ver_v0_10, |
820 | 450d4ff5 | ths | cris_move_mem_to_reg_movem_op}, |
821 | 450d4ff5 | ths | |
822 | 450d4ff5 | ths | {"moveq", 0x0240, 0x0D80, "i,R", 0, SIZE_NONE, 0, |
823 | 450d4ff5 | ths | cris_quick_mode_and_cmp_move_or_op}, |
824 | 450d4ff5 | ths | |
825 | 450d4ff5 | ths | {"movs", 0x0460, 0x0B80, "z r,R", 0, SIZE_NONE, 0, |
826 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
827 | 450d4ff5 | ths | |
828 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
|
829 | 450d4ff5 | ths | {"movs", 0x0860, 0x0380, "z s,R", 0, SIZE_FIELD, 0, |
830 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
831 | 450d4ff5 | ths | |
832 | 450d4ff5 | ths | {"movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE, |
833 | 450d4ff5 | ths | cris_ver_v0_10, |
834 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
835 | 450d4ff5 | ths | |
836 | 450d4ff5 | ths | {"movu", 0x0440, 0x0Ba0, "z r,R", 0, SIZE_NONE, 0, |
837 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
838 | 450d4ff5 | ths | |
839 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
|
840 | 450d4ff5 | ths | {"movu", 0x0840, 0x03a0, "z s,R", 0, SIZE_FIELD, 0, |
841 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
842 | 450d4ff5 | ths | |
843 | 450d4ff5 | ths | {"movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE, |
844 | 450d4ff5 | ths | cris_ver_v0_10, |
845 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
846 | 450d4ff5 | ths | |
847 | 450d4ff5 | ths | {"mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE, |
848 | 450d4ff5 | ths | cris_ver_v0_10, |
849 | 450d4ff5 | ths | cris_dstep_logshift_mstep_neg_not_op}, |
850 | 450d4ff5 | ths | |
851 | 450d4ff5 | ths | {"muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE, |
852 | 450d4ff5 | ths | cris_ver_v10p, |
853 | 450d4ff5 | ths | cris_muls_op}, |
854 | 450d4ff5 | ths | |
855 | 450d4ff5 | ths | {"mulu", 0x0900, 0x06c0, "m r,R", 0, SIZE_NONE, |
856 | 450d4ff5 | ths | cris_ver_v10p, |
857 | 450d4ff5 | ths | cris_mulu_op}, |
858 | 450d4ff5 | ths | |
859 | 450d4ff5 | ths | {"neg", 0x0580, 0x0A40, "m r,R", 0, SIZE_NONE, 0, |
860 | 450d4ff5 | ths | cris_dstep_logshift_mstep_neg_not_op}, |
861 | 450d4ff5 | ths | |
862 | 450d4ff5 | ths | {"nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE, |
863 | 450d4ff5 | ths | cris_ver_v0_10, |
864 | 450d4ff5 | ths | cris_btst_nop_op}, |
865 | 450d4ff5 | ths | |
866 | 450d4ff5 | ths | {"nop", NOP_OPCODE_V32, NOP_Z_BITS_V32, "", 0, SIZE_NONE, |
867 | 450d4ff5 | ths | cris_ver_v32p, |
868 | 450d4ff5 | ths | cris_btst_nop_op}, |
869 | 450d4ff5 | ths | |
870 | 450d4ff5 | ths | {"not", 0x8770, 0x7880, "r", 0, SIZE_NONE, 0, |
871 | 450d4ff5 | ths | cris_dstep_logshift_mstep_neg_not_op}, |
872 | 450d4ff5 | ths | |
873 | 450d4ff5 | ths | {"or", 0x0740, 0x0880, "m r,R", 0, SIZE_NONE, 0, |
874 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
875 | 450d4ff5 | ths | |
876 | 450d4ff5 | ths | {"or", 0x0B40, 0x0080, "m s,R", 0, SIZE_FIELD, 0, |
877 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
878 | 450d4ff5 | ths | |
879 | 450d4ff5 | ths | {"or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE, |
880 | 450d4ff5 | ths | cris_ver_v0_10, |
881 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
882 | 450d4ff5 | ths | |
883 | 450d4ff5 | ths | {"or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE, |
884 | 450d4ff5 | ths | cris_ver_v0_10, |
885 | 450d4ff5 | ths | cris_three_operand_add_sub_cmp_and_or_op}, |
886 | 450d4ff5 | ths | |
887 | 450d4ff5 | ths | {"orq", 0x0340, 0x0C80, "i,R", 0, SIZE_NONE, 0, |
888 | 450d4ff5 | ths | cris_quick_mode_and_cmp_move_or_op}, |
889 | 450d4ff5 | ths | |
890 | 450d4ff5 | ths | {"pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE, |
891 | 450d4ff5 | ths | cris_ver_v0_10, |
892 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
893 | 450d4ff5 | ths | |
894 | 450d4ff5 | ths | {"pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE, |
895 | 450d4ff5 | ths | cris_ver_v0_10, |
896 | 450d4ff5 | ths | cris_none_reg_mode_move_from_preg_op}, |
897 | 450d4ff5 | ths | |
898 | 450d4ff5 | ths | {"push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE, |
899 | 450d4ff5 | ths | cris_ver_v0_10, |
900 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
901 | 450d4ff5 | ths | |
902 | 450d4ff5 | ths | {"push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE, |
903 | 450d4ff5 | ths | cris_ver_v0_10, |
904 | 450d4ff5 | ths | cris_move_to_preg_op}, |
905 | 450d4ff5 | ths | |
906 | 450d4ff5 | ths | {"rbf", 0x3b30, 0xc0c0, "y", 0, SIZE_NONE, |
907 | 450d4ff5 | ths | cris_ver_v10, |
908 | 450d4ff5 | ths | cris_not_implemented_op}, |
909 | 450d4ff5 | ths | |
910 | 450d4ff5 | ths | {"rbf", 0x3b30, 0xc0c0, "S", 0, SIZE_NONE, |
911 | 450d4ff5 | ths | cris_ver_v10, |
912 | 450d4ff5 | ths | cris_not_implemented_op}, |
913 | 450d4ff5 | ths | |
914 | 450d4ff5 | ths | {"rfe", 0x2930, 0xD6CF, "", 0, SIZE_NONE, |
915 | 450d4ff5 | ths | cris_ver_v32p, |
916 | 450d4ff5 | ths | cris_not_implemented_op}, |
917 | 450d4ff5 | ths | |
918 | 450d4ff5 | ths | {"rfg", 0x4930, 0xB6CF, "", 0, SIZE_NONE, |
919 | 450d4ff5 | ths | cris_ver_v32p, |
920 | 450d4ff5 | ths | cris_not_implemented_op}, |
921 | 450d4ff5 | ths | |
922 | 450d4ff5 | ths | {"rfn", 0x5930, 0xA6CF, "", 0, SIZE_NONE, |
923 | 450d4ff5 | ths | cris_ver_v32p, |
924 | 450d4ff5 | ths | cris_not_implemented_op}, |
925 | 450d4ff5 | ths | |
926 | 450d4ff5 | ths | {"ret", 0xB67F, 0x4980, "", 1, SIZE_NONE, |
927 | 450d4ff5 | ths | cris_ver_v0_10, |
928 | 450d4ff5 | ths | cris_reg_mode_move_from_preg_op}, |
929 | 450d4ff5 | ths | |
930 | 450d4ff5 | ths | {"ret", 0xB9F0, 0x460F, "", 1, SIZE_NONE, |
931 | 450d4ff5 | ths | cris_ver_v32p, |
932 | 450d4ff5 | ths | cris_reg_mode_move_from_preg_op}, |
933 | 450d4ff5 | ths | |
934 | 450d4ff5 | ths | {"retb", 0xe67f, 0x1980, "", 1, SIZE_NONE, |
935 | 450d4ff5 | ths | cris_ver_v0_10, |
936 | 450d4ff5 | ths | cris_reg_mode_move_from_preg_op}, |
937 | 450d4ff5 | ths | |
938 | 450d4ff5 | ths | {"rete", 0xA9F0, 0x560F, "", 1, SIZE_NONE, |
939 | 450d4ff5 | ths | cris_ver_v32p, |
940 | 450d4ff5 | ths | cris_reg_mode_move_from_preg_op}, |
941 | 450d4ff5 | ths | |
942 | 450d4ff5 | ths | {"reti", 0xA67F, 0x5980, "", 1, SIZE_NONE, |
943 | 450d4ff5 | ths | cris_ver_v0_10, |
944 | 450d4ff5 | ths | cris_reg_mode_move_from_preg_op}, |
945 | 450d4ff5 | ths | |
946 | 450d4ff5 | ths | {"retn", 0xC9F0, 0x360F, "", 1, SIZE_NONE, |
947 | 450d4ff5 | ths | cris_ver_v32p, |
948 | 450d4ff5 | ths | cris_reg_mode_move_from_preg_op}, |
949 | 450d4ff5 | ths | |
950 | 450d4ff5 | ths | {"sbfs", 0x3b70, 0xc080, "y", 0, SIZE_NONE, |
951 | 450d4ff5 | ths | cris_ver_v10, |
952 | 450d4ff5 | ths | cris_not_implemented_op}, |
953 | 450d4ff5 | ths | |
954 | 450d4ff5 | ths | {"sbfs", 0x3b70, 0xc080, "S", 0, SIZE_NONE, |
955 | 450d4ff5 | ths | cris_ver_v10, |
956 | 450d4ff5 | ths | cris_not_implemented_op}, |
957 | 450d4ff5 | ths | |
958 | 450d4ff5 | ths | {"sa",
|
959 | 450d4ff5 | ths | 0x0530+CC_A*0x1000, |
960 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_A)*0x1000, "r", 0, SIZE_NONE, 0, |
961 | 450d4ff5 | ths | cris_scc_op}, |
962 | 450d4ff5 | ths | |
963 | 450d4ff5 | ths | {"ssb",
|
964 | 450d4ff5 | ths | 0x0530+CC_EXT*0x1000, |
965 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, |
966 | 450d4ff5 | ths | cris_ver_v32p, |
967 | 450d4ff5 | ths | cris_scc_op}, |
968 | 450d4ff5 | ths | |
969 | 450d4ff5 | ths | {"scc",
|
970 | 450d4ff5 | ths | 0x0530+CC_CC*0x1000, |
971 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_CC)*0x1000, "r", 0, SIZE_NONE, 0, |
972 | 450d4ff5 | ths | cris_scc_op}, |
973 | 450d4ff5 | ths | |
974 | 450d4ff5 | ths | {"scs",
|
975 | 450d4ff5 | ths | 0x0530+CC_CS*0x1000, |
976 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_CS)*0x1000, "r", 0, SIZE_NONE, 0, |
977 | 450d4ff5 | ths | cris_scc_op}, |
978 | 450d4ff5 | ths | |
979 | 450d4ff5 | ths | {"seq",
|
980 | 450d4ff5 | ths | 0x0530+CC_EQ*0x1000, |
981 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_EQ)*0x1000, "r", 0, SIZE_NONE, 0, |
982 | 450d4ff5 | ths | cris_scc_op}, |
983 | 450d4ff5 | ths | |
984 | 450d4ff5 | ths | {"setf", 0x05b0, 0x0A40, "f", 0, SIZE_NONE, 0, |
985 | 450d4ff5 | ths | cris_ax_ei_setf_op}, |
986 | 450d4ff5 | ths | |
987 | 450d4ff5 | ths | {"sfe", 0x3930, 0xC6CF, "", 0, SIZE_NONE, |
988 | 450d4ff5 | ths | cris_ver_v32p, |
989 | 450d4ff5 | ths | cris_not_implemented_op}, |
990 | 450d4ff5 | ths | |
991 | 450d4ff5 | ths | /* Need to have "swf" in front of "sext" so it is the one displayed in
|
992 | 450d4ff5 | ths | disassembly. */
|
993 | 450d4ff5 | ths | {"swf",
|
994 | 450d4ff5 | ths | 0x0530+CC_EXT*0x1000, |
995 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, |
996 | 450d4ff5 | ths | cris_ver_v10, |
997 | 450d4ff5 | ths | cris_scc_op}, |
998 | 450d4ff5 | ths | |
999 | 450d4ff5 | ths | {"sext",
|
1000 | 450d4ff5 | ths | 0x0530+CC_EXT*0x1000, |
1001 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, |
1002 | 450d4ff5 | ths | cris_ver_v0_3, |
1003 | 450d4ff5 | ths | cris_scc_op}, |
1004 | 450d4ff5 | ths | |
1005 | 450d4ff5 | ths | {"sge",
|
1006 | 450d4ff5 | ths | 0x0530+CC_GE*0x1000, |
1007 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_GE)*0x1000, "r", 0, SIZE_NONE, 0, |
1008 | 450d4ff5 | ths | cris_scc_op}, |
1009 | 450d4ff5 | ths | |
1010 | 450d4ff5 | ths | {"sgt",
|
1011 | 450d4ff5 | ths | 0x0530+CC_GT*0x1000, |
1012 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_GT)*0x1000, "r", 0, SIZE_NONE, 0, |
1013 | 450d4ff5 | ths | cris_scc_op}, |
1014 | 450d4ff5 | ths | |
1015 | 450d4ff5 | ths | {"shi",
|
1016 | 450d4ff5 | ths | 0x0530+CC_HI*0x1000, |
1017 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_HI)*0x1000, "r", 0, SIZE_NONE, 0, |
1018 | 450d4ff5 | ths | cris_scc_op}, |
1019 | 450d4ff5 | ths | |
1020 | 450d4ff5 | ths | {"shs",
|
1021 | 450d4ff5 | ths | 0x0530+CC_HS*0x1000, |
1022 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_HS)*0x1000, "r", 0, SIZE_NONE, 0, |
1023 | 450d4ff5 | ths | cris_scc_op}, |
1024 | 450d4ff5 | ths | |
1025 | 450d4ff5 | ths | {"sle",
|
1026 | 450d4ff5 | ths | 0x0530+CC_LE*0x1000, |
1027 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_LE)*0x1000, "r", 0, SIZE_NONE, 0, |
1028 | 450d4ff5 | ths | cris_scc_op}, |
1029 | 450d4ff5 | ths | |
1030 | 450d4ff5 | ths | {"slo",
|
1031 | 450d4ff5 | ths | 0x0530+CC_LO*0x1000, |
1032 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_LO)*0x1000, "r", 0, SIZE_NONE, 0, |
1033 | 450d4ff5 | ths | cris_scc_op}, |
1034 | 450d4ff5 | ths | |
1035 | 450d4ff5 | ths | {"sls",
|
1036 | 450d4ff5 | ths | 0x0530+CC_LS*0x1000, |
1037 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_LS)*0x1000, "r", 0, SIZE_NONE, 0, |
1038 | 450d4ff5 | ths | cris_scc_op}, |
1039 | 450d4ff5 | ths | |
1040 | 450d4ff5 | ths | {"slt",
|
1041 | 450d4ff5 | ths | 0x0530+CC_LT*0x1000, |
1042 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_LT)*0x1000, "r", 0, SIZE_NONE, 0, |
1043 | 450d4ff5 | ths | cris_scc_op}, |
1044 | 450d4ff5 | ths | |
1045 | 450d4ff5 | ths | {"smi",
|
1046 | 450d4ff5 | ths | 0x0530+CC_MI*0x1000, |
1047 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_MI)*0x1000, "r", 0, SIZE_NONE, 0, |
1048 | 450d4ff5 | ths | cris_scc_op}, |
1049 | 450d4ff5 | ths | |
1050 | 450d4ff5 | ths | {"sne",
|
1051 | 450d4ff5 | ths | 0x0530+CC_NE*0x1000, |
1052 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_NE)*0x1000, "r", 0, SIZE_NONE, 0, |
1053 | 450d4ff5 | ths | cris_scc_op}, |
1054 | 450d4ff5 | ths | |
1055 | 450d4ff5 | ths | {"spl",
|
1056 | 450d4ff5 | ths | 0x0530+CC_PL*0x1000, |
1057 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_PL)*0x1000, "r", 0, SIZE_NONE, 0, |
1058 | 450d4ff5 | ths | cris_scc_op}, |
1059 | 450d4ff5 | ths | |
1060 | 450d4ff5 | ths | {"sub", 0x0680, 0x0940, "m r,R", 0, SIZE_NONE, 0, |
1061 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
1062 | 450d4ff5 | ths | |
1063 | 450d4ff5 | ths | {"sub", 0x0a80, 0x0140, "m s,R", 0, SIZE_FIELD, 0, |
1064 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
1065 | 450d4ff5 | ths | |
1066 | 450d4ff5 | ths | {"sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE, |
1067 | 450d4ff5 | ths | cris_ver_v0_10, |
1068 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
1069 | 450d4ff5 | ths | |
1070 | 450d4ff5 | ths | {"sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE, |
1071 | 450d4ff5 | ths | cris_ver_v0_10, |
1072 | 450d4ff5 | ths | cris_three_operand_add_sub_cmp_and_or_op}, |
1073 | 450d4ff5 | ths | |
1074 | 450d4ff5 | ths | {"subq", 0x0280, 0x0d40, "I,R", 0, SIZE_NONE, 0, |
1075 | 450d4ff5 | ths | cris_quick_mode_add_sub_op}, |
1076 | 450d4ff5 | ths | |
1077 | 450d4ff5 | ths | {"subs", 0x04a0, 0x0b40, "z r,R", 0, SIZE_NONE, 0, |
1078 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
1079 | 450d4ff5 | ths | |
1080 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
|
1081 | 450d4ff5 | ths | {"subs", 0x08a0, 0x0340, "z s,R", 0, SIZE_FIELD, 0, |
1082 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
1083 | 450d4ff5 | ths | |
1084 | 450d4ff5 | ths | {"subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE, |
1085 | 450d4ff5 | ths | cris_ver_v0_10, |
1086 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
1087 | 450d4ff5 | ths | |
1088 | 450d4ff5 | ths | {"subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE, |
1089 | 450d4ff5 | ths | cris_ver_v0_10, |
1090 | 450d4ff5 | ths | cris_three_operand_add_sub_cmp_and_or_op}, |
1091 | 450d4ff5 | ths | |
1092 | 450d4ff5 | ths | {"subu", 0x0480, 0x0b60, "z r,R", 0, SIZE_NONE, 0, |
1093 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
1094 | 450d4ff5 | ths | |
1095 | 450d4ff5 | ths | /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
|
1096 | 450d4ff5 | ths | {"subu", 0x0880, 0x0360, "z s,R", 0, SIZE_FIELD, 0, |
1097 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
1098 | 450d4ff5 | ths | |
1099 | 450d4ff5 | ths | {"subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE, |
1100 | 450d4ff5 | ths | cris_ver_v0_10, |
1101 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
1102 | 450d4ff5 | ths | |
1103 | 450d4ff5 | ths | {"subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE, |
1104 | 450d4ff5 | ths | cris_ver_v0_10, |
1105 | 450d4ff5 | ths | cris_three_operand_add_sub_cmp_and_or_op}, |
1106 | 450d4ff5 | ths | |
1107 | 450d4ff5 | ths | {"svc",
|
1108 | 450d4ff5 | ths | 0x0530+CC_VC*0x1000, |
1109 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_VC)*0x1000, "r", 0, SIZE_NONE, 0, |
1110 | 450d4ff5 | ths | cris_scc_op}, |
1111 | 450d4ff5 | ths | |
1112 | 450d4ff5 | ths | {"svs",
|
1113 | 450d4ff5 | ths | 0x0530+CC_VS*0x1000, |
1114 | 450d4ff5 | ths | 0x0AC0+(0xf-CC_VS)*0x1000, "r", 0, SIZE_NONE, 0, |
1115 | 450d4ff5 | ths | cris_scc_op}, |
1116 | 450d4ff5 | ths | |
1117 | 450d4ff5 | ths | /* The insn "swapn" is the same as "not" and will be disassembled as
|
1118 | 450d4ff5 | ths | such, but the swap* family of mnmonics are generally v8-and-higher
|
1119 | 450d4ff5 | ths | only, so count it in. */
|
1120 | 450d4ff5 | ths | {"swapn", 0x8770, 0x7880, "r", 0, SIZE_NONE, |
1121 | 450d4ff5 | ths | cris_ver_v8p, |
1122 | 450d4ff5 | ths | cris_not_implemented_op}, |
1123 | 450d4ff5 | ths | |
1124 | 450d4ff5 | ths | {"swapw", 0x4770, 0xb880, "r", 0, SIZE_NONE, |
1125 | 450d4ff5 | ths | cris_ver_v8p, |
1126 | 450d4ff5 | ths | cris_not_implemented_op}, |
1127 | 450d4ff5 | ths | |
1128 | 450d4ff5 | ths | {"swapnw", 0xc770, 0x3880, "r", 0, SIZE_NONE, |
1129 | 450d4ff5 | ths | cris_ver_v8p, |
1130 | 450d4ff5 | ths | cris_not_implemented_op}, |
1131 | 450d4ff5 | ths | |
1132 | 450d4ff5 | ths | {"swapb", 0x2770, 0xd880, "r", 0, SIZE_NONE, |
1133 | 450d4ff5 | ths | cris_ver_v8p, |
1134 | 450d4ff5 | ths | cris_not_implemented_op}, |
1135 | 450d4ff5 | ths | |
1136 | 450d4ff5 | ths | {"swapnb", 0xA770, 0x5880, "r", 0, SIZE_NONE, |
1137 | 450d4ff5 | ths | cris_ver_v8p, |
1138 | 450d4ff5 | ths | cris_not_implemented_op}, |
1139 | 450d4ff5 | ths | |
1140 | 450d4ff5 | ths | {"swapwb", 0x6770, 0x9880, "r", 0, SIZE_NONE, |
1141 | 450d4ff5 | ths | cris_ver_v8p, |
1142 | 450d4ff5 | ths | cris_not_implemented_op}, |
1143 | 450d4ff5 | ths | |
1144 | 450d4ff5 | ths | {"swapnwb", 0xE770, 0x1880, "r", 0, SIZE_NONE, |
1145 | 450d4ff5 | ths | cris_ver_v8p, |
1146 | 450d4ff5 | ths | cris_not_implemented_op}, |
1147 | 450d4ff5 | ths | |
1148 | 450d4ff5 | ths | {"swapr", 0x1770, 0xe880, "r", 0, SIZE_NONE, |
1149 | 450d4ff5 | ths | cris_ver_v8p, |
1150 | 450d4ff5 | ths | cris_not_implemented_op}, |
1151 | 450d4ff5 | ths | |
1152 | 450d4ff5 | ths | {"swapnr", 0x9770, 0x6880, "r", 0, SIZE_NONE, |
1153 | 450d4ff5 | ths | cris_ver_v8p, |
1154 | 450d4ff5 | ths | cris_not_implemented_op}, |
1155 | 450d4ff5 | ths | |
1156 | 450d4ff5 | ths | {"swapwr", 0x5770, 0xa880, "r", 0, SIZE_NONE, |
1157 | 450d4ff5 | ths | cris_ver_v8p, |
1158 | 450d4ff5 | ths | cris_not_implemented_op}, |
1159 | 450d4ff5 | ths | |
1160 | 450d4ff5 | ths | {"swapnwr", 0xd770, 0x2880, "r", 0, SIZE_NONE, |
1161 | 450d4ff5 | ths | cris_ver_v8p, |
1162 | 450d4ff5 | ths | cris_not_implemented_op}, |
1163 | 450d4ff5 | ths | |
1164 | 450d4ff5 | ths | {"swapbr", 0x3770, 0xc880, "r", 0, SIZE_NONE, |
1165 | 450d4ff5 | ths | cris_ver_v8p, |
1166 | 450d4ff5 | ths | cris_not_implemented_op}, |
1167 | 450d4ff5 | ths | |
1168 | 450d4ff5 | ths | {"swapnbr", 0xb770, 0x4880, "r", 0, SIZE_NONE, |
1169 | 450d4ff5 | ths | cris_ver_v8p, |
1170 | 450d4ff5 | ths | cris_not_implemented_op}, |
1171 | 450d4ff5 | ths | |
1172 | 450d4ff5 | ths | {"swapwbr", 0x7770, 0x8880, "r", 0, SIZE_NONE, |
1173 | 450d4ff5 | ths | cris_ver_v8p, |
1174 | 450d4ff5 | ths | cris_not_implemented_op}, |
1175 | 450d4ff5 | ths | |
1176 | 450d4ff5 | ths | {"swapnwbr", 0xf770, 0x0880, "r", 0, SIZE_NONE, |
1177 | 450d4ff5 | ths | cris_ver_v8p, |
1178 | 450d4ff5 | ths | cris_not_implemented_op}, |
1179 | 450d4ff5 | ths | |
1180 | 450d4ff5 | ths | {"test", 0x0640, 0x0980, "m D", 0, SIZE_NONE, |
1181 | 450d4ff5 | ths | cris_ver_v0_10, |
1182 | 450d4ff5 | ths | cris_reg_mode_test_op}, |
1183 | 450d4ff5 | ths | |
1184 | 450d4ff5 | ths | {"test", 0x0b80, 0xf040, "m y", 0, SIZE_FIELD, 0, |
1185 | 450d4ff5 | ths | cris_none_reg_mode_clear_test_op}, |
1186 | 450d4ff5 | ths | |
1187 | 450d4ff5 | ths | {"test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE, |
1188 | 450d4ff5 | ths | cris_ver_v0_10, |
1189 | 450d4ff5 | ths | cris_none_reg_mode_clear_test_op}, |
1190 | 450d4ff5 | ths | |
1191 | 450d4ff5 | ths | {"xor", 0x07B0, 0x0840, "r,R", 0, SIZE_NONE, 0, |
1192 | 450d4ff5 | ths | cris_xor_op}, |
1193 | 450d4ff5 | ths | |
1194 | 450d4ff5 | ths | {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op} |
1195 | 450d4ff5 | ths | }; |
1196 | 450d4ff5 | ths | |
1197 | 450d4ff5 | ths | /* Condition-names, indexed by the CC_* numbers as found in cris.h. */
|
1198 | 450d4ff5 | ths | const char * const |
1199 | 450d4ff5 | ths | cris_cc_strings[] = |
1200 | 450d4ff5 | ths | { |
1201 | 450d4ff5 | ths | "hs",
|
1202 | 450d4ff5 | ths | "lo",
|
1203 | 450d4ff5 | ths | "ne",
|
1204 | 450d4ff5 | ths | "eq",
|
1205 | 450d4ff5 | ths | "vc",
|
1206 | 450d4ff5 | ths | "vs",
|
1207 | 450d4ff5 | ths | "pl",
|
1208 | 450d4ff5 | ths | "mi",
|
1209 | 450d4ff5 | ths | "ls",
|
1210 | 450d4ff5 | ths | "hi",
|
1211 | 450d4ff5 | ths | "ge",
|
1212 | 450d4ff5 | ths | "lt",
|
1213 | 450d4ff5 | ths | "gt",
|
1214 | 450d4ff5 | ths | "le",
|
1215 | 450d4ff5 | ths | "a",
|
1216 | 450d4ff5 | ths | /* This is a placeholder. In v0, this would be "ext". In v32, this
|
1217 | 450d4ff5 | ths | is "sb". See cris_conds15. */
|
1218 | 450d4ff5 | ths | "wf"
|
1219 | 450d4ff5 | ths | }; |
1220 | 450d4ff5 | ths | |
1221 | 450d4ff5 | ths | /* Different names and semantics for condition 1111 (0xf). */
|
1222 | 450d4ff5 | ths | const struct cris_cond15 cris_cond15s[] = |
1223 | 450d4ff5 | ths | { |
1224 | 450d4ff5 | ths | /* FIXME: In what version did condition "ext" disappear? */
|
1225 | 450d4ff5 | ths | {"ext", cris_ver_v0_3},
|
1226 | 450d4ff5 | ths | {"wf", cris_ver_v10},
|
1227 | 450d4ff5 | ths | {"sb", cris_ver_v32p},
|
1228 | 450d4ff5 | ths | {NULL, 0} |
1229 | 450d4ff5 | ths | }; |
1230 | 450d4ff5 | ths | |
1231 | 450d4ff5 | ths | |
1232 | 450d4ff5 | ths | /*
|
1233 | 450d4ff5 | ths | * Local variables:
|
1234 | 450d4ff5 | ths | * eval: (c-set-style "gnu")
|
1235 | 450d4ff5 | ths | * indent-tabs-mode: t
|
1236 | 450d4ff5 | ths | * End:
|
1237 | 450d4ff5 | ths | */
|
1238 | 450d4ff5 | ths | |
1239 | 450d4ff5 | ths | |
1240 | 450d4ff5 | ths | /* No instruction will be disassembled longer than this. In theory, and
|
1241 | 450d4ff5 | ths | in silicon, address prefixes can be cascaded. In practice, cascading
|
1242 | 450d4ff5 | ths | is not used by GCC, and not supported by the assembler. */
|
1243 | 450d4ff5 | ths | #ifndef MAX_BYTES_PER_CRIS_INSN
|
1244 | 450d4ff5 | ths | #define MAX_BYTES_PER_CRIS_INSN 8 |
1245 | 450d4ff5 | ths | #endif
|
1246 | 450d4ff5 | ths | |
1247 | 450d4ff5 | ths | /* Whether or not to decode prefixes, folding it into the following
|
1248 | 450d4ff5 | ths | instruction. FIXME: Make this optional later. */
|
1249 | 450d4ff5 | ths | #ifndef PARSE_PREFIX
|
1250 | 450d4ff5 | ths | #define PARSE_PREFIX 1 |
1251 | 450d4ff5 | ths | #endif
|
1252 | 450d4ff5 | ths | |
1253 | 450d4ff5 | ths | /* Sometimes we prefix all registers with this character. */
|
1254 | 450d4ff5 | ths | #define REGISTER_PREFIX_CHAR '$' |
1255 | 450d4ff5 | ths | |
1256 | 450d4ff5 | ths | /* Whether or not to trace the following sequence:
|
1257 | 450d4ff5 | ths | sub* X,r%d
|
1258 | 450d4ff5 | ths | bound* Y,r%d
|
1259 | 450d4ff5 | ths | adds.w [pc+r%d.w],pc
|
1260 | 450d4ff5 | ths | |
1261 | 450d4ff5 | ths | This is the assembly form of a switch-statement in C.
|
1262 | 450d4ff5 | ths | The "sub is optional. If there is none, then X will be zero.
|
1263 | 450d4ff5 | ths | X is the value of the first case,
|
1264 | 450d4ff5 | ths | Y is the number of cases (including default).
|
1265 | 450d4ff5 | ths | |
1266 | 450d4ff5 | ths | This results in case offsets printed on the form:
|
1267 | 450d4ff5 | ths | case N: -> case_address
|
1268 | 450d4ff5 | ths | where N is an estimation on the corresponding 'case' operand in C,
|
1269 | 450d4ff5 | ths | and case_address is where execution of that case continues after the
|
1270 | 450d4ff5 | ths | sequence presented above.
|
1271 | 450d4ff5 | ths | |
1272 | 450d4ff5 | ths | The old style of output was to print the offsets as instructions,
|
1273 | 450d4ff5 | ths | which made it hard to follow "case"-constructs in the disassembly,
|
1274 | 450d4ff5 | ths | and caused a lot of annoying warnings about undefined instructions.
|
1275 | 450d4ff5 | ths | |
1276 | 450d4ff5 | ths | FIXME: Make this optional later. */
|
1277 | 450d4ff5 | ths | #ifndef TRACE_CASE
|
1278 | 450d4ff5 | ths | #define TRACE_CASE (disdata->trace_case)
|
1279 | 450d4ff5 | ths | #endif
|
1280 | 450d4ff5 | ths | |
1281 | 450d4ff5 | ths | enum cris_disass_family
|
1282 | 450d4ff5 | ths | { cris_dis_v0_v10, cris_dis_common_v10_v32, cris_dis_v32 }; |
1283 | 450d4ff5 | ths | |
1284 | 450d4ff5 | ths | /* Stored in the disasm_info->private_data member. */
|
1285 | 450d4ff5 | ths | struct cris_disasm_data
|
1286 | 450d4ff5 | ths | { |
1287 | 450d4ff5 | ths | /* Whether to print something less confusing if we find something
|
1288 | 450d4ff5 | ths | matching a switch-construct. */
|
1289 | 450d4ff5 | ths | bfd_boolean trace_case; |
1290 | 450d4ff5 | ths | |
1291 | 450d4ff5 | ths | /* Whether this code is flagged as crisv32. FIXME: Should be an enum
|
1292 | 450d4ff5 | ths | that includes "compatible". */
|
1293 | 450d4ff5 | ths | enum cris_disass_family distype;
|
1294 | 450d4ff5 | ths | }; |
1295 | 450d4ff5 | ths | |
1296 | 450d4ff5 | ths | /* Value of first element in switch. */
|
1297 | 450d4ff5 | ths | static long case_offset = 0; |
1298 | 450d4ff5 | ths | |
1299 | 450d4ff5 | ths | /* How many more case-offsets to print. */
|
1300 | 450d4ff5 | ths | static long case_offset_counter = 0; |
1301 | 450d4ff5 | ths | |
1302 | 450d4ff5 | ths | /* Number of case offsets. */
|
1303 | 450d4ff5 | ths | static long no_of_case_offsets = 0; |
1304 | 450d4ff5 | ths | |
1305 | 450d4ff5 | ths | /* Candidate for next case_offset. */
|
1306 | 450d4ff5 | ths | static long last_immediate = 0; |
1307 | 450d4ff5 | ths | |
1308 | 450d4ff5 | ths | static int cris_constraint |
1309 | 450d4ff5 | ths | (const char *, unsigned, unsigned, struct cris_disasm_data *); |
1310 | 450d4ff5 | ths | |
1311 | 450d4ff5 | ths | /* Parse disassembler options and store state in info. FIXME: For the
|
1312 | 450d4ff5 | ths | time being, we abuse static variables. */
|
1313 | 450d4ff5 | ths | |
1314 | 450d4ff5 | ths | static bfd_boolean
|
1315 | 450d4ff5 | ths | cris_parse_disassembler_options (disassemble_info *info, |
1316 | 450d4ff5 | ths | enum cris_disass_family distype)
|
1317 | 450d4ff5 | ths | { |
1318 | 450d4ff5 | ths | struct cris_disasm_data *disdata;
|
1319 | 450d4ff5 | ths | |
1320 | 450d4ff5 | ths | info->private_data = calloc (1, sizeof (struct cris_disasm_data)); |
1321 | 450d4ff5 | ths | disdata = (struct cris_disasm_data *) info->private_data;
|
1322 | 450d4ff5 | ths | if (disdata == NULL) |
1323 | 450d4ff5 | ths | return FALSE;
|
1324 | 450d4ff5 | ths | |
1325 | 450d4ff5 | ths | /* Default true. */
|
1326 | 450d4ff5 | ths | disdata->trace_case |
1327 | 450d4ff5 | ths | = (info->disassembler_options == NULL
|
1328 | 450d4ff5 | ths | || (strcmp (info->disassembler_options, "nocase") != 0)); |
1329 | 450d4ff5 | ths | |
1330 | 450d4ff5 | ths | disdata->distype = distype; |
1331 | 450d4ff5 | ths | return TRUE;
|
1332 | 450d4ff5 | ths | } |
1333 | 450d4ff5 | ths | |
1334 | 450d4ff5 | ths | static const struct cris_spec_reg * |
1335 | 450d4ff5 | ths | spec_reg_info (unsigned int sreg, enum cris_disass_family distype) |
1336 | 450d4ff5 | ths | { |
1337 | 450d4ff5 | ths | int i;
|
1338 | 450d4ff5 | ths | |
1339 | 450d4ff5 | ths | for (i = 0; cris_spec_regs[i].name != NULL; i++) |
1340 | 450d4ff5 | ths | { |
1341 | 450d4ff5 | ths | if (cris_spec_regs[i].number == sreg)
|
1342 | 450d4ff5 | ths | { |
1343 | 450d4ff5 | ths | if (distype == cris_dis_v32)
|
1344 | 450d4ff5 | ths | switch (cris_spec_regs[i].applicable_version)
|
1345 | 450d4ff5 | ths | { |
1346 | 450d4ff5 | ths | case cris_ver_warning:
|
1347 | 450d4ff5 | ths | case cris_ver_version_all:
|
1348 | 450d4ff5 | ths | case cris_ver_v3p:
|
1349 | 450d4ff5 | ths | case cris_ver_v8p:
|
1350 | 450d4ff5 | ths | case cris_ver_v10p:
|
1351 | 450d4ff5 | ths | case cris_ver_v32p:
|
1352 | 450d4ff5 | ths | /* No ambiguous sizes or register names with CRISv32. */
|
1353 | 450d4ff5 | ths | if (cris_spec_regs[i].warning == NULL) |
1354 | 450d4ff5 | ths | return &cris_spec_regs[i];
|
1355 | 450d4ff5 | ths | default:
|
1356 | 450d4ff5 | ths | ; |
1357 | 450d4ff5 | ths | } |
1358 | 450d4ff5 | ths | else if (cris_spec_regs[i].applicable_version != cris_ver_v32p) |
1359 | 450d4ff5 | ths | return &cris_spec_regs[i];
|
1360 | 450d4ff5 | ths | } |
1361 | 450d4ff5 | ths | } |
1362 | 450d4ff5 | ths | |
1363 | 450d4ff5 | ths | return NULL; |
1364 | 450d4ff5 | ths | } |
1365 | 450d4ff5 | ths | |
1366 | 450d4ff5 | ths | /* Return the number of bits in the argument. */
|
1367 | 450d4ff5 | ths | |
1368 | 450d4ff5 | ths | static int |
1369 | 450d4ff5 | ths | number_of_bits (unsigned int val) |
1370 | 450d4ff5 | ths | { |
1371 | 450d4ff5 | ths | int bits;
|
1372 | 450d4ff5 | ths | |
1373 | 450d4ff5 | ths | for (bits = 0; val != 0; val &= val - 1) |
1374 | 450d4ff5 | ths | bits++; |
1375 | 450d4ff5 | ths | |
1376 | 450d4ff5 | ths | return bits;
|
1377 | 450d4ff5 | ths | } |
1378 | 450d4ff5 | ths | |
1379 | 450d4ff5 | ths | /* Get an entry in the opcode-table. */
|
1380 | 450d4ff5 | ths | |
1381 | 450d4ff5 | ths | static const struct cris_opcode * |
1382 | 450d4ff5 | ths | get_opcode_entry (unsigned int insn, |
1383 | 450d4ff5 | ths | unsigned int prefix_insn, |
1384 | 450d4ff5 | ths | struct cris_disasm_data *disdata)
|
1385 | 450d4ff5 | ths | { |
1386 | 450d4ff5 | ths | /* For non-prefixed insns, we keep a table of pointers, indexed by the
|
1387 | 450d4ff5 | ths | insn code. Each entry is initialized when found to be NULL. */
|
1388 | 450d4ff5 | ths | static const struct cris_opcode **opc_table = NULL; |
1389 | 450d4ff5 | ths | |
1390 | 450d4ff5 | ths | const struct cris_opcode *max_matchedp = NULL; |
1391 | 450d4ff5 | ths | const struct cris_opcode **prefix_opc_table = NULL; |
1392 | 450d4ff5 | ths | |
1393 | 450d4ff5 | ths | /* We hold a table for each prefix that need to be handled differently. */
|
1394 | 450d4ff5 | ths | static const struct cris_opcode **dip_prefixes = NULL; |
1395 | 450d4ff5 | ths | static const struct cris_opcode **bdapq_m1_prefixes = NULL; |
1396 | 450d4ff5 | ths | static const struct cris_opcode **bdapq_m2_prefixes = NULL; |
1397 | 450d4ff5 | ths | static const struct cris_opcode **bdapq_m4_prefixes = NULL; |
1398 | 450d4ff5 | ths | static const struct cris_opcode **rest_prefixes = NULL; |
1399 | 450d4ff5 | ths | |
1400 | 450d4ff5 | ths | /* Allocate and clear the opcode-table. */
|
1401 | 450d4ff5 | ths | if (opc_table == NULL) |
1402 | 450d4ff5 | ths | { |
1403 | 1eec614b | aliguori | opc_table = qemu_malloc (65536 * sizeof (opc_table[0])); |
1404 | 450d4ff5 | ths | |
1405 | 450d4ff5 | ths | memset (opc_table, 0, 65536 * sizeof (const struct cris_opcode *)); |
1406 | 450d4ff5 | ths | |
1407 | 450d4ff5 | ths | dip_prefixes |
1408 | 1eec614b | aliguori | = qemu_malloc (65536 * sizeof (const struct cris_opcode **)); |
1409 | 450d4ff5 | ths | |
1410 | 450d4ff5 | ths | memset (dip_prefixes, 0, 65536 * sizeof (dip_prefixes[0])); |
1411 | 450d4ff5 | ths | |
1412 | 450d4ff5 | ths | bdapq_m1_prefixes |
1413 | 1eec614b | aliguori | = qemu_malloc (65536 * sizeof (const struct cris_opcode **)); |
1414 | 450d4ff5 | ths | |
1415 | 450d4ff5 | ths | memset (bdapq_m1_prefixes, 0, 65536 * sizeof (bdapq_m1_prefixes[0])); |
1416 | 450d4ff5 | ths | |
1417 | 450d4ff5 | ths | bdapq_m2_prefixes |
1418 | 1eec614b | aliguori | = qemu_malloc (65536 * sizeof (const struct cris_opcode **)); |
1419 | 450d4ff5 | ths | |
1420 | 450d4ff5 | ths | memset (bdapq_m2_prefixes, 0, 65536 * sizeof (bdapq_m2_prefixes[0])); |
1421 | 450d4ff5 | ths | |
1422 | 450d4ff5 | ths | bdapq_m4_prefixes |
1423 | 1eec614b | aliguori | = qemu_malloc (65536 * sizeof (const struct cris_opcode **)); |
1424 | 450d4ff5 | ths | |
1425 | 450d4ff5 | ths | memset (bdapq_m4_prefixes, 0, 65536 * sizeof (bdapq_m4_prefixes[0])); |
1426 | 450d4ff5 | ths | |
1427 | 450d4ff5 | ths | rest_prefixes |
1428 | 1eec614b | aliguori | = qemu_malloc (65536 * sizeof (const struct cris_opcode **)); |
1429 | 450d4ff5 | ths | |
1430 | 450d4ff5 | ths | memset (rest_prefixes, 0, 65536 * sizeof (rest_prefixes[0])); |
1431 | 450d4ff5 | ths | } |
1432 | 450d4ff5 | ths | |
1433 | 450d4ff5 | ths | /* Get the right table if this is a prefix.
|
1434 | 450d4ff5 | ths | This code is connected to cris_constraints in that it knows what
|
1435 | 450d4ff5 | ths | prefixes play a role in recognition of patterns; the necessary
|
1436 | 450d4ff5 | ths | state is reflected by which table is used. If constraints
|
1437 | 450d4ff5 | ths | involving match or non-match of prefix insns are changed, then this
|
1438 | 450d4ff5 | ths | probably needs changing too. */
|
1439 | 450d4ff5 | ths | if (prefix_insn != NO_CRIS_PREFIX)
|
1440 | 450d4ff5 | ths | { |
1441 | 450d4ff5 | ths | const struct cris_opcode *popcodep |
1442 | 450d4ff5 | ths | = (opc_table[prefix_insn] != NULL
|
1443 | 450d4ff5 | ths | ? opc_table[prefix_insn] |
1444 | 450d4ff5 | ths | : get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata)); |
1445 | 450d4ff5 | ths | |
1446 | 450d4ff5 | ths | if (popcodep == NULL) |
1447 | 450d4ff5 | ths | return NULL; |
1448 | 450d4ff5 | ths | |
1449 | 450d4ff5 | ths | if (popcodep->match == BDAP_QUICK_OPCODE)
|
1450 | 450d4ff5 | ths | { |
1451 | 450d4ff5 | ths | /* Since some offsets are recognized with "push" macros, we
|
1452 | 450d4ff5 | ths | have to have different tables for them. */
|
1453 | 450d4ff5 | ths | int offset = (prefix_insn & 255); |
1454 | 450d4ff5 | ths | |
1455 | 450d4ff5 | ths | if (offset > 127) |
1456 | 450d4ff5 | ths | offset -= 256;
|
1457 | 450d4ff5 | ths | |
1458 | 450d4ff5 | ths | switch (offset)
|
1459 | 450d4ff5 | ths | { |
1460 | 450d4ff5 | ths | case -4: |
1461 | 450d4ff5 | ths | prefix_opc_table = bdapq_m4_prefixes; |
1462 | 450d4ff5 | ths | break;
|
1463 | 450d4ff5 | ths | |
1464 | 450d4ff5 | ths | case -2: |
1465 | 450d4ff5 | ths | prefix_opc_table = bdapq_m2_prefixes; |
1466 | 450d4ff5 | ths | break;
|
1467 | 450d4ff5 | ths | |
1468 | 450d4ff5 | ths | case -1: |
1469 | 450d4ff5 | ths | prefix_opc_table = bdapq_m1_prefixes; |
1470 | 450d4ff5 | ths | break;
|
1471 | 450d4ff5 | ths | |
1472 | 450d4ff5 | ths | default:
|
1473 | 450d4ff5 | ths | prefix_opc_table = rest_prefixes; |
1474 | 450d4ff5 | ths | break;
|
1475 | 450d4ff5 | ths | } |
1476 | 450d4ff5 | ths | } |
1477 | 450d4ff5 | ths | else if (popcodep->match == DIP_OPCODE) |
1478 | 450d4ff5 | ths | /* We don't allow postincrement when the prefix is DIP, so use a
|
1479 | 450d4ff5 | ths | different table for DIP. */
|
1480 | 450d4ff5 | ths | prefix_opc_table = dip_prefixes; |
1481 | 450d4ff5 | ths | else
|
1482 | 450d4ff5 | ths | prefix_opc_table = rest_prefixes; |
1483 | 450d4ff5 | ths | } |
1484 | 450d4ff5 | ths | |
1485 | 450d4ff5 | ths | if (prefix_insn != NO_CRIS_PREFIX
|
1486 | 450d4ff5 | ths | && prefix_opc_table[insn] != NULL)
|
1487 | 450d4ff5 | ths | max_matchedp = prefix_opc_table[insn]; |
1488 | 450d4ff5 | ths | else if (prefix_insn == NO_CRIS_PREFIX && opc_table[insn] != NULL) |
1489 | 450d4ff5 | ths | max_matchedp = opc_table[insn]; |
1490 | 450d4ff5 | ths | else
|
1491 | 450d4ff5 | ths | { |
1492 | 450d4ff5 | ths | const struct cris_opcode *opcodep; |
1493 | 450d4ff5 | ths | int max_level_of_match = -1; |
1494 | 450d4ff5 | ths | |
1495 | 450d4ff5 | ths | for (opcodep = cris_opcodes;
|
1496 | 450d4ff5 | ths | opcodep->name != NULL;
|
1497 | 450d4ff5 | ths | opcodep++) |
1498 | 450d4ff5 | ths | { |
1499 | 450d4ff5 | ths | int level_of_match;
|
1500 | 450d4ff5 | ths | |
1501 | 450d4ff5 | ths | if (disdata->distype == cris_dis_v32)
|
1502 | 450d4ff5 | ths | { |
1503 | 450d4ff5 | ths | switch (opcodep->applicable_version)
|
1504 | 450d4ff5 | ths | { |
1505 | 450d4ff5 | ths | case cris_ver_version_all:
|
1506 | 450d4ff5 | ths | break;
|
1507 | 450d4ff5 | ths | |
1508 | 450d4ff5 | ths | case cris_ver_v0_3:
|
1509 | 450d4ff5 | ths | case cris_ver_v0_10:
|
1510 | 450d4ff5 | ths | case cris_ver_v3_10:
|
1511 | 450d4ff5 | ths | case cris_ver_sim_v0_10:
|
1512 | 450d4ff5 | ths | case cris_ver_v8_10:
|
1513 | 450d4ff5 | ths | case cris_ver_v10:
|
1514 | 450d4ff5 | ths | case cris_ver_warning:
|
1515 | 450d4ff5 | ths | continue;
|
1516 | 450d4ff5 | ths | |
1517 | 450d4ff5 | ths | case cris_ver_v3p:
|
1518 | 450d4ff5 | ths | case cris_ver_v8p:
|
1519 | 450d4ff5 | ths | case cris_ver_v10p:
|
1520 | 450d4ff5 | ths | case cris_ver_v32p:
|
1521 | 450d4ff5 | ths | break;
|
1522 | 450d4ff5 | ths | |
1523 | 450d4ff5 | ths | case cris_ver_v8:
|
1524 | 450d4ff5 | ths | abort (); |
1525 | 450d4ff5 | ths | default:
|
1526 | 450d4ff5 | ths | abort (); |
1527 | 450d4ff5 | ths | } |
1528 | 450d4ff5 | ths | } |
1529 | 450d4ff5 | ths | else
|
1530 | 450d4ff5 | ths | { |
1531 | 450d4ff5 | ths | switch (opcodep->applicable_version)
|
1532 | 450d4ff5 | ths | { |
1533 | 450d4ff5 | ths | case cris_ver_version_all:
|
1534 | 450d4ff5 | ths | case cris_ver_v0_3:
|
1535 | 450d4ff5 | ths | case cris_ver_v3p:
|
1536 | 450d4ff5 | ths | case cris_ver_v0_10:
|
1537 | 450d4ff5 | ths | case cris_ver_v8p:
|
1538 | 450d4ff5 | ths | case cris_ver_v8_10:
|
1539 | 450d4ff5 | ths | case cris_ver_v10:
|
1540 | 450d4ff5 | ths | case cris_ver_sim_v0_10:
|
1541 | 450d4ff5 | ths | case cris_ver_v10p:
|
1542 | 450d4ff5 | ths | case cris_ver_warning:
|
1543 | 450d4ff5 | ths | break;
|
1544 | 450d4ff5 | ths | |
1545 | 450d4ff5 | ths | case cris_ver_v32p:
|
1546 | 450d4ff5 | ths | continue;
|
1547 | 450d4ff5 | ths | |
1548 | 450d4ff5 | ths | case cris_ver_v8:
|
1549 | 450d4ff5 | ths | abort (); |
1550 | 450d4ff5 | ths | default:
|
1551 | 450d4ff5 | ths | abort (); |
1552 | 450d4ff5 | ths | } |
1553 | 450d4ff5 | ths | } |
1554 | 450d4ff5 | ths | |
1555 | 450d4ff5 | ths | /* We give a double lead for bits matching the template in
|
1556 | 450d4ff5 | ths | cris_opcodes. Not even, because then "move p8,r10" would
|
1557 | 450d4ff5 | ths | be given 2 bits lead over "clear.d r10". When there's a
|
1558 | 450d4ff5 | ths | tie, the first entry in the table wins. This is
|
1559 | 450d4ff5 | ths | deliberate, to avoid a more complicated recognition
|
1560 | 450d4ff5 | ths | formula. */
|
1561 | 450d4ff5 | ths | if ((opcodep->match & insn) == opcodep->match
|
1562 | 450d4ff5 | ths | && (opcodep->lose & insn) == 0
|
1563 | 450d4ff5 | ths | && ((level_of_match |
1564 | 450d4ff5 | ths | = cris_constraint (opcodep->args, |
1565 | 450d4ff5 | ths | insn, |
1566 | 450d4ff5 | ths | prefix_insn, |
1567 | 450d4ff5 | ths | disdata)) |
1568 | 450d4ff5 | ths | >= 0)
|
1569 | 450d4ff5 | ths | && ((level_of_match |
1570 | 450d4ff5 | ths | += 2 * number_of_bits (opcodep->match
|
1571 | 450d4ff5 | ths | | opcodep->lose)) |
1572 | 450d4ff5 | ths | > max_level_of_match)) |
1573 | 450d4ff5 | ths | { |
1574 | 450d4ff5 | ths | max_matchedp = opcodep; |
1575 | 450d4ff5 | ths | max_level_of_match = level_of_match; |
1576 | 450d4ff5 | ths | |
1577 | 450d4ff5 | ths | /* If there was a full match, never mind looking
|
1578 | 450d4ff5 | ths | further. */
|
1579 | 450d4ff5 | ths | if (level_of_match >= 2 * 16) |
1580 | 450d4ff5 | ths | break;
|
1581 | 450d4ff5 | ths | } |
1582 | 450d4ff5 | ths | } |
1583 | 450d4ff5 | ths | /* Fill in the new entry.
|
1584 | 450d4ff5 | ths | |
1585 | 450d4ff5 | ths | If there are changes to the opcode-table involving prefixes, and
|
1586 | 450d4ff5 | ths | disassembly then does not work correctly, try removing the
|
1587 | 450d4ff5 | ths | else-clause below that fills in the prefix-table. If that
|
1588 | 450d4ff5 | ths | helps, you need to change the prefix_opc_table setting above, or
|
1589 | 450d4ff5 | ths | something related. */
|
1590 | 450d4ff5 | ths | if (prefix_insn == NO_CRIS_PREFIX)
|
1591 | 450d4ff5 | ths | opc_table[insn] = max_matchedp; |
1592 | 450d4ff5 | ths | else
|
1593 | 450d4ff5 | ths | prefix_opc_table[insn] = max_matchedp; |
1594 | 450d4ff5 | ths | } |
1595 | 450d4ff5 | ths | |
1596 | 450d4ff5 | ths | return max_matchedp;
|
1597 | 450d4ff5 | ths | } |
1598 | 450d4ff5 | ths | |
1599 | 450d4ff5 | ths | /* Return -1 if the constraints of a bitwise-matched instruction say
|
1600 | 450d4ff5 | ths | that there is no match. Otherwise return a nonnegative number
|
1601 | 450d4ff5 | ths | indicating the confidence in the match (higher is better). */
|
1602 | 450d4ff5 | ths | |
1603 | 450d4ff5 | ths | static int |
1604 | 450d4ff5 | ths | cris_constraint (const char *cs, |
1605 | 450d4ff5 | ths | unsigned int insn, |
1606 | 450d4ff5 | ths | unsigned int prefix_insn, |
1607 | 450d4ff5 | ths | struct cris_disasm_data *disdata)
|
1608 | 450d4ff5 | ths | { |
1609 | 450d4ff5 | ths | int retval = 0; |
1610 | 450d4ff5 | ths | int tmp;
|
1611 | 450d4ff5 | ths | int prefix_ok = 0; |
1612 | 450d4ff5 | ths | const char *s; |
1613 | 450d4ff5 | ths | |
1614 | 450d4ff5 | ths | for (s = cs; *s; s++)
|
1615 | 450d4ff5 | ths | switch (*s)
|
1616 | 450d4ff5 | ths | { |
1617 | 450d4ff5 | ths | case '!': |
1618 | 450d4ff5 | ths | /* Do not recognize "pop" if there's a prefix and then only for
|
1619 | 450d4ff5 | ths | v0..v10. */
|
1620 | 450d4ff5 | ths | if (prefix_insn != NO_CRIS_PREFIX
|
1621 | 450d4ff5 | ths | || disdata->distype != cris_dis_v0_v10) |
1622 | 450d4ff5 | ths | return -1; |
1623 | 450d4ff5 | ths | break;
|
1624 | 450d4ff5 | ths | |
1625 | 450d4ff5 | ths | case 'U': |
1626 | 450d4ff5 | ths | /* Not recognized at disassembly. */
|
1627 | 450d4ff5 | ths | return -1; |
1628 | 450d4ff5 | ths | |
1629 | 450d4ff5 | ths | case 'M': |
1630 | 450d4ff5 | ths | /* Size modifier for "clear", i.e. special register 0, 4 or 8.
|
1631 | 450d4ff5 | ths | Check that it is one of them. Only special register 12 could
|
1632 | 450d4ff5 | ths | be mismatched, but checking for matches is more logical than
|
1633 | 450d4ff5 | ths | checking for mismatches when there are only a few cases. */
|
1634 | 450d4ff5 | ths | tmp = ((insn >> 12) & 0xf); |
1635 | 450d4ff5 | ths | if (tmp != 0 && tmp != 4 && tmp != 8) |
1636 | 450d4ff5 | ths | return -1; |
1637 | 450d4ff5 | ths | break;
|
1638 | 450d4ff5 | ths | |
1639 | 450d4ff5 | ths | case 'm': |
1640 | 450d4ff5 | ths | if ((insn & 0x30) == 0x30) |
1641 | 450d4ff5 | ths | return -1; |
1642 | 450d4ff5 | ths | break;
|
1643 | 450d4ff5 | ths | |
1644 | 450d4ff5 | ths | case 'S': |
1645 | 450d4ff5 | ths | /* A prefix operand without side-effect. */
|
1646 | 450d4ff5 | ths | if (prefix_insn != NO_CRIS_PREFIX && (insn & 0x400) == 0) |
1647 | 450d4ff5 | ths | { |
1648 | 450d4ff5 | ths | prefix_ok = 1;
|
1649 | 450d4ff5 | ths | break;
|
1650 | 450d4ff5 | ths | } |
1651 | 450d4ff5 | ths | else
|
1652 | 450d4ff5 | ths | return -1; |
1653 | 450d4ff5 | ths | |
1654 | 450d4ff5 | ths | case 's': |
1655 | 450d4ff5 | ths | case 'y': |
1656 | 450d4ff5 | ths | case 'Y': |
1657 | 450d4ff5 | ths | /* If this is a prefixed insn with postincrement (side-effect),
|
1658 | 450d4ff5 | ths | the prefix must not be DIP. */
|
1659 | 450d4ff5 | ths | if (prefix_insn != NO_CRIS_PREFIX)
|
1660 | 450d4ff5 | ths | { |
1661 | 450d4ff5 | ths | if (insn & 0x400) |
1662 | 450d4ff5 | ths | { |
1663 | 450d4ff5 | ths | const struct cris_opcode *prefix_opcodep |
1664 | 450d4ff5 | ths | = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata); |
1665 | 450d4ff5 | ths | |
1666 | 450d4ff5 | ths | if (prefix_opcodep->match == DIP_OPCODE)
|
1667 | 450d4ff5 | ths | return -1; |
1668 | 450d4ff5 | ths | } |
1669 | 450d4ff5 | ths | |
1670 | 450d4ff5 | ths | prefix_ok = 1;
|
1671 | 450d4ff5 | ths | } |
1672 | 450d4ff5 | ths | break;
|
1673 | 450d4ff5 | ths | |
1674 | 450d4ff5 | ths | case 'B': |
1675 | 450d4ff5 | ths | /* If we don't fall through, then the prefix is ok. */
|
1676 | 450d4ff5 | ths | prefix_ok = 1;
|
1677 | 450d4ff5 | ths | |
1678 | 450d4ff5 | ths | /* A "push" prefix. Check for valid "push" size.
|
1679 | 450d4ff5 | ths | In case of special register, it may be != 4. */
|
1680 | 450d4ff5 | ths | if (prefix_insn != NO_CRIS_PREFIX)
|
1681 | 450d4ff5 | ths | { |
1682 | 450d4ff5 | ths | /* Match the prefix insn to BDAPQ. */
|
1683 | 450d4ff5 | ths | const struct cris_opcode *prefix_opcodep |
1684 | 450d4ff5 | ths | = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata); |
1685 | 450d4ff5 | ths | |
1686 | 450d4ff5 | ths | if (prefix_opcodep->match == BDAP_QUICK_OPCODE)
|
1687 | 450d4ff5 | ths | { |
1688 | 450d4ff5 | ths | int pushsize = (prefix_insn & 255); |
1689 | 450d4ff5 | ths | |
1690 | 450d4ff5 | ths | if (pushsize > 127) |
1691 | 450d4ff5 | ths | pushsize -= 256;
|
1692 | 450d4ff5 | ths | |
1693 | 450d4ff5 | ths | if (s[1] == 'P') |
1694 | 450d4ff5 | ths | { |
1695 | 450d4ff5 | ths | unsigned int spec_reg = (insn >> 12) & 15; |
1696 | 450d4ff5 | ths | const struct cris_spec_reg *sregp |
1697 | 450d4ff5 | ths | = spec_reg_info (spec_reg, disdata->distype); |
1698 | 450d4ff5 | ths | |
1699 | 450d4ff5 | ths | /* For a special-register, the "prefix size" must
|
1700 | 450d4ff5 | ths | match the size of the register. */
|
1701 | 450d4ff5 | ths | if (sregp && sregp->reg_size == (unsigned int) -pushsize) |
1702 | 450d4ff5 | ths | break;
|
1703 | 450d4ff5 | ths | } |
1704 | 450d4ff5 | ths | else if (s[1] == 'R') |
1705 | 450d4ff5 | ths | { |
1706 | 450d4ff5 | ths | if ((insn & 0x30) == 0x20 && pushsize == -4) |
1707 | 450d4ff5 | ths | break;
|
1708 | 450d4ff5 | ths | } |
1709 | 450d4ff5 | ths | /* FIXME: Should abort here; next constraint letter
|
1710 | 450d4ff5 | ths | *must* be 'P' or 'R'. */
|
1711 | 450d4ff5 | ths | } |
1712 | 450d4ff5 | ths | } |
1713 | 450d4ff5 | ths | return -1; |
1714 | 450d4ff5 | ths | |
1715 | 450d4ff5 | ths | case 'D': |
1716 | 450d4ff5 | ths | retval = (((insn >> 12) & 15) == (insn & 15)); |
1717 | 450d4ff5 | ths | if (!retval)
|
1718 | 450d4ff5 | ths | return -1; |
1719 | 450d4ff5 | ths | else
|
1720 | 450d4ff5 | ths | retval += 4;
|
1721 | 450d4ff5 | ths | break;
|
1722 | 450d4ff5 | ths | |
1723 | 450d4ff5 | ths | case 'P': |
1724 | 450d4ff5 | ths | { |
1725 | 450d4ff5 | ths | const struct cris_spec_reg *sregp |
1726 | 450d4ff5 | ths | = spec_reg_info ((insn >> 12) & 15, disdata->distype); |
1727 | 450d4ff5 | ths | |
1728 | 450d4ff5 | ths | /* Since we match four bits, we will give a value of 4-1 = 3
|
1729 | 450d4ff5 | ths | in a match. If there is a corresponding exact match of a
|
1730 | 450d4ff5 | ths | special register in another pattern, it will get a value of
|
1731 | 450d4ff5 | ths | 4, which will be higher. This should be correct in that an
|
1732 | 450d4ff5 | ths | exact pattern would match better than a general pattern.
|
1733 | 450d4ff5 | ths | |
1734 | 450d4ff5 | ths | Note that there is a reason for not returning zero; the
|
1735 | 450d4ff5 | ths | pattern for "clear" is partly matched in the bit-pattern
|
1736 | 450d4ff5 | ths | (the two lower bits must be zero), while the bit-pattern
|
1737 | 450d4ff5 | ths | for a move from a special register is matched in the
|
1738 | 450d4ff5 | ths | register constraint. */
|
1739 | 450d4ff5 | ths | |
1740 | 450d4ff5 | ths | if (sregp != NULL) |
1741 | 450d4ff5 | ths | { |
1742 | 450d4ff5 | ths | retval += 3;
|
1743 | 450d4ff5 | ths | break;
|
1744 | 450d4ff5 | ths | } |
1745 | 450d4ff5 | ths | else
|
1746 | 450d4ff5 | ths | return -1; |
1747 | 450d4ff5 | ths | } |
1748 | 450d4ff5 | ths | } |
1749 | 450d4ff5 | ths | |
1750 | 450d4ff5 | ths | if (prefix_insn != NO_CRIS_PREFIX && ! prefix_ok)
|
1751 | 450d4ff5 | ths | return -1; |
1752 | 450d4ff5 | ths | |
1753 | 450d4ff5 | ths | return retval;
|
1754 | 450d4ff5 | ths | } |
1755 | 450d4ff5 | ths | |
1756 | 450d4ff5 | ths | /* Format number as hex with a leading "0x" into outbuffer. */
|
1757 | 450d4ff5 | ths | |
1758 | 450d4ff5 | ths | static char * |
1759 | 450d4ff5 | ths | format_hex (unsigned long number, |
1760 | 450d4ff5 | ths | char *outbuffer,
|
1761 | 450d4ff5 | ths | struct cris_disasm_data *disdata)
|
1762 | 450d4ff5 | ths | { |
1763 | 450d4ff5 | ths | /* Truncate negative numbers on >32-bit hosts. */
|
1764 | 450d4ff5 | ths | number &= 0xffffffff;
|
1765 | 450d4ff5 | ths | |
1766 | 450d4ff5 | ths | sprintf (outbuffer, "0x%lx", number);
|
1767 | 450d4ff5 | ths | |
1768 | 450d4ff5 | ths | /* Save this value for the "case" support. */
|
1769 | 450d4ff5 | ths | if (TRACE_CASE)
|
1770 | 450d4ff5 | ths | last_immediate = number; |
1771 | 450d4ff5 | ths | |
1772 | 450d4ff5 | ths | return outbuffer + strlen (outbuffer);
|
1773 | 450d4ff5 | ths | } |
1774 | 450d4ff5 | ths | |
1775 | 450d4ff5 | ths | /* Format number as decimal into outbuffer. Parameter signedp says
|
1776 | 450d4ff5 | ths | whether the number should be formatted as signed (!= 0) or
|
1777 | 450d4ff5 | ths | unsigned (== 0). */
|
1778 | 450d4ff5 | ths | |
1779 | 450d4ff5 | ths | static char * |
1780 | 450d4ff5 | ths | format_dec (long number, char *outbuffer, int signedp) |
1781 | 450d4ff5 | ths | { |
1782 | 450d4ff5 | ths | last_immediate = number; |
1783 | 450d4ff5 | ths | sprintf (outbuffer, signedp ? "%ld" : "%lu", number); |
1784 | 450d4ff5 | ths | |
1785 | 450d4ff5 | ths | return outbuffer + strlen (outbuffer);
|
1786 | 450d4ff5 | ths | } |
1787 | 450d4ff5 | ths | |
1788 | 450d4ff5 | ths | /* Format the name of the general register regno into outbuffer. */
|
1789 | 450d4ff5 | ths | |
1790 | 450d4ff5 | ths | static char * |
1791 | 450d4ff5 | ths | format_reg (struct cris_disasm_data *disdata,
|
1792 | 450d4ff5 | ths | int regno,
|
1793 | 450d4ff5 | ths | char *outbuffer_start,
|
1794 | 450d4ff5 | ths | bfd_boolean with_reg_prefix) |
1795 | 450d4ff5 | ths | { |
1796 | 450d4ff5 | ths | char *outbuffer = outbuffer_start;
|
1797 | 450d4ff5 | ths | |
1798 | 450d4ff5 | ths | if (with_reg_prefix)
|
1799 | 450d4ff5 | ths | *outbuffer++ = REGISTER_PREFIX_CHAR; |
1800 | 450d4ff5 | ths | |
1801 | 450d4ff5 | ths | switch (regno)
|
1802 | 450d4ff5 | ths | { |
1803 | 450d4ff5 | ths | case 15: |
1804 | 450d4ff5 | ths | /* For v32, there is no context in which we output PC. */
|
1805 | 450d4ff5 | ths | if (disdata->distype == cris_dis_v32)
|
1806 | 450d4ff5 | ths | strcpy (outbuffer, "acr");
|
1807 | 450d4ff5 | ths | else
|
1808 | 450d4ff5 | ths | strcpy (outbuffer, "pc");
|
1809 | 450d4ff5 | ths | break;
|
1810 | 450d4ff5 | ths | |
1811 | 450d4ff5 | ths | case 14: |
1812 | 450d4ff5 | ths | strcpy (outbuffer, "sp");
|
1813 | 450d4ff5 | ths | break;
|
1814 | 450d4ff5 | ths | |
1815 | 450d4ff5 | ths | default:
|
1816 | 450d4ff5 | ths | sprintf (outbuffer, "r%d", regno);
|
1817 | 450d4ff5 | ths | break;
|
1818 | 450d4ff5 | ths | } |
1819 | 450d4ff5 | ths | |
1820 | 450d4ff5 | ths | return outbuffer_start + strlen (outbuffer_start);
|
1821 | 450d4ff5 | ths | } |
1822 | 450d4ff5 | ths | |
1823 | 450d4ff5 | ths | /* Format the name of a support register into outbuffer. */
|
1824 | 450d4ff5 | ths | |
1825 | 450d4ff5 | ths | static char * |
1826 | 450d4ff5 | ths | format_sup_reg (unsigned int regno, |
1827 | 450d4ff5 | ths | char *outbuffer_start,
|
1828 | 450d4ff5 | ths | bfd_boolean with_reg_prefix) |
1829 | 450d4ff5 | ths | { |
1830 | 450d4ff5 | ths | char *outbuffer = outbuffer_start;
|
1831 | 450d4ff5 | ths | int i;
|
1832 | 450d4ff5 | ths | |
1833 | 450d4ff5 | ths | if (with_reg_prefix)
|
1834 | 450d4ff5 | ths | *outbuffer++ = REGISTER_PREFIX_CHAR; |
1835 | 450d4ff5 | ths | |
1836 | 450d4ff5 | ths | for (i = 0; cris_support_regs[i].name != NULL; i++) |
1837 | 450d4ff5 | ths | if (cris_support_regs[i].number == regno)
|
1838 | 450d4ff5 | ths | { |
1839 | 450d4ff5 | ths | sprintf (outbuffer, "%s", cris_support_regs[i].name);
|
1840 | 450d4ff5 | ths | return outbuffer_start + strlen (outbuffer_start);
|
1841 | 450d4ff5 | ths | } |
1842 | 450d4ff5 | ths | |
1843 | 450d4ff5 | ths | /* There's supposed to be register names covering all numbers, though
|
1844 | 450d4ff5 | ths | some may be generic names. */
|
1845 | 450d4ff5 | ths | sprintf (outbuffer, "format_sup_reg-BUG");
|
1846 | 450d4ff5 | ths | return outbuffer_start + strlen (outbuffer_start);
|
1847 | 450d4ff5 | ths | } |
1848 | 450d4ff5 | ths | |
1849 | 450d4ff5 | ths | /* Return the length of an instruction. */
|
1850 | 450d4ff5 | ths | |
1851 | 450d4ff5 | ths | static unsigned |
1852 | 450d4ff5 | ths | bytes_to_skip (unsigned int insn, |
1853 | 450d4ff5 | ths | const struct cris_opcode *matchedp, |
1854 | 450d4ff5 | ths | enum cris_disass_family distype,
|
1855 | 450d4ff5 | ths | const struct cris_opcode *prefix_matchedp) |
1856 | 450d4ff5 | ths | { |
1857 | 450d4ff5 | ths | /* Each insn is a word plus "immediate" operands. */
|
1858 | 450d4ff5 | ths | unsigned to_skip = 2; |
1859 | 450d4ff5 | ths | const char *template = matchedp->args; |
1860 | 450d4ff5 | ths | const char *s; |
1861 | 450d4ff5 | ths | |
1862 | 450d4ff5 | ths | for (s = template; *s; s++)
|
1863 | 450d4ff5 | ths | if ((*s == 's' || *s == 'N' || *s == 'Y') |
1864 | 450d4ff5 | ths | && (insn & 0x400) && (insn & 15) == 15 |
1865 | 450d4ff5 | ths | && prefix_matchedp == NULL)
|
1866 | 450d4ff5 | ths | { |
1867 | 450d4ff5 | ths | /* Immediate via [pc+], so we have to check the size of the
|
1868 | 450d4ff5 | ths | operand. */
|
1869 | 450d4ff5 | ths | int mode_size = 1 << ((insn >> 4) & (*template == 'z' ? 1 : 3)); |
1870 | 450d4ff5 | ths | |
1871 | 450d4ff5 | ths | if (matchedp->imm_oprnd_size == SIZE_FIX_32)
|
1872 | 450d4ff5 | ths | to_skip += 4;
|
1873 | 450d4ff5 | ths | else if (matchedp->imm_oprnd_size == SIZE_SPEC_REG) |
1874 | 450d4ff5 | ths | { |
1875 | 450d4ff5 | ths | const struct cris_spec_reg *sregp |
1876 | 450d4ff5 | ths | = spec_reg_info ((insn >> 12) & 15, distype); |
1877 | 450d4ff5 | ths | |
1878 | 450d4ff5 | ths | /* FIXME: Improve error handling; should have been caught
|
1879 | 450d4ff5 | ths | earlier. */
|
1880 | 450d4ff5 | ths | if (sregp == NULL) |
1881 | 450d4ff5 | ths | return 2; |
1882 | 450d4ff5 | ths | |
1883 | 450d4ff5 | ths | /* PC is incremented by two, not one, for a byte. Except on
|
1884 | 450d4ff5 | ths | CRISv32, where constants are always DWORD-size for
|
1885 | 450d4ff5 | ths | special registers. */
|
1886 | 450d4ff5 | ths | to_skip += |
1887 | 450d4ff5 | ths | distype == cris_dis_v32 ? 4 : (sregp->reg_size + 1) & ~1; |
1888 | 450d4ff5 | ths | } |
1889 | 450d4ff5 | ths | else
|
1890 | 450d4ff5 | ths | to_skip += (mode_size + 1) & ~1; |
1891 | 450d4ff5 | ths | } |
1892 | 450d4ff5 | ths | else if (*s == 'n') |
1893 | 450d4ff5 | ths | to_skip += 4;
|
1894 | 450d4ff5 | ths | else if (*s == 'b') |
1895 | 450d4ff5 | ths | to_skip += 2;
|
1896 | 450d4ff5 | ths | |
1897 | 450d4ff5 | ths | return to_skip;
|
1898 | 450d4ff5 | ths | } |
1899 | 450d4ff5 | ths | |
1900 | 450d4ff5 | ths | /* Print condition code flags. */
|
1901 | 450d4ff5 | ths | |
1902 | 450d4ff5 | ths | static char * |
1903 | 450d4ff5 | ths | print_flags (struct cris_disasm_data *disdata, unsigned int insn, char *cp) |
1904 | 450d4ff5 | ths | { |
1905 | 450d4ff5 | ths | /* Use the v8 (Etrax 100) flag definitions for disassembly.
|
1906 | 450d4ff5 | ths | The differences with v0 (Etrax 1..4) vs. Svinto are:
|
1907 | 450d4ff5 | ths | v0 'd' <=> v8 'm'
|
1908 | 450d4ff5 | ths | v0 'e' <=> v8 'b'.
|
1909 | 450d4ff5 | ths | FIXME: Emit v0..v3 flag names somehow. */
|
1910 | 450d4ff5 | ths | static const char v8_fnames[] = "cvznxibm"; |
1911 | 450d4ff5 | ths | static const char v32_fnames[] = "cvznxiup"; |
1912 | 450d4ff5 | ths | const char *fnames |
1913 | 450d4ff5 | ths | = disdata->distype == cris_dis_v32 ? v32_fnames : v8_fnames; |
1914 | 450d4ff5 | ths | |
1915 | 450d4ff5 | ths | unsigned char flagbits = (((insn >> 8) & 0xf0) | (insn & 15)); |
1916 | 450d4ff5 | ths | int i;
|
1917 | 450d4ff5 | ths | |
1918 | 450d4ff5 | ths | for (i = 0; i < 8; i++) |
1919 | 450d4ff5 | ths | if (flagbits & (1 << i)) |
1920 | 450d4ff5 | ths | *cp++ = fnames[i]; |
1921 | 450d4ff5 | ths | |
1922 | 450d4ff5 | ths | return cp;
|
1923 | 450d4ff5 | ths | } |
1924 | 450d4ff5 | ths | |
1925 | 450d4ff5 | ths | /* Print out an insn with its operands, and update the info->insn_type
|
1926 | 450d4ff5 | ths | fields. The prefix_opcodep and the rest hold a prefix insn that is
|
1927 | 450d4ff5 | ths | supposed to be output as an address mode. */
|
1928 | 450d4ff5 | ths | |
1929 | 450d4ff5 | ths | static void |
1930 | 450d4ff5 | ths | print_with_operands (const struct cris_opcode *opcodep, |
1931 | 450d4ff5 | ths | unsigned int insn, |
1932 | 450d4ff5 | ths | unsigned char *buffer, |
1933 | 450d4ff5 | ths | bfd_vma addr, |
1934 | 450d4ff5 | ths | disassemble_info *info, |
1935 | 450d4ff5 | ths | /* If a prefix insn was before this insn (and is supposed
|
1936 | 450d4ff5 | ths | to be output as an address), here is a description of
|
1937 | 450d4ff5 | ths | it. */
|
1938 | 450d4ff5 | ths | const struct cris_opcode *prefix_opcodep, |
1939 | 450d4ff5 | ths | unsigned int prefix_insn, |
1940 | 450d4ff5 | ths | unsigned char *prefix_buffer, |
1941 | 450d4ff5 | ths | bfd_boolean with_reg_prefix) |
1942 | 450d4ff5 | ths | { |
1943 | 450d4ff5 | ths | /* Get a buffer of somewhat reasonable size where we store
|
1944 | 450d4ff5 | ths | intermediate parts of the insn. */
|
1945 | 450d4ff5 | ths | char temp[sizeof (".d [$r13=$r12-2147483648],$r10") * 2]; |
1946 | 450d4ff5 | ths | char *tp = temp;
|
1947 | 450d4ff5 | ths | static const char mode_char[] = "bwd?"; |
1948 | 450d4ff5 | ths | const char *s; |
1949 | 450d4ff5 | ths | const char *cs; |
1950 | 450d4ff5 | ths | struct cris_disasm_data *disdata
|
1951 | 450d4ff5 | ths | = (struct cris_disasm_data *) info->private_data;
|
1952 | 450d4ff5 | ths | |
1953 | 450d4ff5 | ths | /* Print out the name first thing we do. */
|
1954 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "%s", opcodep->name);
|
1955 | 450d4ff5 | ths | |
1956 | 450d4ff5 | ths | cs = opcodep->args; |
1957 | 450d4ff5 | ths | s = cs; |
1958 | 450d4ff5 | ths | |
1959 | 450d4ff5 | ths | /* Ignore any prefix indicator. */
|
1960 | 450d4ff5 | ths | if (*s == 'p') |
1961 | 450d4ff5 | ths | s++; |
1962 | 450d4ff5 | ths | |
1963 | 450d4ff5 | ths | if (*s == 'm' || *s == 'M' || *s == 'z') |
1964 | 450d4ff5 | ths | { |
1965 | 450d4ff5 | ths | *tp++ = '.';
|
1966 | 450d4ff5 | ths | |
1967 | 450d4ff5 | ths | /* Get the size-letter. */
|
1968 | 450d4ff5 | ths | *tp++ = *s == 'M'
|
1969 | 450d4ff5 | ths | ? (insn & 0x8000 ? 'd' |
1970 | 450d4ff5 | ths | : insn & 0x4000 ? 'w' : 'b') |
1971 | 450d4ff5 | ths | : mode_char[(insn >> 4) & (*s == 'z' ? 1 : 3)]; |
1972 | 450d4ff5 | ths | |
1973 | 450d4ff5 | ths | /* Ignore the size and the space character that follows. */
|
1974 | 450d4ff5 | ths | s += 2;
|
1975 | 450d4ff5 | ths | } |
1976 | 450d4ff5 | ths | |
1977 | 450d4ff5 | ths | /* Add a space if this isn't a long-branch, because for those will add
|
1978 | 450d4ff5 | ths | the condition part of the name later. */
|
1979 | 450d4ff5 | ths | if (opcodep->match != (BRANCH_PC_LOW + BRANCH_INCR_HIGH * 256)) |
1980 | 450d4ff5 | ths | *tp++ = ' ';
|
1981 | 450d4ff5 | ths | |
1982 | 450d4ff5 | ths | /* Fill in the insn-type if deducible from the name (and there's no
|
1983 | 450d4ff5 | ths | better way). */
|
1984 | 450d4ff5 | ths | if (opcodep->name[0] == 'j') |
1985 | 450d4ff5 | ths | { |
1986 | 450d4ff5 | ths | if (CONST_STRNEQ (opcodep->name, "jsr")) |
1987 | 450d4ff5 | ths | /* It's "jsr" or "jsrc". */
|
1988 | 450d4ff5 | ths | info->insn_type = dis_jsr; |
1989 | 450d4ff5 | ths | else
|
1990 | 450d4ff5 | ths | /* Any other jump-type insn is considered a branch. */
|
1991 | 450d4ff5 | ths | info->insn_type = dis_branch; |
1992 | 450d4ff5 | ths | } |
1993 | 450d4ff5 | ths | |
1994 | 450d4ff5 | ths | /* We might know some more fields right now. */
|
1995 | 450d4ff5 | ths | info->branch_delay_insns = opcodep->delayed; |
1996 | 450d4ff5 | ths | |
1997 | 450d4ff5 | ths | /* Handle operands. */
|
1998 | 450d4ff5 | ths | for (; *s; s++)
|
1999 | 450d4ff5 | ths | { |
2000 | 450d4ff5 | ths | switch (*s)
|
2001 | 450d4ff5 | ths | { |
2002 | 450d4ff5 | ths | case 'T': |
2003 | 450d4ff5 | ths | tp = format_sup_reg ((insn >> 12) & 15, tp, with_reg_prefix); |
2004 | 450d4ff5 | ths | break;
|
2005 | 450d4ff5 | ths | |
2006 | 450d4ff5 | ths | case 'A': |
2007 | 450d4ff5 | ths | if (with_reg_prefix)
|
2008 | 450d4ff5 | ths | *tp++ = REGISTER_PREFIX_CHAR; |
2009 | 450d4ff5 | ths | *tp++ = 'a';
|
2010 | 450d4ff5 | ths | *tp++ = 'c';
|
2011 | 450d4ff5 | ths | *tp++ = 'r';
|
2012 | 450d4ff5 | ths | break;
|
2013 | 450d4ff5 | ths | |
2014 | 450d4ff5 | ths | case '[': |
2015 | 450d4ff5 | ths | case ']': |
2016 | 450d4ff5 | ths | case ',': |
2017 | 450d4ff5 | ths | *tp++ = *s; |
2018 | 450d4ff5 | ths | break;
|
2019 | 450d4ff5 | ths | |
2020 | 450d4ff5 | ths | case '!': |
2021 | 450d4ff5 | ths | /* Ignore at this point; used at earlier stages to avoid
|
2022 | 450d4ff5 | ths | recognition if there's a prefix at something that in other
|
2023 | 450d4ff5 | ths | ways looks like a "pop". */
|
2024 | 450d4ff5 | ths | break;
|
2025 | 450d4ff5 | ths | |
2026 | 450d4ff5 | ths | case 'd': |
2027 | 450d4ff5 | ths | /* Ignore. This is an optional ".d " on the large one of
|
2028 | 450d4ff5 | ths | relaxable insns. */
|
2029 | 450d4ff5 | ths | break;
|
2030 | 450d4ff5 | ths | |
2031 | 450d4ff5 | ths | case 'B': |
2032 | 450d4ff5 | ths | /* This was the prefix that made this a "push". We've already
|
2033 | 450d4ff5 | ths | handled it by recognizing it, so signal that the prefix is
|
2034 | 450d4ff5 | ths | handled by setting it to NULL. */
|
2035 | 450d4ff5 | ths | prefix_opcodep = NULL;
|
2036 | 450d4ff5 | ths | break;
|
2037 | 450d4ff5 | ths | |
2038 | 450d4ff5 | ths | case 'D': |
2039 | 450d4ff5 | ths | case 'r': |
2040 | 450d4ff5 | ths | tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
|
2041 | 450d4ff5 | ths | break;
|
2042 | 450d4ff5 | ths | |
2043 | 450d4ff5 | ths | case 'R': |
2044 | 450d4ff5 | ths | tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix); |
2045 | 450d4ff5 | ths | break;
|
2046 | 450d4ff5 | ths | |
2047 | 450d4ff5 | ths | case 'n': |
2048 | 450d4ff5 | ths | { |
2049 | 450d4ff5 | ths | /* Like N but pc-relative to the start of the insn. */
|
2050 | 450d4ff5 | ths | unsigned long number |
2051 | 450d4ff5 | ths | = (buffer[2] + buffer[3] * 256 + buffer[4] * 65536 |
2052 | 450d4ff5 | ths | + buffer[5] * 0x1000000 + addr); |
2053 | 450d4ff5 | ths | |
2054 | 450d4ff5 | ths | /* Finish off and output previous formatted bytes. */
|
2055 | 450d4ff5 | ths | *tp = 0;
|
2056 | 450d4ff5 | ths | if (temp[0]) |
2057 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "%s", temp);
|
2058 | 450d4ff5 | ths | tp = temp; |
2059 | 450d4ff5 | ths | |
2060 | 450d4ff5 | ths | (*info->print_address_func) ((bfd_vma) number, info); |
2061 | 450d4ff5 | ths | } |
2062 | 450d4ff5 | ths | break;
|
2063 | 450d4ff5 | ths | |
2064 | 450d4ff5 | ths | case 'u': |
2065 | 450d4ff5 | ths | { |
2066 | 450d4ff5 | ths | /* Like n but the offset is bits <3:0> in the instruction. */
|
2067 | 450d4ff5 | ths | unsigned long number = (buffer[0] & 0xf) * 2 + addr; |
2068 | 450d4ff5 | ths | |
2069 | 450d4ff5 | ths | /* Finish off and output previous formatted bytes. */
|
2070 | 450d4ff5 | ths | *tp = 0;
|
2071 | 450d4ff5 | ths | if (temp[0]) |
2072 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "%s", temp);
|
2073 | 450d4ff5 | ths | tp = temp; |
2074 | 450d4ff5 | ths | |
2075 | 450d4ff5 | ths | (*info->print_address_func) ((bfd_vma) number, info); |
2076 | 450d4ff5 | ths | } |
2077 | 450d4ff5 | ths | break;
|
2078 | 450d4ff5 | ths | |
2079 | 450d4ff5 | ths | case 'N': |
2080 | 450d4ff5 | ths | case 'y': |
2081 | 450d4ff5 | ths | case 'Y': |
2082 | 450d4ff5 | ths | case 'S': |
2083 | 450d4ff5 | ths | case 's': |
2084 | 450d4ff5 | ths | /* Any "normal" memory operand. */
|
2085 | 450d4ff5 | ths | if ((insn & 0x400) && (insn & 15) == 15 && prefix_opcodep == NULL) |
2086 | 450d4ff5 | ths | { |
2087 | 450d4ff5 | ths | /* We're looking at [pc+], i.e. we need to output an immediate
|
2088 | 450d4ff5 | ths | number, where the size can depend on different things. */
|
2089 | 450d4ff5 | ths | long number;
|
2090 | 450d4ff5 | ths | int signedp
|
2091 | 450d4ff5 | ths | = ((*cs == 'z' && (insn & 0x20)) |
2092 | 450d4ff5 | ths | || opcodep->match == BDAP_QUICK_OPCODE); |
2093 | 450d4ff5 | ths | int nbytes;
|
2094 | 450d4ff5 | ths | |
2095 | 450d4ff5 | ths | if (opcodep->imm_oprnd_size == SIZE_FIX_32)
|
2096 | 450d4ff5 | ths | nbytes = 4;
|
2097 | 450d4ff5 | ths | else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG) |
2098 | 450d4ff5 | ths | { |
2099 | 450d4ff5 | ths | const struct cris_spec_reg *sregp |
2100 | 450d4ff5 | ths | = spec_reg_info ((insn >> 12) & 15, disdata->distype); |
2101 | 450d4ff5 | ths | |
2102 | 450d4ff5 | ths | /* A NULL return should have been as a non-match earlier,
|
2103 | 450d4ff5 | ths | so catch it as an internal error in the error-case
|
2104 | 450d4ff5 | ths | below. */
|
2105 | 450d4ff5 | ths | if (sregp == NULL) |
2106 | 450d4ff5 | ths | /* Whatever non-valid size. */
|
2107 | 450d4ff5 | ths | nbytes = 42;
|
2108 | 450d4ff5 | ths | else
|
2109 | 450d4ff5 | ths | /* PC is always incremented by a multiple of two.
|
2110 | 450d4ff5 | ths | For CRISv32, immediates are always 4 bytes for
|
2111 | 450d4ff5 | ths | special registers. */
|
2112 | 450d4ff5 | ths | nbytes = disdata->distype == cris_dis_v32 |
2113 | 450d4ff5 | ths | ? 4 : (sregp->reg_size + 1) & ~1; |
2114 | 450d4ff5 | ths | } |
2115 | 450d4ff5 | ths | else
|
2116 | 450d4ff5 | ths | { |
2117 | 450d4ff5 | ths | int mode_size = 1 << ((insn >> 4) & (*cs == 'z' ? 1 : 3)); |
2118 | 450d4ff5 | ths | |
2119 | 450d4ff5 | ths | if (mode_size == 1) |
2120 | 450d4ff5 | ths | nbytes = 2;
|
2121 | 450d4ff5 | ths | else
|
2122 | 450d4ff5 | ths | nbytes = mode_size; |
2123 | 450d4ff5 | ths | } |
2124 | 450d4ff5 | ths | |
2125 | 450d4ff5 | ths | switch (nbytes)
|
2126 | 450d4ff5 | ths | { |
2127 | 450d4ff5 | ths | case 1: |
2128 | 450d4ff5 | ths | number = buffer[2];
|
2129 | 450d4ff5 | ths | if (signedp && number > 127) |
2130 | 450d4ff5 | ths | number -= 256;
|
2131 | 450d4ff5 | ths | break;
|
2132 | 450d4ff5 | ths | |
2133 | 450d4ff5 | ths | case 2: |
2134 | 450d4ff5 | ths | number = buffer[2] + buffer[3] * 256; |
2135 | 450d4ff5 | ths | if (signedp && number > 32767) |
2136 | 450d4ff5 | ths | number -= 65536;
|
2137 | 450d4ff5 | ths | break;
|
2138 | 450d4ff5 | ths | |
2139 | 450d4ff5 | ths | case 4: |
2140 | 450d4ff5 | ths | number |
2141 | 450d4ff5 | ths | = buffer[2] + buffer[3] * 256 + buffer[4] * 65536 |
2142 | 450d4ff5 | ths | + buffer[5] * 0x1000000; |
2143 | 450d4ff5 | ths | break;
|
2144 | 450d4ff5 | ths | |
2145 | 450d4ff5 | ths | default:
|
2146 | 450d4ff5 | ths | strcpy (tp, "bug");
|
2147 | 450d4ff5 | ths | tp += 3;
|
2148 | 450d4ff5 | ths | number = 42;
|
2149 | 450d4ff5 | ths | } |
2150 | 450d4ff5 | ths | |
2151 | 450d4ff5 | ths | if ((*cs == 'z' && (insn & 0x20)) |
2152 | 450d4ff5 | ths | || (opcodep->match == BDAP_QUICK_OPCODE |
2153 | 450d4ff5 | ths | && (nbytes <= 2 || buffer[1 + nbytes] == 0))) |
2154 | 450d4ff5 | ths | tp = format_dec (number, tp, signedp); |
2155 | 450d4ff5 | ths | else
|
2156 | 450d4ff5 | ths | { |
2157 | 450d4ff5 | ths | unsigned int highbyte = (number >> 24) & 0xff; |
2158 | 450d4ff5 | ths | |
2159 | 450d4ff5 | ths | /* Either output this as an address or as a number. If it's
|
2160 | 450d4ff5 | ths | a dword with the same high-byte as the address of the
|
2161 | 450d4ff5 | ths | insn, assume it's an address, and also if it's a non-zero
|
2162 | 450d4ff5 | ths | non-0xff high-byte. If this is a jsr or a jump, then
|
2163 | 450d4ff5 | ths | it's definitely an address. */
|
2164 | 450d4ff5 | ths | if (nbytes == 4 |
2165 | 450d4ff5 | ths | && (highbyte == ((addr >> 24) & 0xff) |
2166 | 450d4ff5 | ths | || (highbyte != 0 && highbyte != 0xff) |
2167 | 450d4ff5 | ths | || info->insn_type == dis_branch |
2168 | 450d4ff5 | ths | || info->insn_type == dis_jsr)) |
2169 | 450d4ff5 | ths | { |
2170 | 450d4ff5 | ths | /* Finish off and output previous formatted bytes. */
|
2171 | 450d4ff5 | ths | *tp = 0;
|
2172 | 450d4ff5 | ths | tp = temp; |
2173 | 450d4ff5 | ths | if (temp[0]) |
2174 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "%s", temp);
|
2175 | 450d4ff5 | ths | |
2176 | 450d4ff5 | ths | (*info->print_address_func) ((bfd_vma) number, info); |
2177 | 450d4ff5 | ths | |
2178 | 450d4ff5 | ths | info->target = number; |
2179 | 450d4ff5 | ths | } |
2180 | 450d4ff5 | ths | else
|
2181 | 450d4ff5 | ths | tp = format_hex (number, tp, disdata); |
2182 | 450d4ff5 | ths | } |
2183 | 450d4ff5 | ths | } |
2184 | 450d4ff5 | ths | else
|
2185 | 450d4ff5 | ths | { |
2186 | 450d4ff5 | ths | /* Not an immediate number. Then this is a (possibly
|
2187 | 450d4ff5 | ths | prefixed) memory operand. */
|
2188 | 450d4ff5 | ths | if (info->insn_type != dis_nonbranch)
|
2189 | 450d4ff5 | ths | { |
2190 | 450d4ff5 | ths | int mode_size
|
2191 | 450d4ff5 | ths | = 1 << ((insn >> 4) |
2192 | 450d4ff5 | ths | & (opcodep->args[0] == 'z' ? 1 : 3)); |
2193 | 450d4ff5 | ths | int size;
|
2194 | 450d4ff5 | ths | info->insn_type = dis_dref; |
2195 | 450d4ff5 | ths | info->flags |= CRIS_DIS_FLAG_MEMREF; |
2196 | 450d4ff5 | ths | |
2197 | 450d4ff5 | ths | if (opcodep->imm_oprnd_size == SIZE_FIX_32)
|
2198 | 450d4ff5 | ths | size = 4;
|
2199 | 450d4ff5 | ths | else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG) |
2200 | 450d4ff5 | ths | { |
2201 | 450d4ff5 | ths | const struct cris_spec_reg *sregp |
2202 | 450d4ff5 | ths | = spec_reg_info ((insn >> 12) & 15, disdata->distype); |
2203 | 450d4ff5 | ths | |
2204 | 450d4ff5 | ths | /* FIXME: Improve error handling; should have been caught
|
2205 | 450d4ff5 | ths | earlier. */
|
2206 | 450d4ff5 | ths | if (sregp == NULL) |
2207 | 450d4ff5 | ths | size = 4;
|
2208 | 450d4ff5 | ths | else
|
2209 | 450d4ff5 | ths | size = sregp->reg_size; |
2210 | 450d4ff5 | ths | } |
2211 | 450d4ff5 | ths | else
|
2212 | 450d4ff5 | ths | size = mode_size; |
2213 | 450d4ff5 | ths | |
2214 | 450d4ff5 | ths | info->data_size = size; |
2215 | 450d4ff5 | ths | } |
2216 | 450d4ff5 | ths | |
2217 | 450d4ff5 | ths | *tp++ = '[';
|
2218 | 450d4ff5 | ths | |
2219 | 450d4ff5 | ths | if (prefix_opcodep
|
2220 | 450d4ff5 | ths | /* We don't match dip with a postincremented field
|
2221 | 450d4ff5 | ths | as a side-effect address mode. */
|
2222 | 450d4ff5 | ths | && ((insn & 0x400) == 0 |
2223 | 450d4ff5 | ths | || prefix_opcodep->match != DIP_OPCODE)) |
2224 | 450d4ff5 | ths | { |
2225 | 450d4ff5 | ths | if (insn & 0x400) |
2226 | 450d4ff5 | ths | { |
2227 | 450d4ff5 | ths | tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
|
2228 | 450d4ff5 | ths | *tp++ = '=';
|
2229 | 450d4ff5 | ths | } |
2230 | 450d4ff5 | ths | |
2231 | 450d4ff5 | ths | |
2232 | 450d4ff5 | ths | /* We mainly ignore the prefix format string when the
|
2233 | 450d4ff5 | ths | address-mode syntax is output. */
|
2234 | 450d4ff5 | ths | switch (prefix_opcodep->match)
|
2235 | 450d4ff5 | ths | { |
2236 | 450d4ff5 | ths | case DIP_OPCODE:
|
2237 | 450d4ff5 | ths | /* It's [r], [r+] or [pc+]. */
|
2238 | 450d4ff5 | ths | if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15) |
2239 | 450d4ff5 | ths | { |
2240 | 450d4ff5 | ths | /* It's [pc+]. This cannot possibly be anything
|
2241 | 450d4ff5 | ths | but an address. */
|
2242 | 450d4ff5 | ths | unsigned long number |
2243 | 450d4ff5 | ths | = prefix_buffer[2] + prefix_buffer[3] * 256 |
2244 | 450d4ff5 | ths | + prefix_buffer[4] * 65536 |
2245 | 450d4ff5 | ths | + prefix_buffer[5] * 0x1000000; |
2246 | 450d4ff5 | ths | |
2247 | 450d4ff5 | ths | info->target = (bfd_vma) number; |
2248 | 450d4ff5 | ths | |
2249 | 450d4ff5 | ths | /* Finish off and output previous formatted
|
2250 | 450d4ff5 | ths | data. */
|
2251 | 450d4ff5 | ths | *tp = 0;
|
2252 | 450d4ff5 | ths | tp = temp; |
2253 | 450d4ff5 | ths | if (temp[0]) |
2254 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "%s", temp);
|
2255 | 450d4ff5 | ths | |
2256 | 450d4ff5 | ths | (*info->print_address_func) ((bfd_vma) number, info); |
2257 | 450d4ff5 | ths | } |
2258 | 450d4ff5 | ths | else
|
2259 | 450d4ff5 | ths | { |
2260 | 450d4ff5 | ths | /* For a memref in an address, we use target2.
|
2261 | 450d4ff5 | ths | In this case, target is zero. */
|
2262 | 450d4ff5 | ths | info->flags |
2263 | 450d4ff5 | ths | |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG |
2264 | 450d4ff5 | ths | | CRIS_DIS_FLAG_MEM_TARGET2_MEM); |
2265 | 450d4ff5 | ths | |
2266 | 450d4ff5 | ths | info->target2 = prefix_insn & 15;
|
2267 | 450d4ff5 | ths | |
2268 | 450d4ff5 | ths | *tp++ = '[';
|
2269 | 450d4ff5 | ths | tp = format_reg (disdata, prefix_insn & 15, tp,
|
2270 | 450d4ff5 | ths | with_reg_prefix); |
2271 | 450d4ff5 | ths | if (prefix_insn & 0x400) |
2272 | 450d4ff5 | ths | *tp++ = '+';
|
2273 | 450d4ff5 | ths | *tp++ = ']';
|
2274 | 450d4ff5 | ths | } |
2275 | 450d4ff5 | ths | break;
|
2276 | 450d4ff5 | ths | |
2277 | 450d4ff5 | ths | case BDAP_QUICK_OPCODE:
|
2278 | 450d4ff5 | ths | { |
2279 | 450d4ff5 | ths | int number;
|
2280 | 450d4ff5 | ths | |
2281 | 450d4ff5 | ths | number = prefix_buffer[0];
|
2282 | 450d4ff5 | ths | if (number > 127) |
2283 | 450d4ff5 | ths | number -= 256;
|
2284 | 450d4ff5 | ths | |
2285 | 450d4ff5 | ths | /* Output "reg+num" or, if num < 0, "reg-num". */
|
2286 | 450d4ff5 | ths | tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp, |
2287 | 450d4ff5 | ths | with_reg_prefix); |
2288 | 450d4ff5 | ths | if (number >= 0) |
2289 | 450d4ff5 | ths | *tp++ = '+';
|
2290 | 450d4ff5 | ths | tp = format_dec (number, tp, 1);
|
2291 | 450d4ff5 | ths | |
2292 | 450d4ff5 | ths | info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG; |
2293 | 450d4ff5 | ths | info->target = (prefix_insn >> 12) & 15; |
2294 | 450d4ff5 | ths | info->target2 = (bfd_vma) number; |
2295 | 450d4ff5 | ths | break;
|
2296 | 450d4ff5 | ths | } |
2297 | 450d4ff5 | ths | |
2298 | 450d4ff5 | ths | case BIAP_OPCODE:
|
2299 | 450d4ff5 | ths | /* Output "r+R.m". */
|
2300 | 450d4ff5 | ths | tp = format_reg (disdata, prefix_insn & 15, tp,
|
2301 | 450d4ff5 | ths | with_reg_prefix); |
2302 | 450d4ff5 | ths | *tp++ = '+';
|
2303 | 450d4ff5 | ths | tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp, |
2304 | 450d4ff5 | ths | with_reg_prefix); |
2305 | 450d4ff5 | ths | *tp++ = '.';
|
2306 | 450d4ff5 | ths | *tp++ = mode_char[(prefix_insn >> 4) & 3]; |
2307 | 450d4ff5 | ths | |
2308 | 450d4ff5 | ths | info->flags |
2309 | 450d4ff5 | ths | |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG |
2310 | 450d4ff5 | ths | | CRIS_DIS_FLAG_MEM_TARGET_IS_REG |
2311 | 450d4ff5 | ths | |
2312 | 450d4ff5 | ths | | ((prefix_insn & 0x8000)
|
2313 | 450d4ff5 | ths | ? CRIS_DIS_FLAG_MEM_TARGET2_MULT4 |
2314 | 450d4ff5 | ths | : ((prefix_insn & 0x8000)
|
2315 | 450d4ff5 | ths | ? CRIS_DIS_FLAG_MEM_TARGET2_MULT2 : 0)));
|
2316 | 450d4ff5 | ths | |
2317 | 450d4ff5 | ths | /* Is it the casejump? It's a "adds.w [pc+r%d.w],pc". */
|
2318 | 450d4ff5 | ths | if (insn == 0xf83f && (prefix_insn & ~0xf000) == 0x55f) |
2319 | 450d4ff5 | ths | /* Then start interpreting data as offsets. */
|
2320 | 450d4ff5 | ths | case_offset_counter = no_of_case_offsets; |
2321 | 450d4ff5 | ths | break;
|
2322 | 450d4ff5 | ths | |
2323 | 450d4ff5 | ths | case BDAP_INDIR_OPCODE:
|
2324 | 450d4ff5 | ths | /* Output "r+s.m", or, if "s" is [pc+], "r+s" or
|
2325 | 450d4ff5 | ths | "r-s". */
|
2326 | 450d4ff5 | ths | tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp, |
2327 | 450d4ff5 | ths | with_reg_prefix); |
2328 | 450d4ff5 | ths | |
2329 | 450d4ff5 | ths | if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15) |
2330 | 450d4ff5 | ths | { |
2331 | 450d4ff5 | ths | long number;
|
2332 | 450d4ff5 | ths | unsigned int nbytes; |
2333 | 450d4ff5 | ths | |
2334 | 450d4ff5 | ths | /* It's a value. Get its size. */
|
2335 | 450d4ff5 | ths | int mode_size = 1 << ((prefix_insn >> 4) & 3); |
2336 | 450d4ff5 | ths | |
2337 | 450d4ff5 | ths | if (mode_size == 1) |
2338 | 450d4ff5 | ths | nbytes = 2;
|
2339 | 450d4ff5 | ths | else
|
2340 | 450d4ff5 | ths | nbytes = mode_size; |
2341 | 450d4ff5 | ths | |
2342 | 450d4ff5 | ths | switch (nbytes)
|
2343 | 450d4ff5 | ths | { |
2344 | 450d4ff5 | ths | case 1: |
2345 | 450d4ff5 | ths | number = prefix_buffer[2];
|
2346 | 450d4ff5 | ths | if (number > 127) |
2347 | 450d4ff5 | ths | number -= 256;
|
2348 | 450d4ff5 | ths | break;
|
2349 | 450d4ff5 | ths | |
2350 | 450d4ff5 | ths | case 2: |
2351 | 450d4ff5 | ths | number = prefix_buffer[2] + prefix_buffer[3] * 256; |
2352 | 450d4ff5 | ths | if (number > 32767) |
2353 | 450d4ff5 | ths | number -= 65536;
|
2354 | 450d4ff5 | ths | break;
|
2355 | 450d4ff5 | ths | |
2356 | 450d4ff5 | ths | case 4: |
2357 | 450d4ff5 | ths | number |
2358 | 450d4ff5 | ths | = prefix_buffer[2] + prefix_buffer[3] * 256 |
2359 | 450d4ff5 | ths | + prefix_buffer[4] * 65536 |
2360 | 450d4ff5 | ths | + prefix_buffer[5] * 0x1000000; |
2361 | 450d4ff5 | ths | break;
|
2362 | 450d4ff5 | ths | |
2363 | 450d4ff5 | ths | default:
|
2364 | 450d4ff5 | ths | strcpy (tp, "bug");
|
2365 | 450d4ff5 | ths | tp += 3;
|
2366 | 450d4ff5 | ths | number = 42;
|
2367 | 450d4ff5 | ths | } |
2368 | 450d4ff5 | ths | |
2369 | 450d4ff5 | ths | info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG; |
2370 | 450d4ff5 | ths | info->target2 = (bfd_vma) number; |
2371 | 450d4ff5 | ths | |
2372 | 450d4ff5 | ths | /* If the size is dword, then assume it's an
|
2373 | 450d4ff5 | ths | address. */
|
2374 | 450d4ff5 | ths | if (nbytes == 4) |
2375 | 450d4ff5 | ths | { |
2376 | 450d4ff5 | ths | /* Finish off and output previous formatted
|
2377 | 450d4ff5 | ths | bytes. */
|
2378 | 450d4ff5 | ths | *tp++ = '+';
|
2379 | 450d4ff5 | ths | *tp = 0;
|
2380 | 450d4ff5 | ths | tp = temp; |
2381 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "%s", temp);
|
2382 | 450d4ff5 | ths | |
2383 | 450d4ff5 | ths | (*info->print_address_func) ((bfd_vma) number, info); |
2384 | 450d4ff5 | ths | } |
2385 | 450d4ff5 | ths | else
|
2386 | 450d4ff5 | ths | { |
2387 | 450d4ff5 | ths | if (number >= 0) |
2388 | 450d4ff5 | ths | *tp++ = '+';
|
2389 | 450d4ff5 | ths | tp = format_dec (number, tp, 1);
|
2390 | 450d4ff5 | ths | } |
2391 | 450d4ff5 | ths | } |
2392 | 450d4ff5 | ths | else
|
2393 | 450d4ff5 | ths | { |
2394 | 450d4ff5 | ths | /* Output "r+[R].m" or "r+[R+].m". */
|
2395 | 450d4ff5 | ths | *tp++ = '+';
|
2396 | 450d4ff5 | ths | *tp++ = '[';
|
2397 | 450d4ff5 | ths | tp = format_reg (disdata, prefix_insn & 15, tp,
|
2398 | 450d4ff5 | ths | with_reg_prefix); |
2399 | 450d4ff5 | ths | if (prefix_insn & 0x400) |
2400 | 450d4ff5 | ths | *tp++ = '+';
|
2401 | 450d4ff5 | ths | *tp++ = ']';
|
2402 | 450d4ff5 | ths | *tp++ = '.';
|
2403 | 450d4ff5 | ths | *tp++ = mode_char[(prefix_insn >> 4) & 3]; |
2404 | 450d4ff5 | ths | |
2405 | 450d4ff5 | ths | info->flags |
2406 | 450d4ff5 | ths | |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG |
2407 | 450d4ff5 | ths | | CRIS_DIS_FLAG_MEM_TARGET2_MEM |
2408 | 450d4ff5 | ths | | CRIS_DIS_FLAG_MEM_TARGET_IS_REG |
2409 | 450d4ff5 | ths | |
2410 | 450d4ff5 | ths | | (((prefix_insn >> 4) == 2) |
2411 | 450d4ff5 | ths | ? 0
|
2412 | 450d4ff5 | ths | : (((prefix_insn >> 4) & 3) == 1 |
2413 | 450d4ff5 | ths | ? CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD |
2414 | 450d4ff5 | ths | : CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE))); |
2415 | 450d4ff5 | ths | } |
2416 | 450d4ff5 | ths | break;
|
2417 | 450d4ff5 | ths | |
2418 | 450d4ff5 | ths | default:
|
2419 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "?prefix-bug");
|
2420 | 450d4ff5 | ths | } |
2421 | 450d4ff5 | ths | |
2422 | 450d4ff5 | ths | /* To mark that the prefix is used, reset it. */
|
2423 | 450d4ff5 | ths | prefix_opcodep = NULL;
|
2424 | 450d4ff5 | ths | } |
2425 | 450d4ff5 | ths | else
|
2426 | 450d4ff5 | ths | { |
2427 | 450d4ff5 | ths | tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
|
2428 | 450d4ff5 | ths | |
2429 | 450d4ff5 | ths | info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG; |
2430 | 450d4ff5 | ths | info->target = insn & 15;
|
2431 | 450d4ff5 | ths | |
2432 | 450d4ff5 | ths | if (insn & 0x400) |
2433 | 450d4ff5 | ths | *tp++ = '+';
|
2434 | 450d4ff5 | ths | } |
2435 | 450d4ff5 | ths | *tp++ = ']';
|
2436 | 450d4ff5 | ths | } |
2437 | 450d4ff5 | ths | break;
|
2438 | 450d4ff5 | ths | |
2439 | 450d4ff5 | ths | case 'x': |
2440 | 450d4ff5 | ths | tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix); |
2441 | 450d4ff5 | ths | *tp++ = '.';
|
2442 | 450d4ff5 | ths | *tp++ = mode_char[(insn >> 4) & 3]; |
2443 | 450d4ff5 | ths | break;
|
2444 | 450d4ff5 | ths | |
2445 | 450d4ff5 | ths | case 'I': |
2446 | 450d4ff5 | ths | tp = format_dec (insn & 63, tp, 0); |
2447 | 450d4ff5 | ths | break;
|
2448 | 450d4ff5 | ths | |
2449 | 450d4ff5 | ths | case 'b': |
2450 | 450d4ff5 | ths | { |
2451 | 450d4ff5 | ths | int where = buffer[2] + buffer[3] * 256; |
2452 | 450d4ff5 | ths | |
2453 | 450d4ff5 | ths | if (where > 32767) |
2454 | 450d4ff5 | ths | where -= 65536;
|
2455 | 450d4ff5 | ths | |
2456 | 450d4ff5 | ths | where += addr + ((disdata->distype == cris_dis_v32) ? 0 : 4); |
2457 | 450d4ff5 | ths | |
2458 | 450d4ff5 | ths | if (insn == BA_PC_INCR_OPCODE)
|
2459 | 450d4ff5 | ths | info->insn_type = dis_branch; |
2460 | 450d4ff5 | ths | else
|
2461 | 450d4ff5 | ths | info->insn_type = dis_condbranch; |
2462 | 450d4ff5 | ths | |
2463 | 450d4ff5 | ths | info->target = (bfd_vma) where; |
2464 | 450d4ff5 | ths | |
2465 | 450d4ff5 | ths | *tp = 0;
|
2466 | 450d4ff5 | ths | tp = temp; |
2467 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "%s%s ",
|
2468 | 450d4ff5 | ths | temp, cris_cc_strings[insn >> 12]);
|
2469 | 450d4ff5 | ths | |
2470 | 450d4ff5 | ths | (*info->print_address_func) ((bfd_vma) where, info); |
2471 | 450d4ff5 | ths | } |
2472 | 450d4ff5 | ths | break;
|
2473 | 450d4ff5 | ths | |
2474 | 450d4ff5 | ths | case 'c': |
2475 | 450d4ff5 | ths | tp = format_dec (insn & 31, tp, 0); |
2476 | 450d4ff5 | ths | break;
|
2477 | 450d4ff5 | ths | |
2478 | 450d4ff5 | ths | case 'C': |
2479 | 450d4ff5 | ths | tp = format_dec (insn & 15, tp, 0); |
2480 | 450d4ff5 | ths | break;
|
2481 | 450d4ff5 | ths | |
2482 | 450d4ff5 | ths | case 'o': |
2483 | 450d4ff5 | ths | { |
2484 | 450d4ff5 | ths | long offset = insn & 0xfe; |
2485 | 450d4ff5 | ths | bfd_vma target; |
2486 | 450d4ff5 | ths | |
2487 | 450d4ff5 | ths | if (insn & 1) |
2488 | 450d4ff5 | ths | offset |= ~0xff;
|
2489 | 450d4ff5 | ths | |
2490 | 450d4ff5 | ths | if (opcodep->match == BA_QUICK_OPCODE)
|
2491 | 450d4ff5 | ths | info->insn_type = dis_branch; |
2492 | 450d4ff5 | ths | else
|
2493 | 450d4ff5 | ths | info->insn_type = dis_condbranch; |
2494 | 450d4ff5 | ths | |
2495 | 450d4ff5 | ths | target = addr + ((disdata->distype == cris_dis_v32) ? 0 : 2) + offset; |
2496 | 450d4ff5 | ths | info->target = target; |
2497 | 450d4ff5 | ths | *tp = 0;
|
2498 | 450d4ff5 | ths | tp = temp; |
2499 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "%s", temp);
|
2500 | 450d4ff5 | ths | (*info->print_address_func) (target, info); |
2501 | 450d4ff5 | ths | } |
2502 | 450d4ff5 | ths | break;
|
2503 | 450d4ff5 | ths | |
2504 | 450d4ff5 | ths | case 'Q': |
2505 | 450d4ff5 | ths | case 'O': |
2506 | 450d4ff5 | ths | { |
2507 | 450d4ff5 | ths | long number = buffer[0]; |
2508 | 450d4ff5 | ths | |
2509 | 450d4ff5 | ths | if (number > 127) |
2510 | 450d4ff5 | ths | number = number - 256;
|
2511 | 450d4ff5 | ths | |
2512 | 450d4ff5 | ths | tp = format_dec (number, tp, 1);
|
2513 | 450d4ff5 | ths | *tp++ = ',';
|
2514 | 450d4ff5 | ths | tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix); |
2515 | 450d4ff5 | ths | } |
2516 | 450d4ff5 | ths | break;
|
2517 | 450d4ff5 | ths | |
2518 | 450d4ff5 | ths | case 'f': |
2519 | 450d4ff5 | ths | tp = print_flags (disdata, insn, tp); |
2520 | 450d4ff5 | ths | break;
|
2521 | 450d4ff5 | ths | |
2522 | 450d4ff5 | ths | case 'i': |
2523 | 450d4ff5 | ths | tp = format_dec ((insn & 32) ? (insn & 31) | ~31L : insn & 31, tp, 1); |
2524 | 450d4ff5 | ths | break;
|
2525 | 450d4ff5 | ths | |
2526 | 450d4ff5 | ths | case 'P': |
2527 | 450d4ff5 | ths | { |
2528 | 450d4ff5 | ths | const struct cris_spec_reg *sregp |
2529 | 450d4ff5 | ths | = spec_reg_info ((insn >> 12) & 15, disdata->distype); |
2530 | 450d4ff5 | ths | |
2531 | 450d4ff5 | ths | if (sregp->name == NULL) |
2532 | 450d4ff5 | ths | /* Should have been caught as a non-match eariler. */
|
2533 | 450d4ff5 | ths | *tp++ = '?';
|
2534 | 450d4ff5 | ths | else
|
2535 | 450d4ff5 | ths | { |
2536 | 450d4ff5 | ths | if (with_reg_prefix)
|
2537 | 450d4ff5 | ths | *tp++ = REGISTER_PREFIX_CHAR; |
2538 | 450d4ff5 | ths | strcpy (tp, sregp->name); |
2539 | 450d4ff5 | ths | tp += strlen (tp); |
2540 | 450d4ff5 | ths | } |
2541 | 450d4ff5 | ths | } |
2542 | 450d4ff5 | ths | break;
|
2543 | 450d4ff5 | ths | |
2544 | 450d4ff5 | ths | default:
|
2545 | 450d4ff5 | ths | strcpy (tp, "???");
|
2546 | 450d4ff5 | ths | tp += 3;
|
2547 | 450d4ff5 | ths | } |
2548 | 450d4ff5 | ths | } |
2549 | 450d4ff5 | ths | |
2550 | 450d4ff5 | ths | *tp = 0;
|
2551 | 450d4ff5 | ths | |
2552 | 450d4ff5 | ths | if (prefix_opcodep)
|
2553 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, " (OOPS unused prefix \"%s: %s\")",
|
2554 | 450d4ff5 | ths | prefix_opcodep->name, prefix_opcodep->args); |
2555 | 450d4ff5 | ths | |
2556 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "%s", temp);
|
2557 | 450d4ff5 | ths | |
2558 | 450d4ff5 | ths | /* Get info for matching case-tables, if we don't have any active.
|
2559 | 450d4ff5 | ths | We assume that the last constant seen is used; either in the insn
|
2560 | 450d4ff5 | ths | itself or in a "move.d const,rN, sub.d rN,rM"-like sequence. */
|
2561 | 450d4ff5 | ths | if (TRACE_CASE && case_offset_counter == 0) |
2562 | 450d4ff5 | ths | { |
2563 | 450d4ff5 | ths | if (CONST_STRNEQ (opcodep->name, "sub")) |
2564 | 450d4ff5 | ths | case_offset = last_immediate; |
2565 | 450d4ff5 | ths | |
2566 | 450d4ff5 | ths | /* It could also be an "add", if there are negative case-values. */
|
2567 | 450d4ff5 | ths | else if (CONST_STRNEQ (opcodep->name, "add")) |
2568 | 450d4ff5 | ths | /* The first case is the negated operand to the add. */
|
2569 | 450d4ff5 | ths | case_offset = -last_immediate; |
2570 | 450d4ff5 | ths | |
2571 | 450d4ff5 | ths | /* A bound insn will tell us the number of cases. */
|
2572 | 450d4ff5 | ths | else if (CONST_STRNEQ (opcodep->name, "bound")) |
2573 | 450d4ff5 | ths | no_of_case_offsets = last_immediate + 1;
|
2574 | 450d4ff5 | ths | |
2575 | 450d4ff5 | ths | /* A jump or jsr or branch breaks the chain of insns for a
|
2576 | 450d4ff5 | ths | case-table, so assume default first-case again. */
|
2577 | 450d4ff5 | ths | else if (info->insn_type == dis_jsr |
2578 | 450d4ff5 | ths | || info->insn_type == dis_branch |
2579 | 450d4ff5 | ths | || info->insn_type == dis_condbranch) |
2580 | 450d4ff5 | ths | case_offset = 0;
|
2581 | 450d4ff5 | ths | } |
2582 | 450d4ff5 | ths | } |
2583 | 450d4ff5 | ths | |
2584 | 450d4ff5 | ths | |
2585 | 450d4ff5 | ths | /* Print the CRIS instruction at address memaddr on stream. Returns
|
2586 | 450d4ff5 | ths | length of the instruction, in bytes. Prefix register names with `$' if
|
2587 | 450d4ff5 | ths | WITH_REG_PREFIX. */
|
2588 | 450d4ff5 | ths | |
2589 | 450d4ff5 | ths | static int |
2590 | 450d4ff5 | ths | print_insn_cris_generic (bfd_vma memaddr, |
2591 | 450d4ff5 | ths | disassemble_info *info, |
2592 | 450d4ff5 | ths | bfd_boolean with_reg_prefix) |
2593 | 450d4ff5 | ths | { |
2594 | 450d4ff5 | ths | int nbytes;
|
2595 | 450d4ff5 | ths | unsigned int insn; |
2596 | 450d4ff5 | ths | const struct cris_opcode *matchedp; |
2597 | 450d4ff5 | ths | int advance = 0; |
2598 | 450d4ff5 | ths | struct cris_disasm_data *disdata
|
2599 | 450d4ff5 | ths | = (struct cris_disasm_data *) info->private_data;
|
2600 | 450d4ff5 | ths | |
2601 | 450d4ff5 | ths | /* No instruction will be disassembled as longer than this number of
|
2602 | 450d4ff5 | ths | bytes; stacked prefixes will not be expanded. */
|
2603 | 450d4ff5 | ths | unsigned char buffer[MAX_BYTES_PER_CRIS_INSN]; |
2604 | 450d4ff5 | ths | unsigned char *bufp; |
2605 | 450d4ff5 | ths | int status = 0; |
2606 | 450d4ff5 | ths | bfd_vma addr; |
2607 | 450d4ff5 | ths | |
2608 | 450d4ff5 | ths | /* There will be an "out of range" error after the last instruction.
|
2609 | 450d4ff5 | ths | Reading pairs of bytes in decreasing number, we hope that we will get
|
2610 | 450d4ff5 | ths | at least the amount that we will consume.
|
2611 | 450d4ff5 | ths | |
2612 | 450d4ff5 | ths | If we can't get any data, or we do not get enough data, we print
|
2613 | 450d4ff5 | ths | the error message. */
|
2614 | 450d4ff5 | ths | |
2615 | bfaf9a43 | edgar_igl | nbytes = info->buffer_length; |
2616 | bfaf9a43 | edgar_igl | if (nbytes > MAX_BYTES_PER_CRIS_INSN)
|
2617 | bfaf9a43 | edgar_igl | nbytes = MAX_BYTES_PER_CRIS_INSN; |
2618 | bfaf9a43 | edgar_igl | status = (*info->read_memory_func) (memaddr, buffer, nbytes, info); |
2619 | 450d4ff5 | ths | |
2620 | 450d4ff5 | ths | /* If we did not get all we asked for, then clear the rest.
|
2621 | 450d4ff5 | ths | Hopefully this makes a reproducible result in case of errors. */
|
2622 | 450d4ff5 | ths | if (nbytes != MAX_BYTES_PER_CRIS_INSN)
|
2623 | 450d4ff5 | ths | memset (buffer + nbytes, 0, MAX_BYTES_PER_CRIS_INSN - nbytes);
|
2624 | 450d4ff5 | ths | |
2625 | 450d4ff5 | ths | addr = memaddr; |
2626 | 450d4ff5 | ths | bufp = buffer; |
2627 | 450d4ff5 | ths | |
2628 | 450d4ff5 | ths | /* Set some defaults for the insn info. */
|
2629 | 450d4ff5 | ths | info->insn_info_valid = 1;
|
2630 | 450d4ff5 | ths | info->branch_delay_insns = 0;
|
2631 | 450d4ff5 | ths | info->data_size = 0;
|
2632 | 450d4ff5 | ths | info->insn_type = dis_nonbranch; |
2633 | 450d4ff5 | ths | info->flags = 0;
|
2634 | 450d4ff5 | ths | info->target = 0;
|
2635 | 450d4ff5 | ths | info->target2 = 0;
|
2636 | 450d4ff5 | ths | |
2637 | 450d4ff5 | ths | /* If we got any data, disassemble it. */
|
2638 | 450d4ff5 | ths | if (nbytes != 0) |
2639 | 450d4ff5 | ths | { |
2640 | 450d4ff5 | ths | matchedp = NULL;
|
2641 | 450d4ff5 | ths | |
2642 | 450d4ff5 | ths | insn = bufp[0] + bufp[1] * 256; |
2643 | 450d4ff5 | ths | |
2644 | 450d4ff5 | ths | /* If we're in a case-table, don't disassemble the offsets. */
|
2645 | 450d4ff5 | ths | if (TRACE_CASE && case_offset_counter != 0) |
2646 | 450d4ff5 | ths | { |
2647 | 450d4ff5 | ths | info->insn_type = dis_noninsn; |
2648 | 450d4ff5 | ths | advance += 2;
|
2649 | 450d4ff5 | ths | |
2650 | 450d4ff5 | ths | /* If to print data as offsets, then shortcut here. */
|
2651 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "case %ld%s: -> ",
|
2652 | 450d4ff5 | ths | case_offset + no_of_case_offsets |
2653 | 450d4ff5 | ths | - case_offset_counter, |
2654 | 450d4ff5 | ths | case_offset_counter == 1 ? "/default" : |
2655 | 450d4ff5 | ths | "");
|
2656 | 450d4ff5 | ths | |
2657 | 450d4ff5 | ths | (*info->print_address_func) ((bfd_vma) |
2658 | 450d4ff5 | ths | ((short) (insn)
|
2659 | 450d4ff5 | ths | + (long) (addr
|
2660 | 450d4ff5 | ths | - (no_of_case_offsets |
2661 | 450d4ff5 | ths | - case_offset_counter) |
2662 | 450d4ff5 | ths | * 2)), info);
|
2663 | 450d4ff5 | ths | case_offset_counter--; |
2664 | 450d4ff5 | ths | |
2665 | 450d4ff5 | ths | /* The default case start (without a "sub" or "add") must be
|
2666 | 450d4ff5 | ths | zero. */
|
2667 | 450d4ff5 | ths | if (case_offset_counter == 0) |
2668 | 450d4ff5 | ths | case_offset = 0;
|
2669 | 450d4ff5 | ths | } |
2670 | 450d4ff5 | ths | else if (insn == 0) |
2671 | 450d4ff5 | ths | { |
2672 | 450d4ff5 | ths | /* We're often called to disassemble zeroes. While this is a
|
2673 | 450d4ff5 | ths | valid "bcc .+2" insn, it is also useless enough and enough
|
2674 | 450d4ff5 | ths | of a nuiscance that we will just output "bcc .+2" for it
|
2675 | 450d4ff5 | ths | and signal it as a noninsn. */
|
2676 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, |
2677 | 450d4ff5 | ths | disdata->distype == cris_dis_v32 |
2678 | 450d4ff5 | ths | ? "bcc ." : "bcc .+2"); |
2679 | 450d4ff5 | ths | info->insn_type = dis_noninsn; |
2680 | 450d4ff5 | ths | advance += 2;
|
2681 | 450d4ff5 | ths | } |
2682 | 450d4ff5 | ths | else
|
2683 | 450d4ff5 | ths | { |
2684 | 450d4ff5 | ths | const struct cris_opcode *prefix_opcodep = NULL; |
2685 | 450d4ff5 | ths | unsigned char *prefix_buffer = bufp; |
2686 | 450d4ff5 | ths | unsigned int prefix_insn = insn; |
2687 | 450d4ff5 | ths | int prefix_size = 0; |
2688 | 450d4ff5 | ths | |
2689 | 450d4ff5 | ths | matchedp = get_opcode_entry (insn, NO_CRIS_PREFIX, disdata); |
2690 | 450d4ff5 | ths | |
2691 | 450d4ff5 | ths | /* Check if we're supposed to write out prefixes as address
|
2692 | 450d4ff5 | ths | modes and if this was a prefix. */
|
2693 | 450d4ff5 | ths | if (matchedp != NULL && PARSE_PREFIX && matchedp->args[0] == 'p') |
2694 | 450d4ff5 | ths | { |
2695 | 450d4ff5 | ths | /* If it's a prefix, put it into the prefix vars and get the
|
2696 | 450d4ff5 | ths | main insn. */
|
2697 | 450d4ff5 | ths | prefix_size = bytes_to_skip (prefix_insn, matchedp, |
2698 | 450d4ff5 | ths | disdata->distype, NULL);
|
2699 | 450d4ff5 | ths | prefix_opcodep = matchedp; |
2700 | 450d4ff5 | ths | |
2701 | 450d4ff5 | ths | insn = bufp[prefix_size] + bufp[prefix_size + 1] * 256; |
2702 | 450d4ff5 | ths | matchedp = get_opcode_entry (insn, prefix_insn, disdata); |
2703 | 450d4ff5 | ths | |
2704 | 450d4ff5 | ths | if (matchedp != NULL) |
2705 | 450d4ff5 | ths | { |
2706 | 450d4ff5 | ths | addr += prefix_size; |
2707 | 450d4ff5 | ths | bufp += prefix_size; |
2708 | 450d4ff5 | ths | advance += prefix_size; |
2709 | 450d4ff5 | ths | } |
2710 | 450d4ff5 | ths | else
|
2711 | 450d4ff5 | ths | { |
2712 | 450d4ff5 | ths | /* The "main" insn wasn't valid, at least not when
|
2713 | 450d4ff5 | ths | prefixed. Put back things enough to output the
|
2714 | 450d4ff5 | ths | prefix insn only, as a normal insn. */
|
2715 | 450d4ff5 | ths | matchedp = prefix_opcodep; |
2716 | 450d4ff5 | ths | insn = prefix_insn; |
2717 | 450d4ff5 | ths | prefix_opcodep = NULL;
|
2718 | 450d4ff5 | ths | } |
2719 | 450d4ff5 | ths | } |
2720 | 450d4ff5 | ths | |
2721 | 450d4ff5 | ths | if (matchedp == NULL) |
2722 | 450d4ff5 | ths | { |
2723 | 450d4ff5 | ths | (*info->fprintf_func) (info->stream, "??0x%x", insn);
|
2724 | 450d4ff5 | ths | advance += 2;
|
2725 | 450d4ff5 | ths | |
2726 | 450d4ff5 | ths | info->insn_type = dis_noninsn; |
2727 | 450d4ff5 | ths | } |
2728 | 450d4ff5 | ths | else
|
2729 | 450d4ff5 | ths | { |
2730 | 450d4ff5 | ths | advance |
2731 | 450d4ff5 | ths | += bytes_to_skip (insn, matchedp, disdata->distype, |
2732 | 450d4ff5 | ths | prefix_opcodep); |
2733 | 450d4ff5 | ths | |
2734 | 450d4ff5 | ths | /* The info_type and assorted fields will be set according
|
2735 | 450d4ff5 | ths | to the operands. */
|
2736 | 450d4ff5 | ths | print_with_operands (matchedp, insn, bufp, addr, info, |
2737 | 450d4ff5 | ths | prefix_opcodep, prefix_insn, |
2738 | 450d4ff5 | ths | prefix_buffer, with_reg_prefix); |
2739 | 450d4ff5 | ths | } |
2740 | 450d4ff5 | ths | } |
2741 | 450d4ff5 | ths | } |
2742 | 450d4ff5 | ths | else
|
2743 | 450d4ff5 | ths | info->insn_type = dis_noninsn; |
2744 | 450d4ff5 | ths | |
2745 | 450d4ff5 | ths | /* If we read less than MAX_BYTES_PER_CRIS_INSN, i.e. we got an error
|
2746 | 450d4ff5 | ths | status when reading that much, and the insn decoding indicated a
|
2747 | 450d4ff5 | ths | length exceeding what we read, there is an error. */
|
2748 | 450d4ff5 | ths | if (status != 0 && (nbytes == 0 || advance > nbytes)) |
2749 | 450d4ff5 | ths | { |
2750 | 450d4ff5 | ths | (*info->memory_error_func) (status, memaddr, info); |
2751 | 450d4ff5 | ths | return -1; |
2752 | 450d4ff5 | ths | } |
2753 | 450d4ff5 | ths | |
2754 | 450d4ff5 | ths | /* Max supported insn size with one folded prefix insn. */
|
2755 | 450d4ff5 | ths | info->bytes_per_line = MAX_BYTES_PER_CRIS_INSN; |
2756 | 450d4ff5 | ths | |
2757 | 450d4ff5 | ths | /* I would like to set this to a fixed value larger than the actual
|
2758 | 450d4ff5 | ths | number of bytes to print in order to avoid spaces between bytes,
|
2759 | 450d4ff5 | ths | but objdump.c (2.9.1) does not like that, so we print 16-bit
|
2760 | 450d4ff5 | ths | chunks, which is the next choice. */
|
2761 | 450d4ff5 | ths | info->bytes_per_chunk = 2;
|
2762 | 450d4ff5 | ths | |
2763 | 450d4ff5 | ths | /* Printing bytes in order of increasing addresses makes sense,
|
2764 | 450d4ff5 | ths | especially on a little-endian target.
|
2765 | 450d4ff5 | ths | This is completely the opposite of what you think; setting this to
|
2766 | 450d4ff5 | ths | BFD_ENDIAN_LITTLE will print bytes in order N..0 rather than the 0..N
|
2767 | 450d4ff5 | ths | we want. */
|
2768 | 450d4ff5 | ths | info->display_endian = BFD_ENDIAN_BIG; |
2769 | 450d4ff5 | ths | |
2770 | 450d4ff5 | ths | return advance;
|
2771 | 450d4ff5 | ths | } |
2772 | 450d4ff5 | ths | |
2773 | 450d4ff5 | ths | /* Disassemble, prefixing register names with `$'. CRIS v0..v10. */
|
2774 | 450d4ff5 | ths | #if 0
|
2775 | 450d4ff5 | ths | static int
|
2776 | 450d4ff5 | ths | print_insn_cris_with_register_prefix (bfd_vma vma,
|
2777 | 450d4ff5 | ths | disassemble_info *info)
|
2778 | 450d4ff5 | ths | {
|
2779 | 450d4ff5 | ths | if (info->private_data == NULL
|
2780 | 450d4ff5 | ths | && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
|
2781 | 450d4ff5 | ths | return -1;
|
2782 | 450d4ff5 | ths | return print_insn_cris_generic (vma, info, TRUE);
|
2783 | 450d4ff5 | ths | }
|
2784 | 450d4ff5 | ths | #endif
|
2785 | 450d4ff5 | ths | /* Disassemble, prefixing register names with `$'. CRIS v32. */
|
2786 | 450d4ff5 | ths | |
2787 | 450d4ff5 | ths | static int |
2788 | 450d4ff5 | ths | print_insn_crisv32_with_register_prefix (bfd_vma vma, |
2789 | 450d4ff5 | ths | disassemble_info *info) |
2790 | 450d4ff5 | ths | { |
2791 | 450d4ff5 | ths | if (info->private_data == NULL |
2792 | 450d4ff5 | ths | && !cris_parse_disassembler_options (info, cris_dis_v32)) |
2793 | 450d4ff5 | ths | return -1; |
2794 | 450d4ff5 | ths | return print_insn_cris_generic (vma, info, TRUE);
|
2795 | 450d4ff5 | ths | } |
2796 | 450d4ff5 | ths | |
2797 | 450d4ff5 | ths | #if 0
|
2798 | 450d4ff5 | ths | /* Disassemble, prefixing register names with `$'.
|
2799 | 450d4ff5 | ths | Common v10 and v32 subset. */
|
2800 | 450d4ff5 | ths | |
2801 | 450d4ff5 | ths | static int
|
2802 | 450d4ff5 | ths | print_insn_crisv10_v32_with_register_prefix (bfd_vma vma,
|
2803 | 450d4ff5 | ths | disassemble_info *info)
|
2804 | 450d4ff5 | ths | {
|
2805 | 450d4ff5 | ths | if (info->private_data == NULL
|
2806 | 450d4ff5 | ths | && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
|
2807 | 450d4ff5 | ths | return -1;
|
2808 | 450d4ff5 | ths | return print_insn_cris_generic (vma, info, TRUE);
|
2809 | 450d4ff5 | ths | }
|
2810 | 450d4ff5 | ths | |
2811 | 450d4ff5 | ths | /* Disassemble, no prefixes on register names. CRIS v0..v10. */
|
2812 | 450d4ff5 | ths | |
2813 | 450d4ff5 | ths | static int
|
2814 | 450d4ff5 | ths | print_insn_cris_without_register_prefix (bfd_vma vma,
|
2815 | 450d4ff5 | ths | disassemble_info *info)
|
2816 | 450d4ff5 | ths | {
|
2817 | 450d4ff5 | ths | if (info->private_data == NULL
|
2818 | 450d4ff5 | ths | && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
|
2819 | 450d4ff5 | ths | return -1;
|
2820 | 450d4ff5 | ths | return print_insn_cris_generic (vma, info, FALSE);
|
2821 | 450d4ff5 | ths | }
|
2822 | 450d4ff5 | ths | |
2823 | 450d4ff5 | ths | /* Disassemble, no prefixes on register names. CRIS v32. */
|
2824 | 450d4ff5 | ths | |
2825 | 450d4ff5 | ths | static int
|
2826 | 450d4ff5 | ths | print_insn_crisv32_without_register_prefix (bfd_vma vma,
|
2827 | 450d4ff5 | ths | disassemble_info *info)
|
2828 | 450d4ff5 | ths | {
|
2829 | 450d4ff5 | ths | if (info->private_data == NULL
|
2830 | 450d4ff5 | ths | && !cris_parse_disassembler_options (info, cris_dis_v32))
|
2831 | 450d4ff5 | ths | return -1;
|
2832 | 450d4ff5 | ths | return print_insn_cris_generic (vma, info, FALSE);
|
2833 | 450d4ff5 | ths | }
|
2834 | 450d4ff5 | ths | |
2835 | 450d4ff5 | ths | /* Disassemble, no prefixes on register names.
|
2836 | 450d4ff5 | ths | Common v10 and v32 subset. */
|
2837 | 450d4ff5 | ths | |
2838 | 450d4ff5 | ths | static int
|
2839 | 450d4ff5 | ths | print_insn_crisv10_v32_without_register_prefix (bfd_vma vma,
|
2840 | 450d4ff5 | ths | disassemble_info *info)
|
2841 | 450d4ff5 | ths | {
|
2842 | 450d4ff5 | ths | if (info->private_data == NULL
|
2843 | 450d4ff5 | ths | && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
|
2844 | 450d4ff5 | ths | return -1;
|
2845 | 450d4ff5 | ths | return print_insn_cris_generic (vma, info, FALSE);
|
2846 | 450d4ff5 | ths | }
|
2847 | 450d4ff5 | ths | #endif
|
2848 | 450d4ff5 | ths | |
2849 | 450d4ff5 | ths | int
|
2850 | 450d4ff5 | ths | print_insn_crisv32 (bfd_vma vma, |
2851 | 450d4ff5 | ths | disassemble_info *info) |
2852 | 450d4ff5 | ths | { |
2853 | 450d4ff5 | ths | return print_insn_crisv32_with_register_prefix(vma, info);
|
2854 | 450d4ff5 | ths | } |
2855 | 450d4ff5 | ths | |
2856 | 450d4ff5 | ths | /* Return a disassembler-function that prints registers with a `$' prefix,
|
2857 | 450d4ff5 | ths | or one that prints registers without a prefix.
|
2858 | 450d4ff5 | ths | FIXME: We should improve the solution to avoid the multitude of
|
2859 | 450d4ff5 | ths | functions seen above. */
|
2860 | 450d4ff5 | ths | #if 0
|
2861 | 450d4ff5 | ths | disassembler_ftype
|
2862 | 450d4ff5 | ths | cris_get_disassembler (bfd *abfd)
|
2863 | 450d4ff5 | ths | {
|
2864 | 450d4ff5 | ths | /* If there's no bfd in sight, we return what is valid as input in all
|
2865 | 450d4ff5 | ths | contexts if fed back to the assembler: disassembly *with* register
|
2866 | 450d4ff5 | ths | prefix. Unfortunately this will be totally wrong for v32. */
|
2867 | 450d4ff5 | ths | if (abfd == NULL)
|
2868 | 450d4ff5 | ths | return print_insn_cris_with_register_prefix;
|
2869 | 450d4ff5 | ths | |
2870 | 450d4ff5 | ths | if (bfd_get_symbol_leading_char (abfd) == 0)
|
2871 | 450d4ff5 | ths | {
|
2872 | 450d4ff5 | ths | if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
|
2873 | 450d4ff5 | ths | return print_insn_crisv32_with_register_prefix;
|
2874 | 450d4ff5 | ths | if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
|
2875 | 450d4ff5 | ths | return print_insn_crisv10_v32_with_register_prefix;
|
2876 | 450d4ff5 | ths | |
2877 | 450d4ff5 | ths | /* We default to v10. This may be specifically specified in the
|
2878 | 450d4ff5 | ths | bfd mach, but is also the default setting. */
|
2879 | 450d4ff5 | ths | return print_insn_cris_with_register_prefix;
|
2880 | 450d4ff5 | ths | }
|
2881 | 450d4ff5 | ths | |
2882 | 450d4ff5 | ths | if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
|
2883 | 450d4ff5 | ths | return print_insn_crisv32_without_register_prefix;
|
2884 | 450d4ff5 | ths | if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
|
2885 | 450d4ff5 | ths | return print_insn_crisv10_v32_without_register_prefix;
|
2886 | 450d4ff5 | ths | return print_insn_cris_without_register_prefix;
|
2887 | 450d4ff5 | ths | }
|
2888 | 450d4ff5 | ths | #endif
|
2889 | 450d4ff5 | ths | /* Local variables:
|
2890 | 450d4ff5 | ths | eval: (c-set-style "gnu")
|
2891 | 450d4ff5 | ths | indent-tabs-mode: t
|
2892 | 450d4ff5 | ths | End: */ |