root / hw / vmware_vga.c @ c4470b25
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/*
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* QEMU VMware-SVGA "chipset".
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*
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* Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "console.h" |
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#include "pci.h" |
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#define VERBOSE
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#define EMBED_STDVGA
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#undef DIRECT_VRAM
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#define HW_RECT_ACCEL
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#define HW_FILL_ACCEL
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#define HW_MOUSE_ACCEL
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#ifdef EMBED_STDVGA
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# include "vga_int.h" |
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#endif
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struct vmsvga_state_s {
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#ifdef EMBED_STDVGA
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VGACommonState vga; |
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#endif
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int width;
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int height;
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int invalidated;
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int depth;
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int bypp;
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int enable;
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int config;
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struct {
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int id;
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int x;
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int y;
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int on;
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} cursor; |
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#ifndef EMBED_STDVGA
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DisplayState *ds; |
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int vram_size;
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ram_addr_t vram_offset; |
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uint8_t *vram_ptr; |
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#endif
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target_phys_addr_t vram_base; |
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int index;
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int scratch_size;
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uint32_t *scratch; |
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int new_width;
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int new_height;
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uint32_t guest; |
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uint32_t svgaid; |
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uint32_t wred; |
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uint32_t wgreen; |
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uint32_t wblue; |
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int syncing;
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int fb_size;
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union {
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uint32_t *fifo; |
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struct __attribute__((__packed__)) {
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uint32_t min; |
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uint32_t max; |
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uint32_t next_cmd; |
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uint32_t stop; |
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/* Add registers here when adding capabilities. */
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uint32_t fifo[0];
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} *cmd; |
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}; |
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#define REDRAW_FIFO_LEN 512 |
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struct vmsvga_rect_s {
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int x, y, w, h;
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} redraw_fifo[REDRAW_FIFO_LEN]; |
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int redraw_fifo_first, redraw_fifo_last;
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}; |
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struct pci_vmsvga_state_s {
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PCIDevice card; |
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struct vmsvga_state_s chip;
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}; |
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#define SVGA_MAGIC 0x900000UL |
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#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) |
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#define SVGA_ID_0 SVGA_MAKE_ID(0) |
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#define SVGA_ID_1 SVGA_MAKE_ID(1) |
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#define SVGA_ID_2 SVGA_MAKE_ID(2) |
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#define SVGA_LEGACY_BASE_PORT 0x4560 |
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#define SVGA_INDEX_PORT 0x0 |
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#define SVGA_VALUE_PORT 0x1 |
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#define SVGA_BIOS_PORT 0x2 |
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#define SVGA_VERSION_2
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#ifdef SVGA_VERSION_2
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# define SVGA_ID SVGA_ID_2
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# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
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# define SVGA_IO_MUL 1 |
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# define SVGA_FIFO_SIZE 0x10000 |
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# define SVGA_MEM_BASE 0xe0000000 |
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# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
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#else
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# define SVGA_ID SVGA_ID_1
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# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
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# define SVGA_IO_MUL 4 |
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# define SVGA_FIFO_SIZE 0x10000 |
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# define SVGA_MEM_BASE 0xe0000000 |
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# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
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#endif
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enum {
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/* ID 0, 1 and 2 registers */
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SVGA_REG_ID = 0,
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SVGA_REG_ENABLE = 1,
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SVGA_REG_WIDTH = 2,
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SVGA_REG_HEIGHT = 3,
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SVGA_REG_MAX_WIDTH = 4,
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SVGA_REG_MAX_HEIGHT = 5,
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SVGA_REG_DEPTH = 6,
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SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ |
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SVGA_REG_PSEUDOCOLOR = 8,
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SVGA_REG_RED_MASK = 9,
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SVGA_REG_GREEN_MASK = 10,
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SVGA_REG_BLUE_MASK = 11,
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SVGA_REG_BYTES_PER_LINE = 12,
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SVGA_REG_FB_START = 13,
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SVGA_REG_FB_OFFSET = 14,
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SVGA_REG_VRAM_SIZE = 15,
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SVGA_REG_FB_SIZE = 16,
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/* ID 1 and 2 registers */
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SVGA_REG_CAPABILITIES = 17,
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SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ |
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SVGA_REG_MEM_SIZE = 19,
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SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ |
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SVGA_REG_SYNC = 21, /* Write to force synchronization */ |
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SVGA_REG_BUSY = 22, /* Read to check if sync is done */ |
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SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ |
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SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ |
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SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ |
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SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ |
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SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ |
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SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ |
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SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ |
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SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ |
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SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ |
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SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ |
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SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ |
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SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
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SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
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}; |
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#define SVGA_CAP_NONE 0 |
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#define SVGA_CAP_RECT_FILL (1 << 0) |
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#define SVGA_CAP_RECT_COPY (1 << 1) |
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#define SVGA_CAP_RECT_PAT_FILL (1 << 2) |
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#define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) |
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#define SVGA_CAP_RASTER_OP (1 << 4) |
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#define SVGA_CAP_CURSOR (1 << 5) |
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#define SVGA_CAP_CURSOR_BYPASS (1 << 6) |
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#define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) |
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#define SVGA_CAP_8BIT_EMULATION (1 << 8) |
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#define SVGA_CAP_ALPHA_CURSOR (1 << 9) |
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#define SVGA_CAP_GLYPH (1 << 10) |
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#define SVGA_CAP_GLYPH_CLIPPING (1 << 11) |
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#define SVGA_CAP_OFFSCREEN_1 (1 << 12) |
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#define SVGA_CAP_ALPHA_BLEND (1 << 13) |
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#define SVGA_CAP_3D (1 << 14) |
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#define SVGA_CAP_EXTENDED_FIFO (1 << 15) |
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#define SVGA_CAP_MULTIMON (1 << 16) |
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#define SVGA_CAP_PITCHLOCK (1 << 17) |
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/*
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* FIFO offsets (seen as an array of 32-bit words)
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*/
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enum {
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/*
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* The original defined FIFO offsets
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*/
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SVGA_FIFO_MIN = 0,
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SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
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SVGA_FIFO_NEXT_CMD, |
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SVGA_FIFO_STOP, |
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/*
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* Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
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*/
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SVGA_FIFO_CAPABILITIES = 4,
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SVGA_FIFO_FLAGS, |
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SVGA_FIFO_FENCE, |
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SVGA_FIFO_3D_HWVERSION, |
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SVGA_FIFO_PITCHLOCK, |
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}; |
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#define SVGA_FIFO_CAP_NONE 0 |
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#define SVGA_FIFO_CAP_FENCE (1 << 0) |
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#define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) |
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#define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) |
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#define SVGA_FIFO_FLAG_NONE 0 |
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#define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) |
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/* These values can probably be changed arbitrarily. */
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#define SVGA_SCRATCH_SIZE 0x8000 |
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#define SVGA_MAX_WIDTH 2360 |
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#define SVGA_MAX_HEIGHT 1770 |
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#ifdef VERBOSE
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# define GUEST_OS_BASE 0x5001 |
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static const char *vmsvga_guest_id[] = { |
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[0x00] = "Dos", |
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[0x01] = "Windows 3.1", |
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[0x02] = "Windows 95", |
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[0x03] = "Windows 98", |
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[0x04] = "Windows ME", |
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[0x05] = "Windows NT", |
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[0x06] = "Windows 2000", |
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[0x07] = "Linux", |
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[0x08] = "OS/2", |
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[0x09] = "an unknown OS", |
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[0x0a] = "BSD", |
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[0x0b] = "Whistler", |
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[0x0c] = "an unknown OS", |
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[0x0d] = "an unknown OS", |
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[0x0e] = "an unknown OS", |
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[0x0f] = "an unknown OS", |
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[0x10] = "an unknown OS", |
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[0x11] = "an unknown OS", |
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[0x12] = "an unknown OS", |
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[0x13] = "an unknown OS", |
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[0x14] = "an unknown OS", |
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[0x15] = "Windows 2003", |
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}; |
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#endif
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enum {
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SVGA_CMD_INVALID_CMD = 0,
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SVGA_CMD_UPDATE = 1,
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SVGA_CMD_RECT_FILL = 2,
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SVGA_CMD_RECT_COPY = 3,
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SVGA_CMD_DEFINE_BITMAP = 4,
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SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
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SVGA_CMD_DEFINE_PIXMAP = 6,
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SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
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SVGA_CMD_RECT_BITMAP_FILL = 8,
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SVGA_CMD_RECT_PIXMAP_FILL = 9,
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SVGA_CMD_RECT_BITMAP_COPY = 10,
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SVGA_CMD_RECT_PIXMAP_COPY = 11,
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SVGA_CMD_FREE_OBJECT = 12,
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SVGA_CMD_RECT_ROP_FILL = 13,
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SVGA_CMD_RECT_ROP_COPY = 14,
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SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
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SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
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SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
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SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
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SVGA_CMD_DEFINE_CURSOR = 19,
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SVGA_CMD_DISPLAY_CURSOR = 20,
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SVGA_CMD_MOVE_CURSOR = 21,
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SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
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SVGA_CMD_DRAW_GLYPH = 23,
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SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
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SVGA_CMD_UPDATE_VERBOSE = 25,
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SVGA_CMD_SURFACE_FILL = 26,
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SVGA_CMD_SURFACE_COPY = 27,
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SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
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SVGA_CMD_FRONT_ROP_FILL = 29,
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SVGA_CMD_FENCE = 30,
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}; |
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/* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
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enum {
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SVGA_CURSOR_ON_HIDE = 0,
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SVGA_CURSOR_ON_SHOW = 1,
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SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
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SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
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}; |
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static inline void vmsvga_update_rect(struct vmsvga_state_s *s, |
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int x, int y, int w, int h) |
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{ |
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#ifndef DIRECT_VRAM
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int line;
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int bypl;
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int width;
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int start;
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uint8_t *src; |
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uint8_t *dst; |
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if (x + w > s->width) {
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fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
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__FUNCTION__, x, w); |
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x = MIN(x, s->width); |
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w = s->width - x; |
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} |
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if (y + h > s->height) {
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fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
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__FUNCTION__, y, h); |
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y = MIN(y, s->height); |
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h = s->height - y; |
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} |
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line = h; |
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bypl = s->bypp * s->width; |
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width = s->bypp * w; |
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start = s->bypp * x + bypl * y; |
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src = s->vga.vram_ptr + start; |
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dst = ds_get_data(s->vga.ds) + start; |
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for (; line > 0; line --, src += bypl, dst += bypl) |
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memcpy(dst, src, width); |
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#endif
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dpy_update(s->vga.ds, x, y, w, h); |
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} |
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static inline void vmsvga_update_screen(struct vmsvga_state_s *s) |
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{ |
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#ifndef DIRECT_VRAM
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memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, s->bypp * s->width * s->height); |
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#endif
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dpy_update(s->vga.ds, 0, 0, s->width, s->height); |
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} |
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#ifdef DIRECT_VRAM
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# define vmsvga_update_rect_delayed vmsvga_update_rect
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#else
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static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, |
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int x, int y, int w, int h) |
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{ |
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struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
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s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
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rect->x = x; |
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rect->y = y; |
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rect->w = w; |
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rect->h = h; |
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} |
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#endif
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static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) |
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{ |
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struct vmsvga_rect_s *rect;
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if (s->invalidated) {
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s->redraw_fifo_first = s->redraw_fifo_last; |
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return;
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} |
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/* Overlapping region updates can be optimised out here - if someone
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* knows a smart algorithm to do that, please share. */
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while (s->redraw_fifo_first != s->redraw_fifo_last) {
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rect = &s->redraw_fifo[s->redraw_fifo_first ++]; |
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s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
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vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h); |
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} |
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} |
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#ifdef HW_RECT_ACCEL
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static inline void vmsvga_copy_rect(struct vmsvga_state_s *s, |
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int x0, int y0, int x1, int y1, int w, int h) |
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{ |
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# ifdef DIRECT_VRAM
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uint8_t *vram = ds_get_data(s->ds); |
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# else
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uint8_t *vram = s->vga.vram_ptr; |
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# endif
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int bypl = s->bypp * s->width;
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int width = s->bypp * w;
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int line = h;
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uint8_t *ptr[2];
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# ifdef DIRECT_VRAM
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if (s->ds->dpy_copy)
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qemu_console_copy(s->ds, x0, y0, x1, y1, w, h); |
396 |
else
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# endif
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{ |
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if (y1 > y0) {
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ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1); |
401 |
ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1); |
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for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) |
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memmove(ptr[1], ptr[0], width); |
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} else {
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ptr[0] = vram + s->bypp * x0 + bypl * y0;
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ptr[1] = vram + s->bypp * x1 + bypl * y1;
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for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) |
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memmove(ptr[1], ptr[0], width); |
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} |
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} |
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|
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vmsvga_update_rect_delayed(s, x1, y1, w, h); |
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} |
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#endif
|
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|
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#ifdef HW_FILL_ACCEL
|
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static inline void vmsvga_fill_rect(struct vmsvga_state_s *s, |
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uint32_t c, int x, int y, int w, int h) |
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{ |
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# ifdef DIRECT_VRAM
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uint8_t *vram = ds_get_data(s->ds); |
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# else
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uint8_t *vram = s->vga.vram_ptr; |
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# endif
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int bypp = s->bypp;
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int bypl = bypp * s->width;
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int width = bypp * w;
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int line = h;
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int column;
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uint8_t *fst = vram + bypp * x + bypl * y; |
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uint8_t *dst; |
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uint8_t *src; |
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uint8_t col[4];
|
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|
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# ifdef DIRECT_VRAM
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if (s->ds->dpy_fill)
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s->ds->dpy_fill(s->ds, x, y, w, h, c); |
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else
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# endif
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{ |
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col[0] = c;
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col[1] = c >> 8; |
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col[2] = c >> 16; |
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col[3] = c >> 24; |
445 |
|
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if (line --) {
|
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dst = fst; |
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src = col; |
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for (column = width; column > 0; column --) { |
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*(dst ++) = *(src ++); |
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if (src - col == bypp)
|
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src = col; |
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} |
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dst = fst; |
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for (; line > 0; line --) { |
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dst += bypl; |
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memcpy(dst, fst, width); |
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} |
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} |
460 |
} |
461 |
|
462 |
vmsvga_update_rect_delayed(s, x, y, w, h); |
463 |
} |
464 |
#endif
|
465 |
|
466 |
struct vmsvga_cursor_definition_s {
|
467 |
int width;
|
468 |
int height;
|
469 |
int id;
|
470 |
int bpp;
|
471 |
int hot_x;
|
472 |
int hot_y;
|
473 |
uint32_t mask[1024];
|
474 |
uint32_t image[1024];
|
475 |
}; |
476 |
|
477 |
#define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) |
478 |
#define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) |
479 |
|
480 |
#ifdef HW_MOUSE_ACCEL
|
481 |
static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, |
482 |
struct vmsvga_cursor_definition_s *c)
|
483 |
{ |
484 |
int i;
|
485 |
for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --) |
486 |
c->mask[i] = ~c->mask[i]; |
487 |
|
488 |
if (s->vga.ds->cursor_define)
|
489 |
s->vga.ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y, |
490 |
(uint8_t *) c->image, (uint8_t *) c->mask); |
491 |
} |
492 |
#endif
|
493 |
|
494 |
#define CMD(f) le32_to_cpu(s->cmd->f)
|
495 |
|
496 |
static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s) |
497 |
{ |
498 |
if (!s->config || !s->enable)
|
499 |
return 1; |
500 |
return (s->cmd->next_cmd == s->cmd->stop);
|
501 |
} |
502 |
|
503 |
static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s) |
504 |
{ |
505 |
uint32_t cmd = s->fifo[CMD(stop) >> 2];
|
506 |
s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
|
507 |
if (CMD(stop) >= CMD(max))
|
508 |
s->cmd->stop = s->cmd->min; |
509 |
return cmd;
|
510 |
} |
511 |
|
512 |
static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s) |
513 |
{ |
514 |
return le32_to_cpu(vmsvga_fifo_read_raw(s));
|
515 |
} |
516 |
|
517 |
static void vmsvga_fifo_run(struct vmsvga_state_s *s) |
518 |
{ |
519 |
uint32_t cmd, colour; |
520 |
int args = 0; |
521 |
int x, y, dx, dy, width, height;
|
522 |
struct vmsvga_cursor_definition_s cursor;
|
523 |
while (!vmsvga_fifo_empty(s))
|
524 |
switch (cmd = vmsvga_fifo_read(s)) {
|
525 |
case SVGA_CMD_UPDATE:
|
526 |
case SVGA_CMD_UPDATE_VERBOSE:
|
527 |
x = vmsvga_fifo_read(s); |
528 |
y = vmsvga_fifo_read(s); |
529 |
width = vmsvga_fifo_read(s); |
530 |
height = vmsvga_fifo_read(s); |
531 |
vmsvga_update_rect_delayed(s, x, y, width, height); |
532 |
break;
|
533 |
|
534 |
case SVGA_CMD_RECT_FILL:
|
535 |
colour = vmsvga_fifo_read(s); |
536 |
x = vmsvga_fifo_read(s); |
537 |
y = vmsvga_fifo_read(s); |
538 |
width = vmsvga_fifo_read(s); |
539 |
height = vmsvga_fifo_read(s); |
540 |
#ifdef HW_FILL_ACCEL
|
541 |
vmsvga_fill_rect(s, colour, x, y, width, height); |
542 |
break;
|
543 |
#else
|
544 |
goto badcmd;
|
545 |
#endif
|
546 |
|
547 |
case SVGA_CMD_RECT_COPY:
|
548 |
x = vmsvga_fifo_read(s); |
549 |
y = vmsvga_fifo_read(s); |
550 |
dx = vmsvga_fifo_read(s); |
551 |
dy = vmsvga_fifo_read(s); |
552 |
width = vmsvga_fifo_read(s); |
553 |
height = vmsvga_fifo_read(s); |
554 |
#ifdef HW_RECT_ACCEL
|
555 |
vmsvga_copy_rect(s, x, y, dx, dy, width, height); |
556 |
break;
|
557 |
#else
|
558 |
goto badcmd;
|
559 |
#endif
|
560 |
|
561 |
case SVGA_CMD_DEFINE_CURSOR:
|
562 |
cursor.id = vmsvga_fifo_read(s); |
563 |
cursor.hot_x = vmsvga_fifo_read(s); |
564 |
cursor.hot_y = vmsvga_fifo_read(s); |
565 |
cursor.width = x = vmsvga_fifo_read(s); |
566 |
cursor.height = y = vmsvga_fifo_read(s); |
567 |
vmsvga_fifo_read(s); |
568 |
cursor.bpp = vmsvga_fifo_read(s); |
569 |
for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++) |
570 |
cursor.mask[args] = vmsvga_fifo_read_raw(s); |
571 |
for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++) |
572 |
cursor.image[args] = vmsvga_fifo_read_raw(s); |
573 |
#ifdef HW_MOUSE_ACCEL
|
574 |
vmsvga_cursor_define(s, &cursor); |
575 |
break;
|
576 |
#else
|
577 |
args = 0;
|
578 |
goto badcmd;
|
579 |
#endif
|
580 |
|
581 |
/*
|
582 |
* Other commands that we at least know the number of arguments
|
583 |
* for so we can avoid FIFO desync if driver uses them illegally.
|
584 |
*/
|
585 |
case SVGA_CMD_DEFINE_ALPHA_CURSOR:
|
586 |
vmsvga_fifo_read(s); |
587 |
vmsvga_fifo_read(s); |
588 |
vmsvga_fifo_read(s); |
589 |
x = vmsvga_fifo_read(s); |
590 |
y = vmsvga_fifo_read(s); |
591 |
args = x * y; |
592 |
goto badcmd;
|
593 |
case SVGA_CMD_RECT_ROP_FILL:
|
594 |
args = 6;
|
595 |
goto badcmd;
|
596 |
case SVGA_CMD_RECT_ROP_COPY:
|
597 |
args = 7;
|
598 |
goto badcmd;
|
599 |
case SVGA_CMD_DRAW_GLYPH_CLIPPED:
|
600 |
vmsvga_fifo_read(s); |
601 |
vmsvga_fifo_read(s); |
602 |
args = 7 + (vmsvga_fifo_read(s) >> 2); |
603 |
goto badcmd;
|
604 |
case SVGA_CMD_SURFACE_ALPHA_BLEND:
|
605 |
args = 12;
|
606 |
goto badcmd;
|
607 |
|
608 |
/*
|
609 |
* Other commands that are not listed as depending on any
|
610 |
* CAPABILITIES bits, but are not described in the README either.
|
611 |
*/
|
612 |
case SVGA_CMD_SURFACE_FILL:
|
613 |
case SVGA_CMD_SURFACE_COPY:
|
614 |
case SVGA_CMD_FRONT_ROP_FILL:
|
615 |
case SVGA_CMD_FENCE:
|
616 |
case SVGA_CMD_INVALID_CMD:
|
617 |
break; /* Nop */ |
618 |
|
619 |
default:
|
620 |
badcmd:
|
621 |
while (args --)
|
622 |
vmsvga_fifo_read(s); |
623 |
printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
|
624 |
__FUNCTION__, cmd); |
625 |
break;
|
626 |
} |
627 |
|
628 |
s->syncing = 0;
|
629 |
} |
630 |
|
631 |
static uint32_t vmsvga_index_read(void *opaque, uint32_t address) |
632 |
{ |
633 |
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
634 |
return s->index;
|
635 |
} |
636 |
|
637 |
static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index) |
638 |
{ |
639 |
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
640 |
s->index = index; |
641 |
} |
642 |
|
643 |
static uint32_t vmsvga_value_read(void *opaque, uint32_t address) |
644 |
{ |
645 |
uint32_t caps; |
646 |
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
647 |
switch (s->index) {
|
648 |
case SVGA_REG_ID:
|
649 |
return s->svgaid;
|
650 |
|
651 |
case SVGA_REG_ENABLE:
|
652 |
return s->enable;
|
653 |
|
654 |
case SVGA_REG_WIDTH:
|
655 |
return s->width;
|
656 |
|
657 |
case SVGA_REG_HEIGHT:
|
658 |
return s->height;
|
659 |
|
660 |
case SVGA_REG_MAX_WIDTH:
|
661 |
return SVGA_MAX_WIDTH;
|
662 |
|
663 |
case SVGA_REG_MAX_HEIGHT:
|
664 |
return SVGA_MAX_HEIGHT;
|
665 |
|
666 |
case SVGA_REG_DEPTH:
|
667 |
return s->depth;
|
668 |
|
669 |
case SVGA_REG_BITS_PER_PIXEL:
|
670 |
return (s->depth + 7) & ~7; |
671 |
|
672 |
case SVGA_REG_PSEUDOCOLOR:
|
673 |
return 0x0; |
674 |
|
675 |
case SVGA_REG_RED_MASK:
|
676 |
return s->wred;
|
677 |
case SVGA_REG_GREEN_MASK:
|
678 |
return s->wgreen;
|
679 |
case SVGA_REG_BLUE_MASK:
|
680 |
return s->wblue;
|
681 |
|
682 |
case SVGA_REG_BYTES_PER_LINE:
|
683 |
return ((s->depth + 7) >> 3) * s->new_width; |
684 |
|
685 |
case SVGA_REG_FB_START:
|
686 |
return s->vram_base;
|
687 |
|
688 |
case SVGA_REG_FB_OFFSET:
|
689 |
return 0x0; |
690 |
|
691 |
case SVGA_REG_VRAM_SIZE:
|
692 |
return s->vga.vram_size - SVGA_FIFO_SIZE;
|
693 |
|
694 |
case SVGA_REG_FB_SIZE:
|
695 |
return s->fb_size;
|
696 |
|
697 |
case SVGA_REG_CAPABILITIES:
|
698 |
caps = SVGA_CAP_NONE; |
699 |
#ifdef HW_RECT_ACCEL
|
700 |
caps |= SVGA_CAP_RECT_COPY; |
701 |
#endif
|
702 |
#ifdef HW_FILL_ACCEL
|
703 |
caps |= SVGA_CAP_RECT_FILL; |
704 |
#endif
|
705 |
#ifdef HW_MOUSE_ACCEL
|
706 |
if (s->vga.ds->mouse_set)
|
707 |
caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | |
708 |
SVGA_CAP_CURSOR_BYPASS; |
709 |
#endif
|
710 |
return caps;
|
711 |
|
712 |
case SVGA_REG_MEM_START:
|
713 |
return s->vram_base + s->vga.vram_size - SVGA_FIFO_SIZE;
|
714 |
|
715 |
case SVGA_REG_MEM_SIZE:
|
716 |
return SVGA_FIFO_SIZE;
|
717 |
|
718 |
case SVGA_REG_CONFIG_DONE:
|
719 |
return s->config;
|
720 |
|
721 |
case SVGA_REG_SYNC:
|
722 |
case SVGA_REG_BUSY:
|
723 |
return s->syncing;
|
724 |
|
725 |
case SVGA_REG_GUEST_ID:
|
726 |
return s->guest;
|
727 |
|
728 |
case SVGA_REG_CURSOR_ID:
|
729 |
return s->cursor.id;
|
730 |
|
731 |
case SVGA_REG_CURSOR_X:
|
732 |
return s->cursor.x;
|
733 |
|
734 |
case SVGA_REG_CURSOR_Y:
|
735 |
return s->cursor.x;
|
736 |
|
737 |
case SVGA_REG_CURSOR_ON:
|
738 |
return s->cursor.on;
|
739 |
|
740 |
case SVGA_REG_HOST_BITS_PER_PIXEL:
|
741 |
return (s->depth + 7) & ~7; |
742 |
|
743 |
case SVGA_REG_SCRATCH_SIZE:
|
744 |
return s->scratch_size;
|
745 |
|
746 |
case SVGA_REG_MEM_REGS:
|
747 |
case SVGA_REG_NUM_DISPLAYS:
|
748 |
case SVGA_REG_PITCHLOCK:
|
749 |
case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
|
750 |
return 0; |
751 |
|
752 |
default:
|
753 |
if (s->index >= SVGA_SCRATCH_BASE &&
|
754 |
s->index < SVGA_SCRATCH_BASE + s->scratch_size) |
755 |
return s->scratch[s->index - SVGA_SCRATCH_BASE];
|
756 |
printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
|
757 |
} |
758 |
|
759 |
return 0; |
760 |
} |
761 |
|
762 |
static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) |
763 |
{ |
764 |
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
765 |
switch (s->index) {
|
766 |
case SVGA_REG_ID:
|
767 |
if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
|
768 |
s->svgaid = value; |
769 |
break;
|
770 |
|
771 |
case SVGA_REG_ENABLE:
|
772 |
s->enable = value; |
773 |
s->config &= !!value; |
774 |
s->width = -1;
|
775 |
s->height = -1;
|
776 |
s->invalidated = 1;
|
777 |
#ifdef EMBED_STDVGA
|
778 |
s->vga.invalidate(&s->vga); |
779 |
#endif
|
780 |
if (s->enable)
|
781 |
s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height; |
782 |
break;
|
783 |
|
784 |
case SVGA_REG_WIDTH:
|
785 |
s->new_width = value; |
786 |
s->invalidated = 1;
|
787 |
break;
|
788 |
|
789 |
case SVGA_REG_HEIGHT:
|
790 |
s->new_height = value; |
791 |
s->invalidated = 1;
|
792 |
break;
|
793 |
|
794 |
case SVGA_REG_DEPTH:
|
795 |
case SVGA_REG_BITS_PER_PIXEL:
|
796 |
if (value != s->depth) {
|
797 |
printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
|
798 |
s->config = 0;
|
799 |
} |
800 |
break;
|
801 |
|
802 |
case SVGA_REG_CONFIG_DONE:
|
803 |
if (value) {
|
804 |
s->fifo = (uint32_t *) &s->vga.vram_ptr[s->vga.vram_size - SVGA_FIFO_SIZE]; |
805 |
/* Check range and alignment. */
|
806 |
if ((CMD(min) | CMD(max) |
|
807 |
CMD(next_cmd) | CMD(stop)) & 3)
|
808 |
break;
|
809 |
if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
|
810 |
break;
|
811 |
if (CMD(max) > SVGA_FIFO_SIZE)
|
812 |
break;
|
813 |
if (CMD(max) < CMD(min) + 10 * 1024) |
814 |
break;
|
815 |
} |
816 |
s->config = !!value; |
817 |
break;
|
818 |
|
819 |
case SVGA_REG_SYNC:
|
820 |
s->syncing = 1;
|
821 |
vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
|
822 |
break;
|
823 |
|
824 |
case SVGA_REG_GUEST_ID:
|
825 |
s->guest = value; |
826 |
#ifdef VERBOSE
|
827 |
if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
|
828 |
ARRAY_SIZE(vmsvga_guest_id)) |
829 |
printf("%s: guest runs %s.\n", __FUNCTION__,
|
830 |
vmsvga_guest_id[value - GUEST_OS_BASE]); |
831 |
#endif
|
832 |
break;
|
833 |
|
834 |
case SVGA_REG_CURSOR_ID:
|
835 |
s->cursor.id = value; |
836 |
break;
|
837 |
|
838 |
case SVGA_REG_CURSOR_X:
|
839 |
s->cursor.x = value; |
840 |
break;
|
841 |
|
842 |
case SVGA_REG_CURSOR_Y:
|
843 |
s->cursor.y = value; |
844 |
break;
|
845 |
|
846 |
case SVGA_REG_CURSOR_ON:
|
847 |
s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); |
848 |
s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); |
849 |
#ifdef HW_MOUSE_ACCEL
|
850 |
if (s->vga.ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
|
851 |
s->vga.ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on); |
852 |
#endif
|
853 |
break;
|
854 |
|
855 |
case SVGA_REG_MEM_REGS:
|
856 |
case SVGA_REG_NUM_DISPLAYS:
|
857 |
case SVGA_REG_PITCHLOCK:
|
858 |
case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
|
859 |
break;
|
860 |
|
861 |
default:
|
862 |
if (s->index >= SVGA_SCRATCH_BASE &&
|
863 |
s->index < SVGA_SCRATCH_BASE + s->scratch_size) { |
864 |
s->scratch[s->index - SVGA_SCRATCH_BASE] = value; |
865 |
break;
|
866 |
} |
867 |
printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
|
868 |
} |
869 |
} |
870 |
|
871 |
static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) |
872 |
{ |
873 |
printf("%s: what are we supposed to return?\n", __FUNCTION__);
|
874 |
return 0xcafe; |
875 |
} |
876 |
|
877 |
static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) |
878 |
{ |
879 |
printf("%s: what are we supposed to do with (%08x)?\n",
|
880 |
__FUNCTION__, data); |
881 |
} |
882 |
|
883 |
static inline void vmsvga_size(struct vmsvga_state_s *s) |
884 |
{ |
885 |
if (s->new_width != s->width || s->new_height != s->height) {
|
886 |
s->width = s->new_width; |
887 |
s->height = s->new_height; |
888 |
qemu_console_resize(s->vga.ds, s->width, s->height); |
889 |
s->invalidated = 1;
|
890 |
} |
891 |
} |
892 |
|
893 |
static void vmsvga_update_display(void *opaque) |
894 |
{ |
895 |
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
896 |
if (!s->enable) {
|
897 |
#ifdef EMBED_STDVGA
|
898 |
s->vga.update(&s->vga); |
899 |
#endif
|
900 |
return;
|
901 |
} |
902 |
|
903 |
vmsvga_size(s); |
904 |
|
905 |
vmsvga_fifo_run(s); |
906 |
vmsvga_update_rect_flush(s); |
907 |
|
908 |
/*
|
909 |
* Is it more efficient to look at vram VGA-dirty bits or wait
|
910 |
* for the driver to issue SVGA_CMD_UPDATE?
|
911 |
*/
|
912 |
if (s->invalidated) {
|
913 |
s->invalidated = 0;
|
914 |
vmsvga_update_screen(s); |
915 |
} |
916 |
} |
917 |
|
918 |
static void vmsvga_reset(struct vmsvga_state_s *s) |
919 |
{ |
920 |
s->index = 0;
|
921 |
s->enable = 0;
|
922 |
s->config = 0;
|
923 |
s->width = -1;
|
924 |
s->height = -1;
|
925 |
s->svgaid = SVGA_ID; |
926 |
s->depth = 24;
|
927 |
s->bypp = (s->depth + 7) >> 3; |
928 |
s->cursor.on = 0;
|
929 |
s->redraw_fifo_first = 0;
|
930 |
s->redraw_fifo_last = 0;
|
931 |
switch (s->depth) {
|
932 |
case 8: |
933 |
s->wred = 0x00000007;
|
934 |
s->wgreen = 0x00000038;
|
935 |
s->wblue = 0x000000c0;
|
936 |
break;
|
937 |
case 15: |
938 |
s->wred = 0x0000001f;
|
939 |
s->wgreen = 0x000003e0;
|
940 |
s->wblue = 0x00007c00;
|
941 |
break;
|
942 |
case 16: |
943 |
s->wred = 0x0000001f;
|
944 |
s->wgreen = 0x000007e0;
|
945 |
s->wblue = 0x0000f800;
|
946 |
break;
|
947 |
case 24: |
948 |
s->wred = 0x00ff0000;
|
949 |
s->wgreen = 0x0000ff00;
|
950 |
s->wblue = 0x000000ff;
|
951 |
break;
|
952 |
case 32: |
953 |
s->wred = 0x00ff0000;
|
954 |
s->wgreen = 0x0000ff00;
|
955 |
s->wblue = 0x000000ff;
|
956 |
break;
|
957 |
} |
958 |
s->syncing = 0;
|
959 |
} |
960 |
|
961 |
static void vmsvga_invalidate_display(void *opaque) |
962 |
{ |
963 |
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
964 |
if (!s->enable) {
|
965 |
#ifdef EMBED_STDVGA
|
966 |
s->vga.invalidate(&s->vga); |
967 |
#endif
|
968 |
return;
|
969 |
} |
970 |
|
971 |
s->invalidated = 1;
|
972 |
} |
973 |
|
974 |
/* save the vga display in a PPM image even if no display is
|
975 |
available */
|
976 |
static void vmsvga_screen_dump(void *opaque, const char *filename) |
977 |
{ |
978 |
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
979 |
if (!s->enable) {
|
980 |
#ifdef EMBED_STDVGA
|
981 |
s->vga.screen_dump(&s->vga, filename); |
982 |
#endif
|
983 |
return;
|
984 |
} |
985 |
|
986 |
if (s->depth == 32) { |
987 |
DisplaySurface *ds = qemu_create_displaysurface_from(s->width, |
988 |
s->height, 32, ds_get_linesize(s->vga.ds), s->vga.vram_ptr);
|
989 |
ppm_save(filename, ds); |
990 |
qemu_free(ds); |
991 |
} |
992 |
} |
993 |
|
994 |
static void vmsvga_text_update(void *opaque, console_ch_t *chardata) |
995 |
{ |
996 |
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
997 |
|
998 |
if (s->vga.text_update)
|
999 |
s->vga.text_update(&s->vga, chardata); |
1000 |
} |
1001 |
|
1002 |
#ifdef DIRECT_VRAM
|
1003 |
static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr) |
1004 |
{ |
1005 |
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
1006 |
if (addr < s->fb_size)
|
1007 |
return *(uint8_t *) (ds_get_data(s->ds) + addr);
|
1008 |
else
|
1009 |
return *(uint8_t *) (s->vram_ptr + addr);
|
1010 |
} |
1011 |
|
1012 |
static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr) |
1013 |
{ |
1014 |
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
1015 |
if (addr < s->fb_size)
|
1016 |
return *(uint16_t *) (ds_get_data(s->ds) + addr);
|
1017 |
else
|
1018 |
return *(uint16_t *) (s->vram_ptr + addr);
|
1019 |
} |
1020 |
|
1021 |
static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr) |
1022 |
{ |
1023 |
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
1024 |
if (addr < s->fb_size)
|
1025 |
return *(uint32_t *) (ds_get_data(s->ds) + addr);
|
1026 |
else
|
1027 |
return *(uint32_t *) (s->vram_ptr + addr);
|
1028 |
} |
1029 |
|
1030 |
static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr, |
1031 |
uint32_t value) |
1032 |
{ |
1033 |
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
1034 |
if (addr < s->fb_size)
|
1035 |
*(uint8_t *) (ds_get_data(s->ds) + addr) = value; |
1036 |
else
|
1037 |
*(uint8_t *) (s->vram_ptr + addr) = value; |
1038 |
} |
1039 |
|
1040 |
static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr, |
1041 |
uint32_t value) |
1042 |
{ |
1043 |
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
1044 |
if (addr < s->fb_size)
|
1045 |
*(uint16_t *) (ds_get_data(s->ds) + addr) = value; |
1046 |
else
|
1047 |
*(uint16_t *) (s->vram_ptr + addr) = value; |
1048 |
} |
1049 |
|
1050 |
static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr, |
1051 |
uint32_t value) |
1052 |
{ |
1053 |
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
1054 |
if (addr < s->fb_size)
|
1055 |
*(uint32_t *) (ds_get_data(s->ds) + addr) = value; |
1056 |
else
|
1057 |
*(uint32_t *) (s->vram_ptr + addr) = value; |
1058 |
} |
1059 |
|
1060 |
static CPUReadMemoryFunc *vmsvga_vram_read[] = {
|
1061 |
vmsvga_vram_readb, |
1062 |
vmsvga_vram_readw, |
1063 |
vmsvga_vram_readl, |
1064 |
}; |
1065 |
|
1066 |
static CPUWriteMemoryFunc *vmsvga_vram_write[] = {
|
1067 |
vmsvga_vram_writeb, |
1068 |
vmsvga_vram_writew, |
1069 |
vmsvga_vram_writel, |
1070 |
}; |
1071 |
#endif
|
1072 |
|
1073 |
static void vmsvga_save(struct vmsvga_state_s *s, QEMUFile *f) |
1074 |
{ |
1075 |
qemu_put_be32(f, s->depth); |
1076 |
qemu_put_be32(f, s->enable); |
1077 |
qemu_put_be32(f, s->config); |
1078 |
qemu_put_be32(f, s->cursor.id); |
1079 |
qemu_put_be32(f, s->cursor.x); |
1080 |
qemu_put_be32(f, s->cursor.y); |
1081 |
qemu_put_be32(f, s->cursor.on); |
1082 |
qemu_put_be32(f, s->index); |
1083 |
qemu_put_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
|
1084 |
qemu_put_be32(f, s->new_width); |
1085 |
qemu_put_be32(f, s->new_height); |
1086 |
qemu_put_be32s(f, &s->guest); |
1087 |
qemu_put_be32s(f, &s->svgaid); |
1088 |
qemu_put_be32(f, s->syncing); |
1089 |
qemu_put_be32(f, s->fb_size); |
1090 |
} |
1091 |
|
1092 |
static int vmsvga_load(struct vmsvga_state_s *s, QEMUFile *f) |
1093 |
{ |
1094 |
int depth;
|
1095 |
depth=qemu_get_be32(f); |
1096 |
s->enable=qemu_get_be32(f); |
1097 |
s->config=qemu_get_be32(f); |
1098 |
s->cursor.id=qemu_get_be32(f); |
1099 |
s->cursor.x=qemu_get_be32(f); |
1100 |
s->cursor.y=qemu_get_be32(f); |
1101 |
s->cursor.on=qemu_get_be32(f); |
1102 |
s->index=qemu_get_be32(f); |
1103 |
qemu_get_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
|
1104 |
s->new_width=qemu_get_be32(f); |
1105 |
s->new_height=qemu_get_be32(f); |
1106 |
qemu_get_be32s(f, &s->guest); |
1107 |
qemu_get_be32s(f, &s->svgaid); |
1108 |
s->syncing=qemu_get_be32(f); |
1109 |
s->fb_size=qemu_get_be32(f); |
1110 |
|
1111 |
if (s->enable && depth != s->depth) {
|
1112 |
printf("%s: need colour depth of %i bits to resume operation.\n",
|
1113 |
__FUNCTION__, depth); |
1114 |
return -EINVAL;
|
1115 |
} |
1116 |
|
1117 |
s->invalidated = 1;
|
1118 |
if (s->config)
|
1119 |
s->fifo = (uint32_t *) &s->vga.vram_ptr[s->vga.vram_size - SVGA_FIFO_SIZE]; |
1120 |
|
1121 |
return 0; |
1122 |
} |
1123 |
|
1124 |
static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size) |
1125 |
{ |
1126 |
s->scratch_size = SVGA_SCRATCH_SIZE; |
1127 |
s->scratch = (uint32_t *) qemu_malloc(s->scratch_size * 4);
|
1128 |
|
1129 |
vmsvga_reset(s); |
1130 |
|
1131 |
#ifdef EMBED_STDVGA
|
1132 |
vga_common_init((VGAState *) s, vga_ram_size); |
1133 |
vga_init((VGAState *) s); |
1134 |
#else
|
1135 |
s->vram_size = vga_ram_size; |
1136 |
s->vram_offset = qemu_ram_alloc(vga_ram_size); |
1137 |
s->vram_ptr = qemu_get_ram_ptr(s->vram_offset); |
1138 |
#endif
|
1139 |
|
1140 |
s->vga.ds = graphic_console_init(vmsvga_update_display, |
1141 |
vmsvga_invalidate_display, |
1142 |
vmsvga_screen_dump, |
1143 |
vmsvga_text_update, &s->vga); |
1144 |
|
1145 |
#ifdef CONFIG_BOCHS_VBE
|
1146 |
/* XXX: use optimized standard vga accesses */
|
1147 |
cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS, |
1148 |
vga_ram_size, s->vga.vram_offset); |
1149 |
#endif
|
1150 |
} |
1151 |
|
1152 |
static void pci_vmsvga_save(QEMUFile *f, void *opaque) |
1153 |
{ |
1154 |
struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque; |
1155 |
pci_device_save(&s->card, f); |
1156 |
vmsvga_save(&s->chip, f); |
1157 |
} |
1158 |
|
1159 |
static int pci_vmsvga_load(QEMUFile *f, void *opaque, int version_id) |
1160 |
{ |
1161 |
struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque; |
1162 |
int ret;
|
1163 |
|
1164 |
ret = pci_device_load(&s->card, f); |
1165 |
if (ret < 0) |
1166 |
return ret;
|
1167 |
|
1168 |
ret = vmsvga_load(&s->chip, f); |
1169 |
if (ret < 0) |
1170 |
return ret;
|
1171 |
|
1172 |
return 0; |
1173 |
} |
1174 |
|
1175 |
static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num, |
1176 |
uint32_t addr, uint32_t size, int type)
|
1177 |
{ |
1178 |
struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev; |
1179 |
struct vmsvga_state_s *s = &d->chip;
|
1180 |
|
1181 |
register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT, |
1182 |
1, 4, vmsvga_index_read, s); |
1183 |
register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT, |
1184 |
1, 4, vmsvga_index_write, s); |
1185 |
register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT, |
1186 |
1, 4, vmsvga_value_read, s); |
1187 |
register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT, |
1188 |
1, 4, vmsvga_value_write, s); |
1189 |
register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT, |
1190 |
1, 4, vmsvga_bios_read, s); |
1191 |
register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT, |
1192 |
1, 4, vmsvga_bios_write, s); |
1193 |
} |
1194 |
|
1195 |
static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num, |
1196 |
uint32_t addr, uint32_t size, int type)
|
1197 |
{ |
1198 |
struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev; |
1199 |
struct vmsvga_state_s *s = &d->chip;
|
1200 |
ram_addr_t iomemtype; |
1201 |
|
1202 |
s->vram_base = addr; |
1203 |
#ifdef DIRECT_VRAM
|
1204 |
iomemtype = cpu_register_io_memory(vmsvga_vram_read, |
1205 |
vmsvga_vram_write, s); |
1206 |
#else
|
1207 |
iomemtype = s->vga.vram_offset | IO_MEM_RAM; |
1208 |
#endif
|
1209 |
cpu_register_physical_memory(s->vram_base, s->vga.vram_size, |
1210 |
iomemtype); |
1211 |
} |
1212 |
|
1213 |
static void pci_vmsvga_initfn(PCIDevice *dev) |
1214 |
{ |
1215 |
struct pci_vmsvga_state_s *s =
|
1216 |
DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
|
1217 |
|
1218 |
pci_config_set_vendor_id(s->card.config, PCI_VENDOR_ID_VMWARE); |
1219 |
pci_config_set_device_id(s->card.config, SVGA_PCI_DEVICE_ID); |
1220 |
s->card.config[PCI_COMMAND] = 0x07; /* I/O + Memory */ |
1221 |
pci_config_set_class(s->card.config, PCI_CLASS_DISPLAY_VGA); |
1222 |
s->card.config[0x0c] = 0x08; /* Cache line size */ |
1223 |
s->card.config[0x0d] = 0x40; /* Latency timer */ |
1224 |
s->card.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; |
1225 |
s->card.config[0x2c] = PCI_VENDOR_ID_VMWARE & 0xff; |
1226 |
s->card.config[0x2d] = PCI_VENDOR_ID_VMWARE >> 8; |
1227 |
s->card.config[0x2e] = SVGA_PCI_DEVICE_ID & 0xff; |
1228 |
s->card.config[0x2f] = SVGA_PCI_DEVICE_ID >> 8; |
1229 |
s->card.config[0x3c] = 0xff; /* End */ |
1230 |
|
1231 |
pci_register_bar(&s->card, 0, 0x10, |
1232 |
PCI_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport); |
1233 |
pci_register_bar(&s->card, 1, VGA_RAM_SIZE,
|
1234 |
PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_vmsvga_map_mem); |
1235 |
|
1236 |
vmsvga_init(&s->chip, VGA_RAM_SIZE); |
1237 |
|
1238 |
register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s); |
1239 |
} |
1240 |
|
1241 |
void pci_vmsvga_init(PCIBus *bus)
|
1242 |
{ |
1243 |
pci_create_simple(bus, -1, "QEMUware SVGA"); |
1244 |
} |
1245 |
|
1246 |
static PCIDeviceInfo vmsvga_info = {
|
1247 |
.qdev.name = "QEMUware SVGA",
|
1248 |
.qdev.size = sizeof(struct pci_vmsvga_state_s), |
1249 |
.init = pci_vmsvga_initfn, |
1250 |
}; |
1251 |
|
1252 |
static void vmsvga_register(void) |
1253 |
{ |
1254 |
pci_qdev_register(&vmsvga_info); |
1255 |
} |
1256 |
device_init(vmsvga_register); |