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/*
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* dyngen helpers
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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int __op_param1, __op_param2, __op_param3;
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int __op_gen_label1, __op_gen_label2, __op_gen_label3;
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int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3;
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#ifdef __i386__
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
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} |
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#endif
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#ifdef __x86_64__
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
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} |
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#endif
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#ifdef __s390__
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
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} |
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#endif
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#ifdef __ia64__
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
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} |
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#endif
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#ifdef __powerpc__
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#define MIN_CACHE_LINE_SIZE 8 /* conservative value */ |
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static void inline flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
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unsigned long p; |
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p = start & ~(MIN_CACHE_LINE_SIZE - 1);
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stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1); |
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for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
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asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); |
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} |
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asm volatile ("sync" : : : "memory"); |
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for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
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asm volatile ("icbi 0,%0" : : "r"(p) : "memory"); |
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} |
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asm volatile ("sync" : : : "memory"); |
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asm volatile ("isync" : : : "memory"); |
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} |
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#endif
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#ifdef __alpha__
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
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asm ("imb"); |
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} |
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#endif
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#ifdef __sparc__
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static void inline flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
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unsigned long p; |
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p = start & ~(8UL - 1UL); |
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stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL); |
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for (; p < stop; p += 8) |
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__asm__ __volatile__("flush\t%0" : : "r" (p)); |
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} |
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#endif
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#ifdef __arm__
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
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register unsigned long _beg __asm ("a1") = start; |
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register unsigned long _end __asm ("a2") = stop; |
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register unsigned long _flg __asm ("a3") = 0; |
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__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); |
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} |
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#endif
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#ifdef __mc68000
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#include <asm/cachectl.h> |
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
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cacheflush(start,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,stop-start+16);
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} |
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#endif
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#ifdef __alpha__
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register int gp asm("$29"); |
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static inline void immediate_ldah(void *p, int val) { |
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uint32_t *dest = p; |
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long high = ((val >> 16) + ((val >> 15) & 1)) & 0xffff; |
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*dest &= ~0xffff;
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*dest |= high; |
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*dest |= 31 << 16; |
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} |
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static inline void immediate_lda(void *dest, int val) { |
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*(uint16_t *) dest = val; |
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} |
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void fix_bsr(void *p, int offset) { |
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uint32_t *dest = p; |
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*dest &= ~((1 << 21) - 1); |
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*dest |= (offset >> 2) & ((1 << 21) - 1); |
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} |
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#endif /* __alpha__ */ |
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#ifdef __arm__
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#define MAX_OP_SIZE (128 * 4) /* in bytes */ |
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/* max size of the code that can be generated without calling arm_flush_ldr */
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#define MAX_FRAG_SIZE (1024 * 4) |
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//#define MAX_FRAG_SIZE (135 * 4) /* for testing */
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typedef struct LDREntry { |
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uint8_t *ptr; |
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uint32_t *data_ptr; |
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} LDREntry; |
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static LDREntry arm_ldr_table[1024]; |
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static uint32_t arm_data_table[1024]; |
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extern char exec_loop; |
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static inline void arm_reloc_pc24(uint32_t *ptr, uint32_t insn, int val) |
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{ |
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*ptr = (insn & ~0xffffff) | ((insn + ((val - (int)ptr) >> 2)) & 0xffffff); |
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} |
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static uint8_t *arm_flush_ldr(uint8_t *gen_code_ptr,
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LDREntry *ldr_start, LDREntry *ldr_end, |
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uint32_t *data_start, uint32_t *data_end, |
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int gen_jmp)
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{ |
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LDREntry *le; |
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uint32_t *ptr; |
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int offset, data_size, target;
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uint8_t *data_ptr; |
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uint32_t insn; |
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data_size = (uint8_t *)data_end - (uint8_t *)data_start; |
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if (gen_jmp) {
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/* generate branch to skip the data */
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if (data_size == 0) |
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return gen_code_ptr;
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target = (long)gen_code_ptr + data_size + 4; |
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arm_reloc_pc24((uint32_t *)gen_code_ptr, 0xeafffffe, target);
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gen_code_ptr += 4;
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} |
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/* copy the data */
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data_ptr = gen_code_ptr; |
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memcpy(gen_code_ptr, data_start, data_size); |
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gen_code_ptr += data_size; |
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/* patch the ldr to point to the data */
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for(le = ldr_start; le < ldr_end; le++) {
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ptr = (uint32_t *)le->ptr; |
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offset = ((unsigned long)(le->data_ptr) - (unsigned long)data_start) + |
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(unsigned long)data_ptr - |
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(unsigned long)ptr - 8; |
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insn = *ptr & ~(0xfff | 0x00800000); |
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if (offset < 0) { |
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offset = - offset; |
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} else {
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insn |= 0x00800000;
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} |
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if (offset > 0xfff) { |
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fprintf(stderr, "Error ldr offset\n");
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abort(); |
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} |
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insn |= offset; |
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*ptr = insn; |
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} |
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return gen_code_ptr;
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} |
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#endif /* __arm__ */ |