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1 | 7d13299d | bellard | /*
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2 | 7d13299d | bellard | * i386 emulator main execution loop
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3 | 7d13299d | bellard | *
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4 | 7d13299d | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 7d13299d | bellard | *
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6 | 3ef693a0 | bellard | * This library is free software; you can redistribute it and/or
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7 | 3ef693a0 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 3ef693a0 | bellard | * License as published by the Free Software Foundation; either
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9 | 3ef693a0 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 7d13299d | bellard | *
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11 | 3ef693a0 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 3ef693a0 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 3ef693a0 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 3ef693a0 | bellard | * Lesser General Public License for more details.
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15 | 7d13299d | bellard | *
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16 | 3ef693a0 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 3ef693a0 | bellard | * License along with this library; if not, write to the Free Software
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18 | 3ef693a0 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 7d13299d | bellard | */
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20 | e4533c7a | bellard | #include "config.h" |
21 | 93ac68bc | bellard | #include "exec.h" |
22 | 956034d7 | bellard | #include "disas.h" |
23 | 7d13299d | bellard | |
24 | fbf9eeb3 | bellard | #if !defined(CONFIG_SOFTMMU)
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25 | fbf9eeb3 | bellard | #undef EAX
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26 | fbf9eeb3 | bellard | #undef ECX
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27 | fbf9eeb3 | bellard | #undef EDX
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28 | fbf9eeb3 | bellard | #undef EBX
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29 | fbf9eeb3 | bellard | #undef ESP
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30 | fbf9eeb3 | bellard | #undef EBP
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31 | fbf9eeb3 | bellard | #undef ESI
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32 | fbf9eeb3 | bellard | #undef EDI
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33 | fbf9eeb3 | bellard | #undef EIP
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34 | fbf9eeb3 | bellard | #include <signal.h> |
35 | fbf9eeb3 | bellard | #include <sys/ucontext.h> |
36 | fbf9eeb3 | bellard | #endif
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37 | fbf9eeb3 | bellard | |
38 | 36bdbe54 | bellard | int tb_invalidated_flag;
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39 | 36bdbe54 | bellard | |
40 | dc99065b | bellard | //#define DEBUG_EXEC
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41 | 9de5e440 | bellard | //#define DEBUG_SIGNAL
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42 | 7d13299d | bellard | |
43 | 93ac68bc | bellard | #if defined(TARGET_ARM) || defined(TARGET_SPARC)
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44 | e4533c7a | bellard | /* XXX: unify with i386 target */
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45 | e4533c7a | bellard | void cpu_loop_exit(void) |
46 | e4533c7a | bellard | { |
47 | e4533c7a | bellard | longjmp(env->jmp_env, 1);
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48 | e4533c7a | bellard | } |
49 | e4533c7a | bellard | #endif
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50 | e4533c7a | bellard | |
51 | fbf9eeb3 | bellard | /* exit the current TB from a signal handler. The host registers are
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52 | fbf9eeb3 | bellard | restored in a state compatible with the CPU emulator
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53 | fbf9eeb3 | bellard | */
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54 | fbf9eeb3 | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc) |
55 | fbf9eeb3 | bellard | { |
56 | fbf9eeb3 | bellard | #if !defined(CONFIG_SOFTMMU)
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57 | fbf9eeb3 | bellard | struct ucontext *uc = puc;
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58 | fbf9eeb3 | bellard | #endif
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59 | fbf9eeb3 | bellard | |
60 | fbf9eeb3 | bellard | env = env1; |
61 | fbf9eeb3 | bellard | |
62 | fbf9eeb3 | bellard | /* XXX: restore cpu registers saved in host registers */
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63 | fbf9eeb3 | bellard | |
64 | fbf9eeb3 | bellard | #if !defined(CONFIG_SOFTMMU)
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65 | fbf9eeb3 | bellard | if (puc) {
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66 | fbf9eeb3 | bellard | /* XXX: use siglongjmp ? */
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67 | fbf9eeb3 | bellard | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
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68 | fbf9eeb3 | bellard | } |
69 | fbf9eeb3 | bellard | #endif
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70 | fbf9eeb3 | bellard | longjmp(env->jmp_env, 1);
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71 | fbf9eeb3 | bellard | } |
72 | fbf9eeb3 | bellard | |
73 | 7d13299d | bellard | /* main execution loop */
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74 | 7d13299d | bellard | |
75 | e4533c7a | bellard | int cpu_exec(CPUState *env1)
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76 | 7d13299d | bellard | { |
77 | e4533c7a | bellard | int saved_T0, saved_T1, saved_T2;
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78 | e4533c7a | bellard | CPUState *saved_env; |
79 | 04369ff2 | bellard | #ifdef reg_EAX
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80 | 04369ff2 | bellard | int saved_EAX;
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81 | 04369ff2 | bellard | #endif
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82 | 04369ff2 | bellard | #ifdef reg_ECX
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83 | 04369ff2 | bellard | int saved_ECX;
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84 | 04369ff2 | bellard | #endif
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85 | 04369ff2 | bellard | #ifdef reg_EDX
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86 | 04369ff2 | bellard | int saved_EDX;
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87 | 04369ff2 | bellard | #endif
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88 | 04369ff2 | bellard | #ifdef reg_EBX
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89 | 04369ff2 | bellard | int saved_EBX;
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90 | 04369ff2 | bellard | #endif
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91 | 04369ff2 | bellard | #ifdef reg_ESP
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92 | 04369ff2 | bellard | int saved_ESP;
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93 | 04369ff2 | bellard | #endif
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94 | 04369ff2 | bellard | #ifdef reg_EBP
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95 | 04369ff2 | bellard | int saved_EBP;
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96 | 04369ff2 | bellard | #endif
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97 | 04369ff2 | bellard | #ifdef reg_ESI
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98 | 04369ff2 | bellard | int saved_ESI;
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99 | 04369ff2 | bellard | #endif
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100 | 04369ff2 | bellard | #ifdef reg_EDI
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101 | 04369ff2 | bellard | int saved_EDI;
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102 | 04369ff2 | bellard | #endif
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103 | 8c6939c0 | bellard | #ifdef __sparc__
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104 | 8c6939c0 | bellard | int saved_i7, tmp_T0;
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105 | 8c6939c0 | bellard | #endif
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106 | 68a79315 | bellard | int code_gen_size, ret, interrupt_request;
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107 | 7d13299d | bellard | void (*gen_func)(void); |
108 | 9de5e440 | bellard | TranslationBlock *tb, **ptb; |
109 | c27004ec | bellard | target_ulong cs_base, pc; |
110 | c27004ec | bellard | uint8_t *tc_ptr; |
111 | 6dbad63e | bellard | unsigned int flags; |
112 | 8c6939c0 | bellard | |
113 | 7d13299d | bellard | /* first we save global registers */
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114 | c27004ec | bellard | saved_env = env; |
115 | c27004ec | bellard | env = env1; |
116 | 7d13299d | bellard | saved_T0 = T0; |
117 | 7d13299d | bellard | saved_T1 = T1; |
118 | e4533c7a | bellard | saved_T2 = T2; |
119 | e4533c7a | bellard | #ifdef __sparc__
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120 | e4533c7a | bellard | /* we also save i7 because longjmp may not restore it */
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121 | e4533c7a | bellard | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); |
122 | e4533c7a | bellard | #endif
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123 | e4533c7a | bellard | |
124 | e4533c7a | bellard | #if defined(TARGET_I386)
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125 | 04369ff2 | bellard | #ifdef reg_EAX
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126 | 04369ff2 | bellard | saved_EAX = EAX; |
127 | 04369ff2 | bellard | #endif
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128 | 04369ff2 | bellard | #ifdef reg_ECX
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129 | 04369ff2 | bellard | saved_ECX = ECX; |
130 | 04369ff2 | bellard | #endif
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131 | 04369ff2 | bellard | #ifdef reg_EDX
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132 | 04369ff2 | bellard | saved_EDX = EDX; |
133 | 04369ff2 | bellard | #endif
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134 | 04369ff2 | bellard | #ifdef reg_EBX
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135 | 04369ff2 | bellard | saved_EBX = EBX; |
136 | 04369ff2 | bellard | #endif
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137 | 04369ff2 | bellard | #ifdef reg_ESP
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138 | 04369ff2 | bellard | saved_ESP = ESP; |
139 | 04369ff2 | bellard | #endif
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140 | 04369ff2 | bellard | #ifdef reg_EBP
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141 | 04369ff2 | bellard | saved_EBP = EBP; |
142 | 04369ff2 | bellard | #endif
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143 | 04369ff2 | bellard | #ifdef reg_ESI
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144 | 04369ff2 | bellard | saved_ESI = ESI; |
145 | 04369ff2 | bellard | #endif
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146 | 04369ff2 | bellard | #ifdef reg_EDI
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147 | 04369ff2 | bellard | saved_EDI = EDI; |
148 | 04369ff2 | bellard | #endif
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149 | 0d1a29f9 | bellard | |
150 | 0d1a29f9 | bellard | env_to_regs(); |
151 | 9de5e440 | bellard | /* put eflags in CPU temporary format */
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152 | fc2b4c48 | bellard | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
153 | fc2b4c48 | bellard | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
154 | 9de5e440 | bellard | CC_OP = CC_OP_EFLAGS; |
155 | fc2b4c48 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
156 | e4533c7a | bellard | #elif defined(TARGET_ARM)
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157 | e4533c7a | bellard | { |
158 | e4533c7a | bellard | unsigned int psr; |
159 | e4533c7a | bellard | psr = env->cpsr; |
160 | e4533c7a | bellard | env->CF = (psr >> 29) & 1; |
161 | e4533c7a | bellard | env->NZF = (psr & 0xc0000000) ^ 0x40000000; |
162 | e4533c7a | bellard | env->VF = (psr << 3) & 0x80000000; |
163 | 99c475ab | bellard | env->QF = (psr >> 27) & 1; |
164 | 99c475ab | bellard | env->cpsr = psr & ~CACHED_CPSR_BITS; |
165 | e4533c7a | bellard | } |
166 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
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167 | 67867308 | bellard | #elif defined(TARGET_PPC)
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168 | e4533c7a | bellard | #else
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169 | e4533c7a | bellard | #error unsupported target CPU
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170 | e4533c7a | bellard | #endif
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171 | 3fb2ded1 | bellard | env->exception_index = -1;
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172 | 9d27abd9 | bellard | |
173 | 7d13299d | bellard | /* prepare setjmp context for exception handling */
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174 | 3fb2ded1 | bellard | for(;;) {
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175 | 3fb2ded1 | bellard | if (setjmp(env->jmp_env) == 0) { |
176 | ee8b7021 | bellard | env->current_tb = NULL;
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177 | 3fb2ded1 | bellard | /* if an exception is pending, we execute it here */
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178 | 3fb2ded1 | bellard | if (env->exception_index >= 0) { |
179 | 3fb2ded1 | bellard | if (env->exception_index >= EXCP_INTERRUPT) {
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180 | 3fb2ded1 | bellard | /* exit request from the cpu execution loop */
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181 | 3fb2ded1 | bellard | ret = env->exception_index; |
182 | 3fb2ded1 | bellard | break;
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183 | 3fb2ded1 | bellard | } else if (env->user_mode_only) { |
184 | 3fb2ded1 | bellard | /* if user mode only, we simulate a fake exception
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185 | 3fb2ded1 | bellard | which will be hanlded outside the cpu execution
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186 | 3fb2ded1 | bellard | loop */
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187 | 83479e77 | bellard | #if defined(TARGET_I386)
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188 | 3fb2ded1 | bellard | do_interrupt_user(env->exception_index, |
189 | 3fb2ded1 | bellard | env->exception_is_int, |
190 | 3fb2ded1 | bellard | env->error_code, |
191 | 3fb2ded1 | bellard | env->exception_next_eip); |
192 | 83479e77 | bellard | #endif
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193 | 3fb2ded1 | bellard | ret = env->exception_index; |
194 | 3fb2ded1 | bellard | break;
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195 | 3fb2ded1 | bellard | } else {
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196 | 83479e77 | bellard | #if defined(TARGET_I386)
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197 | 3fb2ded1 | bellard | /* simulate a real cpu exception. On i386, it can
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198 | 3fb2ded1 | bellard | trigger new exceptions, but we do not handle
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199 | 3fb2ded1 | bellard | double or triple faults yet. */
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200 | 3fb2ded1 | bellard | do_interrupt(env->exception_index, |
201 | 3fb2ded1 | bellard | env->exception_is_int, |
202 | 3fb2ded1 | bellard | env->error_code, |
203 | d05e66d2 | bellard | env->exception_next_eip, 0);
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204 | ce09776b | bellard | #elif defined(TARGET_PPC)
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205 | ce09776b | bellard | do_interrupt(env); |
206 | e95c8d51 | bellard | #elif defined(TARGET_SPARC)
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207 | 1a0c3292 | bellard | do_interrupt(env->exception_index); |
208 | 83479e77 | bellard | #endif
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209 | 3fb2ded1 | bellard | } |
210 | 3fb2ded1 | bellard | env->exception_index = -1;
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211 | 9df217a3 | bellard | } |
212 | 9df217a3 | bellard | #ifdef USE_KQEMU
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213 | 9df217a3 | bellard | if (kqemu_is_ok(env) && env->interrupt_request == 0) { |
214 | 9df217a3 | bellard | int ret;
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215 | 9df217a3 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
216 | 9df217a3 | bellard | ret = kqemu_cpu_exec(env); |
217 | 9df217a3 | bellard | /* put eflags in CPU temporary format */
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218 | 9df217a3 | bellard | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
219 | 9df217a3 | bellard | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
220 | 9df217a3 | bellard | CC_OP = CC_OP_EFLAGS; |
221 | 9df217a3 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
222 | 9df217a3 | bellard | if (ret == 1) { |
223 | 9df217a3 | bellard | /* exception */
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224 | 9df217a3 | bellard | longjmp(env->jmp_env, 1);
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225 | 9df217a3 | bellard | } else if (ret == 2) { |
226 | 9df217a3 | bellard | /* softmmu execution needed */
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227 | 9df217a3 | bellard | } else {
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228 | 9df217a3 | bellard | if (env->interrupt_request != 0) { |
229 | 9df217a3 | bellard | /* hardware interrupt will be executed just after */
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230 | 9df217a3 | bellard | } else {
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231 | 9df217a3 | bellard | /* otherwise, we restart */
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232 | 9df217a3 | bellard | longjmp(env->jmp_env, 1);
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233 | 9df217a3 | bellard | } |
234 | 9df217a3 | bellard | } |
235 | 3fb2ded1 | bellard | } |
236 | 9df217a3 | bellard | #endif
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237 | 9df217a3 | bellard | |
238 | 3fb2ded1 | bellard | T0 = 0; /* force lookup of first TB */ |
239 | 3fb2ded1 | bellard | for(;;) {
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240 | 8c6939c0 | bellard | #ifdef __sparc__
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241 | 3fb2ded1 | bellard | /* g1 can be modified by some libc? functions */
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242 | 3fb2ded1 | bellard | tmp_T0 = T0; |
243 | 8c6939c0 | bellard | #endif
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244 | 68a79315 | bellard | interrupt_request = env->interrupt_request; |
245 | 2e255c6b | bellard | if (__builtin_expect(interrupt_request, 0)) { |
246 | 68a79315 | bellard | #if defined(TARGET_I386)
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247 | 68a79315 | bellard | /* if hardware interrupt pending, we execute it */
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248 | 68a79315 | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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249 | 3f337316 | bellard | (env->eflags & IF_MASK) && |
250 | 3f337316 | bellard | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { |
251 | 68a79315 | bellard | int intno;
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252 | fbf9eeb3 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
253 | a541f297 | bellard | intno = cpu_get_pic_interrupt(env); |
254 | f193c797 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
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255 | 68a79315 | bellard | fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
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256 | 68a79315 | bellard | } |
257 | d05e66d2 | bellard | do_interrupt(intno, 0, 0, 0, 1); |
258 | 907a5b26 | bellard | /* ensure that no TB jump will be modified as
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259 | 907a5b26 | bellard | the program flow was changed */
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260 | 907a5b26 | bellard | #ifdef __sparc__
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261 | 907a5b26 | bellard | tmp_T0 = 0;
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262 | 907a5b26 | bellard | #else
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263 | 907a5b26 | bellard | T0 = 0;
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264 | 907a5b26 | bellard | #endif
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265 | 68a79315 | bellard | } |
266 | ce09776b | bellard | #elif defined(TARGET_PPC)
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267 | 9fddaa0c | bellard | #if 0
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268 | 9fddaa0c | bellard | if ((interrupt_request & CPU_INTERRUPT_RESET)) {
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269 | 9fddaa0c | bellard | cpu_ppc_reset(env);
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270 | 9fddaa0c | bellard | }
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271 | 9fddaa0c | bellard | #endif
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272 | 9fddaa0c | bellard | if (msr_ee != 0) { |
273 | ce09776b | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD)) {
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274 | 9fddaa0c | bellard | /* Raise it */
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275 | 9fddaa0c | bellard | env->exception_index = EXCP_EXTERNAL; |
276 | 9fddaa0c | bellard | env->error_code = 0;
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277 | ce09776b | bellard | do_interrupt(env); |
278 | ce09776b | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
279 | 9fddaa0c | bellard | } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) { |
280 | 9fddaa0c | bellard | /* Raise it */
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281 | 9fddaa0c | bellard | env->exception_index = EXCP_DECR; |
282 | 9fddaa0c | bellard | env->error_code = 0;
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283 | 9fddaa0c | bellard | do_interrupt(env); |
284 | 9fddaa0c | bellard | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
285 | 9fddaa0c | bellard | } |
286 | ce09776b | bellard | } |
287 | e95c8d51 | bellard | #elif defined(TARGET_SPARC)
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288 | e95c8d51 | bellard | if (interrupt_request & CPU_INTERRUPT_HARD) {
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289 | 1a0c3292 | bellard | do_interrupt(env->interrupt_index); |
290 | e95c8d51 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
291 | e95c8d51 | bellard | } else if (interrupt_request & CPU_INTERRUPT_TIMER) { |
292 | e95c8d51 | bellard | //do_interrupt(0, 0, 0, 0, 0);
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293 | e95c8d51 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
294 | e95c8d51 | bellard | } |
295 | 68a79315 | bellard | #endif
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296 | bf3e8bf1 | bellard | if (interrupt_request & CPU_INTERRUPT_EXITTB) {
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297 | bf3e8bf1 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
298 | bf3e8bf1 | bellard | /* ensure that no TB jump will be modified as
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299 | bf3e8bf1 | bellard | the program flow was changed */
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300 | bf3e8bf1 | bellard | #ifdef __sparc__
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301 | bf3e8bf1 | bellard | tmp_T0 = 0;
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302 | bf3e8bf1 | bellard | #else
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303 | bf3e8bf1 | bellard | T0 = 0;
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304 | bf3e8bf1 | bellard | #endif
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305 | bf3e8bf1 | bellard | } |
306 | 68a79315 | bellard | if (interrupt_request & CPU_INTERRUPT_EXIT) {
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307 | 68a79315 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_EXIT; |
308 | 68a79315 | bellard | env->exception_index = EXCP_INTERRUPT; |
309 | 68a79315 | bellard | cpu_loop_exit(); |
310 | 68a79315 | bellard | } |
311 | 3fb2ded1 | bellard | } |
312 | 7d13299d | bellard | #ifdef DEBUG_EXEC
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313 | c27004ec | bellard | if ((loglevel & CPU_LOG_EXEC)) {
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314 | e4533c7a | bellard | #if defined(TARGET_I386)
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315 | 3fb2ded1 | bellard | /* restore flags in standard format */
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316 | 3fb2ded1 | bellard | env->regs[R_EAX] = EAX; |
317 | 3fb2ded1 | bellard | env->regs[R_EBX] = EBX; |
318 | 3fb2ded1 | bellard | env->regs[R_ECX] = ECX; |
319 | 3fb2ded1 | bellard | env->regs[R_EDX] = EDX; |
320 | 3fb2ded1 | bellard | env->regs[R_ESI] = ESI; |
321 | 3fb2ded1 | bellard | env->regs[R_EDI] = EDI; |
322 | 3fb2ded1 | bellard | env->regs[R_EBP] = EBP; |
323 | 3fb2ded1 | bellard | env->regs[R_ESP] = ESP; |
324 | 3fb2ded1 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
325 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
326 | 3fb2ded1 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
327 | e4533c7a | bellard | #elif defined(TARGET_ARM)
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328 | 1b21b62a | bellard | env->cpsr = compute_cpsr(); |
329 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
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330 | 99c475ab | bellard | env->cpsr &= ~CACHED_CPSR_BITS; |
331 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
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332 | 7fe48483 | bellard | cpu_dump_state (env, logfile, fprintf, 0);
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333 | 67867308 | bellard | #elif defined(TARGET_PPC)
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334 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
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335 | e4533c7a | bellard | #else
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336 | e4533c7a | bellard | #error unsupported target CPU
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337 | e4533c7a | bellard | #endif
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338 | 3fb2ded1 | bellard | } |
339 | 7d13299d | bellard | #endif
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340 | 3f337316 | bellard | /* we record a subset of the CPU state. It will
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341 | 3f337316 | bellard | always be the same before a given translated block
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342 | 3f337316 | bellard | is executed. */
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343 | e4533c7a | bellard | #if defined(TARGET_I386)
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344 | 2e255c6b | bellard | flags = env->hflags; |
345 | 3f337316 | bellard | flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
346 | 3fb2ded1 | bellard | cs_base = env->segs[R_CS].base; |
347 | 3fb2ded1 | bellard | pc = cs_base + env->eip; |
348 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
349 | 99c475ab | bellard | flags = env->thumb; |
350 | 3fb2ded1 | bellard | cs_base = 0;
|
351 | c27004ec | bellard | pc = env->regs[15];
|
352 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
353 | 67867308 | bellard | flags = 0;
|
354 | c27004ec | bellard | cs_base = env->npc; |
355 | c27004ec | bellard | pc = env->pc; |
356 | 67867308 | bellard | #elif defined(TARGET_PPC)
|
357 | c4decf37 | bellard | flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) | (msr_se << MSR_SE); |
358 | 67867308 | bellard | cs_base = 0;
|
359 | c27004ec | bellard | pc = env->nip; |
360 | e4533c7a | bellard | #else
|
361 | e4533c7a | bellard | #error unsupported CPU
|
362 | e4533c7a | bellard | #endif
|
363 | c27004ec | bellard | tb = tb_find(&ptb, pc, cs_base, |
364 | 3fb2ded1 | bellard | flags); |
365 | d4e8164f | bellard | if (!tb) {
|
366 | 1376847f | bellard | TranslationBlock **ptb1; |
367 | 1376847f | bellard | unsigned int h; |
368 | 1376847f | bellard | target_ulong phys_pc, phys_page1, phys_page2, virt_page2; |
369 | 1376847f | bellard | |
370 | 1376847f | bellard | |
371 | 3fb2ded1 | bellard | spin_lock(&tb_lock); |
372 | 1376847f | bellard | |
373 | 1376847f | bellard | tb_invalidated_flag = 0;
|
374 | 0d1a29f9 | bellard | |
375 | 0d1a29f9 | bellard | regs_to_env(); /* XXX: do it just before cpu_gen_code() */
|
376 | 1376847f | bellard | |
377 | 1376847f | bellard | /* find translated block using physical mappings */
|
378 | c27004ec | bellard | phys_pc = get_phys_addr_code(env, pc); |
379 | 1376847f | bellard | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
380 | 1376847f | bellard | phys_page2 = -1;
|
381 | 1376847f | bellard | h = tb_phys_hash_func(phys_pc); |
382 | 1376847f | bellard | ptb1 = &tb_phys_hash[h]; |
383 | 1376847f | bellard | for(;;) {
|
384 | 1376847f | bellard | tb = *ptb1; |
385 | 1376847f | bellard | if (!tb)
|
386 | 1376847f | bellard | goto not_found;
|
387 | c27004ec | bellard | if (tb->pc == pc &&
|
388 | 1376847f | bellard | tb->page_addr[0] == phys_page1 &&
|
389 | c27004ec | bellard | tb->cs_base == cs_base && |
390 | 1376847f | bellard | tb->flags == flags) { |
391 | 1376847f | bellard | /* check next page if needed */
|
392 | b516f85c | bellard | if (tb->page_addr[1] != -1) { |
393 | c27004ec | bellard | virt_page2 = (pc & TARGET_PAGE_MASK) + |
394 | b516f85c | bellard | TARGET_PAGE_SIZE; |
395 | 1376847f | bellard | phys_page2 = get_phys_addr_code(env, virt_page2); |
396 | 1376847f | bellard | if (tb->page_addr[1] == phys_page2) |
397 | 1376847f | bellard | goto found;
|
398 | 1376847f | bellard | } else {
|
399 | 1376847f | bellard | goto found;
|
400 | 1376847f | bellard | } |
401 | 1376847f | bellard | } |
402 | 1376847f | bellard | ptb1 = &tb->phys_hash_next; |
403 | 1376847f | bellard | } |
404 | 1376847f | bellard | not_found:
|
405 | 3fb2ded1 | bellard | /* if no translated code available, then translate it now */
|
406 | c27004ec | bellard | tb = tb_alloc(pc); |
407 | 3fb2ded1 | bellard | if (!tb) {
|
408 | 3fb2ded1 | bellard | /* flush must be done */
|
409 | b453b70b | bellard | tb_flush(env); |
410 | 3fb2ded1 | bellard | /* cannot fail at this point */
|
411 | c27004ec | bellard | tb = tb_alloc(pc); |
412 | 3fb2ded1 | bellard | /* don't forget to invalidate previous TB info */
|
413 | c27004ec | bellard | ptb = &tb_hash[tb_hash_func(pc)]; |
414 | 3fb2ded1 | bellard | T0 = 0;
|
415 | 3fb2ded1 | bellard | } |
416 | 3fb2ded1 | bellard | tc_ptr = code_gen_ptr; |
417 | 3fb2ded1 | bellard | tb->tc_ptr = tc_ptr; |
418 | c27004ec | bellard | tb->cs_base = cs_base; |
419 | 3fb2ded1 | bellard | tb->flags = flags; |
420 | facc68be | bellard | cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
421 | 1376847f | bellard | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
422 | 1376847f | bellard | |
423 | 1376847f | bellard | /* check next page if needed */
|
424 | c27004ec | bellard | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
|
425 | 1376847f | bellard | phys_page2 = -1;
|
426 | c27004ec | bellard | if ((pc & TARGET_PAGE_MASK) != virt_page2) {
|
427 | 1376847f | bellard | phys_page2 = get_phys_addr_code(env, virt_page2); |
428 | 1376847f | bellard | } |
429 | 1376847f | bellard | tb_link_phys(tb, phys_pc, phys_page2); |
430 | 1376847f | bellard | |
431 | 1376847f | bellard | found:
|
432 | 36bdbe54 | bellard | if (tb_invalidated_flag) {
|
433 | 36bdbe54 | bellard | /* as some TB could have been invalidated because
|
434 | 36bdbe54 | bellard | of memory exceptions while generating the code, we
|
435 | 36bdbe54 | bellard | must recompute the hash index here */
|
436 | c27004ec | bellard | ptb = &tb_hash[tb_hash_func(pc)]; |
437 | 36bdbe54 | bellard | while (*ptb != NULL) |
438 | 36bdbe54 | bellard | ptb = &(*ptb)->hash_next; |
439 | 36bdbe54 | bellard | T0 = 0;
|
440 | 36bdbe54 | bellard | } |
441 | 1376847f | bellard | /* we add the TB in the virtual pc hash table */
|
442 | 3fb2ded1 | bellard | *ptb = tb; |
443 | 3fb2ded1 | bellard | tb->hash_next = NULL;
|
444 | 3fb2ded1 | bellard | tb_link(tb); |
445 | 25eb4484 | bellard | spin_unlock(&tb_lock); |
446 | 9de5e440 | bellard | } |
447 | 9d27abd9 | bellard | #ifdef DEBUG_EXEC
|
448 | c1135f61 | bellard | if ((loglevel & CPU_LOG_EXEC)) {
|
449 | c27004ec | bellard | fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", |
450 | c27004ec | bellard | (long)tb->tc_ptr, tb->pc,
|
451 | c27004ec | bellard | lookup_symbol(tb->pc)); |
452 | 3fb2ded1 | bellard | } |
453 | 9d27abd9 | bellard | #endif
|
454 | 8c6939c0 | bellard | #ifdef __sparc__
|
455 | 3fb2ded1 | bellard | T0 = tmp_T0; |
456 | 8c6939c0 | bellard | #endif
|
457 | facc68be | bellard | /* see if we can patch the calling TB. */
|
458 | c27004ec | bellard | { |
459 | c27004ec | bellard | if (T0 != 0 |
460 | bf3e8bf1 | bellard | #if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
461 | bf3e8bf1 | bellard | && (tb->cflags & CF_CODE_COPY) == |
462 | bf3e8bf1 | bellard | (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
|
463 | bf3e8bf1 | bellard | #endif
|
464 | bf3e8bf1 | bellard | ) { |
465 | 3fb2ded1 | bellard | spin_lock(&tb_lock); |
466 | c27004ec | bellard | tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb); |
467 | 97eb5b14 | bellard | #if defined(USE_CODE_COPY)
|
468 | 97eb5b14 | bellard | /* propagates the FP use info */
|
469 | 97eb5b14 | bellard | ((TranslationBlock *)(T0 & ~3))->cflags |=
|
470 | 97eb5b14 | bellard | (tb->cflags & CF_FP_USED); |
471 | 97eb5b14 | bellard | #endif
|
472 | 3fb2ded1 | bellard | spin_unlock(&tb_lock); |
473 | 3fb2ded1 | bellard | } |
474 | c27004ec | bellard | } |
475 | 3fb2ded1 | bellard | tc_ptr = tb->tc_ptr; |
476 | 83479e77 | bellard | env->current_tb = tb; |
477 | 3fb2ded1 | bellard | /* execute the generated code */
|
478 | 3fb2ded1 | bellard | gen_func = (void *)tc_ptr;
|
479 | 8c6939c0 | bellard | #if defined(__sparc__)
|
480 | 3fb2ded1 | bellard | __asm__ __volatile__("call %0\n\t"
|
481 | 3fb2ded1 | bellard | "mov %%o7,%%i0"
|
482 | 3fb2ded1 | bellard | : /* no outputs */
|
483 | 3fb2ded1 | bellard | : "r" (gen_func)
|
484 | 3fb2ded1 | bellard | : "i0", "i1", "i2", "i3", "i4", "i5"); |
485 | 8c6939c0 | bellard | #elif defined(__arm__)
|
486 | 3fb2ded1 | bellard | asm volatile ("mov pc, %0\n\t" |
487 | 3fb2ded1 | bellard | ".global exec_loop\n\t"
|
488 | 3fb2ded1 | bellard | "exec_loop:\n\t"
|
489 | 3fb2ded1 | bellard | : /* no outputs */
|
490 | 3fb2ded1 | bellard | : "r" (gen_func)
|
491 | 3fb2ded1 | bellard | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); |
492 | bf3e8bf1 | bellard | #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
|
493 | bf3e8bf1 | bellard | { |
494 | bf3e8bf1 | bellard | if (!(tb->cflags & CF_CODE_COPY)) {
|
495 | 97eb5b14 | bellard | if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
|
496 | 97eb5b14 | bellard | save_native_fp_state(env); |
497 | 97eb5b14 | bellard | } |
498 | bf3e8bf1 | bellard | gen_func(); |
499 | bf3e8bf1 | bellard | } else {
|
500 | 97eb5b14 | bellard | if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
|
501 | 97eb5b14 | bellard | restore_native_fp_state(env); |
502 | 97eb5b14 | bellard | } |
503 | bf3e8bf1 | bellard | /* we work with native eflags */
|
504 | bf3e8bf1 | bellard | CC_SRC = cc_table[CC_OP].compute_all(); |
505 | bf3e8bf1 | bellard | CC_OP = CC_OP_EFLAGS; |
506 | bf3e8bf1 | bellard | asm(".globl exec_loop\n" |
507 | bf3e8bf1 | bellard | "\n"
|
508 | bf3e8bf1 | bellard | "debug1:\n"
|
509 | bf3e8bf1 | bellard | " pushl %%ebp\n"
|
510 | bf3e8bf1 | bellard | " fs movl %10, %9\n"
|
511 | bf3e8bf1 | bellard | " fs movl %11, %%eax\n"
|
512 | bf3e8bf1 | bellard | " andl $0x400, %%eax\n"
|
513 | bf3e8bf1 | bellard | " fs orl %8, %%eax\n"
|
514 | bf3e8bf1 | bellard | " pushl %%eax\n"
|
515 | bf3e8bf1 | bellard | " popf\n"
|
516 | bf3e8bf1 | bellard | " fs movl %%esp, %12\n"
|
517 | bf3e8bf1 | bellard | " fs movl %0, %%eax\n"
|
518 | bf3e8bf1 | bellard | " fs movl %1, %%ecx\n"
|
519 | bf3e8bf1 | bellard | " fs movl %2, %%edx\n"
|
520 | bf3e8bf1 | bellard | " fs movl %3, %%ebx\n"
|
521 | bf3e8bf1 | bellard | " fs movl %4, %%esp\n"
|
522 | bf3e8bf1 | bellard | " fs movl %5, %%ebp\n"
|
523 | bf3e8bf1 | bellard | " fs movl %6, %%esi\n"
|
524 | bf3e8bf1 | bellard | " fs movl %7, %%edi\n"
|
525 | bf3e8bf1 | bellard | " fs jmp *%9\n"
|
526 | bf3e8bf1 | bellard | "exec_loop:\n"
|
527 | bf3e8bf1 | bellard | " fs movl %%esp, %4\n"
|
528 | bf3e8bf1 | bellard | " fs movl %12, %%esp\n"
|
529 | bf3e8bf1 | bellard | " fs movl %%eax, %0\n"
|
530 | bf3e8bf1 | bellard | " fs movl %%ecx, %1\n"
|
531 | bf3e8bf1 | bellard | " fs movl %%edx, %2\n"
|
532 | bf3e8bf1 | bellard | " fs movl %%ebx, %3\n"
|
533 | bf3e8bf1 | bellard | " fs movl %%ebp, %5\n"
|
534 | bf3e8bf1 | bellard | " fs movl %%esi, %6\n"
|
535 | bf3e8bf1 | bellard | " fs movl %%edi, %7\n"
|
536 | bf3e8bf1 | bellard | " pushf\n"
|
537 | bf3e8bf1 | bellard | " popl %%eax\n"
|
538 | bf3e8bf1 | bellard | " movl %%eax, %%ecx\n"
|
539 | bf3e8bf1 | bellard | " andl $0x400, %%ecx\n"
|
540 | bf3e8bf1 | bellard | " shrl $9, %%ecx\n"
|
541 | bf3e8bf1 | bellard | " andl $0x8d5, %%eax\n"
|
542 | bf3e8bf1 | bellard | " fs movl %%eax, %8\n"
|
543 | bf3e8bf1 | bellard | " movl $1, %%eax\n"
|
544 | bf3e8bf1 | bellard | " subl %%ecx, %%eax\n"
|
545 | bf3e8bf1 | bellard | " fs movl %%eax, %11\n"
|
546 | bf3e8bf1 | bellard | " fs movl %9, %%ebx\n" /* get T0 value */ |
547 | bf3e8bf1 | bellard | " popl %%ebp\n"
|
548 | bf3e8bf1 | bellard | : |
549 | bf3e8bf1 | bellard | : "m" (*(uint8_t *)offsetof(CPUState, regs[0])), |
550 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[1])), |
551 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[2])), |
552 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[3])), |
553 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[4])), |
554 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[5])), |
555 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[6])), |
556 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[7])), |
557 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
|
558 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
|
559 | bf3e8bf1 | bellard | "a" (gen_func),
|
560 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, df)),
|
561 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
|
562 | bf3e8bf1 | bellard | : "%ecx", "%edx" |
563 | bf3e8bf1 | bellard | ); |
564 | bf3e8bf1 | bellard | } |
565 | bf3e8bf1 | bellard | } |
566 | ae228531 | bellard | #else
|
567 | 3fb2ded1 | bellard | gen_func(); |
568 | ae228531 | bellard | #endif
|
569 | 83479e77 | bellard | env->current_tb = NULL;
|
570 | 4cbf74b6 | bellard | /* reset soft MMU for next block (it can currently
|
571 | 4cbf74b6 | bellard | only be set by a memory fault) */
|
572 | 4cbf74b6 | bellard | #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
|
573 | 3f337316 | bellard | if (env->hflags & HF_SOFTMMU_MASK) {
|
574 | 3f337316 | bellard | env->hflags &= ~HF_SOFTMMU_MASK; |
575 | 4cbf74b6 | bellard | /* do not allow linking to another block */
|
576 | 4cbf74b6 | bellard | T0 = 0;
|
577 | 4cbf74b6 | bellard | } |
578 | 4cbf74b6 | bellard | #endif
|
579 | 3fb2ded1 | bellard | } |
580 | 3fb2ded1 | bellard | } else {
|
581 | 0d1a29f9 | bellard | env_to_regs(); |
582 | 7d13299d | bellard | } |
583 | 3fb2ded1 | bellard | } /* for(;;) */
|
584 | 3fb2ded1 | bellard | |
585 | 7d13299d | bellard | |
586 | e4533c7a | bellard | #if defined(TARGET_I386)
|
587 | 97eb5b14 | bellard | #if defined(USE_CODE_COPY)
|
588 | 97eb5b14 | bellard | if (env->native_fp_regs) {
|
589 | 97eb5b14 | bellard | save_native_fp_state(env); |
590 | 97eb5b14 | bellard | } |
591 | 97eb5b14 | bellard | #endif
|
592 | 9de5e440 | bellard | /* restore flags in standard format */
|
593 | fc2b4c48 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
594 | 9de5e440 | bellard | |
595 | 7d13299d | bellard | /* restore global registers */
|
596 | 04369ff2 | bellard | #ifdef reg_EAX
|
597 | 04369ff2 | bellard | EAX = saved_EAX; |
598 | 04369ff2 | bellard | #endif
|
599 | 04369ff2 | bellard | #ifdef reg_ECX
|
600 | 04369ff2 | bellard | ECX = saved_ECX; |
601 | 04369ff2 | bellard | #endif
|
602 | 04369ff2 | bellard | #ifdef reg_EDX
|
603 | 04369ff2 | bellard | EDX = saved_EDX; |
604 | 04369ff2 | bellard | #endif
|
605 | 04369ff2 | bellard | #ifdef reg_EBX
|
606 | 04369ff2 | bellard | EBX = saved_EBX; |
607 | 04369ff2 | bellard | #endif
|
608 | 04369ff2 | bellard | #ifdef reg_ESP
|
609 | 04369ff2 | bellard | ESP = saved_ESP; |
610 | 04369ff2 | bellard | #endif
|
611 | 04369ff2 | bellard | #ifdef reg_EBP
|
612 | 04369ff2 | bellard | EBP = saved_EBP; |
613 | 04369ff2 | bellard | #endif
|
614 | 04369ff2 | bellard | #ifdef reg_ESI
|
615 | 04369ff2 | bellard | ESI = saved_ESI; |
616 | 04369ff2 | bellard | #endif
|
617 | 04369ff2 | bellard | #ifdef reg_EDI
|
618 | 04369ff2 | bellard | EDI = saved_EDI; |
619 | 04369ff2 | bellard | #endif
|
620 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
621 | 1b21b62a | bellard | env->cpsr = compute_cpsr(); |
622 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
623 | 67867308 | bellard | #elif defined(TARGET_PPC)
|
624 | e4533c7a | bellard | #else
|
625 | e4533c7a | bellard | #error unsupported target CPU
|
626 | e4533c7a | bellard | #endif
|
627 | 8c6939c0 | bellard | #ifdef __sparc__
|
628 | 8c6939c0 | bellard | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); |
629 | 8c6939c0 | bellard | #endif
|
630 | 7d13299d | bellard | T0 = saved_T0; |
631 | 7d13299d | bellard | T1 = saved_T1; |
632 | e4533c7a | bellard | T2 = saved_T2; |
633 | 7d13299d | bellard | env = saved_env; |
634 | 7d13299d | bellard | return ret;
|
635 | 7d13299d | bellard | } |
636 | 6dbad63e | bellard | |
637 | fbf9eeb3 | bellard | /* must only be called from the generated code as an exception can be
|
638 | fbf9eeb3 | bellard | generated */
|
639 | fbf9eeb3 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end)
|
640 | fbf9eeb3 | bellard | { |
641 | dc5d0b3d | bellard | /* XXX: cannot enable it yet because it yields to MMU exception
|
642 | dc5d0b3d | bellard | where NIP != read address on PowerPC */
|
643 | dc5d0b3d | bellard | #if 0
|
644 | fbf9eeb3 | bellard | target_ulong phys_addr;
|
645 | fbf9eeb3 | bellard | phys_addr = get_phys_addr_code(env, start);
|
646 | fbf9eeb3 | bellard | tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
|
647 | dc5d0b3d | bellard | #endif
|
648 | fbf9eeb3 | bellard | } |
649 | fbf9eeb3 | bellard | |
650 | 1a18c71b | bellard | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
|
651 | e4533c7a | bellard | |
652 | 6dbad63e | bellard | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
653 | 6dbad63e | bellard | { |
654 | 6dbad63e | bellard | CPUX86State *saved_env; |
655 | 6dbad63e | bellard | |
656 | 6dbad63e | bellard | saved_env = env; |
657 | 6dbad63e | bellard | env = s; |
658 | a412ac57 | bellard | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
659 | a513fe19 | bellard | selector &= 0xffff;
|
660 | 2e255c6b | bellard | cpu_x86_load_seg_cache(env, seg_reg, selector, |
661 | c27004ec | bellard | (selector << 4), 0xffff, 0); |
662 | a513fe19 | bellard | } else {
|
663 | b453b70b | bellard | load_seg(seg_reg, selector); |
664 | a513fe19 | bellard | } |
665 | 6dbad63e | bellard | env = saved_env; |
666 | 6dbad63e | bellard | } |
667 | 9de5e440 | bellard | |
668 | d0a1ffc9 | bellard | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
669 | d0a1ffc9 | bellard | { |
670 | d0a1ffc9 | bellard | CPUX86State *saved_env; |
671 | d0a1ffc9 | bellard | |
672 | d0a1ffc9 | bellard | saved_env = env; |
673 | d0a1ffc9 | bellard | env = s; |
674 | d0a1ffc9 | bellard | |
675 | c27004ec | bellard | helper_fsave((target_ulong)ptr, data32); |
676 | d0a1ffc9 | bellard | |
677 | d0a1ffc9 | bellard | env = saved_env; |
678 | d0a1ffc9 | bellard | } |
679 | d0a1ffc9 | bellard | |
680 | d0a1ffc9 | bellard | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) |
681 | d0a1ffc9 | bellard | { |
682 | d0a1ffc9 | bellard | CPUX86State *saved_env; |
683 | d0a1ffc9 | bellard | |
684 | d0a1ffc9 | bellard | saved_env = env; |
685 | d0a1ffc9 | bellard | env = s; |
686 | d0a1ffc9 | bellard | |
687 | c27004ec | bellard | helper_frstor((target_ulong)ptr, data32); |
688 | d0a1ffc9 | bellard | |
689 | d0a1ffc9 | bellard | env = saved_env; |
690 | d0a1ffc9 | bellard | } |
691 | d0a1ffc9 | bellard | |
692 | e4533c7a | bellard | #endif /* TARGET_I386 */ |
693 | e4533c7a | bellard | |
694 | 67b915a5 | bellard | #if !defined(CONFIG_SOFTMMU)
|
695 | 67b915a5 | bellard | |
696 | 3fb2ded1 | bellard | #if defined(TARGET_I386)
|
697 | 3fb2ded1 | bellard | |
698 | b56dad1c | bellard | /* 'pc' is the host PC at which the exception was raised. 'address' is
|
699 | fd6ce8f6 | bellard | the effective address of the memory exception. 'is_write' is 1 if a
|
700 | fd6ce8f6 | bellard | write caused the exception and otherwise 0'. 'old_set' is the
|
701 | fd6ce8f6 | bellard | signal set which should be restored */
|
702 | 2b413144 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
703 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
704 | bf3e8bf1 | bellard | void *puc)
|
705 | 9de5e440 | bellard | { |
706 | a513fe19 | bellard | TranslationBlock *tb; |
707 | a513fe19 | bellard | int ret;
|
708 | 68a79315 | bellard | |
709 | 83479e77 | bellard | if (cpu_single_env)
|
710 | 83479e77 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
711 | fd6ce8f6 | bellard | #if defined(DEBUG_SIGNAL)
|
712 | bf3e8bf1 | bellard | qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
713 | bf3e8bf1 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
714 | 9de5e440 | bellard | #endif
|
715 | 25eb4484 | bellard | /* XXX: locking issue */
|
716 | fbf9eeb3 | bellard | if (is_write && page_unprotect(address, pc, puc)) {
|
717 | fd6ce8f6 | bellard | return 1; |
718 | fd6ce8f6 | bellard | } |
719 | fbf9eeb3 | bellard | |
720 | 3fb2ded1 | bellard | /* see if it is an MMU fault */
|
721 | 93a40ea9 | bellard | ret = cpu_x86_handle_mmu_fault(env, address, is_write, |
722 | 93a40ea9 | bellard | ((env->hflags & HF_CPL_MASK) == 3), 0); |
723 | 3fb2ded1 | bellard | if (ret < 0) |
724 | 3fb2ded1 | bellard | return 0; /* not an MMU fault */ |
725 | 3fb2ded1 | bellard | if (ret == 0) |
726 | 3fb2ded1 | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
727 | 3fb2ded1 | bellard | /* now we have a real cpu fault */
|
728 | a513fe19 | bellard | tb = tb_find_pc(pc); |
729 | a513fe19 | bellard | if (tb) {
|
730 | 9de5e440 | bellard | /* the PC is inside the translated code. It means that we have
|
731 | 9de5e440 | bellard | a virtual CPU fault */
|
732 | bf3e8bf1 | bellard | cpu_restore_state(tb, env, pc, puc); |
733 | 3fb2ded1 | bellard | } |
734 | 4cbf74b6 | bellard | if (ret == 1) { |
735 | 3fb2ded1 | bellard | #if 0
|
736 | 4cbf74b6 | bellard | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
|
737 | 4cbf74b6 | bellard | env->eip, env->cr[2], env->error_code);
|
738 | 3fb2ded1 | bellard | #endif
|
739 | 4cbf74b6 | bellard | /* we restore the process signal mask as the sigreturn should
|
740 | 4cbf74b6 | bellard | do it (XXX: use sigsetjmp) */
|
741 | 4cbf74b6 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
742 | 4cbf74b6 | bellard | raise_exception_err(EXCP0E_PAGE, env->error_code); |
743 | 4cbf74b6 | bellard | } else {
|
744 | 4cbf74b6 | bellard | /* activate soft MMU for this block */
|
745 | 3f337316 | bellard | env->hflags |= HF_SOFTMMU_MASK; |
746 | fbf9eeb3 | bellard | cpu_resume_from_signal(env, puc); |
747 | 4cbf74b6 | bellard | } |
748 | 3fb2ded1 | bellard | /* never comes here */
|
749 | 3fb2ded1 | bellard | return 1; |
750 | 3fb2ded1 | bellard | } |
751 | 3fb2ded1 | bellard | |
752 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
753 | 3fb2ded1 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
754 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
755 | bf3e8bf1 | bellard | void *puc)
|
756 | 3fb2ded1 | bellard | { |
757 | 68016c62 | bellard | TranslationBlock *tb; |
758 | 68016c62 | bellard | int ret;
|
759 | 68016c62 | bellard | |
760 | 68016c62 | bellard | if (cpu_single_env)
|
761 | 68016c62 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
762 | 68016c62 | bellard | #if defined(DEBUG_SIGNAL)
|
763 | 68016c62 | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
764 | 68016c62 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
765 | 68016c62 | bellard | #endif
|
766 | 9f0777ed | bellard | /* XXX: locking issue */
|
767 | 9f0777ed | bellard | if (is_write && page_unprotect(address, pc, puc)) {
|
768 | 9f0777ed | bellard | return 1; |
769 | 9f0777ed | bellard | } |
770 | 68016c62 | bellard | /* see if it is an MMU fault */
|
771 | 68016c62 | bellard | ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0); |
772 | 68016c62 | bellard | if (ret < 0) |
773 | 68016c62 | bellard | return 0; /* not an MMU fault */ |
774 | 68016c62 | bellard | if (ret == 0) |
775 | 68016c62 | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
776 | 68016c62 | bellard | /* now we have a real cpu fault */
|
777 | 68016c62 | bellard | tb = tb_find_pc(pc); |
778 | 68016c62 | bellard | if (tb) {
|
779 | 68016c62 | bellard | /* the PC is inside the translated code. It means that we have
|
780 | 68016c62 | bellard | a virtual CPU fault */
|
781 | 68016c62 | bellard | cpu_restore_state(tb, env, pc, puc); |
782 | 68016c62 | bellard | } |
783 | 68016c62 | bellard | /* we restore the process signal mask as the sigreturn should
|
784 | 68016c62 | bellard | do it (XXX: use sigsetjmp) */
|
785 | 68016c62 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
786 | 68016c62 | bellard | cpu_loop_exit(); |
787 | 3fb2ded1 | bellard | } |
788 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
789 | 93ac68bc | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
790 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
791 | bf3e8bf1 | bellard | void *puc)
|
792 | 93ac68bc | bellard | { |
793 | 68016c62 | bellard | TranslationBlock *tb; |
794 | 68016c62 | bellard | int ret;
|
795 | 68016c62 | bellard | |
796 | 68016c62 | bellard | if (cpu_single_env)
|
797 | 68016c62 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
798 | 68016c62 | bellard | #if defined(DEBUG_SIGNAL)
|
799 | 68016c62 | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
800 | 68016c62 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
801 | 68016c62 | bellard | #endif
|
802 | b453b70b | bellard | /* XXX: locking issue */
|
803 | fbf9eeb3 | bellard | if (is_write && page_unprotect(address, pc, puc)) {
|
804 | b453b70b | bellard | return 1; |
805 | b453b70b | bellard | } |
806 | 68016c62 | bellard | /* see if it is an MMU fault */
|
807 | 68016c62 | bellard | ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0); |
808 | 68016c62 | bellard | if (ret < 0) |
809 | 68016c62 | bellard | return 0; /* not an MMU fault */ |
810 | 68016c62 | bellard | if (ret == 0) |
811 | 68016c62 | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
812 | 68016c62 | bellard | /* now we have a real cpu fault */
|
813 | 68016c62 | bellard | tb = tb_find_pc(pc); |
814 | 68016c62 | bellard | if (tb) {
|
815 | 68016c62 | bellard | /* the PC is inside the translated code. It means that we have
|
816 | 68016c62 | bellard | a virtual CPU fault */
|
817 | 68016c62 | bellard | cpu_restore_state(tb, env, pc, puc); |
818 | 68016c62 | bellard | } |
819 | 68016c62 | bellard | /* we restore the process signal mask as the sigreturn should
|
820 | 68016c62 | bellard | do it (XXX: use sigsetjmp) */
|
821 | 68016c62 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
822 | 68016c62 | bellard | cpu_loop_exit(); |
823 | 93ac68bc | bellard | } |
824 | 67867308 | bellard | #elif defined (TARGET_PPC)
|
825 | 67867308 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
826 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
827 | bf3e8bf1 | bellard | void *puc)
|
828 | 67867308 | bellard | { |
829 | 67867308 | bellard | TranslationBlock *tb; |
830 | ce09776b | bellard | int ret;
|
831 | 67867308 | bellard | |
832 | 67867308 | bellard | if (cpu_single_env)
|
833 | 67867308 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
834 | 67867308 | bellard | #if defined(DEBUG_SIGNAL)
|
835 | 67867308 | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
836 | 67867308 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
837 | 67867308 | bellard | #endif
|
838 | 67867308 | bellard | /* XXX: locking issue */
|
839 | fbf9eeb3 | bellard | if (is_write && page_unprotect(address, pc, puc)) {
|
840 | 67867308 | bellard | return 1; |
841 | 67867308 | bellard | } |
842 | 67867308 | bellard | |
843 | ce09776b | bellard | /* see if it is an MMU fault */
|
844 | 7f957d28 | bellard | ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
|
845 | ce09776b | bellard | if (ret < 0) |
846 | ce09776b | bellard | return 0; /* not an MMU fault */ |
847 | ce09776b | bellard | if (ret == 0) |
848 | ce09776b | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
849 | ce09776b | bellard | |
850 | 67867308 | bellard | /* now we have a real cpu fault */
|
851 | 67867308 | bellard | tb = tb_find_pc(pc); |
852 | 67867308 | bellard | if (tb) {
|
853 | 67867308 | bellard | /* the PC is inside the translated code. It means that we have
|
854 | 67867308 | bellard | a virtual CPU fault */
|
855 | bf3e8bf1 | bellard | cpu_restore_state(tb, env, pc, puc); |
856 | 67867308 | bellard | } |
857 | ce09776b | bellard | if (ret == 1) { |
858 | 67867308 | bellard | #if 0
|
859 | ce09776b | bellard | printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
860 | ce09776b | bellard | env->nip, env->error_code, tb);
|
861 | 67867308 | bellard | #endif
|
862 | 67867308 | bellard | /* we restore the process signal mask as the sigreturn should
|
863 | 67867308 | bellard | do it (XXX: use sigsetjmp) */
|
864 | bf3e8bf1 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
865 | 9fddaa0c | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
866 | ce09776b | bellard | } else {
|
867 | ce09776b | bellard | /* activate soft MMU for this block */
|
868 | fbf9eeb3 | bellard | cpu_resume_from_signal(env, puc); |
869 | ce09776b | bellard | } |
870 | 67867308 | bellard | /* never comes here */
|
871 | 67867308 | bellard | return 1; |
872 | 67867308 | bellard | } |
873 | e4533c7a | bellard | #else
|
874 | e4533c7a | bellard | #error unsupported target CPU
|
875 | e4533c7a | bellard | #endif
|
876 | 9de5e440 | bellard | |
877 | 2b413144 | bellard | #if defined(__i386__)
|
878 | 2b413144 | bellard | |
879 | bf3e8bf1 | bellard | #if defined(USE_CODE_COPY)
|
880 | bf3e8bf1 | bellard | static void cpu_send_trap(unsigned long pc, int trap, |
881 | bf3e8bf1 | bellard | struct ucontext *uc)
|
882 | bf3e8bf1 | bellard | { |
883 | bf3e8bf1 | bellard | TranslationBlock *tb; |
884 | bf3e8bf1 | bellard | |
885 | bf3e8bf1 | bellard | if (cpu_single_env)
|
886 | bf3e8bf1 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
887 | bf3e8bf1 | bellard | /* now we have a real cpu fault */
|
888 | bf3e8bf1 | bellard | tb = tb_find_pc(pc); |
889 | bf3e8bf1 | bellard | if (tb) {
|
890 | bf3e8bf1 | bellard | /* the PC is inside the translated code. It means that we have
|
891 | bf3e8bf1 | bellard | a virtual CPU fault */
|
892 | bf3e8bf1 | bellard | cpu_restore_state(tb, env, pc, uc); |
893 | bf3e8bf1 | bellard | } |
894 | bf3e8bf1 | bellard | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
|
895 | bf3e8bf1 | bellard | raise_exception_err(trap, env->error_code); |
896 | bf3e8bf1 | bellard | } |
897 | bf3e8bf1 | bellard | #endif
|
898 | bf3e8bf1 | bellard | |
899 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
900 | e4533c7a | bellard | void *puc)
|
901 | 9de5e440 | bellard | { |
902 | 9de5e440 | bellard | struct ucontext *uc = puc;
|
903 | 9de5e440 | bellard | unsigned long pc; |
904 | bf3e8bf1 | bellard | int trapno;
|
905 | 97eb5b14 | bellard | |
906 | d691f669 | bellard | #ifndef REG_EIP
|
907 | d691f669 | bellard | /* for glibc 2.1 */
|
908 | fd6ce8f6 | bellard | #define REG_EIP EIP
|
909 | fd6ce8f6 | bellard | #define REG_ERR ERR
|
910 | fd6ce8f6 | bellard | #define REG_TRAPNO TRAPNO
|
911 | d691f669 | bellard | #endif
|
912 | fc2b4c48 | bellard | pc = uc->uc_mcontext.gregs[REG_EIP]; |
913 | bf3e8bf1 | bellard | trapno = uc->uc_mcontext.gregs[REG_TRAPNO]; |
914 | bf3e8bf1 | bellard | #if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
915 | bf3e8bf1 | bellard | if (trapno == 0x00 || trapno == 0x05) { |
916 | bf3e8bf1 | bellard | /* send division by zero or bound exception */
|
917 | bf3e8bf1 | bellard | cpu_send_trap(pc, trapno, uc); |
918 | bf3e8bf1 | bellard | return 1; |
919 | bf3e8bf1 | bellard | } else
|
920 | bf3e8bf1 | bellard | #endif
|
921 | bf3e8bf1 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
922 | bf3e8bf1 | bellard | trapno == 0xe ?
|
923 | bf3e8bf1 | bellard | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
924 | bf3e8bf1 | bellard | &uc->uc_sigmask, puc); |
925 | 2b413144 | bellard | } |
926 | 2b413144 | bellard | |
927 | bc51c5c9 | bellard | #elif defined(__x86_64__)
|
928 | bc51c5c9 | bellard | |
929 | bc51c5c9 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
930 | bc51c5c9 | bellard | void *puc)
|
931 | bc51c5c9 | bellard | { |
932 | bc51c5c9 | bellard | struct ucontext *uc = puc;
|
933 | bc51c5c9 | bellard | unsigned long pc; |
934 | bc51c5c9 | bellard | |
935 | bc51c5c9 | bellard | pc = uc->uc_mcontext.gregs[REG_RIP]; |
936 | bc51c5c9 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
937 | bc51c5c9 | bellard | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
|
938 | bc51c5c9 | bellard | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
939 | bc51c5c9 | bellard | &uc->uc_sigmask, puc); |
940 | bc51c5c9 | bellard | } |
941 | bc51c5c9 | bellard | |
942 | 83fb7adf | bellard | #elif defined(__powerpc__)
|
943 | 2b413144 | bellard | |
944 | 83fb7adf | bellard | /***********************************************************************
|
945 | 83fb7adf | bellard | * signal context platform-specific definitions
|
946 | 83fb7adf | bellard | * From Wine
|
947 | 83fb7adf | bellard | */
|
948 | 83fb7adf | bellard | #ifdef linux
|
949 | 83fb7adf | bellard | /* All Registers access - only for local access */
|
950 | 83fb7adf | bellard | # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
|
951 | 83fb7adf | bellard | /* Gpr Registers access */
|
952 | 83fb7adf | bellard | # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
|
953 | 83fb7adf | bellard | # define IAR_sig(context) REG_sig(nip, context) /* Program counter */ |
954 | 83fb7adf | bellard | # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ |
955 | 83fb7adf | bellard | # define CTR_sig(context) REG_sig(ctr, context) /* Count register */ |
956 | 83fb7adf | bellard | # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ |
957 | 83fb7adf | bellard | # define LR_sig(context) REG_sig(link, context) /* Link register */ |
958 | 83fb7adf | bellard | # define CR_sig(context) REG_sig(ccr, context) /* Condition register */ |
959 | 83fb7adf | bellard | /* Float Registers access */
|
960 | 83fb7adf | bellard | # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) |
961 | 83fb7adf | bellard | # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) |
962 | 83fb7adf | bellard | /* Exception Registers access */
|
963 | 83fb7adf | bellard | # define DAR_sig(context) REG_sig(dar, context)
|
964 | 83fb7adf | bellard | # define DSISR_sig(context) REG_sig(dsisr, context)
|
965 | 83fb7adf | bellard | # define TRAP_sig(context) REG_sig(trap, context)
|
966 | 83fb7adf | bellard | #endif /* linux */ |
967 | 83fb7adf | bellard | |
968 | 83fb7adf | bellard | #ifdef __APPLE__
|
969 | 83fb7adf | bellard | # include <sys/ucontext.h> |
970 | 83fb7adf | bellard | typedef struct ucontext SIGCONTEXT; |
971 | 83fb7adf | bellard | /* All Registers access - only for local access */
|
972 | 83fb7adf | bellard | # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
|
973 | 83fb7adf | bellard | # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
|
974 | 83fb7adf | bellard | # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
|
975 | 83fb7adf | bellard | # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
|
976 | 83fb7adf | bellard | /* Gpr Registers access */
|
977 | 83fb7adf | bellard | # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) |
978 | 83fb7adf | bellard | # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ |
979 | 83fb7adf | bellard | # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ |
980 | 83fb7adf | bellard | # define CTR_sig(context) REG_sig(ctr, context)
|
981 | 83fb7adf | bellard | # define XER_sig(context) REG_sig(xer, context) /* Link register */ |
982 | 83fb7adf | bellard | # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ |
983 | 83fb7adf | bellard | # define CR_sig(context) REG_sig(cr, context) /* Condition register */ |
984 | 83fb7adf | bellard | /* Float Registers access */
|
985 | 83fb7adf | bellard | # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
|
986 | 83fb7adf | bellard | # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) |
987 | 83fb7adf | bellard | /* Exception Registers access */
|
988 | 83fb7adf | bellard | # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ |
989 | 83fb7adf | bellard | # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
|
990 | 83fb7adf | bellard | # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ |
991 | 83fb7adf | bellard | #endif /* __APPLE__ */ |
992 | 83fb7adf | bellard | |
993 | d1d9f421 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
994 | e4533c7a | bellard | void *puc)
|
995 | 2b413144 | bellard | { |
996 | 25eb4484 | bellard | struct ucontext *uc = puc;
|
997 | 25eb4484 | bellard | unsigned long pc; |
998 | 25eb4484 | bellard | int is_write;
|
999 | 25eb4484 | bellard | |
1000 | 83fb7adf | bellard | pc = IAR_sig(uc); |
1001 | 25eb4484 | bellard | is_write = 0;
|
1002 | 25eb4484 | bellard | #if 0
|
1003 | 25eb4484 | bellard | /* ppc 4xx case */
|
1004 | 83fb7adf | bellard | if (DSISR_sig(uc) & 0x00800000)
|
1005 | 25eb4484 | bellard | is_write = 1;
|
1006 | 25eb4484 | bellard | #else
|
1007 | 83fb7adf | bellard | if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
1008 | 25eb4484 | bellard | is_write = 1;
|
1009 | 25eb4484 | bellard | #endif
|
1010 | 25eb4484 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1011 | bf3e8bf1 | bellard | is_write, &uc->uc_sigmask, puc); |
1012 | 2b413144 | bellard | } |
1013 | 2b413144 | bellard | |
1014 | 2f87c607 | bellard | #elif defined(__alpha__)
|
1015 | 2f87c607 | bellard | |
1016 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1017 | 2f87c607 | bellard | void *puc)
|
1018 | 2f87c607 | bellard | { |
1019 | 2f87c607 | bellard | struct ucontext *uc = puc;
|
1020 | 2f87c607 | bellard | uint32_t *pc = uc->uc_mcontext.sc_pc; |
1021 | 2f87c607 | bellard | uint32_t insn = *pc; |
1022 | 2f87c607 | bellard | int is_write = 0; |
1023 | 2f87c607 | bellard | |
1024 | 8c6939c0 | bellard | /* XXX: need kernel patch to get write flag faster */
|
1025 | 2f87c607 | bellard | switch (insn >> 26) { |
1026 | 2f87c607 | bellard | case 0x0d: // stw |
1027 | 2f87c607 | bellard | case 0x0e: // stb |
1028 | 2f87c607 | bellard | case 0x0f: // stq_u |
1029 | 2f87c607 | bellard | case 0x24: // stf |
1030 | 2f87c607 | bellard | case 0x25: // stg |
1031 | 2f87c607 | bellard | case 0x26: // sts |
1032 | 2f87c607 | bellard | case 0x27: // stt |
1033 | 2f87c607 | bellard | case 0x2c: // stl |
1034 | 2f87c607 | bellard | case 0x2d: // stq |
1035 | 2f87c607 | bellard | case 0x2e: // stl_c |
1036 | 2f87c607 | bellard | case 0x2f: // stq_c |
1037 | 2f87c607 | bellard | is_write = 1;
|
1038 | 2f87c607 | bellard | } |
1039 | 2f87c607 | bellard | |
1040 | 2f87c607 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1041 | bf3e8bf1 | bellard | is_write, &uc->uc_sigmask, puc); |
1042 | 2f87c607 | bellard | } |
1043 | 8c6939c0 | bellard | #elif defined(__sparc__)
|
1044 | 8c6939c0 | bellard | |
1045 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1046 | e4533c7a | bellard | void *puc)
|
1047 | 8c6939c0 | bellard | { |
1048 | 8c6939c0 | bellard | uint32_t *regs = (uint32_t *)(info + 1);
|
1049 | 8c6939c0 | bellard | void *sigmask = (regs + 20); |
1050 | 8c6939c0 | bellard | unsigned long pc; |
1051 | 8c6939c0 | bellard | int is_write;
|
1052 | 8c6939c0 | bellard | uint32_t insn; |
1053 | 8c6939c0 | bellard | |
1054 | 8c6939c0 | bellard | /* XXX: is there a standard glibc define ? */
|
1055 | 8c6939c0 | bellard | pc = regs[1];
|
1056 | 8c6939c0 | bellard | /* XXX: need kernel patch to get write flag faster */
|
1057 | 8c6939c0 | bellard | is_write = 0;
|
1058 | 8c6939c0 | bellard | insn = *(uint32_t *)pc; |
1059 | 8c6939c0 | bellard | if ((insn >> 30) == 3) { |
1060 | 8c6939c0 | bellard | switch((insn >> 19) & 0x3f) { |
1061 | 8c6939c0 | bellard | case 0x05: // stb |
1062 | 8c6939c0 | bellard | case 0x06: // sth |
1063 | 8c6939c0 | bellard | case 0x04: // st |
1064 | 8c6939c0 | bellard | case 0x07: // std |
1065 | 8c6939c0 | bellard | case 0x24: // stf |
1066 | 8c6939c0 | bellard | case 0x27: // stdf |
1067 | 8c6939c0 | bellard | case 0x25: // stfsr |
1068 | 8c6939c0 | bellard | is_write = 1;
|
1069 | 8c6939c0 | bellard | break;
|
1070 | 8c6939c0 | bellard | } |
1071 | 8c6939c0 | bellard | } |
1072 | 8c6939c0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1073 | bf3e8bf1 | bellard | is_write, sigmask, NULL);
|
1074 | 8c6939c0 | bellard | } |
1075 | 8c6939c0 | bellard | |
1076 | 8c6939c0 | bellard | #elif defined(__arm__)
|
1077 | 8c6939c0 | bellard | |
1078 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1079 | e4533c7a | bellard | void *puc)
|
1080 | 8c6939c0 | bellard | { |
1081 | 8c6939c0 | bellard | struct ucontext *uc = puc;
|
1082 | 8c6939c0 | bellard | unsigned long pc; |
1083 | 8c6939c0 | bellard | int is_write;
|
1084 | 8c6939c0 | bellard | |
1085 | 8c6939c0 | bellard | pc = uc->uc_mcontext.gregs[R15]; |
1086 | 8c6939c0 | bellard | /* XXX: compute is_write */
|
1087 | 8c6939c0 | bellard | is_write = 0;
|
1088 | 8c6939c0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1089 | 8c6939c0 | bellard | is_write, |
1090 | 8c6939c0 | bellard | &uc->uc_sigmask); |
1091 | 8c6939c0 | bellard | } |
1092 | 8c6939c0 | bellard | |
1093 | 38e584a0 | bellard | #elif defined(__mc68000)
|
1094 | 38e584a0 | bellard | |
1095 | 38e584a0 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1096 | 38e584a0 | bellard | void *puc)
|
1097 | 38e584a0 | bellard | { |
1098 | 38e584a0 | bellard | struct ucontext *uc = puc;
|
1099 | 38e584a0 | bellard | unsigned long pc; |
1100 | 38e584a0 | bellard | int is_write;
|
1101 | 38e584a0 | bellard | |
1102 | 38e584a0 | bellard | pc = uc->uc_mcontext.gregs[16];
|
1103 | 38e584a0 | bellard | /* XXX: compute is_write */
|
1104 | 38e584a0 | bellard | is_write = 0;
|
1105 | 38e584a0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1106 | 38e584a0 | bellard | is_write, |
1107 | bf3e8bf1 | bellard | &uc->uc_sigmask, puc); |
1108 | 38e584a0 | bellard | } |
1109 | 38e584a0 | bellard | |
1110 | 9de5e440 | bellard | #else
|
1111 | 2b413144 | bellard | |
1112 | 3fb2ded1 | bellard | #error host CPU specific signal handler needed
|
1113 | 2b413144 | bellard | |
1114 | 9de5e440 | bellard | #endif
|
1115 | 67b915a5 | bellard | |
1116 | 67b915a5 | bellard | #endif /* !defined(CONFIG_SOFTMMU) */ |