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/*
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* Copyright (C) 2010 Red Hat, Inc.
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*
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* written by Gerd Hoffmann <kraxel@redhat.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h" |
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#include "pci.h" |
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#include "msi.h" |
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#include "qemu-timer.h" |
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#include "audiodev.h" |
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#include "intel-hda.h" |
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#include "intel-hda-defs.h" |
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|
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/* --------------------------------------------------------------------- */
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/* hda bus */
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static struct BusInfo hda_codec_bus_info = { |
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.name = "HDA",
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.size = sizeof(HDACodecBus),
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.props = (Property[]) { |
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DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1), |
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DEFINE_PROP_END_OF_LIST() |
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} |
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}; |
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void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus,
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hda_codec_response_func response, |
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hda_codec_xfer_func xfer) |
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{ |
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qbus_create_inplace(&bus->qbus, &hda_codec_bus_info, dev, NULL);
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bus->response = response; |
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bus->xfer = xfer; |
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} |
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|
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static int hda_codec_dev_init(DeviceState *qdev, DeviceInfo *base) |
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{ |
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HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus); |
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HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
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HDACodecDeviceInfo *info = DO_UPCAST(HDACodecDeviceInfo, qdev, base); |
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dev->info = info; |
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if (dev->cad == -1) { |
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dev->cad = bus->next_cad; |
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} |
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if (dev->cad >= 15) { |
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return -1; |
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} |
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bus->next_cad = dev->cad + 1;
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return info->init(dev);
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} |
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|
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static int hda_codec_dev_exit(DeviceState *qdev) |
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{ |
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HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
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if (dev->info->exit) {
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dev->info->exit(dev); |
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} |
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return 0; |
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} |
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void hda_codec_register(HDACodecDeviceInfo *info)
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{ |
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info->qdev.init = hda_codec_dev_init; |
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info->qdev.exit = hda_codec_dev_exit; |
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info->qdev.bus_info = &hda_codec_bus_info; |
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qdev_register(&info->qdev); |
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} |
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|
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HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad) |
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{ |
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DeviceState *qdev; |
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HDACodecDevice *cdev; |
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QLIST_FOREACH(qdev, &bus->qbus.children, sibling) { |
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cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
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if (cdev->cad == cad) {
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return cdev;
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} |
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} |
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return NULL; |
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} |
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void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response) |
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{ |
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HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
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bus->response(dev, solicited, response); |
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} |
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bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, |
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uint8_t *buf, uint32_t len) |
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{ |
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HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
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return bus->xfer(dev, stnr, output, buf, len);
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} |
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|
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/* --------------------------------------------------------------------- */
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/* intel hda emulation */
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typedef struct IntelHDAStream IntelHDAStream; |
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typedef struct IntelHDAState IntelHDAState; |
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typedef struct IntelHDAReg IntelHDAReg; |
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|
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typedef struct bpl { |
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uint64_t addr; |
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uint32_t len; |
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uint32_t flags; |
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} bpl; |
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struct IntelHDAStream {
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/* registers */
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uint32_t ctl; |
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uint32_t lpib; |
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uint32_t cbl; |
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uint32_t lvi; |
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uint32_t fmt; |
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uint32_t bdlp_lbase; |
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uint32_t bdlp_ubase; |
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/* state */
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bpl *bpl; |
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uint32_t bentries; |
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uint32_t bsize, be, bp; |
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}; |
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struct IntelHDAState {
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PCIDevice pci; |
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const char *name; |
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HDACodecBus codecs; |
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|
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/* registers */
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uint32_t g_ctl; |
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uint32_t wake_en; |
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uint32_t state_sts; |
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uint32_t int_ctl; |
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uint32_t int_sts; |
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uint32_t wall_clk; |
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|
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uint32_t corb_lbase; |
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uint32_t corb_ubase; |
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uint32_t corb_rp; |
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uint32_t corb_wp; |
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uint32_t corb_ctl; |
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uint32_t corb_sts; |
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uint32_t corb_size; |
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uint32_t rirb_lbase; |
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uint32_t rirb_ubase; |
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uint32_t rirb_wp; |
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uint32_t rirb_cnt; |
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uint32_t rirb_ctl; |
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uint32_t rirb_sts; |
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uint32_t rirb_size; |
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uint32_t dp_lbase; |
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uint32_t dp_ubase; |
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uint32_t icw; |
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uint32_t irr; |
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uint32_t ics; |
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/* streams */
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IntelHDAStream st[8];
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/* state */
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int mmio_addr;
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uint32_t rirb_count; |
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int64_t wall_base_ns; |
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/* debug logging */
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const IntelHDAReg *last_reg;
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uint32_t last_val; |
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uint32_t last_write; |
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uint32_t last_sec; |
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uint32_t repeat_count; |
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/* properties */
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uint32_t debug; |
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uint32_t msi; |
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}; |
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struct IntelHDAReg {
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const char *name; /* register name */ |
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uint32_t size; /* size in bytes */
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uint32_t reset; /* reset value */
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uint32_t wmask; /* write mask */
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uint32_t wclear; /* write 1 to clear bits */
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uint32_t offset; /* location in IntelHDAState */
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uint32_t shift; /* byte access entries for dwords */
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uint32_t stream; |
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void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old); |
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void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg); |
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}; |
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static void intel_hda_reset(DeviceState *dev); |
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/* --------------------------------------------------------------------- */
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static target_phys_addr_t intel_hda_addr(uint32_t lbase, uint32_t ubase)
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{ |
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target_phys_addr_t addr; |
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#if TARGET_PHYS_ADDR_BITS == 32 |
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addr = lbase; |
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#else
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addr = ubase; |
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addr <<= 32;
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addr |= lbase; |
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#endif
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return addr;
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} |
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static void stl_phys_le(target_phys_addr_t addr, uint32_t value) |
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{ |
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uint32_t value_le = cpu_to_le32(value); |
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cpu_physical_memory_write(addr, (uint8_t*)(&value_le), sizeof(value_le));
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} |
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static uint32_t ldl_phys_le(target_phys_addr_t addr)
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{ |
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uint32_t value_le; |
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cpu_physical_memory_read(addr, (uint8_t*)(&value_le), sizeof(value_le));
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return le32_to_cpu(value_le);
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} |
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static void intel_hda_update_int_sts(IntelHDAState *d) |
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{ |
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uint32_t sts = 0;
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uint32_t i; |
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/* update controller status */
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if (d->rirb_sts & ICH6_RBSTS_IRQ) {
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sts |= (1 << 30); |
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} |
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if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
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sts |= (1 << 30); |
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} |
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if (d->state_sts & d->wake_en) {
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sts |= (1 << 30); |
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} |
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/* update stream status */
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for (i = 0; i < 8; i++) { |
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/* buffer completion interrupt */
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if (d->st[i].ctl & (1 << 26)) { |
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sts |= (1 << i);
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} |
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} |
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/* update global status */
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if (sts & d->int_ctl) {
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sts |= (1 << 31); |
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} |
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d->int_sts = sts; |
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} |
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static void intel_hda_update_irq(IntelHDAState *d) |
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{ |
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int msi = d->msi && msi_enabled(&d->pci);
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int level;
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intel_hda_update_int_sts(d); |
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if (d->int_sts & (1 << 31) && d->int_ctl & (1 << 31)) { |
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level = 1;
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} else {
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level = 0;
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} |
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dprint(d, 2, "%s: level %d [%s]\n", __FUNCTION__, |
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level, msi ? "msi" : "intx"); |
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if (msi) {
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if (level) {
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msi_notify(&d->pci, 0);
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} |
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} else {
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qemu_set_irq(d->pci.irq[0], level);
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} |
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} |
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static int intel_hda_send_command(IntelHDAState *d, uint32_t verb) |
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{ |
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uint32_t cad, nid, data; |
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HDACodecDevice *codec; |
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cad = (verb >> 28) & 0x0f; |
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if (verb & (1 << 27)) { |
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/* indirect node addressing, not specified in HDA 1.0 */
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dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__); |
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return -1; |
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} |
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nid = (verb >> 20) & 0x7f; |
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data = verb & 0xfffff;
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codec = hda_codec_find(&d->codecs, cad); |
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if (codec == NULL) { |
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dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__); |
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return -1; |
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} |
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codec->info->command(codec, nid, data); |
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return 0; |
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} |
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|
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static void intel_hda_corb_run(IntelHDAState *d) |
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{ |
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target_phys_addr_t addr; |
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uint32_t rp, verb; |
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|
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if (d->ics & ICH6_IRS_BUSY) {
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dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw); |
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intel_hda_send_command(d, d->icw); |
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return;
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} |
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|
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for (;;) {
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if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
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dprint(d, 2, "%s: !run\n", __FUNCTION__); |
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return;
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} |
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if ((d->corb_rp & 0xff) == d->corb_wp) { |
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dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__); |
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return;
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} |
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if (d->rirb_count == d->rirb_cnt) {
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dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__); |
339 |
return;
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} |
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|
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rp = (d->corb_rp + 1) & 0xff; |
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addr = intel_hda_addr(d->corb_lbase, d->corb_ubase); |
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verb = ldl_phys_le(addr + 4*rp);
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d->corb_rp = rp; |
346 |
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dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb); |
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intel_hda_send_command(d, verb); |
349 |
} |
350 |
} |
351 |
|
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static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response) |
353 |
{ |
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HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
355 |
IntelHDAState *d = container_of(bus, IntelHDAState, codecs); |
356 |
target_phys_addr_t addr; |
357 |
uint32_t wp, ex; |
358 |
|
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if (d->ics & ICH6_IRS_BUSY) {
|
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dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n", |
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__FUNCTION__, response, dev->cad); |
362 |
d->irr = response; |
363 |
d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
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d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
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return;
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} |
367 |
|
368 |
if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
|
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dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__); |
370 |
return;
|
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} |
372 |
|
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ex = (solicited ? 0 : (1 << 4)) | dev->cad; |
374 |
wp = (d->rirb_wp + 1) & 0xff; |
375 |
addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase); |
376 |
stl_phys_le(addr + 8*wp, response);
|
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stl_phys_le(addr + 8*wp + 4, ex); |
378 |
d->rirb_wp = wp; |
379 |
|
380 |
dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n", |
381 |
__FUNCTION__, wp, response, ex); |
382 |
|
383 |
d->rirb_count++; |
384 |
if (d->rirb_count == d->rirb_cnt) {
|
385 |
dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count); |
386 |
if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
|
387 |
d->rirb_sts |= ICH6_RBSTS_IRQ; |
388 |
intel_hda_update_irq(d); |
389 |
} |
390 |
} else if ((d->corb_rp & 0xff) == d->corb_wp) { |
391 |
dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__, |
392 |
d->rirb_count, d->rirb_cnt); |
393 |
if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
|
394 |
d->rirb_sts |= ICH6_RBSTS_IRQ; |
395 |
intel_hda_update_irq(d); |
396 |
} |
397 |
} |
398 |
} |
399 |
|
400 |
static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, |
401 |
uint8_t *buf, uint32_t len) |
402 |
{ |
403 |
HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
404 |
IntelHDAState *d = container_of(bus, IntelHDAState, codecs); |
405 |
IntelHDAStream *st = NULL;
|
406 |
target_phys_addr_t addr; |
407 |
uint32_t s, copy, left; |
408 |
bool irq = false; |
409 |
|
410 |
for (s = 0; s < ARRAY_SIZE(d->st); s++) { |
411 |
if (stnr == ((d->st[s].ctl >> 20) & 0x0f)) { |
412 |
st = d->st + s; |
413 |
break;
|
414 |
} |
415 |
} |
416 |
if (st == NULL) { |
417 |
return false; |
418 |
} |
419 |
if (st->bpl == NULL) { |
420 |
return false; |
421 |
} |
422 |
if (st->ctl & (1 << 26)) { |
423 |
/*
|
424 |
* Wait with the next DMA xfer until the guest
|
425 |
* has acked the buffer completion interrupt
|
426 |
*/
|
427 |
return false; |
428 |
} |
429 |
|
430 |
left = len; |
431 |
while (left > 0) { |
432 |
copy = left; |
433 |
if (copy > st->bsize - st->lpib)
|
434 |
copy = st->bsize - st->lpib; |
435 |
if (copy > st->bpl[st->be].len - st->bp)
|
436 |
copy = st->bpl[st->be].len - st->bp; |
437 |
|
438 |
dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n", |
439 |
st->be, st->bp, st->bpl[st->be].len, copy); |
440 |
|
441 |
cpu_physical_memory_rw(st->bpl[st->be].addr + st->bp, |
442 |
buf, copy, !output); |
443 |
st->lpib += copy; |
444 |
st->bp += copy; |
445 |
buf += copy; |
446 |
left -= copy; |
447 |
|
448 |
if (st->bpl[st->be].len == st->bp) {
|
449 |
/* bpl entry filled */
|
450 |
if (st->bpl[st->be].flags & 0x01) { |
451 |
irq = true;
|
452 |
} |
453 |
st->bp = 0;
|
454 |
st->be++; |
455 |
if (st->be == st->bentries) {
|
456 |
/* bpl wrap around */
|
457 |
st->be = 0;
|
458 |
st->lpib = 0;
|
459 |
} |
460 |
} |
461 |
} |
462 |
if (d->dp_lbase & 0x01) { |
463 |
addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
|
464 |
stl_phys_le(addr + 8*s, st->lpib);
|
465 |
} |
466 |
dprint(d, 3, "dma: --\n"); |
467 |
|
468 |
if (irq) {
|
469 |
st->ctl |= (1 << 26); /* buffer completion interrupt */ |
470 |
intel_hda_update_irq(d); |
471 |
} |
472 |
return true; |
473 |
} |
474 |
|
475 |
static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st) |
476 |
{ |
477 |
target_phys_addr_t addr; |
478 |
uint8_t buf[16];
|
479 |
uint32_t i; |
480 |
|
481 |
addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase); |
482 |
st->bentries = st->lvi +1;
|
483 |
qemu_free(st->bpl); |
484 |
st->bpl = qemu_malloc(sizeof(bpl) * st->bentries);
|
485 |
for (i = 0; i < st->bentries; i++, addr += 16) { |
486 |
cpu_physical_memory_read(addr, buf, 16);
|
487 |
st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf); |
488 |
st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
|
489 |
st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
|
490 |
dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n", |
491 |
i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags); |
492 |
} |
493 |
|
494 |
st->bsize = st->cbl; |
495 |
st->lpib = 0;
|
496 |
st->be = 0;
|
497 |
st->bp = 0;
|
498 |
} |
499 |
|
500 |
static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running) |
501 |
{ |
502 |
DeviceState *qdev; |
503 |
HDACodecDevice *cdev; |
504 |
|
505 |
QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) { |
506 |
cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
507 |
if (cdev->info->stream) {
|
508 |
cdev->info->stream(cdev, stream, running); |
509 |
} |
510 |
} |
511 |
} |
512 |
|
513 |
/* --------------------------------------------------------------------- */
|
514 |
|
515 |
static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
516 |
{ |
517 |
if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { |
518 |
intel_hda_reset(&d->pci.qdev); |
519 |
} |
520 |
} |
521 |
|
522 |
static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
523 |
{ |
524 |
intel_hda_update_irq(d); |
525 |
} |
526 |
|
527 |
static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
528 |
{ |
529 |
intel_hda_update_irq(d); |
530 |
} |
531 |
|
532 |
static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
533 |
{ |
534 |
intel_hda_update_irq(d); |
535 |
} |
536 |
|
537 |
static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg) |
538 |
{ |
539 |
int64_t ns; |
540 |
|
541 |
ns = qemu_get_clock_ns(vm_clock) - d->wall_base_ns; |
542 |
d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ |
543 |
} |
544 |
|
545 |
static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
546 |
{ |
547 |
intel_hda_corb_run(d); |
548 |
} |
549 |
|
550 |
static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
551 |
{ |
552 |
intel_hda_corb_run(d); |
553 |
} |
554 |
|
555 |
static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
556 |
{ |
557 |
if (d->rirb_wp & ICH6_RIRBWP_RST) {
|
558 |
d->rirb_wp = 0;
|
559 |
} |
560 |
} |
561 |
|
562 |
static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
563 |
{ |
564 |
intel_hda_update_irq(d); |
565 |
|
566 |
if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
|
567 |
/* cleared ICH6_RBSTS_IRQ */
|
568 |
d->rirb_count = 0;
|
569 |
intel_hda_corb_run(d); |
570 |
} |
571 |
} |
572 |
|
573 |
static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
574 |
{ |
575 |
if (d->ics & ICH6_IRS_BUSY) {
|
576 |
intel_hda_corb_run(d); |
577 |
} |
578 |
} |
579 |
|
580 |
static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
581 |
{ |
582 |
IntelHDAStream *st = d->st + reg->stream; |
583 |
|
584 |
if (st->ctl & 0x01) { |
585 |
/* reset */
|
586 |
dprint(d, 1, "st #%d: reset\n", reg->stream); |
587 |
st->ctl = 0;
|
588 |
} |
589 |
if ((st->ctl & 0x02) != (old & 0x02)) { |
590 |
uint32_t stnr = (st->ctl >> 20) & 0x0f; |
591 |
/* run bit flipped */
|
592 |
if (st->ctl & 0x02) { |
593 |
/* start */
|
594 |
dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n", |
595 |
reg->stream, stnr, st->cbl); |
596 |
intel_hda_parse_bdl(d, st); |
597 |
intel_hda_notify_codecs(d, stnr, true);
|
598 |
} else {
|
599 |
/* stop */
|
600 |
dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr); |
601 |
intel_hda_notify_codecs(d, stnr, false);
|
602 |
} |
603 |
} |
604 |
intel_hda_update_irq(d); |
605 |
} |
606 |
|
607 |
/* --------------------------------------------------------------------- */
|
608 |
|
609 |
#define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o)) |
610 |
|
611 |
static const struct IntelHDAReg regtab[] = { |
612 |
/* global */
|
613 |
[ ICH6_REG_GCAP ] = { |
614 |
.name = "GCAP",
|
615 |
.size = 2,
|
616 |
.reset = 0x4401,
|
617 |
}, |
618 |
[ ICH6_REG_VMIN ] = { |
619 |
.name = "VMIN",
|
620 |
.size = 1,
|
621 |
}, |
622 |
[ ICH6_REG_VMAJ ] = { |
623 |
.name = "VMAJ",
|
624 |
.size = 1,
|
625 |
.reset = 1,
|
626 |
}, |
627 |
[ ICH6_REG_OUTPAY ] = { |
628 |
.name = "OUTPAY",
|
629 |
.size = 2,
|
630 |
.reset = 0x3c,
|
631 |
}, |
632 |
[ ICH6_REG_INPAY ] = { |
633 |
.name = "INPAY",
|
634 |
.size = 2,
|
635 |
.reset = 0x1d,
|
636 |
}, |
637 |
[ ICH6_REG_GCTL ] = { |
638 |
.name = "GCTL",
|
639 |
.size = 4,
|
640 |
.wmask = 0x0103,
|
641 |
.offset = offsetof(IntelHDAState, g_ctl), |
642 |
.whandler = intel_hda_set_g_ctl, |
643 |
}, |
644 |
[ ICH6_REG_WAKEEN ] = { |
645 |
.name = "WAKEEN",
|
646 |
.size = 2,
|
647 |
.wmask = 0x7fff,
|
648 |
.offset = offsetof(IntelHDAState, wake_en), |
649 |
.whandler = intel_hda_set_wake_en, |
650 |
}, |
651 |
[ ICH6_REG_STATESTS ] = { |
652 |
.name = "STATESTS",
|
653 |
.size = 2,
|
654 |
.wmask = 0x7fff,
|
655 |
.wclear = 0x7fff,
|
656 |
.offset = offsetof(IntelHDAState, state_sts), |
657 |
.whandler = intel_hda_set_state_sts, |
658 |
}, |
659 |
|
660 |
/* interrupts */
|
661 |
[ ICH6_REG_INTCTL ] = { |
662 |
.name = "INTCTL",
|
663 |
.size = 4,
|
664 |
.wmask = 0xc00000ff,
|
665 |
.offset = offsetof(IntelHDAState, int_ctl), |
666 |
.whandler = intel_hda_set_int_ctl, |
667 |
}, |
668 |
[ ICH6_REG_INTSTS ] = { |
669 |
.name = "INTSTS",
|
670 |
.size = 4,
|
671 |
.wmask = 0xc00000ff,
|
672 |
.wclear = 0xc00000ff,
|
673 |
.offset = offsetof(IntelHDAState, int_sts), |
674 |
}, |
675 |
|
676 |
/* misc */
|
677 |
[ ICH6_REG_WALLCLK ] = { |
678 |
.name = "WALLCLK",
|
679 |
.size = 4,
|
680 |
.offset = offsetof(IntelHDAState, wall_clk), |
681 |
.rhandler = intel_hda_get_wall_clk, |
682 |
}, |
683 |
[ ICH6_REG_WALLCLK + 0x2000 ] = {
|
684 |
.name = "WALLCLK(alias)",
|
685 |
.size = 4,
|
686 |
.offset = offsetof(IntelHDAState, wall_clk), |
687 |
.rhandler = intel_hda_get_wall_clk, |
688 |
}, |
689 |
|
690 |
/* dma engine */
|
691 |
[ ICH6_REG_CORBLBASE ] = { |
692 |
.name = "CORBLBASE",
|
693 |
.size = 4,
|
694 |
.wmask = 0xffffff80,
|
695 |
.offset = offsetof(IntelHDAState, corb_lbase), |
696 |
}, |
697 |
[ ICH6_REG_CORBUBASE ] = { |
698 |
.name = "CORBUBASE",
|
699 |
.size = 4,
|
700 |
.wmask = 0xffffffff,
|
701 |
.offset = offsetof(IntelHDAState, corb_ubase), |
702 |
}, |
703 |
[ ICH6_REG_CORBWP ] = { |
704 |
.name = "CORBWP",
|
705 |
.size = 2,
|
706 |
.wmask = 0xff,
|
707 |
.offset = offsetof(IntelHDAState, corb_wp), |
708 |
.whandler = intel_hda_set_corb_wp, |
709 |
}, |
710 |
[ ICH6_REG_CORBRP ] = { |
711 |
.name = "CORBRP",
|
712 |
.size = 2,
|
713 |
.wmask = 0x80ff,
|
714 |
.offset = offsetof(IntelHDAState, corb_rp), |
715 |
}, |
716 |
[ ICH6_REG_CORBCTL ] = { |
717 |
.name = "CORBCTL",
|
718 |
.size = 1,
|
719 |
.wmask = 0x03,
|
720 |
.offset = offsetof(IntelHDAState, corb_ctl), |
721 |
.whandler = intel_hda_set_corb_ctl, |
722 |
}, |
723 |
[ ICH6_REG_CORBSTS ] = { |
724 |
.name = "CORBSTS",
|
725 |
.size = 1,
|
726 |
.wmask = 0x01,
|
727 |
.wclear = 0x01,
|
728 |
.offset = offsetof(IntelHDAState, corb_sts), |
729 |
}, |
730 |
[ ICH6_REG_CORBSIZE ] = { |
731 |
.name = "CORBSIZE",
|
732 |
.size = 1,
|
733 |
.reset = 0x42,
|
734 |
.offset = offsetof(IntelHDAState, corb_size), |
735 |
}, |
736 |
[ ICH6_REG_RIRBLBASE ] = { |
737 |
.name = "RIRBLBASE",
|
738 |
.size = 4,
|
739 |
.wmask = 0xffffff80,
|
740 |
.offset = offsetof(IntelHDAState, rirb_lbase), |
741 |
}, |
742 |
[ ICH6_REG_RIRBUBASE ] = { |
743 |
.name = "RIRBUBASE",
|
744 |
.size = 4,
|
745 |
.wmask = 0xffffffff,
|
746 |
.offset = offsetof(IntelHDAState, rirb_ubase), |
747 |
}, |
748 |
[ ICH6_REG_RIRBWP ] = { |
749 |
.name = "RIRBWP",
|
750 |
.size = 2,
|
751 |
.wmask = 0x8000,
|
752 |
.offset = offsetof(IntelHDAState, rirb_wp), |
753 |
.whandler = intel_hda_set_rirb_wp, |
754 |
}, |
755 |
[ ICH6_REG_RINTCNT ] = { |
756 |
.name = "RINTCNT",
|
757 |
.size = 2,
|
758 |
.wmask = 0xff,
|
759 |
.offset = offsetof(IntelHDAState, rirb_cnt), |
760 |
}, |
761 |
[ ICH6_REG_RIRBCTL ] = { |
762 |
.name = "RIRBCTL",
|
763 |
.size = 1,
|
764 |
.wmask = 0x07,
|
765 |
.offset = offsetof(IntelHDAState, rirb_ctl), |
766 |
}, |
767 |
[ ICH6_REG_RIRBSTS ] = { |
768 |
.name = "RIRBSTS",
|
769 |
.size = 1,
|
770 |
.wmask = 0x05,
|
771 |
.wclear = 0x05,
|
772 |
.offset = offsetof(IntelHDAState, rirb_sts), |
773 |
.whandler = intel_hda_set_rirb_sts, |
774 |
}, |
775 |
[ ICH6_REG_RIRBSIZE ] = { |
776 |
.name = "RIRBSIZE",
|
777 |
.size = 1,
|
778 |
.reset = 0x42,
|
779 |
.offset = offsetof(IntelHDAState, rirb_size), |
780 |
}, |
781 |
|
782 |
[ ICH6_REG_DPLBASE ] = { |
783 |
.name = "DPLBASE",
|
784 |
.size = 4,
|
785 |
.wmask = 0xffffff81,
|
786 |
.offset = offsetof(IntelHDAState, dp_lbase), |
787 |
}, |
788 |
[ ICH6_REG_DPUBASE ] = { |
789 |
.name = "DPUBASE",
|
790 |
.size = 4,
|
791 |
.wmask = 0xffffffff,
|
792 |
.offset = offsetof(IntelHDAState, dp_ubase), |
793 |
}, |
794 |
|
795 |
[ ICH6_REG_IC ] = { |
796 |
.name = "ICW",
|
797 |
.size = 4,
|
798 |
.wmask = 0xffffffff,
|
799 |
.offset = offsetof(IntelHDAState, icw), |
800 |
}, |
801 |
[ ICH6_REG_IR ] = { |
802 |
.name = "IRR",
|
803 |
.size = 4,
|
804 |
.offset = offsetof(IntelHDAState, irr), |
805 |
}, |
806 |
[ ICH6_REG_IRS ] = { |
807 |
.name = "ICS",
|
808 |
.size = 2,
|
809 |
.wmask = 0x0003,
|
810 |
.wclear = 0x0002,
|
811 |
.offset = offsetof(IntelHDAState, ics), |
812 |
.whandler = intel_hda_set_ics, |
813 |
}, |
814 |
|
815 |
#define HDA_STREAM(_t, _i) \
|
816 |
[ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \ |
817 |
.stream = _i, \ |
818 |
.name = _t stringify(_i) " CTL", \
|
819 |
.size = 4, \
|
820 |
.wmask = 0x1cff001f, \
|
821 |
.offset = offsetof(IntelHDAState, st[_i].ctl), \ |
822 |
.whandler = intel_hda_set_st_ctl, \ |
823 |
}, \ |
824 |
[ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
|
825 |
.stream = _i, \ |
826 |
.name = _t stringify(_i) " CTL(stnr)", \
|
827 |
.size = 1, \
|
828 |
.shift = 16, \
|
829 |
.wmask = 0x00ff0000, \
|
830 |
.offset = offsetof(IntelHDAState, st[_i].ctl), \ |
831 |
.whandler = intel_hda_set_st_ctl, \ |
832 |
}, \ |
833 |
[ ST_REG(_i, ICH6_REG_SD_STS)] = { \ |
834 |
.stream = _i, \ |
835 |
.name = _t stringify(_i) " CTL(sts)", \
|
836 |
.size = 1, \
|
837 |
.shift = 24, \
|
838 |
.wmask = 0x1c000000, \
|
839 |
.wclear = 0x1c000000, \
|
840 |
.offset = offsetof(IntelHDAState, st[_i].ctl), \ |
841 |
.whandler = intel_hda_set_st_ctl, \ |
842 |
}, \ |
843 |
[ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \ |
844 |
.stream = _i, \ |
845 |
.name = _t stringify(_i) " LPIB", \
|
846 |
.size = 4, \
|
847 |
.offset = offsetof(IntelHDAState, st[_i].lpib), \ |
848 |
}, \ |
849 |
[ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
|
850 |
.stream = _i, \ |
851 |
.name = _t stringify(_i) " LPIB(alias)", \
|
852 |
.size = 4, \
|
853 |
.offset = offsetof(IntelHDAState, st[_i].lpib), \ |
854 |
}, \ |
855 |
[ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \ |
856 |
.stream = _i, \ |
857 |
.name = _t stringify(_i) " CBL", \
|
858 |
.size = 4, \
|
859 |
.wmask = 0xffffffff, \
|
860 |
.offset = offsetof(IntelHDAState, st[_i].cbl), \ |
861 |
}, \ |
862 |
[ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \ |
863 |
.stream = _i, \ |
864 |
.name = _t stringify(_i) " LVI", \
|
865 |
.size = 2, \
|
866 |
.wmask = 0x00ff, \
|
867 |
.offset = offsetof(IntelHDAState, st[_i].lvi), \ |
868 |
}, \ |
869 |
[ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \ |
870 |
.stream = _i, \ |
871 |
.name = _t stringify(_i) " FIFOS", \
|
872 |
.size = 2, \
|
873 |
.reset = HDA_BUFFER_SIZE, \ |
874 |
}, \ |
875 |
[ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \ |
876 |
.stream = _i, \ |
877 |
.name = _t stringify(_i) " FMT", \
|
878 |
.size = 2, \
|
879 |
.wmask = 0x7f7f, \
|
880 |
.offset = offsetof(IntelHDAState, st[_i].fmt), \ |
881 |
}, \ |
882 |
[ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \ |
883 |
.stream = _i, \ |
884 |
.name = _t stringify(_i) " BDLPL", \
|
885 |
.size = 4, \
|
886 |
.wmask = 0xffffff80, \
|
887 |
.offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \ |
888 |
}, \ |
889 |
[ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \ |
890 |
.stream = _i, \ |
891 |
.name = _t stringify(_i) " BDLPU", \
|
892 |
.size = 4, \
|
893 |
.wmask = 0xffffffff, \
|
894 |
.offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \ |
895 |
}, \ |
896 |
|
897 |
HDA_STREAM("IN", 0) |
898 |
HDA_STREAM("IN", 1) |
899 |
HDA_STREAM("IN", 2) |
900 |
HDA_STREAM("IN", 3) |
901 |
|
902 |
HDA_STREAM("OUT", 4) |
903 |
HDA_STREAM("OUT", 5) |
904 |
HDA_STREAM("OUT", 6) |
905 |
HDA_STREAM("OUT", 7) |
906 |
|
907 |
}; |
908 |
|
909 |
static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, target_phys_addr_t addr) |
910 |
{ |
911 |
const IntelHDAReg *reg;
|
912 |
|
913 |
if (addr >= sizeof(regtab)/sizeof(regtab[0])) { |
914 |
goto noreg;
|
915 |
} |
916 |
reg = regtab+addr; |
917 |
if (reg->name == NULL) { |
918 |
goto noreg;
|
919 |
} |
920 |
return reg;
|
921 |
|
922 |
noreg:
|
923 |
dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr); |
924 |
return NULL; |
925 |
} |
926 |
|
927 |
static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg) |
928 |
{ |
929 |
uint8_t *addr = (void*)d;
|
930 |
|
931 |
addr += reg->offset; |
932 |
return (uint32_t*)addr;
|
933 |
} |
934 |
|
935 |
static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val, |
936 |
uint32_t wmask) |
937 |
{ |
938 |
uint32_t *addr; |
939 |
uint32_t old; |
940 |
|
941 |
if (!reg) {
|
942 |
return;
|
943 |
} |
944 |
|
945 |
if (d->debug) {
|
946 |
time_t now = time(NULL);
|
947 |
if (d->last_write && d->last_reg == reg && d->last_val == val) {
|
948 |
d->repeat_count++; |
949 |
if (d->last_sec != now) {
|
950 |
dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
951 |
d->last_sec = now; |
952 |
d->repeat_count = 0;
|
953 |
} |
954 |
} else {
|
955 |
if (d->repeat_count) {
|
956 |
dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
957 |
} |
958 |
dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask); |
959 |
d->last_write = 1;
|
960 |
d->last_reg = reg; |
961 |
d->last_val = val; |
962 |
d->last_sec = now; |
963 |
d->repeat_count = 0;
|
964 |
} |
965 |
} |
966 |
assert(reg->offset != 0);
|
967 |
|
968 |
addr = intel_hda_reg_addr(d, reg); |
969 |
old = *addr; |
970 |
|
971 |
if (reg->shift) {
|
972 |
val <<= reg->shift; |
973 |
wmask <<= reg->shift; |
974 |
} |
975 |
wmask &= reg->wmask; |
976 |
*addr &= ~wmask; |
977 |
*addr |= wmask & val; |
978 |
*addr &= ~(val & reg->wclear); |
979 |
|
980 |
if (reg->whandler) {
|
981 |
reg->whandler(d, reg, old); |
982 |
} |
983 |
} |
984 |
|
985 |
static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg, |
986 |
uint32_t rmask) |
987 |
{ |
988 |
uint32_t *addr, ret; |
989 |
|
990 |
if (!reg) {
|
991 |
return 0; |
992 |
} |
993 |
|
994 |
if (reg->rhandler) {
|
995 |
reg->rhandler(d, reg); |
996 |
} |
997 |
|
998 |
if (reg->offset == 0) { |
999 |
/* constant read-only register */
|
1000 |
ret = reg->reset; |
1001 |
} else {
|
1002 |
addr = intel_hda_reg_addr(d, reg); |
1003 |
ret = *addr; |
1004 |
if (reg->shift) {
|
1005 |
ret >>= reg->shift; |
1006 |
} |
1007 |
ret &= rmask; |
1008 |
} |
1009 |
if (d->debug) {
|
1010 |
time_t now = time(NULL);
|
1011 |
if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
|
1012 |
d->repeat_count++; |
1013 |
if (d->last_sec != now) {
|
1014 |
dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
1015 |
d->last_sec = now; |
1016 |
d->repeat_count = 0;
|
1017 |
} |
1018 |
} else {
|
1019 |
if (d->repeat_count) {
|
1020 |
dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
1021 |
} |
1022 |
dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask); |
1023 |
d->last_write = 0;
|
1024 |
d->last_reg = reg; |
1025 |
d->last_val = ret; |
1026 |
d->last_sec = now; |
1027 |
d->repeat_count = 0;
|
1028 |
} |
1029 |
} |
1030 |
return ret;
|
1031 |
} |
1032 |
|
1033 |
static void intel_hda_regs_reset(IntelHDAState *d) |
1034 |
{ |
1035 |
uint32_t *addr; |
1036 |
int i;
|
1037 |
|
1038 |
for (i = 0; i < sizeof(regtab)/sizeof(regtab[0]); i++) { |
1039 |
if (regtab[i].name == NULL) { |
1040 |
continue;
|
1041 |
} |
1042 |
if (regtab[i].offset == 0) { |
1043 |
continue;
|
1044 |
} |
1045 |
addr = intel_hda_reg_addr(d, regtab + i); |
1046 |
*addr = regtab[i].reset; |
1047 |
} |
1048 |
} |
1049 |
|
1050 |
/* --------------------------------------------------------------------- */
|
1051 |
|
1052 |
static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
1053 |
{ |
1054 |
IntelHDAState *d = opaque; |
1055 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
1056 |
|
1057 |
intel_hda_reg_write(d, reg, val, 0xff);
|
1058 |
} |
1059 |
|
1060 |
static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
1061 |
{ |
1062 |
IntelHDAState *d = opaque; |
1063 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
1064 |
|
1065 |
intel_hda_reg_write(d, reg, val, 0xffff);
|
1066 |
} |
1067 |
|
1068 |
static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
1069 |
{ |
1070 |
IntelHDAState *d = opaque; |
1071 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
1072 |
|
1073 |
intel_hda_reg_write(d, reg, val, 0xffffffff);
|
1074 |
} |
1075 |
|
1076 |
static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr) |
1077 |
{ |
1078 |
IntelHDAState *d = opaque; |
1079 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
1080 |
|
1081 |
return intel_hda_reg_read(d, reg, 0xff); |
1082 |
} |
1083 |
|
1084 |
static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr) |
1085 |
{ |
1086 |
IntelHDAState *d = opaque; |
1087 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
1088 |
|
1089 |
return intel_hda_reg_read(d, reg, 0xffff); |
1090 |
} |
1091 |
|
1092 |
static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr) |
1093 |
{ |
1094 |
IntelHDAState *d = opaque; |
1095 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
1096 |
|
1097 |
return intel_hda_reg_read(d, reg, 0xffffffff); |
1098 |
} |
1099 |
|
1100 |
static CPUReadMemoryFunc * const intel_hda_mmio_read[3] = { |
1101 |
intel_hda_mmio_readb, |
1102 |
intel_hda_mmio_readw, |
1103 |
intel_hda_mmio_readl, |
1104 |
}; |
1105 |
|
1106 |
static CPUWriteMemoryFunc * const intel_hda_mmio_write[3] = { |
1107 |
intel_hda_mmio_writeb, |
1108 |
intel_hda_mmio_writew, |
1109 |
intel_hda_mmio_writel, |
1110 |
}; |
1111 |
|
1112 |
/* --------------------------------------------------------------------- */
|
1113 |
|
1114 |
static void intel_hda_reset(DeviceState *dev) |
1115 |
{ |
1116 |
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci.qdev, dev); |
1117 |
DeviceState *qdev; |
1118 |
HDACodecDevice *cdev; |
1119 |
|
1120 |
intel_hda_regs_reset(d); |
1121 |
d->wall_base_ns = qemu_get_clock_ns(vm_clock); |
1122 |
|
1123 |
/* reset codecs */
|
1124 |
QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) { |
1125 |
cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
1126 |
if (qdev->info->reset) {
|
1127 |
qdev->info->reset(qdev); |
1128 |
} |
1129 |
d->state_sts |= (1 << cdev->cad);
|
1130 |
} |
1131 |
intel_hda_update_irq(d); |
1132 |
} |
1133 |
|
1134 |
static int intel_hda_init(PCIDevice *pci) |
1135 |
{ |
1136 |
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); |
1137 |
uint8_t *conf = d->pci.config; |
1138 |
|
1139 |
d->name = d->pci.qdev.info->name; |
1140 |
|
1141 |
pci_config_set_vendor_id(conf, PCI_VENDOR_ID_INTEL); |
1142 |
pci_config_set_device_id(conf, 0x2668);
|
1143 |
pci_config_set_revision(conf, 1);
|
1144 |
pci_config_set_class(conf, PCI_CLASS_MULTIMEDIA_HD_AUDIO); |
1145 |
pci_config_set_interrupt_pin(conf, 1);
|
1146 |
|
1147 |
/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
|
1148 |
conf[0x40] = 0x01; |
1149 |
|
1150 |
d->mmio_addr = cpu_register_io_memory(intel_hda_mmio_read, |
1151 |
intel_hda_mmio_write, d, |
1152 |
DEVICE_NATIVE_ENDIAN); |
1153 |
pci_register_bar_simple(&d->pci, 0, 0x4000, 0, d->mmio_addr); |
1154 |
if (d->msi) {
|
1155 |
msi_init(&d->pci, 0x50, 1, true, false); |
1156 |
} |
1157 |
|
1158 |
hda_codec_bus_init(&d->pci.qdev, &d->codecs, |
1159 |
intel_hda_response, intel_hda_xfer); |
1160 |
|
1161 |
return 0; |
1162 |
} |
1163 |
|
1164 |
static int intel_hda_exit(PCIDevice *pci) |
1165 |
{ |
1166 |
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); |
1167 |
|
1168 |
msi_uninit(&d->pci); |
1169 |
cpu_unregister_io_memory(d->mmio_addr); |
1170 |
return 0; |
1171 |
} |
1172 |
|
1173 |
static void intel_hda_write_config(PCIDevice *pci, uint32_t addr, |
1174 |
uint32_t val, int len)
|
1175 |
{ |
1176 |
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); |
1177 |
|
1178 |
pci_default_write_config(pci, addr, val, len); |
1179 |
if (d->msi) {
|
1180 |
msi_write_config(pci, addr, val, len); |
1181 |
} |
1182 |
} |
1183 |
|
1184 |
static int intel_hda_post_load(void *opaque, int version) |
1185 |
{ |
1186 |
IntelHDAState* d = opaque; |
1187 |
int i;
|
1188 |
|
1189 |
dprint(d, 1, "%s\n", __FUNCTION__); |
1190 |
for (i = 0; i < ARRAY_SIZE(d->st); i++) { |
1191 |
if (d->st[i].ctl & 0x02) { |
1192 |
intel_hda_parse_bdl(d, &d->st[i]); |
1193 |
} |
1194 |
} |
1195 |
intel_hda_update_irq(d); |
1196 |
return 0; |
1197 |
} |
1198 |
|
1199 |
static const VMStateDescription vmstate_intel_hda_stream = { |
1200 |
.name = "intel-hda-stream",
|
1201 |
.version_id = 1,
|
1202 |
.fields = (VMStateField []) { |
1203 |
VMSTATE_UINT32(ctl, IntelHDAStream), |
1204 |
VMSTATE_UINT32(lpib, IntelHDAStream), |
1205 |
VMSTATE_UINT32(cbl, IntelHDAStream), |
1206 |
VMSTATE_UINT32(lvi, IntelHDAStream), |
1207 |
VMSTATE_UINT32(fmt, IntelHDAStream), |
1208 |
VMSTATE_UINT32(bdlp_lbase, IntelHDAStream), |
1209 |
VMSTATE_UINT32(bdlp_ubase, IntelHDAStream), |
1210 |
VMSTATE_END_OF_LIST() |
1211 |
} |
1212 |
}; |
1213 |
|
1214 |
static const VMStateDescription vmstate_intel_hda = { |
1215 |
.name = "intel-hda",
|
1216 |
.version_id = 1,
|
1217 |
.post_load = intel_hda_post_load, |
1218 |
.fields = (VMStateField []) { |
1219 |
VMSTATE_PCI_DEVICE(pci, IntelHDAState), |
1220 |
|
1221 |
/* registers */
|
1222 |
VMSTATE_UINT32(g_ctl, IntelHDAState), |
1223 |
VMSTATE_UINT32(wake_en, IntelHDAState), |
1224 |
VMSTATE_UINT32(state_sts, IntelHDAState), |
1225 |
VMSTATE_UINT32(int_ctl, IntelHDAState), |
1226 |
VMSTATE_UINT32(int_sts, IntelHDAState), |
1227 |
VMSTATE_UINT32(wall_clk, IntelHDAState), |
1228 |
VMSTATE_UINT32(corb_lbase, IntelHDAState), |
1229 |
VMSTATE_UINT32(corb_ubase, IntelHDAState), |
1230 |
VMSTATE_UINT32(corb_rp, IntelHDAState), |
1231 |
VMSTATE_UINT32(corb_wp, IntelHDAState), |
1232 |
VMSTATE_UINT32(corb_ctl, IntelHDAState), |
1233 |
VMSTATE_UINT32(corb_sts, IntelHDAState), |
1234 |
VMSTATE_UINT32(corb_size, IntelHDAState), |
1235 |
VMSTATE_UINT32(rirb_lbase, IntelHDAState), |
1236 |
VMSTATE_UINT32(rirb_ubase, IntelHDAState), |
1237 |
VMSTATE_UINT32(rirb_wp, IntelHDAState), |
1238 |
VMSTATE_UINT32(rirb_cnt, IntelHDAState), |
1239 |
VMSTATE_UINT32(rirb_ctl, IntelHDAState), |
1240 |
VMSTATE_UINT32(rirb_sts, IntelHDAState), |
1241 |
VMSTATE_UINT32(rirb_size, IntelHDAState), |
1242 |
VMSTATE_UINT32(dp_lbase, IntelHDAState), |
1243 |
VMSTATE_UINT32(dp_ubase, IntelHDAState), |
1244 |
VMSTATE_UINT32(icw, IntelHDAState), |
1245 |
VMSTATE_UINT32(irr, IntelHDAState), |
1246 |
VMSTATE_UINT32(ics, IntelHDAState), |
1247 |
VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0, |
1248 |
vmstate_intel_hda_stream, |
1249 |
IntelHDAStream), |
1250 |
|
1251 |
/* additional state info */
|
1252 |
VMSTATE_UINT32(rirb_count, IntelHDAState), |
1253 |
VMSTATE_INT64(wall_base_ns, IntelHDAState), |
1254 |
|
1255 |
VMSTATE_END_OF_LIST() |
1256 |
} |
1257 |
}; |
1258 |
|
1259 |
static PCIDeviceInfo intel_hda_info = {
|
1260 |
.qdev.name = "intel-hda",
|
1261 |
.qdev.desc = "Intel HD Audio Controller",
|
1262 |
.qdev.size = sizeof(IntelHDAState),
|
1263 |
.qdev.vmsd = &vmstate_intel_hda, |
1264 |
.qdev.reset = intel_hda_reset, |
1265 |
.init = intel_hda_init, |
1266 |
.exit = intel_hda_exit, |
1267 |
.config_write = intel_hda_write_config, |
1268 |
.qdev.props = (Property[]) { |
1269 |
DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0), |
1270 |
DEFINE_PROP_UINT32("msi", IntelHDAState, msi, 1), |
1271 |
DEFINE_PROP_END_OF_LIST(), |
1272 |
} |
1273 |
}; |
1274 |
|
1275 |
static void intel_hda_register(void) |
1276 |
{ |
1277 |
pci_qdev_register(&intel_hda_info); |
1278 |
} |
1279 |
device_init(intel_hda_register); |
1280 |
|
1281 |
/*
|
1282 |
* create intel hda controller with codec attached to it,
|
1283 |
* so '-soundhw hda' works.
|
1284 |
*/
|
1285 |
int intel_hda_and_codec_init(PCIBus *bus)
|
1286 |
{ |
1287 |
PCIDevice *controller; |
1288 |
BusState *hdabus; |
1289 |
DeviceState *codec; |
1290 |
|
1291 |
controller = pci_create_simple(bus, -1, "intel-hda"); |
1292 |
hdabus = QLIST_FIRST(&controller->qdev.child_bus); |
1293 |
codec = qdev_create(hdabus, "hda-duplex");
|
1294 |
qdev_init_nofail(codec); |
1295 |
return 0; |
1296 |
} |
1297 |
|