Revision c5631f48
| b/target-cris/translate.c | ||
|---|---|---|
| 973 | 973 |
return 0; |
| 974 | 974 |
} |
| 975 | 975 |
|
| 976 |
static void gen_tst_cc (DisasContext *dc, int cond) |
|
| 976 |
static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
|
|
| 977 | 977 |
{
|
| 978 | 978 |
int arith_opt, move_opt; |
| 979 | 979 |
|
| ... | ... | |
| 996 | 996 |
non-zero otherwise T0 should be zero. */ |
| 997 | 997 |
int l1; |
| 998 | 998 |
l1 = gen_new_label(); |
| 999 |
tcg_gen_movi_tl(cpu_T[0], 0);
|
|
| 999 |
tcg_gen_movi_tl(cc, 0);
|
|
| 1000 | 1000 |
tcg_gen_brcondi_tl(TCG_COND_NE, cc_result, |
| 1001 | 1001 |
0, l1); |
| 1002 |
tcg_gen_movi_tl(cpu_T[0], 1);
|
|
| 1002 |
tcg_gen_movi_tl(cc, 1);
|
|
| 1003 | 1003 |
gen_set_label(l1); |
| 1004 | 1004 |
} |
| 1005 | 1005 |
else {
|
| 1006 | 1006 |
cris_evaluate_flags(dc); |
| 1007 |
tcg_gen_andi_tl(cpu_T[0],
|
|
| 1007 |
tcg_gen_andi_tl(cc,
|
|
| 1008 | 1008 |
cpu_PR[PR_CCS], Z_FLAG); |
| 1009 | 1009 |
} |
| 1010 | 1010 |
break; |
| 1011 | 1011 |
case CC_NE: |
| 1012 | 1012 |
if (arith_opt || move_opt) |
| 1013 |
tcg_gen_mov_tl(cpu_T[0], cc_result);
|
|
| 1013 |
tcg_gen_mov_tl(cc, cc_result);
|
|
| 1014 | 1014 |
else {
|
| 1015 | 1015 |
cris_evaluate_flags(dc); |
| 1016 |
tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
|
|
| 1016 |
tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
|
|
| 1017 | 1017 |
Z_FLAG); |
| 1018 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
|
|
| 1018 |
tcg_gen_andi_tl(cc, cc, Z_FLAG);
|
|
| 1019 | 1019 |
} |
| 1020 | 1020 |
break; |
| 1021 | 1021 |
case CC_CS: |
| 1022 | 1022 |
cris_evaluate_flags(dc); |
| 1023 |
tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], C_FLAG);
|
|
| 1023 |
tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
|
|
| 1024 | 1024 |
break; |
| 1025 | 1025 |
case CC_CC: |
| 1026 | 1026 |
cris_evaluate_flags(dc); |
| 1027 |
tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS], C_FLAG);
|
|
| 1028 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], C_FLAG);
|
|
| 1027 |
tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
|
|
| 1028 |
tcg_gen_andi_tl(cc, cc, C_FLAG);
|
|
| 1029 | 1029 |
break; |
| 1030 | 1030 |
case CC_VS: |
| 1031 | 1031 |
cris_evaluate_flags(dc); |
| 1032 |
tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], V_FLAG);
|
|
| 1032 |
tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
|
|
| 1033 | 1033 |
break; |
| 1034 | 1034 |
case CC_VC: |
| 1035 | 1035 |
cris_evaluate_flags(dc); |
| 1036 |
tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
|
|
| 1036 |
tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
|
|
| 1037 | 1037 |
V_FLAG); |
| 1038 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], V_FLAG);
|
|
| 1038 |
tcg_gen_andi_tl(cc, cc, V_FLAG);
|
|
| 1039 | 1039 |
break; |
| 1040 | 1040 |
case CC_PL: |
| 1041 | 1041 |
if (arith_opt || move_opt) {
|
| ... | ... | |
| 1046 | 1046 |
else if (dc->cc_size == 2) |
| 1047 | 1047 |
bits = 15; |
| 1048 | 1048 |
|
| 1049 |
tcg_gen_shri_tl(cpu_T[0], cc_result, bits);
|
|
| 1050 |
tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
|
|
| 1049 |
tcg_gen_shri_tl(cc, cc_result, bits);
|
|
| 1050 |
tcg_gen_xori_tl(cc, cc, 1);
|
|
| 1051 | 1051 |
} else {
|
| 1052 | 1052 |
cris_evaluate_flags(dc); |
| 1053 |
tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
|
|
| 1053 |
tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
|
|
| 1054 | 1054 |
N_FLAG); |
| 1055 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
|
|
| 1055 |
tcg_gen_andi_tl(cc, cc, N_FLAG);
|
|
| 1056 | 1056 |
} |
| 1057 | 1057 |
break; |
| 1058 | 1058 |
case CC_MI: |
| ... | ... | |
| 1064 | 1064 |
else if (dc->cc_size == 2) |
| 1065 | 1065 |
bits = 15; |
| 1066 | 1066 |
|
| 1067 |
tcg_gen_shri_tl(cpu_T[0], cc_result, 31);
|
|
| 1067 |
tcg_gen_shri_tl(cc, cc_result, 31);
|
|
| 1068 | 1068 |
} |
| 1069 | 1069 |
else {
|
| 1070 | 1070 |
cris_evaluate_flags(dc); |
| 1071 |
tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
|
|
| 1071 |
tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
|
|
| 1072 | 1072 |
N_FLAG); |
| 1073 | 1073 |
} |
| 1074 | 1074 |
break; |
| 1075 | 1075 |
case CC_LS: |
| 1076 | 1076 |
cris_evaluate_flags(dc); |
| 1077 |
tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
|
|
| 1077 |
tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
|
|
| 1078 | 1078 |
C_FLAG | Z_FLAG); |
| 1079 | 1079 |
break; |
| 1080 | 1080 |
case CC_HI: |
| ... | ... | |
| 1086 | 1086 |
tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS], |
| 1087 | 1087 |
C_FLAG | Z_FLAG); |
| 1088 | 1088 |
/* Overlay the C flag on top of the Z. */ |
| 1089 |
tcg_gen_shli_tl(cpu_T[0], tmp, 2);
|
|
| 1090 |
tcg_gen_and_tl(cpu_T[0], tmp, cpu_T[0]);
|
|
| 1091 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
|
|
| 1089 |
tcg_gen_shli_tl(cc, tmp, 2);
|
|
| 1090 |
tcg_gen_and_tl(cc, tmp, cc);
|
|
| 1091 |
tcg_gen_andi_tl(cc, cc, Z_FLAG);
|
|
| 1092 | 1092 |
|
| 1093 | 1093 |
tcg_temp_free(tmp); |
| 1094 | 1094 |
} |
| ... | ... | |
| 1096 | 1096 |
case CC_GE: |
| 1097 | 1097 |
cris_evaluate_flags(dc); |
| 1098 | 1098 |
/* Overlay the V flag on top of the N. */ |
| 1099 |
tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
|
|
| 1100 |
tcg_gen_xor_tl(cpu_T[0],
|
|
| 1101 |
cpu_PR[PR_CCS], cpu_T[0]);
|
|
| 1102 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
|
|
| 1103 |
tcg_gen_xori_tl(cpu_T[0], cpu_T[0], N_FLAG);
|
|
| 1099 |
tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
|
|
| 1100 |
tcg_gen_xor_tl(cc,
|
|
| 1101 |
cpu_PR[PR_CCS], cc);
|
|
| 1102 |
tcg_gen_andi_tl(cc, cc, N_FLAG);
|
|
| 1103 |
tcg_gen_xori_tl(cc, cc, N_FLAG);
|
|
| 1104 | 1104 |
break; |
| 1105 | 1105 |
case CC_LT: |
| 1106 | 1106 |
cris_evaluate_flags(dc); |
| 1107 | 1107 |
/* Overlay the V flag on top of the N. */ |
| 1108 |
tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
|
|
| 1109 |
tcg_gen_xor_tl(cpu_T[0],
|
|
| 1110 |
cpu_PR[PR_CCS], cpu_T[0]);
|
|
| 1111 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
|
|
| 1108 |
tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
|
|
| 1109 |
tcg_gen_xor_tl(cc,
|
|
| 1110 |
cpu_PR[PR_CCS], cc);
|
|
| 1111 |
tcg_gen_andi_tl(cc, cc, N_FLAG);
|
|
| 1112 | 1112 |
break; |
| 1113 | 1113 |
case CC_GT: |
| 1114 | 1114 |
cris_evaluate_flags(dc); |
| ... | ... | |
| 1127 | 1127 |
|
| 1128 | 1128 |
tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]); |
| 1129 | 1129 |
tcg_gen_xori_tl(n, n, 2); |
| 1130 |
tcg_gen_and_tl(cpu_T[0], z, n);
|
|
| 1131 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
|
|
| 1130 |
tcg_gen_and_tl(cc, z, n);
|
|
| 1131 |
tcg_gen_andi_tl(cc, cc, 2);
|
|
| 1132 | 1132 |
|
| 1133 | 1133 |
tcg_temp_free(n); |
| 1134 | 1134 |
tcg_temp_free(z); |
| ... | ... | |
| 1148 | 1148 |
tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1); |
| 1149 | 1149 |
|
| 1150 | 1150 |
tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]); |
| 1151 |
tcg_gen_or_tl(cpu_T[0], z, n);
|
|
| 1152 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
|
|
| 1151 |
tcg_gen_or_tl(cc, z, n);
|
|
| 1152 |
tcg_gen_andi_tl(cc, cc, 2);
|
|
| 1153 | 1153 |
|
| 1154 | 1154 |
tcg_temp_free(n); |
| 1155 | 1155 |
tcg_temp_free(z); |
| ... | ... | |
| 1157 | 1157 |
break; |
| 1158 | 1158 |
case CC_P: |
| 1159 | 1159 |
cris_evaluate_flags(dc); |
| 1160 |
tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], P_FLAG);
|
|
| 1160 |
tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
|
|
| 1161 | 1161 |
break; |
| 1162 | 1162 |
case CC_A: |
| 1163 |
tcg_gen_movi_tl(cpu_T[0], 1);
|
|
| 1163 |
tcg_gen_movi_tl(cc, 1);
|
|
| 1164 | 1164 |
break; |
| 1165 | 1165 |
default: |
| 1166 | 1166 |
BUG(); |
| ... | ... | |
| 1188 | 1188 |
if (cond != CC_A) |
| 1189 | 1189 |
{
|
| 1190 | 1190 |
dc->jmp = JMP_INDIRECT; |
| 1191 |
gen_tst_cc (dc, cond); |
|
| 1192 |
tcg_gen_mov_tl(env_btaken, cpu_T[0]); |
|
| 1191 |
gen_tst_cc (dc, env_btaken, cond); |
|
| 1193 | 1192 |
tcg_gen_movi_tl(env_btarget, dc->jmp_pc); |
| 1194 | 1193 |
} else {
|
| 1195 | 1194 |
/* Allow chaining. */ |
| ... | ... | |
| 1623 | 1622 |
{
|
| 1624 | 1623 |
int l1; |
| 1625 | 1624 |
|
| 1626 |
gen_tst_cc (dc, cond); |
|
| 1627 |
|
|
| 1625 |
gen_tst_cc (dc, cpu_R[dc->op1], cond); |
|
| 1628 | 1626 |
l1 = gen_new_label(); |
| 1629 |
tcg_gen_movi_tl(cpu_R[dc->op1], 0); |
|
| 1630 |
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1); |
|
| 1627 |
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1); |
|
| 1631 | 1628 |
tcg_gen_movi_tl(cpu_R[dc->op1], 1); |
| 1632 | 1629 |
gen_set_label(l1); |
| 1633 | 1630 |
} |
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