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1 | 827df9f3 | balrog | /*
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2 | 827df9f3 | balrog | * TI OMAP processors emulation.
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3 | 827df9f3 | balrog | *
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4 | 827df9f3 | balrog | * Copyright (C) 2007-2008 Nokia Corporation
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5 | 827df9f3 | balrog | * Written by Andrzej Zaborowski <andrew@openedhand.com>
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6 | 827df9f3 | balrog | *
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7 | 827df9f3 | balrog | * This program is free software; you can redistribute it and/or
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8 | 827df9f3 | balrog | * modify it under the terms of the GNU General Public License as
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9 | 827df9f3 | balrog | * published by the Free Software Foundation; either version 2 or
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10 | 827df9f3 | balrog | * (at your option) version 3 of the License.
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11 | 827df9f3 | balrog | *
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12 | 827df9f3 | balrog | * This program is distributed in the hope that it will be useful,
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13 | 827df9f3 | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 827df9f3 | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | 827df9f3 | balrog | * GNU General Public License for more details.
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16 | 827df9f3 | balrog | *
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17 | 827df9f3 | balrog | * You should have received a copy of the GNU General Public License
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18 | 827df9f3 | balrog | * along with this program; if not, write to the Free Software
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19 | 827df9f3 | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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20 | 827df9f3 | balrog | * MA 02111-1307 USA
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21 | 827df9f3 | balrog | */
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22 | 827df9f3 | balrog | #include "hw.h" |
23 | 827df9f3 | balrog | #include "arm-misc.h" |
24 | 827df9f3 | balrog | #include "omap.h" |
25 | 827df9f3 | balrog | #include "sysemu.h" |
26 | 827df9f3 | balrog | #include "qemu-timer.h" |
27 | 827df9f3 | balrog | #include "qemu-char.h" |
28 | 827df9f3 | balrog | #include "flash.h" |
29 | 827df9f3 | balrog | |
30 | 827df9f3 | balrog | /* GP timers */
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31 | 827df9f3 | balrog | struct omap_gp_timer_s {
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32 | 827df9f3 | balrog | qemu_irq irq; |
33 | 827df9f3 | balrog | qemu_irq wkup; |
34 | 827df9f3 | balrog | qemu_irq in; |
35 | 827df9f3 | balrog | qemu_irq out; |
36 | 827df9f3 | balrog | omap_clk clk; |
37 | 827df9f3 | balrog | target_phys_addr_t base; |
38 | 827df9f3 | balrog | QEMUTimer *timer; |
39 | 827df9f3 | balrog | QEMUTimer *match; |
40 | 827df9f3 | balrog | struct omap_target_agent_s *ta;
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41 | 827df9f3 | balrog | |
42 | 827df9f3 | balrog | int in_val;
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43 | 827df9f3 | balrog | int out_val;
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44 | 827df9f3 | balrog | int64_t time; |
45 | 827df9f3 | balrog | int64_t rate; |
46 | 827df9f3 | balrog | int64_t ticks_per_sec; |
47 | 827df9f3 | balrog | |
48 | 827df9f3 | balrog | int16_t config; |
49 | 827df9f3 | balrog | int status;
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50 | 827df9f3 | balrog | int it_ena;
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51 | 827df9f3 | balrog | int wu_ena;
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52 | 827df9f3 | balrog | int enable;
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53 | 827df9f3 | balrog | int inout;
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54 | 827df9f3 | balrog | int capt2;
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55 | 827df9f3 | balrog | int pt;
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56 | 827df9f3 | balrog | enum {
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57 | 827df9f3 | balrog | gpt_trigger_none, gpt_trigger_overflow, gpt_trigger_both |
58 | 827df9f3 | balrog | } trigger; |
59 | 827df9f3 | balrog | enum {
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60 | 827df9f3 | balrog | gpt_capture_none, gpt_capture_rising, |
61 | 827df9f3 | balrog | gpt_capture_falling, gpt_capture_both |
62 | 827df9f3 | balrog | } capture; |
63 | 827df9f3 | balrog | int scpwm;
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64 | 827df9f3 | balrog | int ce;
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65 | 827df9f3 | balrog | int pre;
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66 | 827df9f3 | balrog | int ptv;
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67 | 827df9f3 | balrog | int ar;
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68 | 827df9f3 | balrog | int st;
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69 | 827df9f3 | balrog | int posted;
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70 | 827df9f3 | balrog | uint32_t val; |
71 | 827df9f3 | balrog | uint32_t load_val; |
72 | 827df9f3 | balrog | uint32_t capture_val[2];
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73 | 827df9f3 | balrog | uint32_t match_val; |
74 | 827df9f3 | balrog | int capt_num;
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75 | 827df9f3 | balrog | |
76 | 827df9f3 | balrog | uint16_t writeh; /* LSB */
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77 | 827df9f3 | balrog | uint16_t readh; /* MSB */
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78 | 827df9f3 | balrog | }; |
79 | 827df9f3 | balrog | |
80 | 827df9f3 | balrog | #define GPT_TCAR_IT (1 << 2) |
81 | 827df9f3 | balrog | #define GPT_OVF_IT (1 << 1) |
82 | 827df9f3 | balrog | #define GPT_MAT_IT (1 << 0) |
83 | 827df9f3 | balrog | |
84 | 827df9f3 | balrog | static inline void omap_gp_timer_intr(struct omap_gp_timer_s *timer, int it) |
85 | 827df9f3 | balrog | { |
86 | 827df9f3 | balrog | if (timer->it_ena & it) {
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87 | 827df9f3 | balrog | if (!timer->status)
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88 | 827df9f3 | balrog | qemu_irq_raise(timer->irq); |
89 | 827df9f3 | balrog | |
90 | 827df9f3 | balrog | timer->status |= it; |
91 | 827df9f3 | balrog | /* Or are the status bits set even when masked?
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92 | 827df9f3 | balrog | * i.e. is masking applied before or after the status register? */
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93 | 827df9f3 | balrog | } |
94 | 827df9f3 | balrog | |
95 | 827df9f3 | balrog | if (timer->wu_ena & it)
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96 | 827df9f3 | balrog | qemu_irq_pulse(timer->wkup); |
97 | 827df9f3 | balrog | } |
98 | 827df9f3 | balrog | |
99 | 827df9f3 | balrog | static inline void omap_gp_timer_out(struct omap_gp_timer_s *timer, int level) |
100 | 827df9f3 | balrog | { |
101 | 827df9f3 | balrog | if (!timer->inout && timer->out_val != level) {
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102 | 827df9f3 | balrog | timer->out_val = level; |
103 | 827df9f3 | balrog | qemu_set_irq(timer->out, level); |
104 | 827df9f3 | balrog | } |
105 | 827df9f3 | balrog | } |
106 | 827df9f3 | balrog | |
107 | 827df9f3 | balrog | static inline uint32_t omap_gp_timer_read(struct omap_gp_timer_s *timer) |
108 | 827df9f3 | balrog | { |
109 | 827df9f3 | balrog | uint64_t distance; |
110 | 827df9f3 | balrog | |
111 | 827df9f3 | balrog | if (timer->st && timer->rate) {
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112 | 827df9f3 | balrog | distance = qemu_get_clock(vm_clock) - timer->time; |
113 | 827df9f3 | balrog | distance = muldiv64(distance, timer->rate, timer->ticks_per_sec); |
114 | 827df9f3 | balrog | |
115 | 827df9f3 | balrog | if (distance >= 0xffffffff - timer->val) |
116 | 827df9f3 | balrog | return 0xffffffff; |
117 | 827df9f3 | balrog | else
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118 | 827df9f3 | balrog | return timer->val + distance;
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119 | 827df9f3 | balrog | } else
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120 | 827df9f3 | balrog | return timer->val;
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121 | 827df9f3 | balrog | } |
122 | 827df9f3 | balrog | |
123 | 827df9f3 | balrog | static inline void omap_gp_timer_sync(struct omap_gp_timer_s *timer) |
124 | 827df9f3 | balrog | { |
125 | 827df9f3 | balrog | if (timer->st) {
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126 | 827df9f3 | balrog | timer->val = omap_gp_timer_read(timer); |
127 | 827df9f3 | balrog | timer->time = qemu_get_clock(vm_clock); |
128 | 827df9f3 | balrog | } |
129 | 827df9f3 | balrog | } |
130 | 827df9f3 | balrog | |
131 | 827df9f3 | balrog | static inline void omap_gp_timer_update(struct omap_gp_timer_s *timer) |
132 | 827df9f3 | balrog | { |
133 | 827df9f3 | balrog | int64_t expires, matches; |
134 | 827df9f3 | balrog | |
135 | 827df9f3 | balrog | if (timer->st && timer->rate) {
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136 | 827df9f3 | balrog | expires = muldiv64(0x100000000ll - timer->val,
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137 | 827df9f3 | balrog | timer->ticks_per_sec, timer->rate); |
138 | 827df9f3 | balrog | qemu_mod_timer(timer->timer, timer->time + expires); |
139 | 827df9f3 | balrog | |
140 | 827df9f3 | balrog | if (timer->ce && timer->match_val >= timer->val) {
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141 | 827df9f3 | balrog | matches = muldiv64(timer->match_val - timer->val, |
142 | 827df9f3 | balrog | timer->ticks_per_sec, timer->rate); |
143 | 827df9f3 | balrog | qemu_mod_timer(timer->match, timer->time + matches); |
144 | 827df9f3 | balrog | } else
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145 | 827df9f3 | balrog | qemu_del_timer(timer->match); |
146 | 827df9f3 | balrog | } else {
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147 | 827df9f3 | balrog | qemu_del_timer(timer->timer); |
148 | 827df9f3 | balrog | qemu_del_timer(timer->match); |
149 | 827df9f3 | balrog | omap_gp_timer_out(timer, timer->scpwm); |
150 | 827df9f3 | balrog | } |
151 | 827df9f3 | balrog | } |
152 | 827df9f3 | balrog | |
153 | 827df9f3 | balrog | static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer) |
154 | 827df9f3 | balrog | { |
155 | 827df9f3 | balrog | if (timer->pt)
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156 | 827df9f3 | balrog | /* TODO in overflow-and-match mode if the first event to
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157 | 827df9f3 | balrog | * occurs is the match, don't toggle. */
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158 | 827df9f3 | balrog | omap_gp_timer_out(timer, !timer->out_val); |
159 | 827df9f3 | balrog | else
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160 | 827df9f3 | balrog | /* TODO inverted pulse on timer->out_val == 1? */
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161 | 827df9f3 | balrog | qemu_irq_pulse(timer->out); |
162 | 827df9f3 | balrog | } |
163 | 827df9f3 | balrog | |
164 | 827df9f3 | balrog | static void omap_gp_timer_tick(void *opaque) |
165 | 827df9f3 | balrog | { |
166 | 827df9f3 | balrog | struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque; |
167 | 827df9f3 | balrog | |
168 | 827df9f3 | balrog | if (!timer->ar) {
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169 | 827df9f3 | balrog | timer->st = 0;
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170 | 827df9f3 | balrog | timer->val = 0;
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171 | 827df9f3 | balrog | } else {
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172 | 827df9f3 | balrog | timer->val = timer->load_val; |
173 | 827df9f3 | balrog | timer->time = qemu_get_clock(vm_clock); |
174 | 827df9f3 | balrog | } |
175 | 827df9f3 | balrog | |
176 | 827df9f3 | balrog | if (timer->trigger == gpt_trigger_overflow ||
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177 | 827df9f3 | balrog | timer->trigger == gpt_trigger_both) |
178 | 827df9f3 | balrog | omap_gp_timer_trigger(timer); |
179 | 827df9f3 | balrog | |
180 | 827df9f3 | balrog | omap_gp_timer_intr(timer, GPT_OVF_IT); |
181 | 827df9f3 | balrog | omap_gp_timer_update(timer); |
182 | 827df9f3 | balrog | } |
183 | 827df9f3 | balrog | |
184 | 827df9f3 | balrog | static void omap_gp_timer_match(void *opaque) |
185 | 827df9f3 | balrog | { |
186 | 827df9f3 | balrog | struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque; |
187 | 827df9f3 | balrog | |
188 | 827df9f3 | balrog | if (timer->trigger == gpt_trigger_both)
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189 | 827df9f3 | balrog | omap_gp_timer_trigger(timer); |
190 | 827df9f3 | balrog | |
191 | 827df9f3 | balrog | omap_gp_timer_intr(timer, GPT_MAT_IT); |
192 | 827df9f3 | balrog | } |
193 | 827df9f3 | balrog | |
194 | 827df9f3 | balrog | static void omap_gp_timer_input(void *opaque, int line, int on) |
195 | 827df9f3 | balrog | { |
196 | 827df9f3 | balrog | struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; |
197 | 827df9f3 | balrog | int trigger;
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198 | 827df9f3 | balrog | |
199 | 827df9f3 | balrog | switch (s->capture) {
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200 | 827df9f3 | balrog | default:
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201 | 827df9f3 | balrog | case gpt_capture_none:
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202 | 827df9f3 | balrog | trigger = 0;
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203 | 827df9f3 | balrog | break;
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204 | 827df9f3 | balrog | case gpt_capture_rising:
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205 | 827df9f3 | balrog | trigger = !s->in_val && on; |
206 | 827df9f3 | balrog | break;
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207 | 827df9f3 | balrog | case gpt_capture_falling:
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208 | 827df9f3 | balrog | trigger = s->in_val && !on; |
209 | 827df9f3 | balrog | break;
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210 | 827df9f3 | balrog | case gpt_capture_both:
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211 | 827df9f3 | balrog | trigger = (s->in_val == !on); |
212 | 827df9f3 | balrog | break;
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213 | 827df9f3 | balrog | } |
214 | 827df9f3 | balrog | s->in_val = on; |
215 | 827df9f3 | balrog | |
216 | 827df9f3 | balrog | if (s->inout && trigger && s->capt_num < 2) { |
217 | 827df9f3 | balrog | s->capture_val[s->capt_num] = omap_gp_timer_read(s); |
218 | 827df9f3 | balrog | |
219 | 827df9f3 | balrog | if (s->capt2 == s->capt_num ++)
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220 | 827df9f3 | balrog | omap_gp_timer_intr(s, GPT_TCAR_IT); |
221 | 827df9f3 | balrog | } |
222 | 827df9f3 | balrog | } |
223 | 827df9f3 | balrog | |
224 | 827df9f3 | balrog | static void omap_gp_timer_clk_update(void *opaque, int line, int on) |
225 | 827df9f3 | balrog | { |
226 | 827df9f3 | balrog | struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque; |
227 | 827df9f3 | balrog | |
228 | 827df9f3 | balrog | omap_gp_timer_sync(timer); |
229 | 827df9f3 | balrog | timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
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230 | 827df9f3 | balrog | omap_gp_timer_update(timer); |
231 | 827df9f3 | balrog | } |
232 | 827df9f3 | balrog | |
233 | 827df9f3 | balrog | static void omap_gp_timer_clk_setup(struct omap_gp_timer_s *timer) |
234 | 827df9f3 | balrog | { |
235 | 827df9f3 | balrog | omap_clk_adduser(timer->clk, |
236 | 827df9f3 | balrog | qemu_allocate_irqs(omap_gp_timer_clk_update, timer, 1)[0]); |
237 | 827df9f3 | balrog | timer->rate = omap_clk_getrate(timer->clk); |
238 | 827df9f3 | balrog | } |
239 | 827df9f3 | balrog | |
240 | 827df9f3 | balrog | static void omap_gp_timer_reset(struct omap_gp_timer_s *s) |
241 | 827df9f3 | balrog | { |
242 | 827df9f3 | balrog | s->config = 0x000;
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243 | 827df9f3 | balrog | s->status = 0;
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244 | 827df9f3 | balrog | s->it_ena = 0;
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245 | 827df9f3 | balrog | s->wu_ena = 0;
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246 | 827df9f3 | balrog | s->inout = 0;
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247 | 827df9f3 | balrog | s->capt2 = 0;
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248 | 827df9f3 | balrog | s->capt_num = 0;
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249 | 827df9f3 | balrog | s->pt = 0;
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250 | 827df9f3 | balrog | s->trigger = gpt_trigger_none; |
251 | 827df9f3 | balrog | s->capture = gpt_capture_none; |
252 | 827df9f3 | balrog | s->scpwm = 0;
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253 | 827df9f3 | balrog | s->ce = 0;
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254 | 827df9f3 | balrog | s->pre = 0;
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255 | 827df9f3 | balrog | s->ptv = 0;
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256 | 827df9f3 | balrog | s->ar = 0;
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257 | 827df9f3 | balrog | s->st = 0;
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258 | 827df9f3 | balrog | s->posted = 1;
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259 | 827df9f3 | balrog | s->val = 0x00000000;
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260 | 827df9f3 | balrog | s->load_val = 0x00000000;
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261 | 827df9f3 | balrog | s->capture_val[0] = 0x00000000; |
262 | 827df9f3 | balrog | s->capture_val[1] = 0x00000000; |
263 | 827df9f3 | balrog | s->match_val = 0x00000000;
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264 | 827df9f3 | balrog | omap_gp_timer_update(s); |
265 | 827df9f3 | balrog | } |
266 | 827df9f3 | balrog | |
267 | 827df9f3 | balrog | static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr) |
268 | 827df9f3 | balrog | { |
269 | 827df9f3 | balrog | struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; |
270 | 827df9f3 | balrog | int offset = addr - s->base;
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271 | 827df9f3 | balrog | |
272 | 827df9f3 | balrog | switch (offset) {
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273 | 827df9f3 | balrog | case 0x00: /* TIDR */ |
274 | 827df9f3 | balrog | return 0x21; |
275 | 827df9f3 | balrog | |
276 | 827df9f3 | balrog | case 0x10: /* TIOCP_CFG */ |
277 | 827df9f3 | balrog | return s->config;
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278 | 827df9f3 | balrog | |
279 | 827df9f3 | balrog | case 0x14: /* TISTAT */ |
280 | 827df9f3 | balrog | /* ??? When's this bit reset? */
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281 | 827df9f3 | balrog | return 1; /* RESETDONE */ |
282 | 827df9f3 | balrog | |
283 | 827df9f3 | balrog | case 0x18: /* TISR */ |
284 | 827df9f3 | balrog | return s->status;
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285 | 827df9f3 | balrog | |
286 | 827df9f3 | balrog | case 0x1c: /* TIER */ |
287 | 827df9f3 | balrog | return s->it_ena;
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288 | 827df9f3 | balrog | |
289 | 827df9f3 | balrog | case 0x20: /* TWER */ |
290 | 827df9f3 | balrog | return s->wu_ena;
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291 | 827df9f3 | balrog | |
292 | 827df9f3 | balrog | case 0x24: /* TCLR */ |
293 | 827df9f3 | balrog | return (s->inout << 14) | |
294 | 827df9f3 | balrog | (s->capt2 << 13) |
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295 | 827df9f3 | balrog | (s->pt << 12) |
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296 | 827df9f3 | balrog | (s->trigger << 10) |
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297 | 827df9f3 | balrog | (s->capture << 8) |
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298 | 827df9f3 | balrog | (s->scpwm << 7) |
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299 | 827df9f3 | balrog | (s->ce << 6) |
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300 | 827df9f3 | balrog | (s->pre << 5) |
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301 | 827df9f3 | balrog | (s->ptv << 2) |
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302 | 827df9f3 | balrog | (s->ar << 1) |
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303 | 827df9f3 | balrog | (s->st << 0);
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304 | 827df9f3 | balrog | |
305 | 827df9f3 | balrog | case 0x28: /* TCRR */ |
306 | 827df9f3 | balrog | return omap_gp_timer_read(s);
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307 | 827df9f3 | balrog | |
308 | 827df9f3 | balrog | case 0x2c: /* TLDR */ |
309 | 827df9f3 | balrog | return s->load_val;
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310 | 827df9f3 | balrog | |
311 | 827df9f3 | balrog | case 0x30: /* TTGR */ |
312 | 827df9f3 | balrog | return 0xffffffff; |
313 | 827df9f3 | balrog | |
314 | 827df9f3 | balrog | case 0x34: /* TWPS */ |
315 | 827df9f3 | balrog | return 0x00000000; /* No posted writes pending. */ |
316 | 827df9f3 | balrog | |
317 | 827df9f3 | balrog | case 0x38: /* TMAR */ |
318 | 827df9f3 | balrog | return s->match_val;
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319 | 827df9f3 | balrog | |
320 | 827df9f3 | balrog | case 0x3c: /* TCAR1 */ |
321 | 827df9f3 | balrog | return s->capture_val[0]; |
322 | 827df9f3 | balrog | |
323 | 827df9f3 | balrog | case 0x40: /* TSICR */ |
324 | 827df9f3 | balrog | return s->posted << 2; |
325 | 827df9f3 | balrog | |
326 | 827df9f3 | balrog | case 0x44: /* TCAR2 */ |
327 | 827df9f3 | balrog | return s->capture_val[1]; |
328 | 827df9f3 | balrog | } |
329 | 827df9f3 | balrog | |
330 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
331 | 827df9f3 | balrog | return 0; |
332 | 827df9f3 | balrog | } |
333 | 827df9f3 | balrog | |
334 | 827df9f3 | balrog | static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr) |
335 | 827df9f3 | balrog | { |
336 | 827df9f3 | balrog | struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; |
337 | 827df9f3 | balrog | uint32_t ret; |
338 | 827df9f3 | balrog | |
339 | 827df9f3 | balrog | if (addr & 2) |
340 | 827df9f3 | balrog | return s->readh;
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341 | 827df9f3 | balrog | else {
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342 | 827df9f3 | balrog | ret = omap_gp_timer_readw(opaque, addr); |
343 | 827df9f3 | balrog | s->readh = ret >> 16;
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344 | 827df9f3 | balrog | return ret & 0xffff; |
345 | 827df9f3 | balrog | } |
346 | 827df9f3 | balrog | } |
347 | 827df9f3 | balrog | |
348 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap_gp_timer_readfn[] = {
|
349 | 827df9f3 | balrog | omap_badwidth_read32, |
350 | 827df9f3 | balrog | omap_gp_timer_readh, |
351 | 827df9f3 | balrog | omap_gp_timer_readw, |
352 | 827df9f3 | balrog | }; |
353 | 827df9f3 | balrog | |
354 | 827df9f3 | balrog | static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr, |
355 | 827df9f3 | balrog | uint32_t value) |
356 | 827df9f3 | balrog | { |
357 | 827df9f3 | balrog | struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; |
358 | 827df9f3 | balrog | int offset = addr - s->base;
|
359 | 827df9f3 | balrog | |
360 | 827df9f3 | balrog | switch (offset) {
|
361 | 827df9f3 | balrog | case 0x00: /* TIDR */ |
362 | 827df9f3 | balrog | case 0x14: /* TISTAT */ |
363 | 827df9f3 | balrog | case 0x34: /* TWPS */ |
364 | 827df9f3 | balrog | case 0x3c: /* TCAR1 */ |
365 | 827df9f3 | balrog | case 0x44: /* TCAR2 */ |
366 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
367 | 827df9f3 | balrog | break;
|
368 | 827df9f3 | balrog | |
369 | 827df9f3 | balrog | case 0x10: /* TIOCP_CFG */ |
370 | 827df9f3 | balrog | s->config = value & 0x33d;
|
371 | 827df9f3 | balrog | if (((value >> 3) & 3) == 3) /* IDLEMODE */ |
372 | 827df9f3 | balrog | fprintf(stderr, "%s: illegal IDLEMODE value in TIOCP_CFG\n",
|
373 | 827df9f3 | balrog | __FUNCTION__); |
374 | 827df9f3 | balrog | if (value & 2) /* SOFTRESET */ |
375 | 827df9f3 | balrog | omap_gp_timer_reset(s); |
376 | 827df9f3 | balrog | break;
|
377 | 827df9f3 | balrog | |
378 | 827df9f3 | balrog | case 0x18: /* TISR */ |
379 | 827df9f3 | balrog | if (value & GPT_TCAR_IT)
|
380 | 827df9f3 | balrog | s->capt_num = 0;
|
381 | 827df9f3 | balrog | if (s->status && !(s->status &= ~value))
|
382 | 827df9f3 | balrog | qemu_irq_lower(s->irq); |
383 | 827df9f3 | balrog | break;
|
384 | 827df9f3 | balrog | |
385 | 827df9f3 | balrog | case 0x1c: /* TIER */ |
386 | 827df9f3 | balrog | s->it_ena = value & 7;
|
387 | 827df9f3 | balrog | break;
|
388 | 827df9f3 | balrog | |
389 | 827df9f3 | balrog | case 0x20: /* TWER */ |
390 | 827df9f3 | balrog | s->wu_ena = value & 7;
|
391 | 827df9f3 | balrog | break;
|
392 | 827df9f3 | balrog | |
393 | 827df9f3 | balrog | case 0x24: /* TCLR */ |
394 | 827df9f3 | balrog | omap_gp_timer_sync(s); |
395 | 827df9f3 | balrog | s->inout = (value >> 14) & 1; |
396 | 827df9f3 | balrog | s->capt2 = (value >> 13) & 1; |
397 | 827df9f3 | balrog | s->pt = (value >> 12) & 1; |
398 | 827df9f3 | balrog | s->trigger = (value >> 10) & 3; |
399 | 827df9f3 | balrog | if (s->capture == gpt_capture_none &&
|
400 | 827df9f3 | balrog | ((value >> 8) & 3) != gpt_capture_none) |
401 | 827df9f3 | balrog | s->capt_num = 0;
|
402 | 827df9f3 | balrog | s->capture = (value >> 8) & 3; |
403 | 827df9f3 | balrog | s->scpwm = (value >> 7) & 1; |
404 | 827df9f3 | balrog | s->ce = (value >> 6) & 1; |
405 | 827df9f3 | balrog | s->pre = (value >> 5) & 1; |
406 | 827df9f3 | balrog | s->ptv = (value >> 2) & 7; |
407 | 827df9f3 | balrog | s->ar = (value >> 1) & 1; |
408 | 827df9f3 | balrog | s->st = (value >> 0) & 1; |
409 | 827df9f3 | balrog | if (s->inout && s->trigger != gpt_trigger_none)
|
410 | 827df9f3 | balrog | fprintf(stderr, "%s: GP timer pin must be an output "
|
411 | 827df9f3 | balrog | "for this trigger mode\n", __FUNCTION__);
|
412 | 827df9f3 | balrog | if (!s->inout && s->capture != gpt_capture_none)
|
413 | 827df9f3 | balrog | fprintf(stderr, "%s: GP timer pin must be an input "
|
414 | 827df9f3 | balrog | "for this capture mode\n", __FUNCTION__);
|
415 | 827df9f3 | balrog | if (s->trigger == gpt_trigger_none)
|
416 | 827df9f3 | balrog | omap_gp_timer_out(s, s->scpwm); |
417 | 827df9f3 | balrog | /* TODO: make sure this doesn't overflow 32-bits */
|
418 | 827df9f3 | balrog | s->ticks_per_sec = ticks_per_sec << (s->pre ? s->ptv + 1 : 0); |
419 | 827df9f3 | balrog | omap_gp_timer_update(s); |
420 | 827df9f3 | balrog | break;
|
421 | 827df9f3 | balrog | |
422 | 827df9f3 | balrog | case 0x28: /* TCRR */ |
423 | 827df9f3 | balrog | s->time = qemu_get_clock(vm_clock); |
424 | 827df9f3 | balrog | s->val = value; |
425 | 827df9f3 | balrog | omap_gp_timer_update(s); |
426 | 827df9f3 | balrog | break;
|
427 | 827df9f3 | balrog | |
428 | 827df9f3 | balrog | case 0x2c: /* TLDR */ |
429 | 827df9f3 | balrog | s->load_val = value; |
430 | 827df9f3 | balrog | break;
|
431 | 827df9f3 | balrog | |
432 | 827df9f3 | balrog | case 0x30: /* TTGR */ |
433 | 827df9f3 | balrog | s->time = qemu_get_clock(vm_clock); |
434 | 827df9f3 | balrog | s->val = s->load_val; |
435 | 827df9f3 | balrog | omap_gp_timer_update(s); |
436 | 827df9f3 | balrog | break;
|
437 | 827df9f3 | balrog | |
438 | 827df9f3 | balrog | case 0x38: /* TMAR */ |
439 | 827df9f3 | balrog | omap_gp_timer_sync(s); |
440 | 827df9f3 | balrog | s->match_val = value; |
441 | 827df9f3 | balrog | omap_gp_timer_update(s); |
442 | 827df9f3 | balrog | break;
|
443 | 827df9f3 | balrog | |
444 | 827df9f3 | balrog | case 0x40: /* TSICR */ |
445 | 827df9f3 | balrog | s->posted = (value >> 2) & 1; |
446 | 827df9f3 | balrog | if (value & 2) /* How much exactly are we supposed to reset? */ |
447 | 827df9f3 | balrog | omap_gp_timer_reset(s); |
448 | 827df9f3 | balrog | break;
|
449 | 827df9f3 | balrog | |
450 | 827df9f3 | balrog | default:
|
451 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
452 | 827df9f3 | balrog | } |
453 | 827df9f3 | balrog | } |
454 | 827df9f3 | balrog | |
455 | 827df9f3 | balrog | static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr, |
456 | 827df9f3 | balrog | uint32_t value) |
457 | 827df9f3 | balrog | { |
458 | 827df9f3 | balrog | struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; |
459 | 827df9f3 | balrog | |
460 | 827df9f3 | balrog | if (addr & 2) |
461 | 827df9f3 | balrog | return omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh); |
462 | 827df9f3 | balrog | else
|
463 | 827df9f3 | balrog | s->writeh = (uint16_t) value; |
464 | 827df9f3 | balrog | } |
465 | 827df9f3 | balrog | |
466 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap_gp_timer_writefn[] = {
|
467 | 827df9f3 | balrog | omap_badwidth_write32, |
468 | 827df9f3 | balrog | omap_gp_timer_writeh, |
469 | 827df9f3 | balrog | omap_gp_timer_write, |
470 | 827df9f3 | balrog | }; |
471 | 827df9f3 | balrog | |
472 | 827df9f3 | balrog | struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, |
473 | 827df9f3 | balrog | qemu_irq irq, omap_clk fclk, omap_clk iclk) |
474 | 827df9f3 | balrog | { |
475 | 827df9f3 | balrog | int iomemtype;
|
476 | 827df9f3 | balrog | struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) |
477 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_gp_timer_s)); |
478 | 827df9f3 | balrog | |
479 | 827df9f3 | balrog | s->ta = ta; |
480 | 827df9f3 | balrog | s->irq = irq; |
481 | 827df9f3 | balrog | s->clk = fclk; |
482 | 827df9f3 | balrog | s->timer = qemu_new_timer(vm_clock, omap_gp_timer_tick, s); |
483 | 827df9f3 | balrog | s->match = qemu_new_timer(vm_clock, omap_gp_timer_match, s); |
484 | 827df9f3 | balrog | s->in = qemu_allocate_irqs(omap_gp_timer_input, s, 1)[0]; |
485 | 827df9f3 | balrog | omap_gp_timer_reset(s); |
486 | 827df9f3 | balrog | omap_gp_timer_clk_setup(s); |
487 | 827df9f3 | balrog | |
488 | c66fb5bc | balrog | iomemtype = l4_register_io_memory(0, omap_gp_timer_readfn,
|
489 | 827df9f3 | balrog | omap_gp_timer_writefn, s); |
490 | 827df9f3 | balrog | s->base = omap_l4_attach(ta, 0, iomemtype);
|
491 | 827df9f3 | balrog | |
492 | 827df9f3 | balrog | return s;
|
493 | 827df9f3 | balrog | } |
494 | 827df9f3 | balrog | |
495 | 827df9f3 | balrog | /* 32-kHz Sync Timer of the OMAP2 */
|
496 | 827df9f3 | balrog | static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) { |
497 | 827df9f3 | balrog | return muldiv64(qemu_get_clock(vm_clock), 0x8000, ticks_per_sec); |
498 | 827df9f3 | balrog | } |
499 | 827df9f3 | balrog | |
500 | 827df9f3 | balrog | static void omap_synctimer_reset(struct omap_synctimer_s *s) |
501 | 827df9f3 | balrog | { |
502 | 827df9f3 | balrog | s->val = omap_synctimer_read(s); |
503 | 827df9f3 | balrog | } |
504 | 827df9f3 | balrog | |
505 | 827df9f3 | balrog | static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr) |
506 | 827df9f3 | balrog | { |
507 | 827df9f3 | balrog | struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque; |
508 | 827df9f3 | balrog | int offset = addr - s->base;
|
509 | 827df9f3 | balrog | |
510 | 827df9f3 | balrog | switch (offset) {
|
511 | 827df9f3 | balrog | case 0x00: /* 32KSYNCNT_REV */ |
512 | 827df9f3 | balrog | return 0x21; |
513 | 827df9f3 | balrog | |
514 | 827df9f3 | balrog | case 0x10: /* CR */ |
515 | 827df9f3 | balrog | return omap_synctimer_read(s) - s->val;
|
516 | 827df9f3 | balrog | } |
517 | 827df9f3 | balrog | |
518 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
519 | 827df9f3 | balrog | return 0; |
520 | 827df9f3 | balrog | } |
521 | 827df9f3 | balrog | |
522 | 827df9f3 | balrog | static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr) |
523 | 827df9f3 | balrog | { |
524 | 827df9f3 | balrog | struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque; |
525 | 827df9f3 | balrog | uint32_t ret; |
526 | 827df9f3 | balrog | |
527 | 827df9f3 | balrog | if (addr & 2) |
528 | 827df9f3 | balrog | return s->readh;
|
529 | 827df9f3 | balrog | else {
|
530 | 827df9f3 | balrog | ret = omap_synctimer_readw(opaque, addr); |
531 | 827df9f3 | balrog | s->readh = ret >> 16;
|
532 | 827df9f3 | balrog | return ret & 0xffff; |
533 | 827df9f3 | balrog | } |
534 | 827df9f3 | balrog | } |
535 | 827df9f3 | balrog | |
536 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap_synctimer_readfn[] = {
|
537 | 827df9f3 | balrog | omap_badwidth_read32, |
538 | 827df9f3 | balrog | omap_synctimer_readh, |
539 | 827df9f3 | balrog | omap_synctimer_readw, |
540 | 827df9f3 | balrog | }; |
541 | 827df9f3 | balrog | |
542 | 827df9f3 | balrog | static void omap_synctimer_write(void *opaque, target_phys_addr_t addr, |
543 | 827df9f3 | balrog | uint32_t value) |
544 | 827df9f3 | balrog | { |
545 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
546 | 827df9f3 | balrog | } |
547 | 827df9f3 | balrog | |
548 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap_synctimer_writefn[] = {
|
549 | 827df9f3 | balrog | omap_badwidth_write32, |
550 | 827df9f3 | balrog | omap_synctimer_write, |
551 | 827df9f3 | balrog | omap_synctimer_write, |
552 | 827df9f3 | balrog | }; |
553 | 827df9f3 | balrog | |
554 | 827df9f3 | balrog | void omap_synctimer_init(struct omap_target_agent_s *ta, |
555 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk)
|
556 | 827df9f3 | balrog | { |
557 | 827df9f3 | balrog | struct omap_synctimer_s *s = &mpu->synctimer;
|
558 | 827df9f3 | balrog | |
559 | 827df9f3 | balrog | omap_synctimer_reset(s); |
560 | c66fb5bc | balrog | s->base = omap_l4_attach(ta, 0, l4_register_io_memory(0, |
561 | 827df9f3 | balrog | omap_synctimer_readfn, omap_synctimer_writefn, s)); |
562 | 827df9f3 | balrog | } |
563 | 827df9f3 | balrog | |
564 | 827df9f3 | balrog | /* General-Purpose Interface of OMAP2 */
|
565 | 827df9f3 | balrog | struct omap2_gpio_s {
|
566 | 827df9f3 | balrog | target_phys_addr_t base; |
567 | 827df9f3 | balrog | qemu_irq irq[2];
|
568 | 827df9f3 | balrog | qemu_irq wkup; |
569 | 827df9f3 | balrog | qemu_irq *in; |
570 | 827df9f3 | balrog | qemu_irq handler[32];
|
571 | 827df9f3 | balrog | |
572 | 827df9f3 | balrog | uint8_t config[2];
|
573 | 827df9f3 | balrog | uint32_t inputs; |
574 | 827df9f3 | balrog | uint32_t outputs; |
575 | 827df9f3 | balrog | uint32_t dir; |
576 | 827df9f3 | balrog | uint32_t level[2];
|
577 | 827df9f3 | balrog | uint32_t edge[2];
|
578 | 827df9f3 | balrog | uint32_t mask[2];
|
579 | 827df9f3 | balrog | uint32_t wumask; |
580 | 827df9f3 | balrog | uint32_t ints[2];
|
581 | 827df9f3 | balrog | uint32_t debounce; |
582 | 827df9f3 | balrog | uint8_t delay; |
583 | 827df9f3 | balrog | }; |
584 | 827df9f3 | balrog | |
585 | 827df9f3 | balrog | static inline void omap_gpio_module_int_update(struct omap2_gpio_s *s, |
586 | 827df9f3 | balrog | int line)
|
587 | 827df9f3 | balrog | { |
588 | 827df9f3 | balrog | qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]); |
589 | 827df9f3 | balrog | } |
590 | 827df9f3 | balrog | |
591 | 827df9f3 | balrog | static void omap_gpio_module_wake(struct omap2_gpio_s *s, int line) |
592 | 827df9f3 | balrog | { |
593 | 827df9f3 | balrog | if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */ |
594 | 827df9f3 | balrog | return;
|
595 | 827df9f3 | balrog | if (!(s->config[0] & (3 << 3))) /* Force Idle */ |
596 | 827df9f3 | balrog | return;
|
597 | 827df9f3 | balrog | if (!(s->wumask & (1 << line))) |
598 | 827df9f3 | balrog | return;
|
599 | 827df9f3 | balrog | |
600 | 827df9f3 | balrog | qemu_irq_raise(s->wkup); |
601 | 827df9f3 | balrog | } |
602 | 827df9f3 | balrog | |
603 | 827df9f3 | balrog | static inline void omap_gpio_module_out_update(struct omap2_gpio_s *s, |
604 | 827df9f3 | balrog | uint32_t diff) |
605 | 827df9f3 | balrog | { |
606 | 827df9f3 | balrog | int ln;
|
607 | 827df9f3 | balrog | |
608 | 827df9f3 | balrog | s->outputs ^= diff; |
609 | 827df9f3 | balrog | diff &= ~s->dir; |
610 | 827df9f3 | balrog | while ((ln = ffs(diff))) {
|
611 | 827df9f3 | balrog | ln --; |
612 | 827df9f3 | balrog | qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1);
|
613 | 827df9f3 | balrog | diff &= ~(1 << ln);
|
614 | 827df9f3 | balrog | } |
615 | 827df9f3 | balrog | } |
616 | 827df9f3 | balrog | |
617 | 827df9f3 | balrog | static void omap_gpio_module_level_update(struct omap2_gpio_s *s, int line) |
618 | 827df9f3 | balrog | { |
619 | 827df9f3 | balrog | s->ints[line] |= s->dir & |
620 | 827df9f3 | balrog | ((s->inputs & s->level[1]) | (~s->inputs & s->level[0])); |
621 | 827df9f3 | balrog | omap_gpio_module_int_update(s, line); |
622 | 827df9f3 | balrog | } |
623 | 827df9f3 | balrog | |
624 | 827df9f3 | balrog | static inline void omap_gpio_module_int(struct omap2_gpio_s *s, int line) |
625 | 827df9f3 | balrog | { |
626 | 827df9f3 | balrog | s->ints[0] |= 1 << line; |
627 | 827df9f3 | balrog | omap_gpio_module_int_update(s, 0);
|
628 | 827df9f3 | balrog | s->ints[1] |= 1 << line; |
629 | 827df9f3 | balrog | omap_gpio_module_int_update(s, 1);
|
630 | 827df9f3 | balrog | omap_gpio_module_wake(s, line); |
631 | 827df9f3 | balrog | } |
632 | 827df9f3 | balrog | |
633 | 827df9f3 | balrog | static void omap_gpio_module_set(void *opaque, int line, int level) |
634 | 827df9f3 | balrog | { |
635 | 827df9f3 | balrog | struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; |
636 | 827df9f3 | balrog | |
637 | 827df9f3 | balrog | if (level) {
|
638 | 827df9f3 | balrog | if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1])) |
639 | 827df9f3 | balrog | omap_gpio_module_int(s, line); |
640 | 827df9f3 | balrog | s->inputs |= 1 << line;
|
641 | 827df9f3 | balrog | } else {
|
642 | 827df9f3 | balrog | if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0])) |
643 | 827df9f3 | balrog | omap_gpio_module_int(s, line); |
644 | 827df9f3 | balrog | s->inputs &= ~(1 << line);
|
645 | 827df9f3 | balrog | } |
646 | 827df9f3 | balrog | } |
647 | 827df9f3 | balrog | |
648 | 827df9f3 | balrog | static void omap_gpio_module_reset(struct omap2_gpio_s *s) |
649 | 827df9f3 | balrog | { |
650 | 827df9f3 | balrog | s->config[0] = 0; |
651 | 827df9f3 | balrog | s->config[1] = 2; |
652 | 827df9f3 | balrog | s->ints[0] = 0; |
653 | 827df9f3 | balrog | s->ints[1] = 0; |
654 | 827df9f3 | balrog | s->mask[0] = 0; |
655 | 827df9f3 | balrog | s->mask[1] = 0; |
656 | 827df9f3 | balrog | s->wumask = 0;
|
657 | 827df9f3 | balrog | s->dir = ~0;
|
658 | 827df9f3 | balrog | s->level[0] = 0; |
659 | 827df9f3 | balrog | s->level[1] = 0; |
660 | 827df9f3 | balrog | s->edge[0] = 0; |
661 | 827df9f3 | balrog | s->edge[1] = 0; |
662 | 827df9f3 | balrog | s->debounce = 0;
|
663 | 827df9f3 | balrog | s->delay = 0;
|
664 | 827df9f3 | balrog | } |
665 | 827df9f3 | balrog | |
666 | 827df9f3 | balrog | static uint32_t omap_gpio_module_read(void *opaque, target_phys_addr_t addr) |
667 | 827df9f3 | balrog | { |
668 | 827df9f3 | balrog | struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; |
669 | 827df9f3 | balrog | int offset = addr - s->base;
|
670 | 827df9f3 | balrog | |
671 | 827df9f3 | balrog | switch (offset) {
|
672 | 827df9f3 | balrog | case 0x00: /* GPIO_REVISION */ |
673 | 827df9f3 | balrog | return 0x18; |
674 | 827df9f3 | balrog | |
675 | 827df9f3 | balrog | case 0x10: /* GPIO_SYSCONFIG */ |
676 | 827df9f3 | balrog | return s->config[0]; |
677 | 827df9f3 | balrog | |
678 | 827df9f3 | balrog | case 0x14: /* GPIO_SYSSTATUS */ |
679 | 827df9f3 | balrog | return 0x01; |
680 | 827df9f3 | balrog | |
681 | 827df9f3 | balrog | case 0x18: /* GPIO_IRQSTATUS1 */ |
682 | 827df9f3 | balrog | return s->ints[0]; |
683 | 827df9f3 | balrog | |
684 | 827df9f3 | balrog | case 0x1c: /* GPIO_IRQENABLE1 */ |
685 | 827df9f3 | balrog | case 0x60: /* GPIO_CLEARIRQENABLE1 */ |
686 | 827df9f3 | balrog | case 0x64: /* GPIO_SETIRQENABLE1 */ |
687 | 827df9f3 | balrog | return s->mask[0]; |
688 | 827df9f3 | balrog | |
689 | 827df9f3 | balrog | case 0x20: /* GPIO_WAKEUPENABLE */ |
690 | 827df9f3 | balrog | case 0x80: /* GPIO_CLEARWKUENA */ |
691 | 827df9f3 | balrog | case 0x84: /* GPIO_SETWKUENA */ |
692 | 827df9f3 | balrog | return s->wumask;
|
693 | 827df9f3 | balrog | |
694 | 827df9f3 | balrog | case 0x28: /* GPIO_IRQSTATUS2 */ |
695 | 827df9f3 | balrog | return s->ints[1]; |
696 | 827df9f3 | balrog | |
697 | 827df9f3 | balrog | case 0x2c: /* GPIO_IRQENABLE2 */ |
698 | 827df9f3 | balrog | case 0x70: /* GPIO_CLEARIRQENABLE2 */ |
699 | 827df9f3 | balrog | case 0x74: /* GPIO_SETIREQNEABLE2 */ |
700 | 827df9f3 | balrog | return s->mask[1]; |
701 | 827df9f3 | balrog | |
702 | 827df9f3 | balrog | case 0x30: /* GPIO_CTRL */ |
703 | 827df9f3 | balrog | return s->config[1]; |
704 | 827df9f3 | balrog | |
705 | 827df9f3 | balrog | case 0x34: /* GPIO_OE */ |
706 | 827df9f3 | balrog | return s->dir;
|
707 | 827df9f3 | balrog | |
708 | 827df9f3 | balrog | case 0x38: /* GPIO_DATAIN */ |
709 | 827df9f3 | balrog | return s->inputs;
|
710 | 827df9f3 | balrog | |
711 | 827df9f3 | balrog | case 0x3c: /* GPIO_DATAOUT */ |
712 | 827df9f3 | balrog | case 0x90: /* GPIO_CLEARDATAOUT */ |
713 | 827df9f3 | balrog | case 0x94: /* GPIO_SETDATAOUT */ |
714 | 827df9f3 | balrog | return s->outputs;
|
715 | 827df9f3 | balrog | |
716 | 827df9f3 | balrog | case 0x40: /* GPIO_LEVELDETECT0 */ |
717 | 827df9f3 | balrog | return s->level[0]; |
718 | 827df9f3 | balrog | |
719 | 827df9f3 | balrog | case 0x44: /* GPIO_LEVELDETECT1 */ |
720 | 827df9f3 | balrog | return s->level[1]; |
721 | 827df9f3 | balrog | |
722 | 827df9f3 | balrog | case 0x48: /* GPIO_RISINGDETECT */ |
723 | 827df9f3 | balrog | return s->edge[0]; |
724 | 827df9f3 | balrog | |
725 | 827df9f3 | balrog | case 0x4c: /* GPIO_FALLINGDETECT */ |
726 | 827df9f3 | balrog | return s->edge[1]; |
727 | 827df9f3 | balrog | |
728 | 827df9f3 | balrog | case 0x50: /* GPIO_DEBOUNCENABLE */ |
729 | 827df9f3 | balrog | return s->debounce;
|
730 | 827df9f3 | balrog | |
731 | 827df9f3 | balrog | case 0x54: /* GPIO_DEBOUNCINGTIME */ |
732 | 827df9f3 | balrog | return s->delay;
|
733 | 827df9f3 | balrog | } |
734 | 827df9f3 | balrog | |
735 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
736 | 827df9f3 | balrog | return 0; |
737 | 827df9f3 | balrog | } |
738 | 827df9f3 | balrog | |
739 | 827df9f3 | balrog | static void omap_gpio_module_write(void *opaque, target_phys_addr_t addr, |
740 | 827df9f3 | balrog | uint32_t value) |
741 | 827df9f3 | balrog | { |
742 | 827df9f3 | balrog | struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; |
743 | 827df9f3 | balrog | int offset = addr - s->base;
|
744 | 827df9f3 | balrog | uint32_t diff; |
745 | 827df9f3 | balrog | int ln;
|
746 | 827df9f3 | balrog | |
747 | 827df9f3 | balrog | switch (offset) {
|
748 | 827df9f3 | balrog | case 0x00: /* GPIO_REVISION */ |
749 | 827df9f3 | balrog | case 0x14: /* GPIO_SYSSTATUS */ |
750 | 827df9f3 | balrog | case 0x38: /* GPIO_DATAIN */ |
751 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
752 | 827df9f3 | balrog | break;
|
753 | 827df9f3 | balrog | |
754 | 827df9f3 | balrog | case 0x10: /* GPIO_SYSCONFIG */ |
755 | 827df9f3 | balrog | if (((value >> 3) & 3) == 3) |
756 | 827df9f3 | balrog | fprintf(stderr, "%s: bad IDLEMODE value\n", __FUNCTION__);
|
757 | 827df9f3 | balrog | if (value & 2) |
758 | 827df9f3 | balrog | omap_gpio_module_reset(s); |
759 | 827df9f3 | balrog | s->config[0] = value & 0x1d; |
760 | 827df9f3 | balrog | break;
|
761 | 827df9f3 | balrog | |
762 | 827df9f3 | balrog | case 0x18: /* GPIO_IRQSTATUS1 */ |
763 | 827df9f3 | balrog | if (s->ints[0] & value) { |
764 | 827df9f3 | balrog | s->ints[0] &= ~value;
|
765 | 827df9f3 | balrog | omap_gpio_module_level_update(s, 0);
|
766 | 827df9f3 | balrog | } |
767 | 827df9f3 | balrog | break;
|
768 | 827df9f3 | balrog | |
769 | 827df9f3 | balrog | case 0x1c: /* GPIO_IRQENABLE1 */ |
770 | 827df9f3 | balrog | s->mask[0] = value;
|
771 | 827df9f3 | balrog | omap_gpio_module_int_update(s, 0);
|
772 | 827df9f3 | balrog | break;
|
773 | 827df9f3 | balrog | |
774 | 827df9f3 | balrog | case 0x20: /* GPIO_WAKEUPENABLE */ |
775 | 827df9f3 | balrog | s->wumask = value; |
776 | 827df9f3 | balrog | break;
|
777 | 827df9f3 | balrog | |
778 | 827df9f3 | balrog | case 0x28: /* GPIO_IRQSTATUS2 */ |
779 | 827df9f3 | balrog | if (s->ints[1] & value) { |
780 | 827df9f3 | balrog | s->ints[1] &= ~value;
|
781 | 827df9f3 | balrog | omap_gpio_module_level_update(s, 1);
|
782 | 827df9f3 | balrog | } |
783 | 827df9f3 | balrog | break;
|
784 | 827df9f3 | balrog | |
785 | 827df9f3 | balrog | case 0x2c: /* GPIO_IRQENABLE2 */ |
786 | 827df9f3 | balrog | s->mask[1] = value;
|
787 | 827df9f3 | balrog | omap_gpio_module_int_update(s, 1);
|
788 | 827df9f3 | balrog | break;
|
789 | 827df9f3 | balrog | |
790 | 827df9f3 | balrog | case 0x30: /* GPIO_CTRL */ |
791 | 827df9f3 | balrog | s->config[1] = value & 7; |
792 | 827df9f3 | balrog | break;
|
793 | 827df9f3 | balrog | |
794 | 827df9f3 | balrog | case 0x34: /* GPIO_OE */ |
795 | 827df9f3 | balrog | diff = s->outputs & (s->dir ^ value); |
796 | 827df9f3 | balrog | s->dir = value; |
797 | 827df9f3 | balrog | |
798 | 827df9f3 | balrog | value = s->outputs & ~s->dir; |
799 | 827df9f3 | balrog | while ((ln = ffs(diff))) {
|
800 | 827df9f3 | balrog | diff &= ~(1 <<-- ln);
|
801 | 827df9f3 | balrog | qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
802 | 827df9f3 | balrog | } |
803 | 827df9f3 | balrog | |
804 | 827df9f3 | balrog | omap_gpio_module_level_update(s, 0);
|
805 | 827df9f3 | balrog | omap_gpio_module_level_update(s, 1);
|
806 | 827df9f3 | balrog | break;
|
807 | 827df9f3 | balrog | |
808 | 827df9f3 | balrog | case 0x3c: /* GPIO_DATAOUT */ |
809 | 827df9f3 | balrog | omap_gpio_module_out_update(s, s->outputs ^ value); |
810 | 827df9f3 | balrog | break;
|
811 | 827df9f3 | balrog | |
812 | 827df9f3 | balrog | case 0x40: /* GPIO_LEVELDETECT0 */ |
813 | 827df9f3 | balrog | s->level[0] = value;
|
814 | 827df9f3 | balrog | omap_gpio_module_level_update(s, 0);
|
815 | 827df9f3 | balrog | omap_gpio_module_level_update(s, 1);
|
816 | 827df9f3 | balrog | break;
|
817 | 827df9f3 | balrog | |
818 | 827df9f3 | balrog | case 0x44: /* GPIO_LEVELDETECT1 */ |
819 | 827df9f3 | balrog | s->level[1] = value;
|
820 | 827df9f3 | balrog | omap_gpio_module_level_update(s, 0);
|
821 | 827df9f3 | balrog | omap_gpio_module_level_update(s, 1);
|
822 | 827df9f3 | balrog | break;
|
823 | 827df9f3 | balrog | |
824 | 827df9f3 | balrog | case 0x48: /* GPIO_RISINGDETECT */ |
825 | 827df9f3 | balrog | s->edge[0] = value;
|
826 | 827df9f3 | balrog | break;
|
827 | 827df9f3 | balrog | |
828 | 827df9f3 | balrog | case 0x4c: /* GPIO_FALLINGDETECT */ |
829 | 827df9f3 | balrog | s->edge[1] = value;
|
830 | 827df9f3 | balrog | break;
|
831 | 827df9f3 | balrog | |
832 | 827df9f3 | balrog | case 0x50: /* GPIO_DEBOUNCENABLE */ |
833 | 827df9f3 | balrog | s->debounce = value; |
834 | 827df9f3 | balrog | break;
|
835 | 827df9f3 | balrog | |
836 | 827df9f3 | balrog | case 0x54: /* GPIO_DEBOUNCINGTIME */ |
837 | 827df9f3 | balrog | s->delay = value; |
838 | 827df9f3 | balrog | break;
|
839 | 827df9f3 | balrog | |
840 | 827df9f3 | balrog | case 0x60: /* GPIO_CLEARIRQENABLE1 */ |
841 | 827df9f3 | balrog | s->mask[0] &= ~value;
|
842 | 827df9f3 | balrog | omap_gpio_module_int_update(s, 0);
|
843 | 827df9f3 | balrog | break;
|
844 | 827df9f3 | balrog | |
845 | 827df9f3 | balrog | case 0x64: /* GPIO_SETIRQENABLE1 */ |
846 | 827df9f3 | balrog | s->mask[0] |= value;
|
847 | 827df9f3 | balrog | omap_gpio_module_int_update(s, 0);
|
848 | 827df9f3 | balrog | break;
|
849 | 827df9f3 | balrog | |
850 | 827df9f3 | balrog | case 0x70: /* GPIO_CLEARIRQENABLE2 */ |
851 | 827df9f3 | balrog | s->mask[1] &= ~value;
|
852 | 827df9f3 | balrog | omap_gpio_module_int_update(s, 1);
|
853 | 827df9f3 | balrog | break;
|
854 | 827df9f3 | balrog | |
855 | 827df9f3 | balrog | case 0x74: /* GPIO_SETIREQNEABLE2 */ |
856 | 827df9f3 | balrog | s->mask[1] |= value;
|
857 | 827df9f3 | balrog | omap_gpio_module_int_update(s, 1);
|
858 | 827df9f3 | balrog | break;
|
859 | 827df9f3 | balrog | |
860 | 827df9f3 | balrog | case 0x80: /* GPIO_CLEARWKUENA */ |
861 | 827df9f3 | balrog | s->wumask &= ~value; |
862 | 827df9f3 | balrog | break;
|
863 | 827df9f3 | balrog | |
864 | 827df9f3 | balrog | case 0x84: /* GPIO_SETWKUENA */ |
865 | 827df9f3 | balrog | s->wumask |= value; |
866 | 827df9f3 | balrog | break;
|
867 | 827df9f3 | balrog | |
868 | 827df9f3 | balrog | case 0x90: /* GPIO_CLEARDATAOUT */ |
869 | 827df9f3 | balrog | omap_gpio_module_out_update(s, s->outputs & value); |
870 | 827df9f3 | balrog | break;
|
871 | 827df9f3 | balrog | |
872 | 827df9f3 | balrog | case 0x94: /* GPIO_SETDATAOUT */ |
873 | 827df9f3 | balrog | omap_gpio_module_out_update(s, ~s->outputs & value); |
874 | 827df9f3 | balrog | break;
|
875 | 827df9f3 | balrog | |
876 | 827df9f3 | balrog | default:
|
877 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
878 | 827df9f3 | balrog | return;
|
879 | 827df9f3 | balrog | } |
880 | 827df9f3 | balrog | } |
881 | 827df9f3 | balrog | |
882 | 827df9f3 | balrog | static uint32_t omap_gpio_module_readp(void *opaque, target_phys_addr_t addr) |
883 | 827df9f3 | balrog | { |
884 | 827df9f3 | balrog | return omap_gpio_module_readp(opaque, addr) >> ((addr & 3) << 3); |
885 | 827df9f3 | balrog | } |
886 | 827df9f3 | balrog | |
887 | 827df9f3 | balrog | static void omap_gpio_module_writep(void *opaque, target_phys_addr_t addr, |
888 | 827df9f3 | balrog | uint32_t value) |
889 | 827df9f3 | balrog | { |
890 | 827df9f3 | balrog | struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; |
891 | 827df9f3 | balrog | int offset = addr - s->base;
|
892 | 827df9f3 | balrog | uint32_t cur = 0;
|
893 | 827df9f3 | balrog | uint32_t mask = 0xffff;
|
894 | 827df9f3 | balrog | |
895 | 827df9f3 | balrog | switch (offset & ~3) { |
896 | 827df9f3 | balrog | case 0x00: /* GPIO_REVISION */ |
897 | 827df9f3 | balrog | case 0x14: /* GPIO_SYSSTATUS */ |
898 | 827df9f3 | balrog | case 0x38: /* GPIO_DATAIN */ |
899 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
900 | 827df9f3 | balrog | break;
|
901 | 827df9f3 | balrog | |
902 | 827df9f3 | balrog | case 0x10: /* GPIO_SYSCONFIG */ |
903 | 827df9f3 | balrog | case 0x1c: /* GPIO_IRQENABLE1 */ |
904 | 827df9f3 | balrog | case 0x20: /* GPIO_WAKEUPENABLE */ |
905 | 827df9f3 | balrog | case 0x2c: /* GPIO_IRQENABLE2 */ |
906 | 827df9f3 | balrog | case 0x30: /* GPIO_CTRL */ |
907 | 827df9f3 | balrog | case 0x34: /* GPIO_OE */ |
908 | 827df9f3 | balrog | case 0x3c: /* GPIO_DATAOUT */ |
909 | 827df9f3 | balrog | case 0x40: /* GPIO_LEVELDETECT0 */ |
910 | 827df9f3 | balrog | case 0x44: /* GPIO_LEVELDETECT1 */ |
911 | 827df9f3 | balrog | case 0x48: /* GPIO_RISINGDETECT */ |
912 | 827df9f3 | balrog | case 0x4c: /* GPIO_FALLINGDETECT */ |
913 | 827df9f3 | balrog | case 0x50: /* GPIO_DEBOUNCENABLE */ |
914 | 827df9f3 | balrog | case 0x54: /* GPIO_DEBOUNCINGTIME */ |
915 | 827df9f3 | balrog | cur = omap_gpio_module_read(opaque, addr & ~3) &
|
916 | 827df9f3 | balrog | ~(mask << ((addr & 3) << 3)); |
917 | 827df9f3 | balrog | |
918 | 827df9f3 | balrog | /* Fall through. */
|
919 | 827df9f3 | balrog | case 0x18: /* GPIO_IRQSTATUS1 */ |
920 | 827df9f3 | balrog | case 0x28: /* GPIO_IRQSTATUS2 */ |
921 | 827df9f3 | balrog | case 0x60: /* GPIO_CLEARIRQENABLE1 */ |
922 | 827df9f3 | balrog | case 0x64: /* GPIO_SETIRQENABLE1 */ |
923 | 827df9f3 | balrog | case 0x70: /* GPIO_CLEARIRQENABLE2 */ |
924 | 827df9f3 | balrog | case 0x74: /* GPIO_SETIREQNEABLE2 */ |
925 | 827df9f3 | balrog | case 0x80: /* GPIO_CLEARWKUENA */ |
926 | 827df9f3 | balrog | case 0x84: /* GPIO_SETWKUENA */ |
927 | 827df9f3 | balrog | case 0x90: /* GPIO_CLEARDATAOUT */ |
928 | 827df9f3 | balrog | case 0x94: /* GPIO_SETDATAOUT */ |
929 | 827df9f3 | balrog | value <<= (addr & 3) << 3; |
930 | 827df9f3 | balrog | omap_gpio_module_write(opaque, addr, cur | value); |
931 | 827df9f3 | balrog | break;
|
932 | 827df9f3 | balrog | |
933 | 827df9f3 | balrog | default:
|
934 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
935 | 827df9f3 | balrog | return;
|
936 | 827df9f3 | balrog | } |
937 | 827df9f3 | balrog | } |
938 | 827df9f3 | balrog | |
939 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap_gpio_module_readfn[] = {
|
940 | 827df9f3 | balrog | omap_gpio_module_readp, |
941 | 827df9f3 | balrog | omap_gpio_module_readp, |
942 | 827df9f3 | balrog | omap_gpio_module_read, |
943 | 827df9f3 | balrog | }; |
944 | 827df9f3 | balrog | |
945 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap_gpio_module_writefn[] = {
|
946 | 827df9f3 | balrog | omap_gpio_module_writep, |
947 | 827df9f3 | balrog | omap_gpio_module_writep, |
948 | 827df9f3 | balrog | omap_gpio_module_write, |
949 | 827df9f3 | balrog | }; |
950 | 827df9f3 | balrog | |
951 | 827df9f3 | balrog | static void omap_gpio_module_init(struct omap2_gpio_s *s, |
952 | 827df9f3 | balrog | struct omap_target_agent_s *ta, int region, |
953 | 827df9f3 | balrog | qemu_irq mpu, qemu_irq dsp, qemu_irq wkup, |
954 | 827df9f3 | balrog | omap_clk fclk, omap_clk iclk) |
955 | 827df9f3 | balrog | { |
956 | 827df9f3 | balrog | int iomemtype;
|
957 | 827df9f3 | balrog | |
958 | 827df9f3 | balrog | s->irq[0] = mpu;
|
959 | 827df9f3 | balrog | s->irq[1] = dsp;
|
960 | 827df9f3 | balrog | s->wkup = wkup; |
961 | 827df9f3 | balrog | s->in = qemu_allocate_irqs(omap_gpio_module_set, s, 32);
|
962 | 827df9f3 | balrog | |
963 | c66fb5bc | balrog | iomemtype = l4_register_io_memory(0, omap_gpio_module_readfn,
|
964 | 827df9f3 | balrog | omap_gpio_module_writefn, s); |
965 | 827df9f3 | balrog | s->base = omap_l4_attach(ta, region, iomemtype); |
966 | 827df9f3 | balrog | } |
967 | 827df9f3 | balrog | |
968 | 827df9f3 | balrog | struct omap_gpif_s {
|
969 | 827df9f3 | balrog | struct omap2_gpio_s module[5]; |
970 | 827df9f3 | balrog | int modules;
|
971 | 827df9f3 | balrog | |
972 | 827df9f3 | balrog | target_phys_addr_t topbase; |
973 | 827df9f3 | balrog | int autoidle;
|
974 | 827df9f3 | balrog | int gpo;
|
975 | 827df9f3 | balrog | }; |
976 | 827df9f3 | balrog | |
977 | 827df9f3 | balrog | static void omap_gpif_reset(struct omap_gpif_s *s) |
978 | 827df9f3 | balrog | { |
979 | 827df9f3 | balrog | int i;
|
980 | 827df9f3 | balrog | |
981 | 827df9f3 | balrog | for (i = 0; i < s->modules; i ++) |
982 | 827df9f3 | balrog | omap_gpio_module_reset(s->module + i); |
983 | 827df9f3 | balrog | |
984 | 827df9f3 | balrog | s->autoidle = 0;
|
985 | 827df9f3 | balrog | s->gpo = 0;
|
986 | 827df9f3 | balrog | } |
987 | 827df9f3 | balrog | |
988 | 827df9f3 | balrog | static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr) |
989 | 827df9f3 | balrog | { |
990 | 827df9f3 | balrog | struct omap_gpif_s *s = (struct omap_gpif_s *) opaque; |
991 | 827df9f3 | balrog | int offset = addr - s->topbase;
|
992 | 827df9f3 | balrog | |
993 | 827df9f3 | balrog | switch (offset) {
|
994 | 827df9f3 | balrog | case 0x00: /* IPGENERICOCPSPL_REVISION */ |
995 | 827df9f3 | balrog | return 0x18; |
996 | 827df9f3 | balrog | |
997 | 827df9f3 | balrog | case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ |
998 | 827df9f3 | balrog | return s->autoidle;
|
999 | 827df9f3 | balrog | |
1000 | 827df9f3 | balrog | case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ |
1001 | 827df9f3 | balrog | return 0x01; |
1002 | 827df9f3 | balrog | |
1003 | 827df9f3 | balrog | case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ |
1004 | 827df9f3 | balrog | return 0x00; |
1005 | 827df9f3 | balrog | |
1006 | 827df9f3 | balrog | case 0x40: /* IPGENERICOCPSPL_GPO */ |
1007 | 827df9f3 | balrog | return s->gpo;
|
1008 | 827df9f3 | balrog | |
1009 | 827df9f3 | balrog | case 0x50: /* IPGENERICOCPSPL_GPI */ |
1010 | 827df9f3 | balrog | return 0x00; |
1011 | 827df9f3 | balrog | } |
1012 | 827df9f3 | balrog | |
1013 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1014 | 827df9f3 | balrog | return 0; |
1015 | 827df9f3 | balrog | } |
1016 | 827df9f3 | balrog | |
1017 | 827df9f3 | balrog | static void omap_gpif_top_write(void *opaque, target_phys_addr_t addr, |
1018 | 827df9f3 | balrog | uint32_t value) |
1019 | 827df9f3 | balrog | { |
1020 | 827df9f3 | balrog | struct omap_gpif_s *s = (struct omap_gpif_s *) opaque; |
1021 | 827df9f3 | balrog | int offset = addr - s->topbase;
|
1022 | 827df9f3 | balrog | |
1023 | 827df9f3 | balrog | switch (offset) {
|
1024 | 827df9f3 | balrog | case 0x00: /* IPGENERICOCPSPL_REVISION */ |
1025 | 827df9f3 | balrog | case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ |
1026 | 827df9f3 | balrog | case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ |
1027 | 827df9f3 | balrog | case 0x50: /* IPGENERICOCPSPL_GPI */ |
1028 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
1029 | 827df9f3 | balrog | break;
|
1030 | 827df9f3 | balrog | |
1031 | 827df9f3 | balrog | case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ |
1032 | 827df9f3 | balrog | if (value & (1 << 1)) /* SOFTRESET */ |
1033 | 827df9f3 | balrog | omap_gpif_reset(s); |
1034 | 827df9f3 | balrog | s->autoidle = value & 1;
|
1035 | 827df9f3 | balrog | break;
|
1036 | 827df9f3 | balrog | |
1037 | 827df9f3 | balrog | case 0x40: /* IPGENERICOCPSPL_GPO */ |
1038 | 827df9f3 | balrog | s->gpo = value & 1;
|
1039 | 827df9f3 | balrog | break;
|
1040 | 827df9f3 | balrog | |
1041 | 827df9f3 | balrog | default:
|
1042 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1043 | 827df9f3 | balrog | return;
|
1044 | 827df9f3 | balrog | } |
1045 | 827df9f3 | balrog | } |
1046 | 827df9f3 | balrog | |
1047 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap_gpif_top_readfn[] = {
|
1048 | 827df9f3 | balrog | omap_gpif_top_read, |
1049 | 827df9f3 | balrog | omap_gpif_top_read, |
1050 | 827df9f3 | balrog | omap_gpif_top_read, |
1051 | 827df9f3 | balrog | }; |
1052 | 827df9f3 | balrog | |
1053 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap_gpif_top_writefn[] = {
|
1054 | 827df9f3 | balrog | omap_gpif_top_write, |
1055 | 827df9f3 | balrog | omap_gpif_top_write, |
1056 | 827df9f3 | balrog | omap_gpif_top_write, |
1057 | 827df9f3 | balrog | }; |
1058 | 827df9f3 | balrog | |
1059 | 827df9f3 | balrog | struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta, |
1060 | 827df9f3 | balrog | qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules)
|
1061 | 827df9f3 | balrog | { |
1062 | 827df9f3 | balrog | int iomemtype, i;
|
1063 | 827df9f3 | balrog | struct omap_gpif_s *s = (struct omap_gpif_s *) |
1064 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_gpif_s)); |
1065 | 827df9f3 | balrog | int region[4] = { 0, 2, 4, 5 }; |
1066 | 827df9f3 | balrog | |
1067 | 827df9f3 | balrog | s->modules = modules; |
1068 | 827df9f3 | balrog | for (i = 0; i < modules; i ++) |
1069 | 827df9f3 | balrog | omap_gpio_module_init(s->module + i, ta, region[i], |
1070 | 827df9f3 | balrog | irq[i], 0, 0, fclk[i], iclk); |
1071 | 827df9f3 | balrog | |
1072 | 827df9f3 | balrog | omap_gpif_reset(s); |
1073 | 827df9f3 | balrog | |
1074 | c66fb5bc | balrog | iomemtype = l4_register_io_memory(0, omap_gpif_top_readfn,
|
1075 | 827df9f3 | balrog | omap_gpif_top_writefn, s); |
1076 | 827df9f3 | balrog | s->topbase = omap_l4_attach(ta, 1, iomemtype);
|
1077 | 827df9f3 | balrog | |
1078 | 827df9f3 | balrog | return s;
|
1079 | 827df9f3 | balrog | } |
1080 | 827df9f3 | balrog | |
1081 | 827df9f3 | balrog | qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start) |
1082 | 827df9f3 | balrog | { |
1083 | 827df9f3 | balrog | if (start >= s->modules * 32 || start < 0) |
1084 | 827df9f3 | balrog | cpu_abort(cpu_single_env, "%s: No GPIO line %i\n",
|
1085 | 827df9f3 | balrog | __FUNCTION__, start); |
1086 | 827df9f3 | balrog | return s->module[start >> 5].in + (start & 31); |
1087 | 827df9f3 | balrog | } |
1088 | 827df9f3 | balrog | |
1089 | 827df9f3 | balrog | void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler) |
1090 | 827df9f3 | balrog | { |
1091 | 827df9f3 | balrog | if (line >= s->modules * 32 || line < 0) |
1092 | 827df9f3 | balrog | cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
|
1093 | 827df9f3 | balrog | s->module[line >> 5].handler[line & 31] = handler; |
1094 | 827df9f3 | balrog | } |
1095 | 827df9f3 | balrog | |
1096 | 827df9f3 | balrog | /* Multichannel SPI */
|
1097 | 827df9f3 | balrog | struct omap_mcspi_s {
|
1098 | 827df9f3 | balrog | target_phys_addr_t base; |
1099 | 827df9f3 | balrog | qemu_irq irq; |
1100 | 827df9f3 | balrog | int chnum;
|
1101 | 827df9f3 | balrog | |
1102 | 827df9f3 | balrog | uint32_t sysconfig; |
1103 | 827df9f3 | balrog | uint32_t systest; |
1104 | 827df9f3 | balrog | uint32_t irqst; |
1105 | 827df9f3 | balrog | uint32_t irqen; |
1106 | 827df9f3 | balrog | uint32_t wken; |
1107 | 827df9f3 | balrog | uint32_t control; |
1108 | 827df9f3 | balrog | |
1109 | 827df9f3 | balrog | struct omap_mcspi_ch_s {
|
1110 | 827df9f3 | balrog | qemu_irq txdrq; |
1111 | 827df9f3 | balrog | qemu_irq rxdrq; |
1112 | e927bb00 | balrog | uint32_t (*txrx)(void *opaque, uint32_t, int); |
1113 | 827df9f3 | balrog | void *opaque;
|
1114 | 827df9f3 | balrog | |
1115 | 827df9f3 | balrog | uint32_t tx; |
1116 | 827df9f3 | balrog | uint32_t rx; |
1117 | 827df9f3 | balrog | |
1118 | 827df9f3 | balrog | uint32_t config; |
1119 | 827df9f3 | balrog | uint32_t status; |
1120 | 827df9f3 | balrog | uint32_t control; |
1121 | 827df9f3 | balrog | } ch[4];
|
1122 | 827df9f3 | balrog | }; |
1123 | 827df9f3 | balrog | |
1124 | 827df9f3 | balrog | static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s) |
1125 | 827df9f3 | balrog | { |
1126 | 827df9f3 | balrog | qemu_set_irq(s->irq, s->irqst & s->irqen); |
1127 | 827df9f3 | balrog | } |
1128 | 827df9f3 | balrog | |
1129 | 827df9f3 | balrog | static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch) |
1130 | 827df9f3 | balrog | { |
1131 | 827df9f3 | balrog | qemu_set_irq(ch->txdrq, |
1132 | 827df9f3 | balrog | (ch->control & 1) && /* EN */ |
1133 | 827df9f3 | balrog | (ch->config & (1 << 14)) && /* DMAW */ |
1134 | 827df9f3 | balrog | (ch->status & (1 << 1)) && /* TXS */ |
1135 | 827df9f3 | balrog | ((ch->config >> 12) & 3) != 1); /* TRM */ |
1136 | 827df9f3 | balrog | qemu_set_irq(ch->rxdrq, |
1137 | 827df9f3 | balrog | (ch->control & 1) && /* EN */ |
1138 | 827df9f3 | balrog | (ch->config & (1 << 15)) && /* DMAW */ |
1139 | 827df9f3 | balrog | (ch->status & (1 << 0)) && /* RXS */ |
1140 | 827df9f3 | balrog | ((ch->config >> 12) & 3) != 2); /* TRM */ |
1141 | 827df9f3 | balrog | } |
1142 | 827df9f3 | balrog | |
1143 | 827df9f3 | balrog | static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum) |
1144 | 827df9f3 | balrog | { |
1145 | 827df9f3 | balrog | struct omap_mcspi_ch_s *ch = s->ch + chnum;
|
1146 | 827df9f3 | balrog | |
1147 | 827df9f3 | balrog | if (!(ch->control & 1)) /* EN */ |
1148 | 827df9f3 | balrog | return;
|
1149 | 827df9f3 | balrog | if ((ch->status & (1 << 0)) && /* RXS */ |
1150 | 827df9f3 | balrog | ((ch->config >> 12) & 3) != 2 && /* TRM */ |
1151 | 827df9f3 | balrog | !(ch->config & (1 << 19))) /* TURBO */ |
1152 | 827df9f3 | balrog | goto intr_update;
|
1153 | 827df9f3 | balrog | if ((ch->status & (1 << 1)) && /* TXS */ |
1154 | 827df9f3 | balrog | ((ch->config >> 12) & 3) != 1) /* TRM */ |
1155 | 827df9f3 | balrog | goto intr_update;
|
1156 | 827df9f3 | balrog | |
1157 | 827df9f3 | balrog | if (!(s->control & 1) || /* SINGLE */ |
1158 | 827df9f3 | balrog | (ch->config & (1 << 20))) { /* FORCE */ |
1159 | 827df9f3 | balrog | if (ch->txrx)
|
1160 | e927bb00 | balrog | ch->rx = ch->txrx(ch->opaque, ch->tx, /* WL */
|
1161 | e927bb00 | balrog | 1 + (0x1f & (ch->config >> 7))); |
1162 | 827df9f3 | balrog | } |
1163 | 827df9f3 | balrog | |
1164 | 827df9f3 | balrog | ch->tx = 0;
|
1165 | 827df9f3 | balrog | ch->status |= 1 << 2; /* EOT */ |
1166 | 827df9f3 | balrog | ch->status |= 1 << 1; /* TXS */ |
1167 | 827df9f3 | balrog | if (((ch->config >> 12) & 3) != 2) /* TRM */ |
1168 | 827df9f3 | balrog | ch->status |= 1 << 0; /* RXS */ |
1169 | 827df9f3 | balrog | |
1170 | 827df9f3 | balrog | intr_update:
|
1171 | 827df9f3 | balrog | if ((ch->status & (1 << 0)) && /* RXS */ |
1172 | 827df9f3 | balrog | ((ch->config >> 12) & 3) != 2 && /* TRM */ |
1173 | 827df9f3 | balrog | !(ch->config & (1 << 19))) /* TURBO */ |
1174 | 827df9f3 | balrog | s->irqst |= 1 << (2 + 4 * chnum); /* RX_FULL */ |
1175 | 827df9f3 | balrog | if ((ch->status & (1 << 1)) && /* TXS */ |
1176 | 827df9f3 | balrog | ((ch->config >> 12) & 3) != 1) /* TRM */ |
1177 | 827df9f3 | balrog | s->irqst |= 1 << (0 + 4 * chnum); /* TX_EMPTY */ |
1178 | 827df9f3 | balrog | omap_mcspi_interrupt_update(s); |
1179 | 827df9f3 | balrog | omap_mcspi_dmarequest_update(ch); |
1180 | 827df9f3 | balrog | } |
1181 | 827df9f3 | balrog | |
1182 | 827df9f3 | balrog | static void omap_mcspi_reset(struct omap_mcspi_s *s) |
1183 | 827df9f3 | balrog | { |
1184 | 827df9f3 | balrog | int ch;
|
1185 | 827df9f3 | balrog | |
1186 | 827df9f3 | balrog | s->sysconfig = 0;
|
1187 | 827df9f3 | balrog | s->systest = 0;
|
1188 | 827df9f3 | balrog | s->irqst = 0;
|
1189 | 827df9f3 | balrog | s->irqen = 0;
|
1190 | 827df9f3 | balrog | s->wken = 0;
|
1191 | 827df9f3 | balrog | s->control = 4;
|
1192 | 827df9f3 | balrog | |
1193 | 827df9f3 | balrog | for (ch = 0; ch < 4; ch ++) { |
1194 | 827df9f3 | balrog | s->ch[ch].config = 0x060000;
|
1195 | 827df9f3 | balrog | s->ch[ch].status = 2; /* TXS */ |
1196 | 827df9f3 | balrog | s->ch[ch].control = 0;
|
1197 | 827df9f3 | balrog | |
1198 | 827df9f3 | balrog | omap_mcspi_dmarequest_update(s->ch + ch); |
1199 | 827df9f3 | balrog | } |
1200 | 827df9f3 | balrog | |
1201 | 827df9f3 | balrog | omap_mcspi_interrupt_update(s); |
1202 | 827df9f3 | balrog | } |
1203 | 827df9f3 | balrog | |
1204 | 827df9f3 | balrog | static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr) |
1205 | 827df9f3 | balrog | { |
1206 | 827df9f3 | balrog | struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque; |
1207 | 827df9f3 | balrog | int offset = addr - s->base;
|
1208 | 827df9f3 | balrog | int ch = 0; |
1209 | 827df9f3 | balrog | uint32_t ret; |
1210 | 827df9f3 | balrog | |
1211 | 827df9f3 | balrog | switch (offset) {
|
1212 | 827df9f3 | balrog | case 0x00: /* MCSPI_REVISION */ |
1213 | 827df9f3 | balrog | return 0x91; |
1214 | 827df9f3 | balrog | |
1215 | 827df9f3 | balrog | case 0x10: /* MCSPI_SYSCONFIG */ |
1216 | 827df9f3 | balrog | return s->sysconfig;
|
1217 | 827df9f3 | balrog | |
1218 | 827df9f3 | balrog | case 0x14: /* MCSPI_SYSSTATUS */ |
1219 | 827df9f3 | balrog | return 1; /* RESETDONE */ |
1220 | 827df9f3 | balrog | |
1221 | 827df9f3 | balrog | case 0x18: /* MCSPI_IRQSTATUS */ |
1222 | 827df9f3 | balrog | return s->irqst;
|
1223 | 827df9f3 | balrog | |
1224 | 827df9f3 | balrog | case 0x1c: /* MCSPI_IRQENABLE */ |
1225 | 827df9f3 | balrog | return s->irqen;
|
1226 | 827df9f3 | balrog | |
1227 | 827df9f3 | balrog | case 0x20: /* MCSPI_WAKEUPENABLE */ |
1228 | 827df9f3 | balrog | return s->wken;
|
1229 | 827df9f3 | balrog | |
1230 | 827df9f3 | balrog | case 0x24: /* MCSPI_SYST */ |
1231 | 827df9f3 | balrog | return s->systest;
|
1232 | 827df9f3 | balrog | |
1233 | 827df9f3 | balrog | case 0x28: /* MCSPI_MODULCTRL */ |
1234 | 827df9f3 | balrog | return s->control;
|
1235 | 827df9f3 | balrog | |
1236 | 827df9f3 | balrog | case 0x68: ch ++; |
1237 | 827df9f3 | balrog | case 0x54: ch ++; |
1238 | 827df9f3 | balrog | case 0x40: ch ++; |
1239 | 827df9f3 | balrog | case 0x2c: /* MCSPI_CHCONF */ |
1240 | 827df9f3 | balrog | return s->ch[ch].config;
|
1241 | 827df9f3 | balrog | |
1242 | 827df9f3 | balrog | case 0x6c: ch ++; |
1243 | 827df9f3 | balrog | case 0x58: ch ++; |
1244 | 827df9f3 | balrog | case 0x44: ch ++; |
1245 | 827df9f3 | balrog | case 0x30: /* MCSPI_CHSTAT */ |
1246 | 827df9f3 | balrog | return s->ch[ch].status;
|
1247 | 827df9f3 | balrog | |
1248 | 827df9f3 | balrog | case 0x70: ch ++; |
1249 | 827df9f3 | balrog | case 0x5c: ch ++; |
1250 | 827df9f3 | balrog | case 0x48: ch ++; |
1251 | 827df9f3 | balrog | case 0x34: /* MCSPI_CHCTRL */ |
1252 | 827df9f3 | balrog | return s->ch[ch].control;
|
1253 | 827df9f3 | balrog | |
1254 | 827df9f3 | balrog | case 0x74: ch ++; |
1255 | 827df9f3 | balrog | case 0x60: ch ++; |
1256 | 827df9f3 | balrog | case 0x4c: ch ++; |
1257 | 827df9f3 | balrog | case 0x38: /* MCSPI_TX */ |
1258 | 827df9f3 | balrog | return s->ch[ch].tx;
|
1259 | 827df9f3 | balrog | |
1260 | 827df9f3 | balrog | case 0x78: ch ++; |
1261 | 827df9f3 | balrog | case 0x64: ch ++; |
1262 | 827df9f3 | balrog | case 0x50: ch ++; |
1263 | 827df9f3 | balrog | case 0x3c: /* MCSPI_RX */ |
1264 | 827df9f3 | balrog | s->ch[ch].status &= ~(1 << 0); /* RXS */ |
1265 | 827df9f3 | balrog | ret = s->ch[ch].rx; |
1266 | 827df9f3 | balrog | omap_mcspi_transfer_run(s, ch); |
1267 | 827df9f3 | balrog | return ret;
|
1268 | 827df9f3 | balrog | } |
1269 | 827df9f3 | balrog | |
1270 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1271 | 827df9f3 | balrog | return 0; |
1272 | 827df9f3 | balrog | } |
1273 | 827df9f3 | balrog | |
1274 | 827df9f3 | balrog | static void omap_mcspi_write(void *opaque, target_phys_addr_t addr, |
1275 | 827df9f3 | balrog | uint32_t value) |
1276 | 827df9f3 | balrog | { |
1277 | 827df9f3 | balrog | struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque; |
1278 | 827df9f3 | balrog | int offset = addr - s->base;
|
1279 | 827df9f3 | balrog | int ch = 0; |
1280 | 827df9f3 | balrog | |
1281 | 827df9f3 | balrog | switch (offset) {
|
1282 | 827df9f3 | balrog | case 0x00: /* MCSPI_REVISION */ |
1283 | 827df9f3 | balrog | case 0x14: /* MCSPI_SYSSTATUS */ |
1284 | 827df9f3 | balrog | case 0x30: /* MCSPI_CHSTAT0 */ |
1285 | 827df9f3 | balrog | case 0x3c: /* MCSPI_RX0 */ |
1286 | 827df9f3 | balrog | case 0x44: /* MCSPI_CHSTAT1 */ |
1287 | 827df9f3 | balrog | case 0x50: /* MCSPI_RX1 */ |
1288 | 827df9f3 | balrog | case 0x58: /* MCSPI_CHSTAT2 */ |
1289 | 827df9f3 | balrog | case 0x64: /* MCSPI_RX2 */ |
1290 | 827df9f3 | balrog | case 0x6c: /* MCSPI_CHSTAT3 */ |
1291 | 827df9f3 | balrog | case 0x78: /* MCSPI_RX3 */ |
1292 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
1293 | 827df9f3 | balrog | return;
|
1294 | 827df9f3 | balrog | |
1295 | 827df9f3 | balrog | case 0x10: /* MCSPI_SYSCONFIG */ |
1296 | 827df9f3 | balrog | if (value & (1 << 1)) /* SOFTRESET */ |
1297 | 827df9f3 | balrog | omap_mcspi_reset(s); |
1298 | 827df9f3 | balrog | s->sysconfig = value & 0x31d;
|
1299 | 827df9f3 | balrog | break;
|
1300 | 827df9f3 | balrog | |
1301 | 827df9f3 | balrog | case 0x18: /* MCSPI_IRQSTATUS */ |
1302 | 827df9f3 | balrog | if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) { |
1303 | 827df9f3 | balrog | s->irqst &= ~value; |
1304 | 827df9f3 | balrog | omap_mcspi_interrupt_update(s); |
1305 | 827df9f3 | balrog | } |
1306 | 827df9f3 | balrog | break;
|
1307 | 827df9f3 | balrog | |
1308 | 827df9f3 | balrog | case 0x1c: /* MCSPI_IRQENABLE */ |
1309 | 827df9f3 | balrog | s->irqen = value & 0x1777f;
|
1310 | 827df9f3 | balrog | omap_mcspi_interrupt_update(s); |
1311 | 827df9f3 | balrog | break;
|
1312 | 827df9f3 | balrog | |
1313 | 827df9f3 | balrog | case 0x20: /* MCSPI_WAKEUPENABLE */ |
1314 | 827df9f3 | balrog | s->wken = value & 1;
|
1315 | 827df9f3 | balrog | break;
|
1316 | 827df9f3 | balrog | |
1317 | 827df9f3 | balrog | case 0x24: /* MCSPI_SYST */ |
1318 | 827df9f3 | balrog | if (s->control & (1 << 3)) /* SYSTEM_TEST */ |
1319 | 827df9f3 | balrog | if (value & (1 << 11)) { /* SSB */ |
1320 | 827df9f3 | balrog | s->irqst |= 0x1777f;
|
1321 | 827df9f3 | balrog | omap_mcspi_interrupt_update(s); |
1322 | 827df9f3 | balrog | } |
1323 | 827df9f3 | balrog | s->systest = value & 0xfff;
|
1324 | 827df9f3 | balrog | break;
|
1325 | 827df9f3 | balrog | |
1326 | 827df9f3 | balrog | case 0x28: /* MCSPI_MODULCTRL */ |
1327 | 827df9f3 | balrog | if (value & (1 << 3)) /* SYSTEM_TEST */ |
1328 | 827df9f3 | balrog | if (s->systest & (1 << 11)) { /* SSB */ |
1329 | 827df9f3 | balrog | s->irqst |= 0x1777f;
|
1330 | 827df9f3 | balrog | omap_mcspi_interrupt_update(s); |
1331 | 827df9f3 | balrog | } |
1332 | 827df9f3 | balrog | s->control = value & 0xf;
|
1333 | 827df9f3 | balrog | break;
|
1334 | 827df9f3 | balrog | |
1335 | 827df9f3 | balrog | case 0x68: ch ++; |
1336 | 827df9f3 | balrog | case 0x54: ch ++; |
1337 | 827df9f3 | balrog | case 0x40: ch ++; |
1338 | 827df9f3 | balrog | case 0x2c: /* MCSPI_CHCONF */ |
1339 | 827df9f3 | balrog | if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */ |
1340 | 827df9f3 | balrog | omap_mcspi_dmarequest_update(s->ch + ch); |
1341 | 827df9f3 | balrog | if (((value >> 12) & 3) == 3) /* TRM */ |
1342 | 827df9f3 | balrog | fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
|
1343 | 827df9f3 | balrog | if (((value >> 7) & 0x1f) < 3) /* WL */ |
1344 | 827df9f3 | balrog | fprintf(stderr, "%s: invalid WL value (%i)\n",
|
1345 | 827df9f3 | balrog | __FUNCTION__, (value >> 7) & 0x1f); |
1346 | 827df9f3 | balrog | s->ch[ch].config = value & 0x7fffff;
|
1347 | 827df9f3 | balrog | break;
|
1348 | 827df9f3 | balrog | |
1349 | 827df9f3 | balrog | case 0x70: ch ++; |
1350 | 827df9f3 | balrog | case 0x5c: ch ++; |
1351 | 827df9f3 | balrog | case 0x48: ch ++; |
1352 | 827df9f3 | balrog | case 0x34: /* MCSPI_CHCTRL */ |
1353 | 827df9f3 | balrog | if (value & ~s->ch[ch].control & 1) { /* EN */ |
1354 | 827df9f3 | balrog | s->ch[ch].control |= 1;
|
1355 | 827df9f3 | balrog | omap_mcspi_transfer_run(s, ch); |
1356 | 827df9f3 | balrog | } else
|
1357 | 827df9f3 | balrog | s->ch[ch].control = value & 1;
|
1358 | 827df9f3 | balrog | break;
|
1359 | 827df9f3 | balrog | |
1360 | 827df9f3 | balrog | case 0x74: ch ++; |
1361 | 827df9f3 | balrog | case 0x60: ch ++; |
1362 | 827df9f3 | balrog | case 0x4c: ch ++; |
1363 | 827df9f3 | balrog | case 0x38: /* MCSPI_TX */ |
1364 | 827df9f3 | balrog | s->ch[ch].tx = value; |
1365 | 827df9f3 | balrog | s->ch[ch].status &= ~(1 << 1); /* TXS */ |
1366 | 827df9f3 | balrog | omap_mcspi_transfer_run(s, ch); |
1367 | 827df9f3 | balrog | break;
|
1368 | 827df9f3 | balrog | |
1369 | 827df9f3 | balrog | default:
|
1370 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1371 | 827df9f3 | balrog | return;
|
1372 | 827df9f3 | balrog | } |
1373 | 827df9f3 | balrog | } |
1374 | 827df9f3 | balrog | |
1375 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap_mcspi_readfn[] = {
|
1376 | 827df9f3 | balrog | omap_badwidth_read32, |
1377 | 827df9f3 | balrog | omap_badwidth_read32, |
1378 | 827df9f3 | balrog | omap_mcspi_read, |
1379 | 827df9f3 | balrog | }; |
1380 | 827df9f3 | balrog | |
1381 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap_mcspi_writefn[] = {
|
1382 | 827df9f3 | balrog | omap_badwidth_write32, |
1383 | 827df9f3 | balrog | omap_badwidth_write32, |
1384 | 827df9f3 | balrog | omap_mcspi_write, |
1385 | 827df9f3 | balrog | }; |
1386 | 827df9f3 | balrog | |
1387 | 827df9f3 | balrog | struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, |
1388 | 827df9f3 | balrog | qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk) |
1389 | 827df9f3 | balrog | { |
1390 | 827df9f3 | balrog | int iomemtype;
|
1391 | 827df9f3 | balrog | struct omap_mcspi_s *s = (struct omap_mcspi_s *) |
1392 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_mcspi_s)); |
1393 | 827df9f3 | balrog | struct omap_mcspi_ch_s *ch = s->ch;
|
1394 | 827df9f3 | balrog | |
1395 | 827df9f3 | balrog | s->irq = irq; |
1396 | 827df9f3 | balrog | s->chnum = chnum; |
1397 | 827df9f3 | balrog | while (chnum --) {
|
1398 | 827df9f3 | balrog | ch->txdrq = *drq ++; |
1399 | 827df9f3 | balrog | ch->rxdrq = *drq ++; |
1400 | 827df9f3 | balrog | ch ++; |
1401 | 827df9f3 | balrog | } |
1402 | 827df9f3 | balrog | omap_mcspi_reset(s); |
1403 | 827df9f3 | balrog | |
1404 | c66fb5bc | balrog | iomemtype = l4_register_io_memory(0, omap_mcspi_readfn,
|
1405 | 827df9f3 | balrog | omap_mcspi_writefn, s); |
1406 | 827df9f3 | balrog | s->base = omap_l4_attach(ta, 0, iomemtype);
|
1407 | 827df9f3 | balrog | |
1408 | 827df9f3 | balrog | return s;
|
1409 | 827df9f3 | balrog | } |
1410 | 827df9f3 | balrog | |
1411 | 827df9f3 | balrog | void omap_mcspi_attach(struct omap_mcspi_s *s, |
1412 | e927bb00 | balrog | uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, |
1413 | 827df9f3 | balrog | int chipselect)
|
1414 | 827df9f3 | balrog | { |
1415 | 827df9f3 | balrog | if (chipselect < 0 || chipselect >= s->chnum) |
1416 | 827df9f3 | balrog | cpu_abort(cpu_single_env, "%s: Bad chipselect %i\n",
|
1417 | 827df9f3 | balrog | __FUNCTION__, chipselect); |
1418 | 827df9f3 | balrog | |
1419 | 827df9f3 | balrog | s->ch[chipselect].txrx = txrx; |
1420 | 827df9f3 | balrog | s->ch[chipselect].opaque = opaque; |
1421 | 827df9f3 | balrog | } |
1422 | 827df9f3 | balrog | |
1423 | 54585ffe | balrog | /* STI/XTI (emulation interface) console - reverse engineered only */
|
1424 | 54585ffe | balrog | struct omap_sti_s {
|
1425 | 54585ffe | balrog | target_phys_addr_t base; |
1426 | 54585ffe | balrog | target_phys_addr_t channel_base; |
1427 | 54585ffe | balrog | qemu_irq irq; |
1428 | 54585ffe | balrog | CharDriverState *chr; |
1429 | 54585ffe | balrog | |
1430 | 54585ffe | balrog | uint32_t sysconfig; |
1431 | 54585ffe | balrog | uint32_t systest; |
1432 | 54585ffe | balrog | uint32_t irqst; |
1433 | 54585ffe | balrog | uint32_t irqen; |
1434 | 54585ffe | balrog | uint32_t clkcontrol; |
1435 | 54585ffe | balrog | uint32_t serial_config; |
1436 | 54585ffe | balrog | }; |
1437 | 54585ffe | balrog | |
1438 | 54585ffe | balrog | #define STI_TRACE_CONSOLE_CHANNEL 239 |
1439 | 54585ffe | balrog | #define STI_TRACE_CONTROL_CHANNEL 253 |
1440 | 54585ffe | balrog | |
1441 | 54585ffe | balrog | static inline void omap_sti_interrupt_update(struct omap_sti_s *s) |
1442 | 54585ffe | balrog | { |
1443 | 54585ffe | balrog | qemu_set_irq(s->irq, s->irqst & s->irqen); |
1444 | 54585ffe | balrog | } |
1445 | 54585ffe | balrog | |
1446 | 54585ffe | balrog | static void omap_sti_reset(struct omap_sti_s *s) |
1447 | 54585ffe | balrog | { |
1448 | 54585ffe | balrog | s->sysconfig = 0;
|
1449 | 54585ffe | balrog | s->irqst = 0;
|
1450 | 54585ffe | balrog | s->irqen = 0;
|
1451 | 54585ffe | balrog | s->clkcontrol = 0;
|
1452 | 54585ffe | balrog | s->serial_config = 0;
|
1453 | 54585ffe | balrog | |
1454 | 54585ffe | balrog | omap_sti_interrupt_update(s); |
1455 | 54585ffe | balrog | } |
1456 | 54585ffe | balrog | |
1457 | 54585ffe | balrog | static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr) |
1458 | 54585ffe | balrog | { |
1459 | 54585ffe | balrog | struct omap_sti_s *s = (struct omap_sti_s *) opaque; |
1460 | 54585ffe | balrog | int offset = addr - s->base;
|
1461 | 54585ffe | balrog | |
1462 | 54585ffe | balrog | switch (offset) {
|
1463 | 54585ffe | balrog | case 0x00: /* STI_REVISION */ |
1464 | 54585ffe | balrog | return 0x10; |
1465 | 54585ffe | balrog | |
1466 | 54585ffe | balrog | case 0x10: /* STI_SYSCONFIG */ |
1467 | 54585ffe | balrog | return s->sysconfig;
|
1468 | 54585ffe | balrog | |
1469 | 54585ffe | balrog | case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */ |
1470 | 54585ffe | balrog | return 0x00; |
1471 | 54585ffe | balrog | |
1472 | 54585ffe | balrog | case 0x18: /* STI_IRQSTATUS */ |
1473 | 54585ffe | balrog | return s->irqst;
|
1474 | 54585ffe | balrog | |
1475 | 54585ffe | balrog | case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */ |
1476 | 54585ffe | balrog | return s->irqen;
|
1477 | 54585ffe | balrog | |
1478 | 54585ffe | balrog | case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */ |
1479 | 54585ffe | balrog | case 0x28: /* STI_RX_DR / XTI_RXDATA */ |
1480 | e927bb00 | balrog | /* TODO */
|
1481 | e927bb00 | balrog | return 0; |
1482 | 54585ffe | balrog | |
1483 | 54585ffe | balrog | case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */ |
1484 | 54585ffe | balrog | return s->clkcontrol;
|
1485 | 54585ffe | balrog | |
1486 | 54585ffe | balrog | case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */ |
1487 | 54585ffe | balrog | return s->serial_config;
|
1488 | 54585ffe | balrog | } |
1489 | 54585ffe | balrog | |
1490 | 54585ffe | balrog | OMAP_BAD_REG(addr); |
1491 | 54585ffe | balrog | return 0; |
1492 | 54585ffe | balrog | } |
1493 | 54585ffe | balrog | |
1494 | 54585ffe | balrog | static void omap_sti_write(void *opaque, target_phys_addr_t addr, |
1495 | 54585ffe | balrog | uint32_t value) |
1496 | 54585ffe | balrog | { |
1497 | 54585ffe | balrog | struct omap_sti_s *s = (struct omap_sti_s *) opaque; |
1498 | 54585ffe | balrog | int offset = addr - s->base;
|
1499 | 54585ffe | balrog | |
1500 | 54585ffe | balrog | switch (offset) {
|
1501 | 54585ffe | balrog | case 0x00: /* STI_REVISION */ |
1502 | 54585ffe | balrog | case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */ |
1503 | 54585ffe | balrog | OMAP_RO_REG(addr); |
1504 | 54585ffe | balrog | return;
|
1505 | 54585ffe | balrog | |
1506 | 54585ffe | balrog | case 0x10: /* STI_SYSCONFIG */ |
1507 | 54585ffe | balrog | if (value & (1 << 1)) /* SOFTRESET */ |
1508 | 54585ffe | balrog | omap_sti_reset(s); |
1509 | 54585ffe | balrog | s->sysconfig = value & 0xfe;
|
1510 | 54585ffe | balrog | break;
|
1511 | 54585ffe | balrog | |
1512 | 54585ffe | balrog | case 0x18: /* STI_IRQSTATUS */ |
1513 | 54585ffe | balrog | s->irqst &= ~value; |
1514 | 54585ffe | balrog | omap_sti_interrupt_update(s); |
1515 | 54585ffe | balrog | break;
|
1516 | 54585ffe | balrog | |
1517 | 54585ffe | balrog | case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */ |
1518 | 54585ffe | balrog | s->irqen = value & 0xffff;
|
1519 | 54585ffe | balrog | omap_sti_interrupt_update(s); |
1520 | 54585ffe | balrog | break;
|
1521 | 54585ffe | balrog | |
1522 | 54585ffe | balrog | case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */ |
1523 | 54585ffe | balrog | s->clkcontrol = value & 0xff;
|
1524 | 54585ffe | balrog | break;
|
1525 | 54585ffe | balrog | |
1526 | 54585ffe | balrog | case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */ |
1527 | 54585ffe | balrog | s->serial_config = value & 0xff;
|
1528 | 54585ffe | balrog | break;
|
1529 | 54585ffe | balrog | |
1530 | 54585ffe | balrog | case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */ |
1531 | 54585ffe | balrog | case 0x28: /* STI_RX_DR / XTI_RXDATA */ |
1532 | e927bb00 | balrog | /* TODO */
|
1533 | e927bb00 | balrog | return;
|
1534 | e927bb00 | balrog | |
1535 | 54585ffe | balrog | default:
|
1536 | 54585ffe | balrog | OMAP_BAD_REG(addr); |
1537 | 54585ffe | balrog | return;
|
1538 | 54585ffe | balrog | } |
1539 | 54585ffe | balrog | } |
1540 | 54585ffe | balrog | |
1541 | 54585ffe | balrog | static CPUReadMemoryFunc *omap_sti_readfn[] = {
|
1542 | 54585ffe | balrog | omap_badwidth_read32, |
1543 | 54585ffe | balrog | omap_badwidth_read32, |
1544 | 54585ffe | balrog | omap_sti_read, |
1545 | 54585ffe | balrog | }; |
1546 | 54585ffe | balrog | |
1547 | 54585ffe | balrog | static CPUWriteMemoryFunc *omap_sti_writefn[] = {
|
1548 | 54585ffe | balrog | omap_badwidth_write32, |
1549 | 54585ffe | balrog | omap_badwidth_write32, |
1550 | 54585ffe | balrog | omap_sti_write, |
1551 | 54585ffe | balrog | }; |
1552 | 54585ffe | balrog | |
1553 | 54585ffe | balrog | static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr) |
1554 | 54585ffe | balrog | { |
1555 | 54585ffe | balrog | OMAP_BAD_REG(addr); |
1556 | 54585ffe | balrog | return 0; |
1557 | 54585ffe | balrog | } |
1558 | 54585ffe | balrog | |
1559 | 54585ffe | balrog | static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr, |
1560 | 54585ffe | balrog | uint32_t value) |
1561 | 54585ffe | balrog | { |
1562 | 54585ffe | balrog | struct omap_sti_s *s = (struct omap_sti_s *) opaque; |
1563 | 54585ffe | balrog | int offset = addr - s->channel_base;
|
1564 | 54585ffe | balrog | int ch = offset >> 6; |
1565 | 54585ffe | balrog | uint8_t byte = value; |
1566 | 54585ffe | balrog | |
1567 | 54585ffe | balrog | if (ch == STI_TRACE_CONTROL_CHANNEL) {
|
1568 | 54585ffe | balrog | /* Flush channel <i>value</i>. */
|
1569 | 54585ffe | balrog | qemu_chr_write(s->chr, "\r", 1); |
1570 | 54585ffe | balrog | } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) { |
1571 | 54585ffe | balrog | if (value == 0xc0 || value == 0xc3) { |
1572 | 54585ffe | balrog | /* Open channel <i>ch</i>. */
|
1573 | 54585ffe | balrog | } else if (value == 0x00) |
1574 | 54585ffe | balrog | qemu_chr_write(s->chr, "\n", 1); |
1575 | 54585ffe | balrog | else
|
1576 | 54585ffe | balrog | qemu_chr_write(s->chr, &byte, 1);
|
1577 | 54585ffe | balrog | } |
1578 | 54585ffe | balrog | } |
1579 | 54585ffe | balrog | |
1580 | 54585ffe | balrog | static CPUReadMemoryFunc *omap_sti_fifo_readfn[] = {
|
1581 | 54585ffe | balrog | omap_sti_fifo_read, |
1582 | 54585ffe | balrog | omap_badwidth_read8, |
1583 | 54585ffe | balrog | omap_badwidth_read8, |
1584 | 54585ffe | balrog | }; |
1585 | 54585ffe | balrog | |
1586 | 54585ffe | balrog | static CPUWriteMemoryFunc *omap_sti_fifo_writefn[] = {
|
1587 | 54585ffe | balrog | omap_sti_fifo_write, |
1588 | 54585ffe | balrog | omap_badwidth_write8, |
1589 | 54585ffe | balrog | omap_badwidth_write8, |
1590 | 54585ffe | balrog | }; |
1591 | 54585ffe | balrog | |
1592 | 54585ffe | balrog | struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta, |
1593 | 54585ffe | balrog | target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk, |
1594 | 54585ffe | balrog | CharDriverState *chr) |
1595 | 54585ffe | balrog | { |
1596 | 54585ffe | balrog | int iomemtype;
|
1597 | 54585ffe | balrog | struct omap_sti_s *s = (struct omap_sti_s *) |
1598 | 54585ffe | balrog | qemu_mallocz(sizeof(struct omap_sti_s)); |
1599 | 54585ffe | balrog | |
1600 | 54585ffe | balrog | s->irq = irq; |
1601 | 54585ffe | balrog | omap_sti_reset(s); |
1602 | 54585ffe | balrog | |
1603 | 54585ffe | balrog | s->chr = chr ?: qemu_chr_open("null");
|
1604 | 54585ffe | balrog | |
1605 | c66fb5bc | balrog | iomemtype = l4_register_io_memory(0, omap_sti_readfn,
|
1606 | 54585ffe | balrog | omap_sti_writefn, s); |
1607 | 54585ffe | balrog | s->base = omap_l4_attach(ta, 0, iomemtype);
|
1608 | 54585ffe | balrog | |
1609 | 54585ffe | balrog | iomemtype = cpu_register_io_memory(0, omap_sti_fifo_readfn,
|
1610 | 54585ffe | balrog | omap_sti_fifo_writefn, s); |
1611 | 54585ffe | balrog | s->channel_base = channel_base; |
1612 | 54585ffe | balrog | cpu_register_physical_memory(s->channel_base, 0x10000, iomemtype);
|
1613 | 54585ffe | balrog | |
1614 | 54585ffe | balrog | return s;
|
1615 | 54585ffe | balrog | } |
1616 | 54585ffe | balrog | |
1617 | 827df9f3 | balrog | /* L4 Interconnect */
|
1618 | 827df9f3 | balrog | struct omap_target_agent_s {
|
1619 | 827df9f3 | balrog | struct omap_l4_s *bus;
|
1620 | 827df9f3 | balrog | int regions;
|
1621 | 827df9f3 | balrog | struct omap_l4_region_s *start;
|
1622 | 827df9f3 | balrog | target_phys_addr_t base; |
1623 | 827df9f3 | balrog | uint32_t component; |
1624 | 827df9f3 | balrog | uint32_t control; |
1625 | 827df9f3 | balrog | uint32_t status; |
1626 | 827df9f3 | balrog | }; |
1627 | 827df9f3 | balrog | |
1628 | 827df9f3 | balrog | struct omap_l4_s {
|
1629 | 827df9f3 | balrog | target_phys_addr_t base; |
1630 | 827df9f3 | balrog | int ta_num;
|
1631 | 827df9f3 | balrog | struct omap_target_agent_s ta[0]; |
1632 | 827df9f3 | balrog | }; |
1633 | 827df9f3 | balrog | |
1634 | c66fb5bc | balrog | #ifdef L4_MUX_HACK
|
1635 | c66fb5bc | balrog | static int omap_l4_io_entries; |
1636 | c66fb5bc | balrog | static int omap_cpu_io_entry; |
1637 | c66fb5bc | balrog | static struct omap_l4_entry { |
1638 | c66fb5bc | balrog | CPUReadMemoryFunc **mem_read; |
1639 | c66fb5bc | balrog | CPUWriteMemoryFunc **mem_write; |
1640 | c66fb5bc | balrog | void *opaque;
|
1641 | c66fb5bc | balrog | } *omap_l4_io_entry; |
1642 | c66fb5bc | balrog | static CPUReadMemoryFunc **omap_l4_io_readb_fn;
|
1643 | c66fb5bc | balrog | static CPUReadMemoryFunc **omap_l4_io_readh_fn;
|
1644 | c66fb5bc | balrog | static CPUReadMemoryFunc **omap_l4_io_readw_fn;
|
1645 | c66fb5bc | balrog | static CPUWriteMemoryFunc **omap_l4_io_writeb_fn;
|
1646 | c66fb5bc | balrog | static CPUWriteMemoryFunc **omap_l4_io_writeh_fn;
|
1647 | c66fb5bc | balrog | static CPUWriteMemoryFunc **omap_l4_io_writew_fn;
|
1648 | c66fb5bc | balrog | static void **omap_l4_io_opaque; |
1649 | c66fb5bc | balrog | |
1650 | c66fb5bc | balrog | int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read, |
1651 | c66fb5bc | balrog | CPUWriteMemoryFunc **mem_write, void *opaque)
|
1652 | c66fb5bc | balrog | { |
1653 | c66fb5bc | balrog | omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read; |
1654 | c66fb5bc | balrog | omap_l4_io_entry[omap_l4_io_entries].mem_write = mem_write; |
1655 | c66fb5bc | balrog | omap_l4_io_entry[omap_l4_io_entries].opaque = opaque; |
1656 | c66fb5bc | balrog | |
1657 | c66fb5bc | balrog | return omap_l4_io_entries ++;
|
1658 | c66fb5bc | balrog | } |
1659 | c66fb5bc | balrog | |
1660 | c66fb5bc | balrog | static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr) |
1661 | c66fb5bc | balrog | { |
1662 | c66fb5bc | balrog | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
1663 | c66fb5bc | balrog | |
1664 | c66fb5bc | balrog | return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr);
|
1665 | c66fb5bc | balrog | } |
1666 | c66fb5bc | balrog | |
1667 | c66fb5bc | balrog | static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr) |
1668 | c66fb5bc | balrog | { |
1669 | c66fb5bc | balrog | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
1670 | c66fb5bc | balrog | |
1671 | c66fb5bc | balrog | return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr);
|
1672 | c66fb5bc | balrog | } |
1673 | c66fb5bc | balrog | |
1674 | c66fb5bc | balrog | static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr) |
1675 | c66fb5bc | balrog | { |
1676 | c66fb5bc | balrog | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
1677 | c66fb5bc | balrog | |
1678 | c66fb5bc | balrog | return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr);
|
1679 | c66fb5bc | balrog | } |
1680 | c66fb5bc | balrog | |
1681 | c66fb5bc | balrog | static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr, |
1682 | c66fb5bc | balrog | uint32_t value) |
1683 | c66fb5bc | balrog | { |
1684 | c66fb5bc | balrog | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
1685 | c66fb5bc | balrog | |
1686 | c66fb5bc | balrog | return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value);
|
1687 | c66fb5bc | balrog | } |
1688 | c66fb5bc | balrog | |
1689 | c66fb5bc | balrog | static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr, |
1690 | c66fb5bc | balrog | uint32_t value) |
1691 | c66fb5bc | balrog | { |
1692 | c66fb5bc | balrog | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
1693 | c66fb5bc | balrog | |
1694 | c66fb5bc | balrog | return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value);
|
1695 | c66fb5bc | balrog | } |
1696 | c66fb5bc | balrog | |
1697 | c66fb5bc | balrog | static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr, |
1698 | c66fb5bc | balrog | uint32_t value) |
1699 | c66fb5bc | balrog | { |
1700 | c66fb5bc | balrog | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
1701 | c66fb5bc | balrog | |
1702 | c66fb5bc | balrog | return omap_l4_io_writew_fn[i](omap_l4_io_opaque[i], addr, value);
|
1703 | c66fb5bc | balrog | } |
1704 | c66fb5bc | balrog | |
1705 | c66fb5bc | balrog | static CPUReadMemoryFunc *omap_l4_io_readfn[] = {
|
1706 | c66fb5bc | balrog | omap_l4_io_readb, |
1707 | c66fb5bc | balrog | omap_l4_io_readh, |
1708 | c66fb5bc | balrog | omap_l4_io_readw, |
1709 | c66fb5bc | balrog | }; |
1710 | c66fb5bc | balrog | |
1711 | c66fb5bc | balrog | static CPUWriteMemoryFunc *omap_l4_io_writefn[] = {
|
1712 | c66fb5bc | balrog | omap_l4_io_writeb, |
1713 | c66fb5bc | balrog | omap_l4_io_writeh, |
1714 | c66fb5bc | balrog | omap_l4_io_writew, |
1715 | c66fb5bc | balrog | }; |
1716 | c66fb5bc | balrog | #endif
|
1717 | c66fb5bc | balrog | |
1718 | 827df9f3 | balrog | struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num) |
1719 | 827df9f3 | balrog | { |
1720 | 827df9f3 | balrog | struct omap_l4_s *bus = qemu_mallocz(
|
1721 | 827df9f3 | balrog | sizeof(*bus) + ta_num * sizeof(*bus->ta)); |
1722 | 827df9f3 | balrog | |
1723 | 827df9f3 | balrog | bus->ta_num = ta_num; |
1724 | 827df9f3 | balrog | bus->base = base; |
1725 | 827df9f3 | balrog | |
1726 | c66fb5bc | balrog | #ifdef L4_MUX_HACK
|
1727 | c66fb5bc | balrog | omap_l4_io_entries = 1;
|
1728 | c66fb5bc | balrog | omap_l4_io_entry = qemu_mallocz(125 * sizeof(*omap_l4_io_entry)); |
1729 | c66fb5bc | balrog | |
1730 | c66fb5bc | balrog | omap_cpu_io_entry = |
1731 | c66fb5bc | balrog | cpu_register_io_memory(0, omap_l4_io_readfn,
|
1732 | c66fb5bc | balrog | omap_l4_io_writefn, bus); |
1733 | c66fb5bc | balrog | # define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE) |
1734 | c66fb5bc | balrog | omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
1735 | c66fb5bc | balrog | omap_l4_io_readh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
1736 | c66fb5bc | balrog | omap_l4_io_readw_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
1737 | c66fb5bc | balrog | omap_l4_io_writeb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
1738 | c66fb5bc | balrog | omap_l4_io_writeh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
1739 | c66fb5bc | balrog | omap_l4_io_writew_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
1740 | c66fb5bc | balrog | omap_l4_io_opaque = qemu_mallocz(sizeof(void *) * L4_PAGES); |
1741 | c66fb5bc | balrog | #endif
|
1742 | c66fb5bc | balrog | |
1743 | 827df9f3 | balrog | return bus;
|
1744 | 827df9f3 | balrog | } |
1745 | 827df9f3 | balrog | |
1746 | 827df9f3 | balrog | static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr) |
1747 | 827df9f3 | balrog | { |
1748 | 827df9f3 | balrog | struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; |
1749 | 827df9f3 | balrog | target_phys_addr_t reg = addr - s->base; |
1750 | 827df9f3 | balrog | |
1751 | 827df9f3 | balrog | switch (reg) {
|
1752 | 827df9f3 | balrog | case 0x00: /* COMPONENT */ |
1753 | 827df9f3 | balrog | return s->component;
|
1754 | 827df9f3 | balrog | |
1755 | 827df9f3 | balrog | case 0x20: /* AGENT_CONTROL */ |
1756 | 827df9f3 | balrog | return s->control;
|
1757 | 827df9f3 | balrog | |
1758 | 827df9f3 | balrog | case 0x28: /* AGENT_STATUS */ |
1759 | 827df9f3 | balrog | return s->status;
|
1760 | 827df9f3 | balrog | } |
1761 | 827df9f3 | balrog | |
1762 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1763 | 827df9f3 | balrog | return 0; |
1764 | 827df9f3 | balrog | } |
1765 | 827df9f3 | balrog | |
1766 | 827df9f3 | balrog | static void omap_l4ta_write(void *opaque, target_phys_addr_t addr, |
1767 | 827df9f3 | balrog | uint32_t value) |
1768 | 827df9f3 | balrog | { |
1769 | 827df9f3 | balrog | struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; |
1770 | 827df9f3 | balrog | target_phys_addr_t reg = addr - s->base; |
1771 | 827df9f3 | balrog | |
1772 | 827df9f3 | balrog | switch (reg) {
|
1773 | 827df9f3 | balrog | case 0x00: /* COMPONENT */ |
1774 | 827df9f3 | balrog | case 0x28: /* AGENT_STATUS */ |
1775 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
1776 | 827df9f3 | balrog | break;
|
1777 | 827df9f3 | balrog | |
1778 | 827df9f3 | balrog | case 0x20: /* AGENT_CONTROL */ |
1779 | 827df9f3 | balrog | s->control = value & 0x01000700;
|
1780 | 827df9f3 | balrog | if (value & 1) /* OCP_RESET */ |
1781 | 827df9f3 | balrog | s->status &= ~1; /* REQ_TIMEOUT */ |
1782 | 827df9f3 | balrog | break;
|
1783 | 827df9f3 | balrog | |
1784 | 827df9f3 | balrog | default:
|
1785 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1786 | 827df9f3 | balrog | } |
1787 | 827df9f3 | balrog | } |
1788 | 827df9f3 | balrog | |
1789 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap_l4ta_readfn[] = {
|
1790 | 827df9f3 | balrog | omap_badwidth_read16, |
1791 | 827df9f3 | balrog | omap_l4ta_read, |
1792 | 827df9f3 | balrog | omap_badwidth_read16, |
1793 | 827df9f3 | balrog | }; |
1794 | 827df9f3 | balrog | |
1795 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap_l4ta_writefn[] = {
|
1796 | 827df9f3 | balrog | omap_badwidth_write32, |
1797 | 827df9f3 | balrog | omap_badwidth_write32, |
1798 | 827df9f3 | balrog | omap_l4ta_write, |
1799 | 827df9f3 | balrog | }; |
1800 | 827df9f3 | balrog | |
1801 | 827df9f3 | balrog | #define L4TA(n) (n)
|
1802 | 827df9f3 | balrog | #define L4TAO(n) ((n) + 39) |
1803 | 827df9f3 | balrog | |
1804 | 827df9f3 | balrog | static struct omap_l4_region_s { |
1805 | 827df9f3 | balrog | target_phys_addr_t offset; |
1806 | 827df9f3 | balrog | size_t size; |
1807 | 827df9f3 | balrog | int access;
|
1808 | 827df9f3 | balrog | } omap_l4_region[125] = {
|
1809 | 827df9f3 | balrog | [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */ |
1810 | 827df9f3 | balrog | [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */ |
1811 | 827df9f3 | balrog | [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */ |
1812 | 827df9f3 | balrog | [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */ |
1813 | 827df9f3 | balrog | [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */ |
1814 | 827df9f3 | balrog | [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */ |
1815 | 827df9f3 | balrog | [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */ |
1816 | 827df9f3 | balrog | [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */ |
1817 | 827df9f3 | balrog | [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */ |
1818 | 827df9f3 | balrog | [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */ |
1819 | 827df9f3 | balrog | [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */ |
1820 | 827df9f3 | balrog | [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */ |
1821 | 827df9f3 | balrog | [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */ |
1822 | 827df9f3 | balrog | [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */ |
1823 | 827df9f3 | balrog | [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */ |
1824 | 827df9f3 | balrog | [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */ |
1825 | 827df9f3 | balrog | [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */ |
1826 | 827df9f3 | balrog | [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */ |
1827 | 827df9f3 | balrog | [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */ |
1828 | 827df9f3 | balrog | [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */ |
1829 | 827df9f3 | balrog | [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */ |
1830 | 827df9f3 | balrog | [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */ |
1831 | 827df9f3 | balrog | [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */ |
1832 | 827df9f3 | balrog | [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */ |
1833 | 827df9f3 | balrog | [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */ |
1834 | 827df9f3 | balrog | [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */ |
1835 | 827df9f3 | balrog | [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */ |
1836 | 827df9f3 | balrog | [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */ |
1837 | 827df9f3 | balrog | [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */ |
1838 | 827df9f3 | balrog | [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */ |
1839 | 827df9f3 | balrog | [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */ |
1840 | 827df9f3 | balrog | [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */ |
1841 | 827df9f3 | balrog | [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */ |
1842 | 827df9f3 | balrog | [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */ |
1843 | 827df9f3 | balrog | [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */ |
1844 | 827df9f3 | balrog | [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */ |
1845 | 827df9f3 | balrog | [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */ |
1846 | 827df9f3 | balrog | [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */ |
1847 | 827df9f3 | balrog | [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */ |
1848 | 827df9f3 | balrog | [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */ |
1849 | 827df9f3 | balrog | [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */ |
1850 | 827df9f3 | balrog | [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */ |
1851 | 827df9f3 | balrog | [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */ |
1852 | 827df9f3 | balrog | [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */ |
1853 | 827df9f3 | balrog | [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */ |
1854 | 827df9f3 | balrog | [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */ |
1855 | 827df9f3 | balrog | [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */ |
1856 | 827df9f3 | balrog | [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */ |
1857 | 827df9f3 | balrog | [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */ |
1858 | 827df9f3 | balrog | [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */ |
1859 | 827df9f3 | balrog | [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */ |
1860 | 827df9f3 | balrog | [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */ |
1861 | 827df9f3 | balrog | [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */ |
1862 | 827df9f3 | balrog | [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */ |
1863 | 827df9f3 | balrog | [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */ |
1864 | 827df9f3 | balrog | [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */ |
1865 | 827df9f3 | balrog | [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */ |
1866 | 827df9f3 | balrog | [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */ |
1867 | 827df9f3 | balrog | [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */ |
1868 | 827df9f3 | balrog | [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */ |
1869 | 827df9f3 | balrog | [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */ |
1870 | 827df9f3 | balrog | [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */ |
1871 | 827df9f3 | balrog | [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */ |
1872 | 827df9f3 | balrog | [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */ |
1873 | 827df9f3 | balrog | [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */ |
1874 | 827df9f3 | balrog | [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */ |
1875 | 827df9f3 | balrog | [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */ |
1876 | 827df9f3 | balrog | [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */ |
1877 | 827df9f3 | balrog | [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */ |
1878 | 827df9f3 | balrog | [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */ |
1879 | 827df9f3 | balrog | [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */ |
1880 | 827df9f3 | balrog | [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */ |
1881 | 827df9f3 | balrog | [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */ |
1882 | 827df9f3 | balrog | [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */ |
1883 | 827df9f3 | balrog | [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */ |
1884 | 827df9f3 | balrog | [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */ |
1885 | 827df9f3 | balrog | [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */ |
1886 | 827df9f3 | balrog | [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */ |
1887 | 827df9f3 | balrog | [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */ |
1888 | 827df9f3 | balrog | [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */ |
1889 | 827df9f3 | balrog | [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */ |
1890 | 827df9f3 | balrog | [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */ |
1891 | 827df9f3 | balrog | [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */ |
1892 | 827df9f3 | balrog | [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */ |
1893 | 827df9f3 | balrog | [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */ |
1894 | 827df9f3 | balrog | [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */ |
1895 | 827df9f3 | balrog | [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */ |
1896 | 827df9f3 | balrog | [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */ |
1897 | 827df9f3 | balrog | [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */ |
1898 | 827df9f3 | balrog | [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */ |
1899 | 827df9f3 | balrog | [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */ |
1900 | 827df9f3 | balrog | [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */ |
1901 | 827df9f3 | balrog | [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */ |
1902 | 827df9f3 | balrog | [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */ |
1903 | 827df9f3 | balrog | [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */ |
1904 | 827df9f3 | balrog | [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */ |
1905 | 827df9f3 | balrog | [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */ |
1906 | 827df9f3 | balrog | [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */ |
1907 | 827df9f3 | balrog | [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */ |
1908 | 827df9f3 | balrog | [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */ |
1909 | 827df9f3 | balrog | [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */ |
1910 | 827df9f3 | balrog | [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */ |
1911 | 827df9f3 | balrog | [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */ |
1912 | 827df9f3 | balrog | [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */ |
1913 | 827df9f3 | balrog | [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */ |
1914 | 827df9f3 | balrog | [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */ |
1915 | 827df9f3 | balrog | [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */ |
1916 | 827df9f3 | balrog | [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */ |
1917 | 827df9f3 | balrog | [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */ |
1918 | 827df9f3 | balrog | [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */ |
1919 | 827df9f3 | balrog | [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */ |
1920 | 827df9f3 | balrog | [111] = { 0xa0000, 0x1000, 32 }, /* RNG */ |
1921 | 827df9f3 | balrog | [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */ |
1922 | 827df9f3 | balrog | [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */ |
1923 | 827df9f3 | balrog | [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */ |
1924 | 827df9f3 | balrog | [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */ |
1925 | 827df9f3 | balrog | [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */ |
1926 | 827df9f3 | balrog | [117] = { 0xa6000, 0x1000, 32 }, /* AES */ |
1927 | 827df9f3 | balrog | [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */ |
1928 | 827df9f3 | balrog | [119] = { 0xa8000, 0x2000, 32 }, /* PKA */ |
1929 | 827df9f3 | balrog | [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */ |
1930 | 827df9f3 | balrog | [121] = { 0xb0000, 0x1000, 32 }, /* MG */ |
1931 | 827df9f3 | balrog | [122] = { 0xb1000, 0x1000, 32 | 16 | 8 }, |
1932 | 827df9f3 | balrog | [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */ |
1933 | 827df9f3 | balrog | [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */ |
1934 | 827df9f3 | balrog | }; |
1935 | 827df9f3 | balrog | |
1936 | 827df9f3 | balrog | static struct omap_l4_agent_info_s { |
1937 | 827df9f3 | balrog | int ta;
|
1938 | 827df9f3 | balrog | int region;
|
1939 | 827df9f3 | balrog | int regions;
|
1940 | 827df9f3 | balrog | int ta_region;
|
1941 | 827df9f3 | balrog | } omap_l4_agent_info[54] = {
|
1942 | 827df9f3 | balrog | { 0, 0, 3, 2 }, /* L4IA initiatior agent */ |
1943 | 827df9f3 | balrog | { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */ |
1944 | 827df9f3 | balrog | { L4TAO(2), 5, 2, 1 }, /* 32K timer */ |
1945 | 827df9f3 | balrog | { L4TAO(3), 7, 3, 2 }, /* PRCM */ |
1946 | 827df9f3 | balrog | { L4TA(1), 10, 2, 1 }, /* BCM */ |
1947 | 827df9f3 | balrog | { L4TA(2), 12, 2, 1 }, /* Test JTAG */ |
1948 | 827df9f3 | balrog | { L4TA(3), 14, 6, 3 }, /* Quad GPIO */ |
1949 | 827df9f3 | balrog | { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */ |
1950 | 827df9f3 | balrog | { L4TA(7), 24, 2, 1 }, /* GP timer 1 */ |
1951 | 827df9f3 | balrog | { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */ |
1952 | 827df9f3 | balrog | { L4TA(10), 28, 5, 4 }, /* Display subsystem */ |
1953 | 827df9f3 | balrog | { L4TA(11), 33, 5, 4 }, /* Camera subsystem */ |
1954 | 827df9f3 | balrog | { L4TA(12), 38, 2, 1 }, /* sDMA */ |
1955 | 827df9f3 | balrog | { L4TA(13), 40, 5, 4 }, /* SSI */ |
1956 | 827df9f3 | balrog | { L4TAO(4), 45, 2, 1 }, /* USB */ |
1957 | 827df9f3 | balrog | { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */ |
1958 | 827df9f3 | balrog | { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */ |
1959 | 827df9f3 | balrog | { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */ |
1960 | 827df9f3 | balrog | { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */ |
1961 | 827df9f3 | balrog | { L4TA(18), 55, 2, 1 }, /* XTI */ |
1962 | 827df9f3 | balrog | { L4TA(19), 57, 2, 1 }, /* UART1 */ |
1963 | 827df9f3 | balrog | { L4TA(20), 59, 2, 1 }, /* UART2 */ |
1964 | 827df9f3 | balrog | { L4TA(21), 61, 2, 1 }, /* UART3 */ |
1965 | 827df9f3 | balrog | { L4TAO(5), 63, 2, 1 }, /* I2C1 */ |
1966 | 827df9f3 | balrog | { L4TAO(6), 65, 2, 1 }, /* I2C2 */ |
1967 | 827df9f3 | balrog | { L4TAO(7), 67, 2, 1 }, /* McBSP1 */ |
1968 | 827df9f3 | balrog | { L4TAO(8), 69, 2, 1 }, /* McBSP2 */ |
1969 | 827df9f3 | balrog | { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */ |
1970 | 827df9f3 | balrog | { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */ |
1971 | 827df9f3 | balrog | { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */ |
1972 | 827df9f3 | balrog | { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */ |
1973 | 827df9f3 | balrog | { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */ |
1974 | 827df9f3 | balrog | { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */ |
1975 | 827df9f3 | balrog | { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */ |
1976 | 827df9f3 | balrog | { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */ |
1977 | 827df9f3 | balrog | { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */ |
1978 | 827df9f3 | balrog | { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */ |
1979 | 827df9f3 | balrog | { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */ |
1980 | 827df9f3 | balrog | { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */ |
1981 | 827df9f3 | balrog | { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */ |
1982 | 827df9f3 | balrog | { L4TA(32), 97, 2, 1 }, /* EAC */ |
1983 | 827df9f3 | balrog | { L4TA(33), 99, 2, 1 }, /* FAC */ |
1984 | 827df9f3 | balrog | { L4TA(34), 101, 2, 1 }, /* IPC */ |
1985 | 827df9f3 | balrog | { L4TA(35), 103, 2, 1 }, /* SPI1 */ |
1986 | 827df9f3 | balrog | { L4TA(36), 105, 2, 1 }, /* SPI2 */ |
1987 | 827df9f3 | balrog | { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */ |
1988 | 827df9f3 | balrog | { L4TAO(10), 109, 2, 1 }, |
1989 | 827df9f3 | balrog | { L4TAO(11), 111, 2, 1 }, /* RNG */ |
1990 | 827df9f3 | balrog | { L4TAO(12), 113, 2, 1 }, /* DES3DES */ |
1991 | 827df9f3 | balrog | { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */ |
1992 | 827df9f3 | balrog | { L4TA(37), 117, 2, 1 }, /* AES */ |
1993 | 827df9f3 | balrog | { L4TA(38), 119, 2, 1 }, /* PKA */ |
1994 | 827df9f3 | balrog | { -1, 121, 2, 1 }, |
1995 | 827df9f3 | balrog | { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */ |
1996 | 827df9f3 | balrog | }; |
1997 | 827df9f3 | balrog | |
1998 | 827df9f3 | balrog | #define omap_l4ta(bus, cs) omap_l4ta_get(bus, L4TA(cs))
|
1999 | 827df9f3 | balrog | #define omap_l4tao(bus, cs) omap_l4ta_get(bus, L4TAO(cs))
|
2000 | 827df9f3 | balrog | |
2001 | 827df9f3 | balrog | struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs) |
2002 | 827df9f3 | balrog | { |
2003 | 827df9f3 | balrog | int i, iomemtype;
|
2004 | 827df9f3 | balrog | struct omap_target_agent_s *ta = 0; |
2005 | 827df9f3 | balrog | struct omap_l4_agent_info_s *info = 0; |
2006 | 827df9f3 | balrog | |
2007 | 827df9f3 | balrog | for (i = 0; i < bus->ta_num; i ++) |
2008 | 827df9f3 | balrog | if (omap_l4_agent_info[i].ta == cs) {
|
2009 | 827df9f3 | balrog | ta = &bus->ta[i]; |
2010 | 827df9f3 | balrog | info = &omap_l4_agent_info[i]; |
2011 | 827df9f3 | balrog | break;
|
2012 | 827df9f3 | balrog | } |
2013 | 827df9f3 | balrog | if (!ta) {
|
2014 | 827df9f3 | balrog | fprintf(stderr, "%s: bad target agent (%i)\n", __FUNCTION__, cs);
|
2015 | 827df9f3 | balrog | exit(-1);
|
2016 | 827df9f3 | balrog | } |
2017 | 827df9f3 | balrog | |
2018 | 827df9f3 | balrog | ta->bus = bus; |
2019 | 827df9f3 | balrog | ta->start = &omap_l4_region[info->region]; |
2020 | 827df9f3 | balrog | ta->regions = info->regions; |
2021 | 827df9f3 | balrog | |
2022 | 827df9f3 | balrog | ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); |
2023 | 827df9f3 | balrog | ta->status = 0x00000000;
|
2024 | 827df9f3 | balrog | ta->control = 0x00000200; /* XXX 01000200 for L4TAO */ |
2025 | 827df9f3 | balrog | |
2026 | c66fb5bc | balrog | iomemtype = l4_register_io_memory(0, omap_l4ta_readfn,
|
2027 | 827df9f3 | balrog | omap_l4ta_writefn, ta); |
2028 | c66fb5bc | balrog | ta->base = omap_l4_attach(ta, info->ta_region, iomemtype); |
2029 | 827df9f3 | balrog | |
2030 | 827df9f3 | balrog | return ta;
|
2031 | 827df9f3 | balrog | } |
2032 | 827df9f3 | balrog | |
2033 | 827df9f3 | balrog | target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region, |
2034 | 827df9f3 | balrog | int iotype)
|
2035 | 827df9f3 | balrog | { |
2036 | 827df9f3 | balrog | target_phys_addr_t base; |
2037 | c66fb5bc | balrog | ssize_t size; |
2038 | c66fb5bc | balrog | #ifdef L4_MUX_HACK
|
2039 | c66fb5bc | balrog | int i;
|
2040 | c66fb5bc | balrog | #endif
|
2041 | 827df9f3 | balrog | |
2042 | 827df9f3 | balrog | if (region < 0 || region >= ta->regions) { |
2043 | 827df9f3 | balrog | fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
|
2044 | 827df9f3 | balrog | exit(-1);
|
2045 | 827df9f3 | balrog | } |
2046 | 827df9f3 | balrog | |
2047 | 827df9f3 | balrog | base = ta->bus->base + ta->start[region].offset; |
2048 | 827df9f3 | balrog | size = ta->start[region].size; |
2049 | c66fb5bc | balrog | if (iotype) {
|
2050 | c66fb5bc | balrog | #ifndef L4_MUX_HACK
|
2051 | 827df9f3 | balrog | cpu_register_physical_memory(base, size, iotype); |
2052 | c66fb5bc | balrog | #else
|
2053 | c66fb5bc | balrog | cpu_register_physical_memory(base, size, omap_cpu_io_entry); |
2054 | c66fb5bc | balrog | i = (base - ta->bus->base) / TARGET_PAGE_SIZE; |
2055 | c66fb5bc | balrog | for (; size > 0; size -= TARGET_PAGE_SIZE, i ++) { |
2056 | c66fb5bc | balrog | omap_l4_io_readb_fn[i] = omap_l4_io_entry[iotype].mem_read[0];
|
2057 | c66fb5bc | balrog | omap_l4_io_readh_fn[i] = omap_l4_io_entry[iotype].mem_read[1];
|
2058 | c66fb5bc | balrog | omap_l4_io_readw_fn[i] = omap_l4_io_entry[iotype].mem_read[2];
|
2059 | c66fb5bc | balrog | omap_l4_io_writeb_fn[i] = omap_l4_io_entry[iotype].mem_write[0];
|
2060 | c66fb5bc | balrog | omap_l4_io_writeh_fn[i] = omap_l4_io_entry[iotype].mem_write[1];
|
2061 | c66fb5bc | balrog | omap_l4_io_writew_fn[i] = omap_l4_io_entry[iotype].mem_write[2];
|
2062 | c66fb5bc | balrog | omap_l4_io_opaque[i] = omap_l4_io_entry[iotype].opaque; |
2063 | c66fb5bc | balrog | } |
2064 | c66fb5bc | balrog | #endif
|
2065 | c66fb5bc | balrog | } |
2066 | 827df9f3 | balrog | |
2067 | 827df9f3 | balrog | return base;
|
2068 | 827df9f3 | balrog | } |
2069 | 827df9f3 | balrog | |
2070 | 827df9f3 | balrog | /* TEST-Chip-level TAP */
|
2071 | 827df9f3 | balrog | static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr) |
2072 | 827df9f3 | balrog | { |
2073 | 827df9f3 | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2074 | 827df9f3 | balrog | target_phys_addr_t reg = addr - s->tap_base; |
2075 | 827df9f3 | balrog | |
2076 | 827df9f3 | balrog | switch (reg) {
|
2077 | 827df9f3 | balrog | case 0x204: /* IDCODE_reg */ |
2078 | 827df9f3 | balrog | switch (s->mpu_model) {
|
2079 | 827df9f3 | balrog | case omap2420:
|
2080 | 827df9f3 | balrog | case omap2422:
|
2081 | 827df9f3 | balrog | case omap2423:
|
2082 | 827df9f3 | balrog | return 0x5b5d902f; /* ES 2.2 */ |
2083 | 827df9f3 | balrog | case omap2430:
|
2084 | 827df9f3 | balrog | return 0x5b68a02f; /* ES 2.2 */ |
2085 | 827df9f3 | balrog | case omap3430:
|
2086 | 827df9f3 | balrog | return 0x1b7ae02f; /* ES 2 */ |
2087 | 827df9f3 | balrog | default:
|
2088 | 827df9f3 | balrog | cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
|
2089 | 827df9f3 | balrog | } |
2090 | 827df9f3 | balrog | |
2091 | 827df9f3 | balrog | case 0x208: /* PRODUCTION_ID_reg for OMAP2 */ |
2092 | 827df9f3 | balrog | case 0x210: /* PRODUCTION_ID_reg for OMAP3 */ |
2093 | 827df9f3 | balrog | switch (s->mpu_model) {
|
2094 | 827df9f3 | balrog | case omap2420:
|
2095 | 827df9f3 | balrog | return 0x000254f0; /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */ |
2096 | 827df9f3 | balrog | case omap2422:
|
2097 | 827df9f3 | balrog | return 0x000400f0; |
2098 | 827df9f3 | balrog | case omap2423:
|
2099 | 827df9f3 | balrog | return 0x000800f0; |
2100 | 827df9f3 | balrog | case omap2430:
|
2101 | 827df9f3 | balrog | return 0x000000f0; |
2102 | 827df9f3 | balrog | case omap3430:
|
2103 | 827df9f3 | balrog | return 0x000000f0; |
2104 | 827df9f3 | balrog | default:
|
2105 | 827df9f3 | balrog | cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
|
2106 | 827df9f3 | balrog | } |
2107 | 827df9f3 | balrog | |
2108 | 827df9f3 | balrog | case 0x20c: |
2109 | 827df9f3 | balrog | switch (s->mpu_model) {
|
2110 | 827df9f3 | balrog | case omap2420:
|
2111 | 827df9f3 | balrog | case omap2422:
|
2112 | 827df9f3 | balrog | case omap2423:
|
2113 | 827df9f3 | balrog | return 0xcafeb5d9; /* ES 2.2 */ |
2114 | 827df9f3 | balrog | case omap2430:
|
2115 | 827df9f3 | balrog | return 0xcafeb68a; /* ES 2.2 */ |
2116 | 827df9f3 | balrog | case omap3430:
|
2117 | 827df9f3 | balrog | return 0xcafeb7ae; /* ES 2 */ |
2118 | 827df9f3 | balrog | default:
|
2119 | 827df9f3 | balrog | cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
|
2120 | 827df9f3 | balrog | } |
2121 | 827df9f3 | balrog | |
2122 | 827df9f3 | balrog | case 0x218: /* DIE_ID_reg */ |
2123 | 827df9f3 | balrog | return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); |
2124 | 827df9f3 | balrog | case 0x21c: /* DIE_ID_reg */ |
2125 | 827df9f3 | balrog | return 0x54 << 24; |
2126 | 827df9f3 | balrog | case 0x220: /* DIE_ID_reg */ |
2127 | 827df9f3 | balrog | return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); |
2128 | 827df9f3 | balrog | case 0x224: /* DIE_ID_reg */ |
2129 | 827df9f3 | balrog | return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); |
2130 | 827df9f3 | balrog | } |
2131 | 827df9f3 | balrog | |
2132 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
2133 | 827df9f3 | balrog | return 0; |
2134 | 827df9f3 | balrog | } |
2135 | 827df9f3 | balrog | |
2136 | 827df9f3 | balrog | static void omap_tap_write(void *opaque, target_phys_addr_t addr, |
2137 | 827df9f3 | balrog | uint32_t value) |
2138 | 827df9f3 | balrog | { |
2139 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
2140 | 827df9f3 | balrog | } |
2141 | 827df9f3 | balrog | |
2142 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap_tap_readfn[] = {
|
2143 | 827df9f3 | balrog | omap_badwidth_read32, |
2144 | 827df9f3 | balrog | omap_badwidth_read32, |
2145 | 827df9f3 | balrog | omap_tap_read, |
2146 | 827df9f3 | balrog | }; |
2147 | 827df9f3 | balrog | |
2148 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap_tap_writefn[] = {
|
2149 | 827df9f3 | balrog | omap_badwidth_write32, |
2150 | 827df9f3 | balrog | omap_badwidth_write32, |
2151 | 827df9f3 | balrog | omap_tap_write, |
2152 | 827df9f3 | balrog | }; |
2153 | 827df9f3 | balrog | |
2154 | 827df9f3 | balrog | void omap_tap_init(struct omap_target_agent_s *ta, |
2155 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu)
|
2156 | 827df9f3 | balrog | { |
2157 | c66fb5bc | balrog | mpu->tap_base = omap_l4_attach(ta, 0, l4_register_io_memory(0, |
2158 | 827df9f3 | balrog | omap_tap_readfn, omap_tap_writefn, mpu)); |
2159 | 827df9f3 | balrog | } |
2160 | 827df9f3 | balrog | |
2161 | 827df9f3 | balrog | /* Power, Reset, and Clock Management */
|
2162 | 827df9f3 | balrog | struct omap_prcm_s {
|
2163 | 827df9f3 | balrog | target_phys_addr_t base; |
2164 | 827df9f3 | balrog | qemu_irq irq[3];
|
2165 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu;
|
2166 | 827df9f3 | balrog | |
2167 | 827df9f3 | balrog | uint32_t irqst[3];
|
2168 | 827df9f3 | balrog | uint32_t irqen[3];
|
2169 | 827df9f3 | balrog | |
2170 | 827df9f3 | balrog | uint32_t sysconfig; |
2171 | 827df9f3 | balrog | uint32_t voltctrl; |
2172 | 827df9f3 | balrog | uint32_t scratch[20];
|
2173 | 827df9f3 | balrog | |
2174 | 827df9f3 | balrog | uint32_t clksrc[1];
|
2175 | 827df9f3 | balrog | uint32_t clkout[1];
|
2176 | 827df9f3 | balrog | uint32_t clkemul[1];
|
2177 | 827df9f3 | balrog | uint32_t clkpol[1];
|
2178 | 827df9f3 | balrog | uint32_t clksel[8];
|
2179 | 827df9f3 | balrog | uint32_t clken[12];
|
2180 | 827df9f3 | balrog | uint32_t clkctrl[4];
|
2181 | 827df9f3 | balrog | uint32_t clkidle[7];
|
2182 | 827df9f3 | balrog | uint32_t setuptime[2];
|
2183 | 827df9f3 | balrog | |
2184 | 827df9f3 | balrog | uint32_t wkup[3];
|
2185 | 827df9f3 | balrog | uint32_t wken[3];
|
2186 | 827df9f3 | balrog | uint32_t wkst[3];
|
2187 | 827df9f3 | balrog | uint32_t rst[4];
|
2188 | 827df9f3 | balrog | uint32_t rstctrl[1];
|
2189 | 827df9f3 | balrog | uint32_t power[4];
|
2190 | 827df9f3 | balrog | uint32_t rsttime_wkup; |
2191 | 827df9f3 | balrog | |
2192 | 827df9f3 | balrog | uint32_t ev; |
2193 | 827df9f3 | balrog | uint32_t evtime[2];
|
2194 | 827df9f3 | balrog | }; |
2195 | 827df9f3 | balrog | |
2196 | 827df9f3 | balrog | static void omap_prcm_int_update(struct omap_prcm_s *s, int dom) |
2197 | 827df9f3 | balrog | { |
2198 | 827df9f3 | balrog | qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]); |
2199 | 827df9f3 | balrog | /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
|
2200 | 827df9f3 | balrog | } |
2201 | 827df9f3 | balrog | |
2202 | 827df9f3 | balrog | static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr) |
2203 | 827df9f3 | balrog | { |
2204 | 827df9f3 | balrog | struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; |
2205 | 827df9f3 | balrog | int offset = addr - s->base;
|
2206 | 827df9f3 | balrog | |
2207 | 827df9f3 | balrog | switch (offset) {
|
2208 | 827df9f3 | balrog | case 0x000: /* PRCM_REVISION */ |
2209 | 827df9f3 | balrog | return 0x10; |
2210 | 827df9f3 | balrog | |
2211 | 827df9f3 | balrog | case 0x010: /* PRCM_SYSCONFIG */ |
2212 | 827df9f3 | balrog | return s->sysconfig;
|
2213 | 827df9f3 | balrog | |
2214 | 827df9f3 | balrog | case 0x018: /* PRCM_IRQSTATUS_MPU */ |
2215 | 827df9f3 | balrog | return s->irqst[0]; |
2216 | 827df9f3 | balrog | |
2217 | 827df9f3 | balrog | case 0x01c: /* PRCM_IRQENABLE_MPU */ |
2218 | 827df9f3 | balrog | return s->irqen[0]; |
2219 | 827df9f3 | balrog | |
2220 | 827df9f3 | balrog | case 0x050: /* PRCM_VOLTCTRL */ |
2221 | 827df9f3 | balrog | return s->voltctrl;
|
2222 | 827df9f3 | balrog | case 0x054: /* PRCM_VOLTST */ |
2223 | 827df9f3 | balrog | return s->voltctrl & 3; |
2224 | 827df9f3 | balrog | |
2225 | 827df9f3 | balrog | case 0x060: /* PRCM_CLKSRC_CTRL */ |
2226 | 827df9f3 | balrog | return s->clksrc[0]; |
2227 | 827df9f3 | balrog | case 0x070: /* PRCM_CLKOUT_CTRL */ |
2228 | 827df9f3 | balrog | return s->clkout[0]; |
2229 | 827df9f3 | balrog | case 0x078: /* PRCM_CLKEMUL_CTRL */ |
2230 | 827df9f3 | balrog | return s->clkemul[0]; |
2231 | 827df9f3 | balrog | case 0x080: /* PRCM_CLKCFG_CTRL */ |
2232 | 827df9f3 | balrog | case 0x084: /* PRCM_CLKCFG_STATUS */ |
2233 | 827df9f3 | balrog | return 0; |
2234 | 827df9f3 | balrog | |
2235 | 827df9f3 | balrog | case 0x090: /* PRCM_VOLTSETUP */ |
2236 | 827df9f3 | balrog | return s->setuptime[0]; |
2237 | 827df9f3 | balrog | |
2238 | 827df9f3 | balrog | case 0x094: /* PRCM_CLKSSETUP */ |
2239 | 827df9f3 | balrog | return s->setuptime[1]; |
2240 | 827df9f3 | balrog | |
2241 | 827df9f3 | balrog | case 0x098: /* PRCM_POLCTRL */ |
2242 | 827df9f3 | balrog | return s->clkpol[0]; |
2243 | 827df9f3 | balrog | |
2244 | 827df9f3 | balrog | case 0x0b0: /* GENERAL_PURPOSE1 */ |
2245 | 827df9f3 | balrog | case 0x0b4: /* GENERAL_PURPOSE2 */ |
2246 | 827df9f3 | balrog | case 0x0b8: /* GENERAL_PURPOSE3 */ |
2247 | 827df9f3 | balrog | case 0x0bc: /* GENERAL_PURPOSE4 */ |
2248 | 827df9f3 | balrog | case 0x0c0: /* GENERAL_PURPOSE5 */ |
2249 | 827df9f3 | balrog | case 0x0c4: /* GENERAL_PURPOSE6 */ |
2250 | 827df9f3 | balrog | case 0x0c8: /* GENERAL_PURPOSE7 */ |
2251 | 827df9f3 | balrog | case 0x0cc: /* GENERAL_PURPOSE8 */ |
2252 | 827df9f3 | balrog | case 0x0d0: /* GENERAL_PURPOSE9 */ |
2253 | 827df9f3 | balrog | case 0x0d4: /* GENERAL_PURPOSE10 */ |
2254 | 827df9f3 | balrog | case 0x0d8: /* GENERAL_PURPOSE11 */ |
2255 | 827df9f3 | balrog | case 0x0dc: /* GENERAL_PURPOSE12 */ |
2256 | 827df9f3 | balrog | case 0x0e0: /* GENERAL_PURPOSE13 */ |
2257 | 827df9f3 | balrog | case 0x0e4: /* GENERAL_PURPOSE14 */ |
2258 | 827df9f3 | balrog | case 0x0e8: /* GENERAL_PURPOSE15 */ |
2259 | 827df9f3 | balrog | case 0x0ec: /* GENERAL_PURPOSE16 */ |
2260 | 827df9f3 | balrog | case 0x0f0: /* GENERAL_PURPOSE17 */ |
2261 | 827df9f3 | balrog | case 0x0f4: /* GENERAL_PURPOSE18 */ |
2262 | 827df9f3 | balrog | case 0x0f8: /* GENERAL_PURPOSE19 */ |
2263 | 827df9f3 | balrog | case 0x0fc: /* GENERAL_PURPOSE20 */ |
2264 | 827df9f3 | balrog | return s->scratch[(offset - 0xb0) >> 2]; |
2265 | 827df9f3 | balrog | |
2266 | 827df9f3 | balrog | case 0x140: /* CM_CLKSEL_MPU */ |
2267 | 827df9f3 | balrog | return s->clksel[0]; |
2268 | 827df9f3 | balrog | case 0x148: /* CM_CLKSTCTRL_MPU */ |
2269 | 827df9f3 | balrog | return s->clkctrl[0]; |
2270 | 827df9f3 | balrog | |
2271 | 827df9f3 | balrog | case 0x158: /* RM_RSTST_MPU */ |
2272 | 827df9f3 | balrog | return s->rst[0]; |
2273 | 827df9f3 | balrog | case 0x1c8: /* PM_WKDEP_MPU */ |
2274 | 827df9f3 | balrog | return s->wkup[0]; |
2275 | 827df9f3 | balrog | case 0x1d4: /* PM_EVGENCTRL_MPU */ |
2276 | 827df9f3 | balrog | return s->ev;
|
2277 | 827df9f3 | balrog | case 0x1d8: /* PM_EVEGENONTIM_MPU */ |
2278 | 827df9f3 | balrog | return s->evtime[0]; |
2279 | 827df9f3 | balrog | case 0x1dc: /* PM_EVEGENOFFTIM_MPU */ |
2280 | 827df9f3 | balrog | return s->evtime[1]; |
2281 | 827df9f3 | balrog | case 0x1e0: /* PM_PWSTCTRL_MPU */ |
2282 | 827df9f3 | balrog | return s->power[0]; |
2283 | 827df9f3 | balrog | case 0x1e4: /* PM_PWSTST_MPU */ |
2284 | 827df9f3 | balrog | return 0; |
2285 | 827df9f3 | balrog | |
2286 | 827df9f3 | balrog | case 0x200: /* CM_FCLKEN1_CORE */ |
2287 | 827df9f3 | balrog | return s->clken[0]; |
2288 | 827df9f3 | balrog | case 0x204: /* CM_FCLKEN2_CORE */ |
2289 | 827df9f3 | balrog | return s->clken[1]; |
2290 | 827df9f3 | balrog | case 0x210: /* CM_ICLKEN1_CORE */ |
2291 | 827df9f3 | balrog | return s->clken[2]; |
2292 | 827df9f3 | balrog | case 0x214: /* CM_ICLKEN2_CORE */ |
2293 | 827df9f3 | balrog | return s->clken[3]; |
2294 | 827df9f3 | balrog | case 0x21c: /* CM_ICLKEN4_CORE */ |
2295 | 827df9f3 | balrog | return s->clken[4]; |
2296 | 827df9f3 | balrog | |
2297 | 827df9f3 | balrog | case 0x220: /* CM_IDLEST1_CORE */ |
2298 | 827df9f3 | balrog | /* TODO: check the actual iclk status */
|
2299 | 827df9f3 | balrog | return 0x7ffffff9; |
2300 | 827df9f3 | balrog | case 0x224: /* CM_IDLEST2_CORE */ |
2301 | 827df9f3 | balrog | /* TODO: check the actual iclk status */
|
2302 | 827df9f3 | balrog | return 0x00000007; |
2303 | 827df9f3 | balrog | case 0x22c: /* CM_IDLEST4_CORE */ |
2304 | 827df9f3 | balrog | /* TODO: check the actual iclk status */
|
2305 | 827df9f3 | balrog | return 0x0000001f; |
2306 | 827df9f3 | balrog | |
2307 | 827df9f3 | balrog | case 0x230: /* CM_AUTOIDLE1_CORE */ |
2308 | 827df9f3 | balrog | return s->clkidle[0]; |
2309 | 827df9f3 | balrog | case 0x234: /* CM_AUTOIDLE2_CORE */ |
2310 | 827df9f3 | balrog | return s->clkidle[1]; |
2311 | 827df9f3 | balrog | case 0x238: /* CM_AUTOIDLE3_CORE */ |
2312 | 827df9f3 | balrog | return s->clkidle[2]; |
2313 | 827df9f3 | balrog | case 0x23c: /* CM_AUTOIDLE4_CORE */ |
2314 | 827df9f3 | balrog | return s->clkidle[3]; |
2315 | 827df9f3 | balrog | |
2316 | 827df9f3 | balrog | case 0x240: /* CM_CLKSEL1_CORE */ |
2317 | 827df9f3 | balrog | return s->clksel[1]; |
2318 | 827df9f3 | balrog | case 0x244: /* CM_CLKSEL2_CORE */ |
2319 | 827df9f3 | balrog | return s->clksel[2]; |
2320 | 827df9f3 | balrog | |
2321 | 827df9f3 | balrog | case 0x248: /* CM_CLKSTCTRL_CORE */ |
2322 | 827df9f3 | balrog | return s->clkctrl[1]; |
2323 | 827df9f3 | balrog | |
2324 | 827df9f3 | balrog | case 0x2a0: /* PM_WKEN1_CORE */ |
2325 | 827df9f3 | balrog | return s->wken[0]; |
2326 | 827df9f3 | balrog | case 0x2a4: /* PM_WKEN2_CORE */ |
2327 | 827df9f3 | balrog | return s->wken[1]; |
2328 | 827df9f3 | balrog | |
2329 | 827df9f3 | balrog | case 0x2b0: /* PM_WKST1_CORE */ |
2330 | 827df9f3 | balrog | return s->wkst[0]; |
2331 | 827df9f3 | balrog | case 0x2b4: /* PM_WKST2_CORE */ |
2332 | 827df9f3 | balrog | return s->wkst[1]; |
2333 | 827df9f3 | balrog | case 0x2c8: /* PM_WKDEP_CORE */ |
2334 | 827df9f3 | balrog | return 0x1e; |
2335 | 827df9f3 | balrog | |
2336 | 827df9f3 | balrog | case 0x2e0: /* PM_PWSTCTRL_CORE */ |
2337 | 827df9f3 | balrog | return s->power[1]; |
2338 | 827df9f3 | balrog | case 0x2e4: /* PM_PWSTST_CORE */ |
2339 | 827df9f3 | balrog | return 0x000030 | (s->power[1] & 0xfc00); |
2340 | 827df9f3 | balrog | |
2341 | 827df9f3 | balrog | case 0x300: /* CM_FCLKEN_GFX */ |
2342 | 827df9f3 | balrog | return s->clken[5]; |
2343 | 827df9f3 | balrog | case 0x310: /* CM_ICLKEN_GFX */ |
2344 | 827df9f3 | balrog | return s->clken[6]; |
2345 | 827df9f3 | balrog | case 0x320: /* CM_IDLEST_GFX */ |
2346 | 827df9f3 | balrog | /* TODO: check the actual iclk status */
|
2347 | 827df9f3 | balrog | return 0x00000001; |
2348 | 827df9f3 | balrog | case 0x340: /* CM_CLKSEL_GFX */ |
2349 | 827df9f3 | balrog | return s->clksel[3]; |
2350 | 827df9f3 | balrog | case 0x348: /* CM_CLKSTCTRL_GFX */ |
2351 | 827df9f3 | balrog | return s->clkctrl[2]; |
2352 | 827df9f3 | balrog | case 0x350: /* RM_RSTCTRL_GFX */ |
2353 | 827df9f3 | balrog | return s->rstctrl[0]; |
2354 | 827df9f3 | balrog | case 0x358: /* RM_RSTST_GFX */ |
2355 | 827df9f3 | balrog | return s->rst[1]; |
2356 | 827df9f3 | balrog | case 0x3c8: /* PM_WKDEP_GFX */ |
2357 | 827df9f3 | balrog | return s->wkup[1]; |
2358 | 827df9f3 | balrog | |
2359 | 827df9f3 | balrog | case 0x3e0: /* PM_PWSTCTRL_GFX */ |
2360 | 827df9f3 | balrog | return s->power[2]; |
2361 | 827df9f3 | balrog | case 0x3e4: /* PM_PWSTST_GFX */ |
2362 | 827df9f3 | balrog | return s->power[2] & 3; |
2363 | 827df9f3 | balrog | |
2364 | 827df9f3 | balrog | case 0x400: /* CM_FCLKEN_WKUP */ |
2365 | 827df9f3 | balrog | return s->clken[7]; |
2366 | 827df9f3 | balrog | case 0x410: /* CM_ICLKEN_WKUP */ |
2367 | 827df9f3 | balrog | return s->clken[8]; |
2368 | 827df9f3 | balrog | case 0x420: /* CM_IDLEST_WKUP */ |
2369 | 827df9f3 | balrog | /* TODO: check the actual iclk status */
|
2370 | 827df9f3 | balrog | return 0x0000003f; |
2371 | 827df9f3 | balrog | case 0x430: /* CM_AUTOIDLE_WKUP */ |
2372 | 827df9f3 | balrog | return s->clkidle[4]; |
2373 | 827df9f3 | balrog | case 0x440: /* CM_CLKSEL_WKUP */ |
2374 | 827df9f3 | balrog | return s->clksel[4]; |
2375 | 827df9f3 | balrog | case 0x450: /* RM_RSTCTRL_WKUP */ |
2376 | 827df9f3 | balrog | return 0; |
2377 | 827df9f3 | balrog | case 0x454: /* RM_RSTTIME_WKUP */ |
2378 | 827df9f3 | balrog | return s->rsttime_wkup;
|
2379 | 827df9f3 | balrog | case 0x458: /* RM_RSTST_WKUP */ |
2380 | 827df9f3 | balrog | return s->rst[2]; |
2381 | 827df9f3 | balrog | case 0x4a0: /* PM_WKEN_WKUP */ |
2382 | 827df9f3 | balrog | return s->wken[2]; |
2383 | 827df9f3 | balrog | case 0x4b0: /* PM_WKST_WKUP */ |
2384 | 827df9f3 | balrog | return s->wkst[2]; |
2385 | 827df9f3 | balrog | |
2386 | 827df9f3 | balrog | case 0x500: /* CM_CLKEN_PLL */ |
2387 | 827df9f3 | balrog | return s->clken[9]; |
2388 | 827df9f3 | balrog | case 0x520: /* CM_IDLEST_CKGEN */ |
2389 | 827df9f3 | balrog | /* Core uses 32-kHz clock */
|
2390 | 827df9f3 | balrog | if (!(s->clksel[6] & 3)) |
2391 | 827df9f3 | balrog | return 0x00000377; |
2392 | 827df9f3 | balrog | /* DPLL not in lock mode, core uses ref_clk */
|
2393 | 827df9f3 | balrog | if ((s->clken[9] & 3) != 3) |
2394 | 827df9f3 | balrog | return 0x00000375; |
2395 | 827df9f3 | balrog | /* Core uses DPLL */
|
2396 | 827df9f3 | balrog | return 0x00000376; |
2397 | 827df9f3 | balrog | case 0x530: /* CM_AUTOIDLE_PLL */ |
2398 | 827df9f3 | balrog | return s->clkidle[5]; |
2399 | 827df9f3 | balrog | case 0x540: /* CM_CLKSEL1_PLL */ |
2400 | 827df9f3 | balrog | return s->clksel[5]; |
2401 | 827df9f3 | balrog | case 0x544: /* CM_CLKSEL2_PLL */ |
2402 | 827df9f3 | balrog | return s->clksel[6]; |
2403 | 827df9f3 | balrog | |
2404 | 827df9f3 | balrog | case 0x800: /* CM_FCLKEN_DSP */ |
2405 | 827df9f3 | balrog | return s->clken[10]; |
2406 | 827df9f3 | balrog | case 0x810: /* CM_ICLKEN_DSP */ |
2407 | 827df9f3 | balrog | return s->clken[11]; |
2408 | 827df9f3 | balrog | case 0x820: /* CM_IDLEST_DSP */ |
2409 | 827df9f3 | balrog | /* TODO: check the actual iclk status */
|
2410 | 827df9f3 | balrog | return 0x00000103; |
2411 | 827df9f3 | balrog | case 0x830: /* CM_AUTOIDLE_DSP */ |
2412 | 827df9f3 | balrog | return s->clkidle[6]; |
2413 | 827df9f3 | balrog | case 0x840: /* CM_CLKSEL_DSP */ |
2414 | 827df9f3 | balrog | return s->clksel[7]; |
2415 | 827df9f3 | balrog | case 0x848: /* CM_CLKSTCTRL_DSP */ |
2416 | 827df9f3 | balrog | return s->clkctrl[3]; |
2417 | 827df9f3 | balrog | case 0x850: /* RM_RSTCTRL_DSP */ |
2418 | 827df9f3 | balrog | return 0; |
2419 | 827df9f3 | balrog | case 0x858: /* RM_RSTST_DSP */ |
2420 | 827df9f3 | balrog | return s->rst[3]; |
2421 | 827df9f3 | balrog | case 0x8c8: /* PM_WKDEP_DSP */ |
2422 | 827df9f3 | balrog | return s->wkup[2]; |
2423 | 827df9f3 | balrog | case 0x8e0: /* PM_PWSTCTRL_DSP */ |
2424 | 827df9f3 | balrog | return s->power[3]; |
2425 | 827df9f3 | balrog | case 0x8e4: /* PM_PWSTST_DSP */ |
2426 | 827df9f3 | balrog | return 0x008030 | (s->power[3] & 0x3003); |
2427 | 827df9f3 | balrog | |
2428 | 827df9f3 | balrog | case 0x8f0: /* PRCM_IRQSTATUS_DSP */ |
2429 | 827df9f3 | balrog | return s->irqst[1]; |
2430 | 827df9f3 | balrog | case 0x8f4: /* PRCM_IRQENABLE_DSP */ |
2431 | 827df9f3 | balrog | return s->irqen[1]; |
2432 | 827df9f3 | balrog | |
2433 | 827df9f3 | balrog | case 0x8f8: /* PRCM_IRQSTATUS_IVA */ |
2434 | 827df9f3 | balrog | return s->irqst[2]; |
2435 | 827df9f3 | balrog | case 0x8fc: /* PRCM_IRQENABLE_IVA */ |
2436 | 827df9f3 | balrog | return s->irqen[2]; |
2437 | 827df9f3 | balrog | } |
2438 | 827df9f3 | balrog | |
2439 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
2440 | 827df9f3 | balrog | return 0; |
2441 | 827df9f3 | balrog | } |
2442 | 827df9f3 | balrog | |
2443 | 827df9f3 | balrog | static void omap_prcm_write(void *opaque, target_phys_addr_t addr, |
2444 | 827df9f3 | balrog | uint32_t value) |
2445 | 827df9f3 | balrog | { |
2446 | 827df9f3 | balrog | struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; |
2447 | 827df9f3 | balrog | int offset = addr - s->base;
|
2448 | 827df9f3 | balrog | |
2449 | 827df9f3 | balrog | switch (offset) {
|
2450 | 827df9f3 | balrog | case 0x000: /* PRCM_REVISION */ |
2451 | 827df9f3 | balrog | case 0x054: /* PRCM_VOLTST */ |
2452 | 827df9f3 | balrog | case 0x084: /* PRCM_CLKCFG_STATUS */ |
2453 | 827df9f3 | balrog | case 0x1e4: /* PM_PWSTST_MPU */ |
2454 | 827df9f3 | balrog | case 0x220: /* CM_IDLEST1_CORE */ |
2455 | 827df9f3 | balrog | case 0x224: /* CM_IDLEST2_CORE */ |
2456 | 827df9f3 | balrog | case 0x22c: /* CM_IDLEST4_CORE */ |
2457 | 827df9f3 | balrog | case 0x2c8: /* PM_WKDEP_CORE */ |
2458 | 827df9f3 | balrog | case 0x2e4: /* PM_PWSTST_CORE */ |
2459 | 827df9f3 | balrog | case 0x320: /* CM_IDLEST_GFX */ |
2460 | 827df9f3 | balrog | case 0x3e4: /* PM_PWSTST_GFX */ |
2461 | 827df9f3 | balrog | case 0x420: /* CM_IDLEST_WKUP */ |
2462 | 827df9f3 | balrog | case 0x520: /* CM_IDLEST_CKGEN */ |
2463 | 827df9f3 | balrog | case 0x820: /* CM_IDLEST_DSP */ |
2464 | 827df9f3 | balrog | case 0x8e4: /* PM_PWSTST_DSP */ |
2465 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
2466 | 827df9f3 | balrog | return;
|
2467 | 827df9f3 | balrog | |
2468 | 827df9f3 | balrog | case 0x010: /* PRCM_SYSCONFIG */ |
2469 | 827df9f3 | balrog | s->sysconfig = value & 1;
|
2470 | 827df9f3 | balrog | break;
|
2471 | 827df9f3 | balrog | |
2472 | 827df9f3 | balrog | case 0x018: /* PRCM_IRQSTATUS_MPU */ |
2473 | 827df9f3 | balrog | s->irqst[0] &= ~value;
|
2474 | 827df9f3 | balrog | omap_prcm_int_update(s, 0);
|
2475 | 827df9f3 | balrog | break;
|
2476 | 827df9f3 | balrog | case 0x01c: /* PRCM_IRQENABLE_MPU */ |
2477 | 827df9f3 | balrog | s->irqen[0] = value & 0x3f; |
2478 | 827df9f3 | balrog | omap_prcm_int_update(s, 0);
|
2479 | 827df9f3 | balrog | break;
|
2480 | 827df9f3 | balrog | |
2481 | 827df9f3 | balrog | case 0x050: /* PRCM_VOLTCTRL */ |
2482 | 827df9f3 | balrog | s->voltctrl = value & 0xf1c3;
|
2483 | 827df9f3 | balrog | break;
|
2484 | 827df9f3 | balrog | |
2485 | 827df9f3 | balrog | case 0x060: /* PRCM_CLKSRC_CTRL */ |
2486 | 827df9f3 | balrog | s->clksrc[0] = value & 0xdb; |
2487 | 827df9f3 | balrog | /* TODO update clocks */
|
2488 | 827df9f3 | balrog | break;
|
2489 | 827df9f3 | balrog | |
2490 | 827df9f3 | balrog | case 0x070: /* PRCM_CLKOUT_CTRL */ |
2491 | 827df9f3 | balrog | s->clkout[0] = value & 0xbbbb; |
2492 | 827df9f3 | balrog | /* TODO update clocks */
|
2493 | 827df9f3 | balrog | break;
|
2494 | 827df9f3 | balrog | |
2495 | 827df9f3 | balrog | case 0x078: /* PRCM_CLKEMUL_CTRL */ |
2496 | 827df9f3 | balrog | s->clkemul[0] = value & 1; |
2497 | 827df9f3 | balrog | /* TODO update clocks */
|
2498 | 827df9f3 | balrog | break;
|
2499 | 827df9f3 | balrog | |
2500 | 827df9f3 | balrog | case 0x080: /* PRCM_CLKCFG_CTRL */ |
2501 | 827df9f3 | balrog | break;
|
2502 | 827df9f3 | balrog | |
2503 | 827df9f3 | balrog | case 0x090: /* PRCM_VOLTSETUP */ |
2504 | 827df9f3 | balrog | s->setuptime[0] = value & 0xffff; |
2505 | 827df9f3 | balrog | break;
|
2506 | 827df9f3 | balrog | case 0x094: /* PRCM_CLKSSETUP */ |
2507 | 827df9f3 | balrog | s->setuptime[1] = value & 0xffff; |
2508 | 827df9f3 | balrog | break;
|
2509 | 827df9f3 | balrog | |
2510 | 827df9f3 | balrog | case 0x098: /* PRCM_POLCTRL */ |
2511 | 827df9f3 | balrog | s->clkpol[0] = value & 0x701; |
2512 | 827df9f3 | balrog | break;
|
2513 | 827df9f3 | balrog | |
2514 | 827df9f3 | balrog | case 0x0b0: /* GENERAL_PURPOSE1 */ |
2515 | 827df9f3 | balrog | case 0x0b4: /* GENERAL_PURPOSE2 */ |
2516 | 827df9f3 | balrog | case 0x0b8: /* GENERAL_PURPOSE3 */ |
2517 | 827df9f3 | balrog | case 0x0bc: /* GENERAL_PURPOSE4 */ |
2518 | 827df9f3 | balrog | case 0x0c0: /* GENERAL_PURPOSE5 */ |
2519 | 827df9f3 | balrog | case 0x0c4: /* GENERAL_PURPOSE6 */ |
2520 | 827df9f3 | balrog | case 0x0c8: /* GENERAL_PURPOSE7 */ |
2521 | 827df9f3 | balrog | case 0x0cc: /* GENERAL_PURPOSE8 */ |
2522 | 827df9f3 | balrog | case 0x0d0: /* GENERAL_PURPOSE9 */ |
2523 | 827df9f3 | balrog | case 0x0d4: /* GENERAL_PURPOSE10 */ |
2524 | 827df9f3 | balrog | case 0x0d8: /* GENERAL_PURPOSE11 */ |
2525 | 827df9f3 | balrog | case 0x0dc: /* GENERAL_PURPOSE12 */ |
2526 | 827df9f3 | balrog | case 0x0e0: /* GENERAL_PURPOSE13 */ |
2527 | 827df9f3 | balrog | case 0x0e4: /* GENERAL_PURPOSE14 */ |
2528 | 827df9f3 | balrog | case 0x0e8: /* GENERAL_PURPOSE15 */ |
2529 | 827df9f3 | balrog | case 0x0ec: /* GENERAL_PURPOSE16 */ |
2530 | 827df9f3 | balrog | case 0x0f0: /* GENERAL_PURPOSE17 */ |
2531 | 827df9f3 | balrog | case 0x0f4: /* GENERAL_PURPOSE18 */ |
2532 | 827df9f3 | balrog | case 0x0f8: /* GENERAL_PURPOSE19 */ |
2533 | 827df9f3 | balrog | case 0x0fc: /* GENERAL_PURPOSE20 */ |
2534 | 827df9f3 | balrog | s->scratch[(offset - 0xb0) >> 2] = value; |
2535 | 827df9f3 | balrog | break;
|
2536 | 827df9f3 | balrog | |
2537 | 827df9f3 | balrog | case 0x140: /* CM_CLKSEL_MPU */ |
2538 | 827df9f3 | balrog | s->clksel[0] = value & 0x1f; |
2539 | 827df9f3 | balrog | /* TODO update clocks */
|
2540 | 827df9f3 | balrog | break;
|
2541 | 827df9f3 | balrog | case 0x148: /* CM_CLKSTCTRL_MPU */ |
2542 | 827df9f3 | balrog | s->clkctrl[0] = value & 0x1f; |
2543 | 827df9f3 | balrog | break;
|
2544 | 827df9f3 | balrog | |
2545 | 827df9f3 | balrog | case 0x158: /* RM_RSTST_MPU */ |
2546 | 827df9f3 | balrog | s->rst[0] &= ~value;
|
2547 | 827df9f3 | balrog | break;
|
2548 | 827df9f3 | balrog | case 0x1c8: /* PM_WKDEP_MPU */ |
2549 | 827df9f3 | balrog | s->wkup[0] = value & 0x15; |
2550 | 827df9f3 | balrog | break;
|
2551 | 827df9f3 | balrog | |
2552 | 827df9f3 | balrog | case 0x1d4: /* PM_EVGENCTRL_MPU */ |
2553 | 827df9f3 | balrog | s->ev = value & 0x1f;
|
2554 | 827df9f3 | balrog | break;
|
2555 | 827df9f3 | balrog | case 0x1d8: /* PM_EVEGENONTIM_MPU */ |
2556 | 827df9f3 | balrog | s->evtime[0] = value;
|
2557 | 827df9f3 | balrog | break;
|
2558 | 827df9f3 | balrog | case 0x1dc: /* PM_EVEGENOFFTIM_MPU */ |
2559 | 827df9f3 | balrog | s->evtime[1] = value;
|
2560 | 827df9f3 | balrog | break;
|
2561 | 827df9f3 | balrog | |
2562 | 827df9f3 | balrog | case 0x1e0: /* PM_PWSTCTRL_MPU */ |
2563 | 827df9f3 | balrog | s->power[0] = value & 0xc0f; |
2564 | 827df9f3 | balrog | break;
|
2565 | 827df9f3 | balrog | |
2566 | 827df9f3 | balrog | case 0x200: /* CM_FCLKEN1_CORE */ |
2567 | 827df9f3 | balrog | s->clken[0] = value & 0xbfffffff; |
2568 | 827df9f3 | balrog | /* TODO update clocks */
|
2569 | 827df9f3 | balrog | break;
|
2570 | 827df9f3 | balrog | case 0x204: /* CM_FCLKEN2_CORE */ |
2571 | 827df9f3 | balrog | s->clken[1] = value & 0x00000007; |
2572 | 827df9f3 | balrog | /* TODO update clocks */
|
2573 | 827df9f3 | balrog | break;
|
2574 | 827df9f3 | balrog | case 0x210: /* CM_ICLKEN1_CORE */ |
2575 | 827df9f3 | balrog | s->clken[2] = value & 0xfffffff9; |
2576 | 827df9f3 | balrog | /* TODO update clocks */
|
2577 | 827df9f3 | balrog | break;
|
2578 | 827df9f3 | balrog | case 0x214: /* CM_ICLKEN2_CORE */ |
2579 | 827df9f3 | balrog | s->clken[3] = value & 0x00000007; |
2580 | 827df9f3 | balrog | /* TODO update clocks */
|
2581 | 827df9f3 | balrog | break;
|
2582 | 827df9f3 | balrog | case 0x21c: /* CM_ICLKEN4_CORE */ |
2583 | 827df9f3 | balrog | s->clken[4] = value & 0x0000001f; |
2584 | 827df9f3 | balrog | /* TODO update clocks */
|
2585 | 827df9f3 | balrog | break;
|
2586 | 827df9f3 | balrog | |
2587 | 827df9f3 | balrog | case 0x230: /* CM_AUTOIDLE1_CORE */ |
2588 | 827df9f3 | balrog | s->clkidle[0] = value & 0xfffffff9; |
2589 | 827df9f3 | balrog | /* TODO update clocks */
|
2590 | 827df9f3 | balrog | break;
|
2591 | 827df9f3 | balrog | case 0x234: /* CM_AUTOIDLE2_CORE */ |
2592 | 827df9f3 | balrog | s->clkidle[1] = value & 0x00000007; |
2593 | 827df9f3 | balrog | /* TODO update clocks */
|
2594 | 827df9f3 | balrog | break;
|
2595 | 827df9f3 | balrog | case 0x238: /* CM_AUTOIDLE3_CORE */ |
2596 | 827df9f3 | balrog | s->clkidle[2] = value & 0x00000007; |
2597 | 827df9f3 | balrog | /* TODO update clocks */
|
2598 | 827df9f3 | balrog | break;
|
2599 | 827df9f3 | balrog | case 0x23c: /* CM_AUTOIDLE4_CORE */ |
2600 | 827df9f3 | balrog | s->clkidle[3] = value & 0x0000001f; |
2601 | 827df9f3 | balrog | /* TODO update clocks */
|
2602 | 827df9f3 | balrog | break;
|
2603 | 827df9f3 | balrog | |
2604 | 827df9f3 | balrog | case 0x240: /* CM_CLKSEL1_CORE */ |
2605 | 827df9f3 | balrog | s->clksel[1] = value & 0x0fffbf7f; |
2606 | 827df9f3 | balrog | /* TODO update clocks */
|
2607 | 827df9f3 | balrog | break;
|
2608 | 827df9f3 | balrog | |
2609 | 827df9f3 | balrog | case 0x244: /* CM_CLKSEL2_CORE */ |
2610 | 827df9f3 | balrog | s->clksel[2] = value & 0x00fffffc; |
2611 | 827df9f3 | balrog | /* TODO update clocks */
|
2612 | 827df9f3 | balrog | break;
|
2613 | 827df9f3 | balrog | |
2614 | 827df9f3 | balrog | case 0x248: /* CM_CLKSTCTRL_CORE */ |
2615 | 827df9f3 | balrog | s->clkctrl[1] = value & 0x7; |
2616 | 827df9f3 | balrog | break;
|
2617 | 827df9f3 | balrog | |
2618 | 827df9f3 | balrog | case 0x2a0: /* PM_WKEN1_CORE */ |
2619 | 827df9f3 | balrog | s->wken[0] = value & 0x04667ff8; |
2620 | 827df9f3 | balrog | break;
|
2621 | 827df9f3 | balrog | case 0x2a4: /* PM_WKEN2_CORE */ |
2622 | 827df9f3 | balrog | s->wken[1] = value & 0x00000005; |
2623 | 827df9f3 | balrog | break;
|
2624 | 827df9f3 | balrog | |
2625 | 827df9f3 | balrog | case 0x2b0: /* PM_WKST1_CORE */ |
2626 | 827df9f3 | balrog | s->wkst[0] &= ~value;
|
2627 | 827df9f3 | balrog | break;
|
2628 | 827df9f3 | balrog | case 0x2b4: /* PM_WKST2_CORE */ |
2629 | 827df9f3 | balrog | s->wkst[1] &= ~value;
|
2630 | 827df9f3 | balrog | break;
|
2631 | 827df9f3 | balrog | |
2632 | 827df9f3 | balrog | case 0x2e0: /* PM_PWSTCTRL_CORE */ |
2633 | 827df9f3 | balrog | s->power[1] = (value & 0x00fc3f) | (1 << 2); |
2634 | 827df9f3 | balrog | break;
|
2635 | 827df9f3 | balrog | |
2636 | 827df9f3 | balrog | case 0x300: /* CM_FCLKEN_GFX */ |
2637 | 827df9f3 | balrog | s->clken[5] = value & 6; |
2638 | 827df9f3 | balrog | /* TODO update clocks */
|
2639 | 827df9f3 | balrog | break;
|
2640 | 827df9f3 | balrog | case 0x310: /* CM_ICLKEN_GFX */ |
2641 | 827df9f3 | balrog | s->clken[6] = value & 1; |
2642 | 827df9f3 | balrog | /* TODO update clocks */
|
2643 | 827df9f3 | balrog | break;
|
2644 | 827df9f3 | balrog | case 0x340: /* CM_CLKSEL_GFX */ |
2645 | 827df9f3 | balrog | s->clksel[3] = value & 7; |
2646 | 827df9f3 | balrog | /* TODO update clocks */
|
2647 | 827df9f3 | balrog | break;
|
2648 | 827df9f3 | balrog | case 0x348: /* CM_CLKSTCTRL_GFX */ |
2649 | 827df9f3 | balrog | s->clkctrl[2] = value & 1; |
2650 | 827df9f3 | balrog | break;
|
2651 | 827df9f3 | balrog | case 0x350: /* RM_RSTCTRL_GFX */ |
2652 | 827df9f3 | balrog | s->rstctrl[0] = value & 1; |
2653 | 827df9f3 | balrog | /* TODO: reset */
|
2654 | 827df9f3 | balrog | break;
|
2655 | 827df9f3 | balrog | case 0x358: /* RM_RSTST_GFX */ |
2656 | 827df9f3 | balrog | s->rst[1] &= ~value;
|
2657 | 827df9f3 | balrog | break;
|
2658 | 827df9f3 | balrog | case 0x3c8: /* PM_WKDEP_GFX */ |
2659 | 827df9f3 | balrog | s->wkup[1] = value & 0x13; |
2660 | 827df9f3 | balrog | break;
|
2661 | 827df9f3 | balrog | case 0x3e0: /* PM_PWSTCTRL_GFX */ |
2662 | 827df9f3 | balrog | s->power[2] = (value & 0x00c0f) | (3 << 2); |
2663 | 827df9f3 | balrog | break;
|
2664 | 827df9f3 | balrog | |
2665 | 827df9f3 | balrog | case 0x400: /* CM_FCLKEN_WKUP */ |
2666 | 827df9f3 | balrog | s->clken[7] = value & 0xd; |
2667 | 827df9f3 | balrog | /* TODO update clocks */
|
2668 | 827df9f3 | balrog | break;
|
2669 | 827df9f3 | balrog | case 0x410: /* CM_ICLKEN_WKUP */ |
2670 | 827df9f3 | balrog | s->clken[8] = value & 0x3f; |
2671 | 827df9f3 | balrog | /* TODO update clocks */
|
2672 | 827df9f3 | balrog | break;
|
2673 | 827df9f3 | balrog | case 0x430: /* CM_AUTOIDLE_WKUP */ |
2674 | 827df9f3 | balrog | s->clkidle[4] = value & 0x0000003f; |
2675 | 827df9f3 | balrog | /* TODO update clocks */
|
2676 | 827df9f3 | balrog | break;
|
2677 | 827df9f3 | balrog | case 0x440: /* CM_CLKSEL_WKUP */ |
2678 | 827df9f3 | balrog | s->clksel[4] = value & 3; |
2679 | 827df9f3 | balrog | /* TODO update clocks */
|
2680 | 827df9f3 | balrog | break;
|
2681 | 827df9f3 | balrog | case 0x450: /* RM_RSTCTRL_WKUP */ |
2682 | 827df9f3 | balrog | /* TODO: reset */
|
2683 | 827df9f3 | balrog | if (value & 2) |
2684 | 827df9f3 | balrog | qemu_system_reset_request(); |
2685 | 827df9f3 | balrog | break;
|
2686 | 827df9f3 | balrog | case 0x454: /* RM_RSTTIME_WKUP */ |
2687 | 827df9f3 | balrog | s->rsttime_wkup = value & 0x1fff;
|
2688 | 827df9f3 | balrog | break;
|
2689 | 827df9f3 | balrog | case 0x458: /* RM_RSTST_WKUP */ |
2690 | 827df9f3 | balrog | s->rst[2] &= ~value;
|
2691 | 827df9f3 | balrog | break;
|
2692 | 827df9f3 | balrog | case 0x4a0: /* PM_WKEN_WKUP */ |
2693 | 827df9f3 | balrog | s->wken[2] = value & 0x00000005; |
2694 | 827df9f3 | balrog | break;
|
2695 | 827df9f3 | balrog | case 0x4b0: /* PM_WKST_WKUP */ |
2696 | 827df9f3 | balrog | s->wkst[2] &= ~value;
|
2697 | 827df9f3 | balrog | break;
|
2698 | 827df9f3 | balrog | |
2699 | 827df9f3 | balrog | case 0x500: /* CM_CLKEN_PLL */ |
2700 | 827df9f3 | balrog | s->clken[9] = value & 0xcf; |
2701 | 827df9f3 | balrog | /* TODO update clocks */
|
2702 | 827df9f3 | balrog | break;
|
2703 | 827df9f3 | balrog | case 0x530: /* CM_AUTOIDLE_PLL */ |
2704 | 827df9f3 | balrog | s->clkidle[5] = value & 0x000000cf; |
2705 | 827df9f3 | balrog | /* TODO update clocks */
|
2706 | 827df9f3 | balrog | break;
|
2707 | 827df9f3 | balrog | case 0x540: /* CM_CLKSEL1_PLL */ |
2708 | 827df9f3 | balrog | s->clksel[5] = value & 0x03bfff28; |
2709 | 827df9f3 | balrog | /* TODO update clocks */
|
2710 | 827df9f3 | balrog | break;
|
2711 | 827df9f3 | balrog | case 0x544: /* CM_CLKSEL2_PLL */ |
2712 | 827df9f3 | balrog | s->clksel[6] = value & 3; |
2713 | 827df9f3 | balrog | /* TODO update clocks */
|
2714 | 827df9f3 | balrog | break;
|
2715 | 827df9f3 | balrog | |
2716 | 827df9f3 | balrog | case 0x800: /* CM_FCLKEN_DSP */ |
2717 | 827df9f3 | balrog | s->clken[10] = value & 0x501; |
2718 | 827df9f3 | balrog | /* TODO update clocks */
|
2719 | 827df9f3 | balrog | break;
|
2720 | 827df9f3 | balrog | case 0x810: /* CM_ICLKEN_DSP */ |
2721 | 827df9f3 | balrog | s->clken[11] = value & 0x2; |
2722 | 827df9f3 | balrog | /* TODO update clocks */
|
2723 | 827df9f3 | balrog | break;
|
2724 | 827df9f3 | balrog | case 0x830: /* CM_AUTOIDLE_DSP */ |
2725 | 827df9f3 | balrog | s->clkidle[6] = value & 0x2; |
2726 | 827df9f3 | balrog | /* TODO update clocks */
|
2727 | 827df9f3 | balrog | break;
|
2728 | 827df9f3 | balrog | case 0x840: /* CM_CLKSEL_DSP */ |
2729 | 827df9f3 | balrog | s->clksel[7] = value & 0x3fff; |
2730 | 827df9f3 | balrog | /* TODO update clocks */
|
2731 | 827df9f3 | balrog | break;
|
2732 | 827df9f3 | balrog | case 0x848: /* CM_CLKSTCTRL_DSP */ |
2733 | 827df9f3 | balrog | s->clkctrl[3] = value & 0x101; |
2734 | 827df9f3 | balrog | break;
|
2735 | 827df9f3 | balrog | case 0x850: /* RM_RSTCTRL_DSP */ |
2736 | 827df9f3 | balrog | /* TODO: reset */
|
2737 | 827df9f3 | balrog | break;
|
2738 | 827df9f3 | balrog | case 0x858: /* RM_RSTST_DSP */ |
2739 | 827df9f3 | balrog | s->rst[3] &= ~value;
|
2740 | 827df9f3 | balrog | break;
|
2741 | 827df9f3 | balrog | case 0x8c8: /* PM_WKDEP_DSP */ |
2742 | 827df9f3 | balrog | s->wkup[2] = value & 0x13; |
2743 | 827df9f3 | balrog | break;
|
2744 | 827df9f3 | balrog | case 0x8e0: /* PM_PWSTCTRL_DSP */ |
2745 | 827df9f3 | balrog | s->power[3] = (value & 0x03017) | (3 << 2); |
2746 | 827df9f3 | balrog | break;
|
2747 | 827df9f3 | balrog | |
2748 | 827df9f3 | balrog | case 0x8f0: /* PRCM_IRQSTATUS_DSP */ |
2749 | 827df9f3 | balrog | s->irqst[1] &= ~value;
|
2750 | 827df9f3 | balrog | omap_prcm_int_update(s, 1);
|
2751 | 827df9f3 | balrog | break;
|
2752 | 827df9f3 | balrog | case 0x8f4: /* PRCM_IRQENABLE_DSP */ |
2753 | 827df9f3 | balrog | s->irqen[1] = value & 0x7; |
2754 | 827df9f3 | balrog | omap_prcm_int_update(s, 1);
|
2755 | 827df9f3 | balrog | break;
|
2756 | 827df9f3 | balrog | |
2757 | 827df9f3 | balrog | case 0x8f8: /* PRCM_IRQSTATUS_IVA */ |
2758 | 827df9f3 | balrog | s->irqst[2] &= ~value;
|
2759 | 827df9f3 | balrog | omap_prcm_int_update(s, 2);
|
2760 | 827df9f3 | balrog | break;
|
2761 | 827df9f3 | balrog | case 0x8fc: /* PRCM_IRQENABLE_IVA */ |
2762 | 827df9f3 | balrog | s->irqen[2] = value & 0x7; |
2763 | 827df9f3 | balrog | omap_prcm_int_update(s, 2);
|
2764 | 827df9f3 | balrog | break;
|
2765 | 827df9f3 | balrog | |
2766 | 827df9f3 | balrog | default:
|
2767 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
2768 | 827df9f3 | balrog | return;
|
2769 | 827df9f3 | balrog | } |
2770 | 827df9f3 | balrog | } |
2771 | 827df9f3 | balrog | |
2772 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap_prcm_readfn[] = {
|
2773 | 827df9f3 | balrog | omap_badwidth_read32, |
2774 | 827df9f3 | balrog | omap_badwidth_read32, |
2775 | 827df9f3 | balrog | omap_prcm_read, |
2776 | 827df9f3 | balrog | }; |
2777 | 827df9f3 | balrog | |
2778 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap_prcm_writefn[] = {
|
2779 | 827df9f3 | balrog | omap_badwidth_write32, |
2780 | 827df9f3 | balrog | omap_badwidth_write32, |
2781 | 827df9f3 | balrog | omap_prcm_write, |
2782 | 827df9f3 | balrog | }; |
2783 | 827df9f3 | balrog | |
2784 | 827df9f3 | balrog | static void omap_prcm_reset(struct omap_prcm_s *s) |
2785 | 827df9f3 | balrog | { |
2786 | 827df9f3 | balrog | s->sysconfig = 0;
|
2787 | 827df9f3 | balrog | s->irqst[0] = 0; |
2788 | 827df9f3 | balrog | s->irqst[1] = 0; |
2789 | 827df9f3 | balrog | s->irqst[2] = 0; |
2790 | 827df9f3 | balrog | s->irqen[0] = 0; |
2791 | 827df9f3 | balrog | s->irqen[1] = 0; |
2792 | 827df9f3 | balrog | s->irqen[2] = 0; |
2793 | 827df9f3 | balrog | s->voltctrl = 0x1040;
|
2794 | 827df9f3 | balrog | s->ev = 0x14;
|
2795 | 827df9f3 | balrog | s->evtime[0] = 0; |
2796 | 827df9f3 | balrog | s->evtime[1] = 0; |
2797 | 827df9f3 | balrog | s->clkctrl[0] = 0; |
2798 | 827df9f3 | balrog | s->clkctrl[1] = 0; |
2799 | 827df9f3 | balrog | s->clkctrl[2] = 0; |
2800 | 827df9f3 | balrog | s->clkctrl[3] = 0; |
2801 | 827df9f3 | balrog | s->clken[1] = 7; |
2802 | 827df9f3 | balrog | s->clken[3] = 7; |
2803 | 827df9f3 | balrog | s->clken[4] = 0; |
2804 | 827df9f3 | balrog | s->clken[5] = 0; |
2805 | 827df9f3 | balrog | s->clken[6] = 0; |
2806 | 827df9f3 | balrog | s->clken[7] = 0xc; |
2807 | 827df9f3 | balrog | s->clken[8] = 0x3e; |
2808 | 827df9f3 | balrog | s->clken[9] = 0x0d; |
2809 | 827df9f3 | balrog | s->clken[10] = 0; |
2810 | 827df9f3 | balrog | s->clken[11] = 0; |
2811 | 827df9f3 | balrog | s->clkidle[0] = 0; |
2812 | 827df9f3 | balrog | s->clkidle[2] = 7; |
2813 | 827df9f3 | balrog | s->clkidle[3] = 0; |
2814 | 827df9f3 | balrog | s->clkidle[4] = 0; |
2815 | 827df9f3 | balrog | s->clkidle[5] = 0x0c; |
2816 | 827df9f3 | balrog | s->clkidle[6] = 0; |
2817 | 827df9f3 | balrog | s->clksel[0] = 0x01; |
2818 | 827df9f3 | balrog | s->clksel[1] = 0x02100121; |
2819 | 827df9f3 | balrog | s->clksel[2] = 0x00000000; |
2820 | 827df9f3 | balrog | s->clksel[3] = 0x01; |
2821 | 827df9f3 | balrog | s->clksel[4] = 0; |
2822 | 827df9f3 | balrog | s->clksel[7] = 0x0121; |
2823 | 827df9f3 | balrog | s->wkup[0] = 0x15; |
2824 | 827df9f3 | balrog | s->wkup[1] = 0x13; |
2825 | 827df9f3 | balrog | s->wkup[2] = 0x13; |
2826 | 827df9f3 | balrog | s->wken[0] = 0x04667ff8; |
2827 | 827df9f3 | balrog | s->wken[1] = 0x00000005; |
2828 | 827df9f3 | balrog | s->wken[2] = 5; |
2829 | 827df9f3 | balrog | s->wkst[0] = 0; |
2830 | 827df9f3 | balrog | s->wkst[1] = 0; |
2831 | 827df9f3 | balrog | s->wkst[2] = 0; |
2832 | 827df9f3 | balrog | s->power[0] = 0x00c; |
2833 | 827df9f3 | balrog | s->power[1] = 4; |
2834 | 827df9f3 | balrog | s->power[2] = 0x0000c; |
2835 | 827df9f3 | balrog | s->power[3] = 0x14; |
2836 | 827df9f3 | balrog | s->rstctrl[0] = 1; |
2837 | 827df9f3 | balrog | s->rst[3] = 1; |
2838 | 827df9f3 | balrog | } |
2839 | 827df9f3 | balrog | |
2840 | 827df9f3 | balrog | static void omap_prcm_coldreset(struct omap_prcm_s *s) |
2841 | 827df9f3 | balrog | { |
2842 | 827df9f3 | balrog | s->setuptime[0] = 0; |
2843 | 827df9f3 | balrog | s->setuptime[1] = 0; |
2844 | 827df9f3 | balrog | memset(&s->scratch, 0, sizeof(s->scratch)); |
2845 | 827df9f3 | balrog | s->rst[0] = 0x01; |
2846 | 827df9f3 | balrog | s->rst[1] = 0x00; |
2847 | 827df9f3 | balrog | s->rst[2] = 0x01; |
2848 | 827df9f3 | balrog | s->clken[0] = 0; |
2849 | 827df9f3 | balrog | s->clken[2] = 0; |
2850 | 827df9f3 | balrog | s->clkidle[1] = 0; |
2851 | 827df9f3 | balrog | s->clksel[5] = 0; |
2852 | 827df9f3 | balrog | s->clksel[6] = 2; |
2853 | 827df9f3 | balrog | s->clksrc[0] = 0x43; |
2854 | 827df9f3 | balrog | s->clkout[0] = 0x0303; |
2855 | 827df9f3 | balrog | s->clkemul[0] = 0; |
2856 | 827df9f3 | balrog | s->clkpol[0] = 0x100; |
2857 | 827df9f3 | balrog | s->rsttime_wkup = 0x1002;
|
2858 | 827df9f3 | balrog | |
2859 | 827df9f3 | balrog | omap_prcm_reset(s); |
2860 | 827df9f3 | balrog | } |
2861 | 827df9f3 | balrog | |
2862 | 827df9f3 | balrog | struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta, |
2863 | 827df9f3 | balrog | qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int, |
2864 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu)
|
2865 | 827df9f3 | balrog | { |
2866 | 827df9f3 | balrog | int iomemtype;
|
2867 | 827df9f3 | balrog | struct omap_prcm_s *s = (struct omap_prcm_s *) |
2868 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_prcm_s)); |
2869 | 827df9f3 | balrog | |
2870 | 827df9f3 | balrog | s->irq[0] = mpu_int;
|
2871 | 827df9f3 | balrog | s->irq[1] = dsp_int;
|
2872 | 827df9f3 | balrog | s->irq[2] = iva_int;
|
2873 | 827df9f3 | balrog | s->mpu = mpu; |
2874 | 827df9f3 | balrog | omap_prcm_coldreset(s); |
2875 | 827df9f3 | balrog | |
2876 | c66fb5bc | balrog | iomemtype = l4_register_io_memory(0, omap_prcm_readfn,
|
2877 | 827df9f3 | balrog | omap_prcm_writefn, s); |
2878 | 827df9f3 | balrog | s->base = omap_l4_attach(ta, 0, iomemtype);
|
2879 | 827df9f3 | balrog | omap_l4_attach(ta, 1, iomemtype);
|
2880 | 827df9f3 | balrog | |
2881 | 827df9f3 | balrog | return s;
|
2882 | 827df9f3 | balrog | } |
2883 | 827df9f3 | balrog | |
2884 | 827df9f3 | balrog | /* System and Pinout control */
|
2885 | 827df9f3 | balrog | struct omap_sysctl_s {
|
2886 | 827df9f3 | balrog | target_phys_addr_t base; |
2887 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu;
|
2888 | 827df9f3 | balrog | |
2889 | 827df9f3 | balrog | uint32_t sysconfig; |
2890 | 827df9f3 | balrog | uint32_t devconfig; |
2891 | 827df9f3 | balrog | uint32_t psaconfig; |
2892 | 827df9f3 | balrog | uint32_t padconf[0x45];
|
2893 | 827df9f3 | balrog | uint8_t obs; |
2894 | 827df9f3 | balrog | uint32_t msuspendmux[5];
|
2895 | 827df9f3 | balrog | }; |
2896 | 827df9f3 | balrog | |
2897 | 827df9f3 | balrog | static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr) |
2898 | 827df9f3 | balrog | { |
2899 | 827df9f3 | balrog | struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; |
2900 | 827df9f3 | balrog | int offset = addr - s->base;
|
2901 | 827df9f3 | balrog | |
2902 | 827df9f3 | balrog | switch (offset) {
|
2903 | 827df9f3 | balrog | case 0x000: /* CONTROL_REVISION */ |
2904 | 827df9f3 | balrog | return 0x20; |
2905 | 827df9f3 | balrog | |
2906 | 827df9f3 | balrog | case 0x010: /* CONTROL_SYSCONFIG */ |
2907 | 827df9f3 | balrog | return s->sysconfig;
|
2908 | 827df9f3 | balrog | |
2909 | 827df9f3 | balrog | case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ |
2910 | 827df9f3 | balrog | return s->padconf[(offset - 0x30) >> 2]; |
2911 | 827df9f3 | balrog | |
2912 | 827df9f3 | balrog | case 0x270: /* CONTROL_DEBOBS */ |
2913 | 827df9f3 | balrog | return s->obs;
|
2914 | 827df9f3 | balrog | |
2915 | 827df9f3 | balrog | case 0x274: /* CONTROL_DEVCONF */ |
2916 | 827df9f3 | balrog | return s->devconfig;
|
2917 | 827df9f3 | balrog | |
2918 | 827df9f3 | balrog | case 0x28c: /* CONTROL_EMU_SUPPORT */ |
2919 | 827df9f3 | balrog | return 0; |
2920 | 827df9f3 | balrog | |
2921 | 827df9f3 | balrog | case 0x290: /* CONTROL_MSUSPENDMUX_0 */ |
2922 | 827df9f3 | balrog | return s->msuspendmux[0]; |
2923 | 827df9f3 | balrog | case 0x294: /* CONTROL_MSUSPENDMUX_1 */ |
2924 | 827df9f3 | balrog | return s->msuspendmux[1]; |
2925 | 827df9f3 | balrog | case 0x298: /* CONTROL_MSUSPENDMUX_2 */ |
2926 | 827df9f3 | balrog | return s->msuspendmux[2]; |
2927 | 827df9f3 | balrog | case 0x29c: /* CONTROL_MSUSPENDMUX_3 */ |
2928 | 827df9f3 | balrog | return s->msuspendmux[3]; |
2929 | 827df9f3 | balrog | case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */ |
2930 | 827df9f3 | balrog | return s->msuspendmux[4]; |
2931 | 827df9f3 | balrog | case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */ |
2932 | 827df9f3 | balrog | return 0; |
2933 | 827df9f3 | balrog | |
2934 | 827df9f3 | balrog | case 0x2b8: /* CONTROL_PSA_CTRL */ |
2935 | 827df9f3 | balrog | return s->psaconfig;
|
2936 | 827df9f3 | balrog | case 0x2bc: /* CONTROL_PSA_CMD */ |
2937 | 827df9f3 | balrog | case 0x2c0: /* CONTROL_PSA_VALUE */ |
2938 | 827df9f3 | balrog | return 0; |
2939 | 827df9f3 | balrog | |
2940 | 827df9f3 | balrog | case 0x2b0: /* CONTROL_SEC_CTRL */ |
2941 | 827df9f3 | balrog | return 0x800000f1; |
2942 | 827df9f3 | balrog | case 0x2d0: /* CONTROL_SEC_EMU */ |
2943 | 827df9f3 | balrog | return 0x80000015; |
2944 | 827df9f3 | balrog | case 0x2d4: /* CONTROL_SEC_TAP */ |
2945 | 827df9f3 | balrog | return 0x8000007f; |
2946 | 827df9f3 | balrog | case 0x2b4: /* CONTROL_SEC_TEST */ |
2947 | 827df9f3 | balrog | case 0x2f0: /* CONTROL_SEC_STATUS */ |
2948 | 827df9f3 | balrog | case 0x2f4: /* CONTROL_SEC_ERR_STATUS */ |
2949 | 827df9f3 | balrog | /* Secure mode is not present on general-pusrpose device. Outside
|
2950 | 827df9f3 | balrog | * secure mode these values cannot be read or written. */
|
2951 | 827df9f3 | balrog | return 0; |
2952 | 827df9f3 | balrog | |
2953 | 827df9f3 | balrog | case 0x2d8: /* CONTROL_OCM_RAM_PERM */ |
2954 | 827df9f3 | balrog | return 0xff; |
2955 | 827df9f3 | balrog | case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */ |
2956 | 827df9f3 | balrog | case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */ |
2957 | 827df9f3 | balrog | case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */ |
2958 | 827df9f3 | balrog | /* No secure mode so no Extended Secure RAM present. */
|
2959 | 827df9f3 | balrog | return 0; |
2960 | 827df9f3 | balrog | |
2961 | 827df9f3 | balrog | case 0x2f8: /* CONTROL_STATUS */ |
2962 | 827df9f3 | balrog | /* Device Type => General-purpose */
|
2963 | 827df9f3 | balrog | return 0x0300; |
2964 | 827df9f3 | balrog | case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */ |
2965 | 827df9f3 | balrog | |
2966 | 827df9f3 | balrog | case 0x300: /* CONTROL_RPUB_KEY_H_0 */ |
2967 | 827df9f3 | balrog | case 0x304: /* CONTROL_RPUB_KEY_H_1 */ |
2968 | 827df9f3 | balrog | case 0x308: /* CONTROL_RPUB_KEY_H_2 */ |
2969 | 827df9f3 | balrog | case 0x30c: /* CONTROL_RPUB_KEY_H_3 */ |
2970 | 827df9f3 | balrog | return 0xdecafbad; |
2971 | 827df9f3 | balrog | |
2972 | 827df9f3 | balrog | case 0x310: /* CONTROL_RAND_KEY_0 */ |
2973 | 827df9f3 | balrog | case 0x314: /* CONTROL_RAND_KEY_1 */ |
2974 | 827df9f3 | balrog | case 0x318: /* CONTROL_RAND_KEY_2 */ |
2975 | 827df9f3 | balrog | case 0x31c: /* CONTROL_RAND_KEY_3 */ |
2976 | 827df9f3 | balrog | case 0x320: /* CONTROL_CUST_KEY_0 */ |
2977 | 827df9f3 | balrog | case 0x324: /* CONTROL_CUST_KEY_1 */ |
2978 | 827df9f3 | balrog | case 0x330: /* CONTROL_TEST_KEY_0 */ |
2979 | 827df9f3 | balrog | case 0x334: /* CONTROL_TEST_KEY_1 */ |
2980 | 827df9f3 | balrog | case 0x338: /* CONTROL_TEST_KEY_2 */ |
2981 | 827df9f3 | balrog | case 0x33c: /* CONTROL_TEST_KEY_3 */ |
2982 | 827df9f3 | balrog | case 0x340: /* CONTROL_TEST_KEY_4 */ |
2983 | 827df9f3 | balrog | case 0x344: /* CONTROL_TEST_KEY_5 */ |
2984 | 827df9f3 | balrog | case 0x348: /* CONTROL_TEST_KEY_6 */ |
2985 | 827df9f3 | balrog | case 0x34c: /* CONTROL_TEST_KEY_7 */ |
2986 | 827df9f3 | balrog | case 0x350: /* CONTROL_TEST_KEY_8 */ |
2987 | 827df9f3 | balrog | case 0x354: /* CONTROL_TEST_KEY_9 */ |
2988 | 827df9f3 | balrog | /* Can only be accessed in secure mode and when C_FieldAccEnable
|
2989 | 827df9f3 | balrog | * bit is set in CONTROL_SEC_CTRL.
|
2990 | 827df9f3 | balrog | * TODO: otherwise an interconnect access error is generated. */
|
2991 | 827df9f3 | balrog | return 0; |
2992 | 827df9f3 | balrog | } |
2993 | 827df9f3 | balrog | |
2994 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
2995 | 827df9f3 | balrog | return 0; |
2996 | 827df9f3 | balrog | } |
2997 | 827df9f3 | balrog | |
2998 | 827df9f3 | balrog | static void omap_sysctl_write(void *opaque, target_phys_addr_t addr, |
2999 | 827df9f3 | balrog | uint32_t value) |
3000 | 827df9f3 | balrog | { |
3001 | 827df9f3 | balrog | struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; |
3002 | 827df9f3 | balrog | int offset = addr - s->base;
|
3003 | 827df9f3 | balrog | |
3004 | 827df9f3 | balrog | switch (offset) {
|
3005 | 827df9f3 | balrog | case 0x000: /* CONTROL_REVISION */ |
3006 | 827df9f3 | balrog | case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */ |
3007 | 827df9f3 | balrog | case 0x2c0: /* CONTROL_PSA_VALUE */ |
3008 | 827df9f3 | balrog | case 0x2f8: /* CONTROL_STATUS */ |
3009 | 827df9f3 | balrog | case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */ |
3010 | 827df9f3 | balrog | case 0x300: /* CONTROL_RPUB_KEY_H_0 */ |
3011 | 827df9f3 | balrog | case 0x304: /* CONTROL_RPUB_KEY_H_1 */ |
3012 | 827df9f3 | balrog | case 0x308: /* CONTROL_RPUB_KEY_H_2 */ |
3013 | 827df9f3 | balrog | case 0x30c: /* CONTROL_RPUB_KEY_H_3 */ |
3014 | 827df9f3 | balrog | case 0x310: /* CONTROL_RAND_KEY_0 */ |
3015 | 827df9f3 | balrog | case 0x314: /* CONTROL_RAND_KEY_1 */ |
3016 | 827df9f3 | balrog | case 0x318: /* CONTROL_RAND_KEY_2 */ |
3017 | 827df9f3 | balrog | case 0x31c: /* CONTROL_RAND_KEY_3 */ |
3018 | 827df9f3 | balrog | case 0x320: /* CONTROL_CUST_KEY_0 */ |
3019 | 827df9f3 | balrog | case 0x324: /* CONTROL_CUST_KEY_1 */ |
3020 | 827df9f3 | balrog | case 0x330: /* CONTROL_TEST_KEY_0 */ |
3021 | 827df9f3 | balrog | case 0x334: /* CONTROL_TEST_KEY_1 */ |
3022 | 827df9f3 | balrog | case 0x338: /* CONTROL_TEST_KEY_2 */ |
3023 | 827df9f3 | balrog | case 0x33c: /* CONTROL_TEST_KEY_3 */ |
3024 | 827df9f3 | balrog | case 0x340: /* CONTROL_TEST_KEY_4 */ |
3025 | 827df9f3 | balrog | case 0x344: /* CONTROL_TEST_KEY_5 */ |
3026 | 827df9f3 | balrog | case 0x348: /* CONTROL_TEST_KEY_6 */ |
3027 | 827df9f3 | balrog | case 0x34c: /* CONTROL_TEST_KEY_7 */ |
3028 | 827df9f3 | balrog | case 0x350: /* CONTROL_TEST_KEY_8 */ |
3029 | 827df9f3 | balrog | case 0x354: /* CONTROL_TEST_KEY_9 */ |
3030 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
3031 | 827df9f3 | balrog | return;
|
3032 | 827df9f3 | balrog | |
3033 | 827df9f3 | balrog | case 0x010: /* CONTROL_SYSCONFIG */ |
3034 | 827df9f3 | balrog | s->sysconfig = value & 0x1e;
|
3035 | 827df9f3 | balrog | break;
|
3036 | 827df9f3 | balrog | |
3037 | 827df9f3 | balrog | case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ |
3038 | 827df9f3 | balrog | /* XXX: should check constant bits */
|
3039 | 827df9f3 | balrog | s->padconf[(offset - 0x30) >> 2] = value & 0x1f1f1f1f; |
3040 | 827df9f3 | balrog | break;
|
3041 | 827df9f3 | balrog | |
3042 | 827df9f3 | balrog | case 0x270: /* CONTROL_DEBOBS */ |
3043 | 827df9f3 | balrog | s->obs = value & 0xff;
|
3044 | 827df9f3 | balrog | break;
|
3045 | 827df9f3 | balrog | |
3046 | 827df9f3 | balrog | case 0x274: /* CONTROL_DEVCONF */ |
3047 | 827df9f3 | balrog | s->devconfig = value & 0xffffc7ff;
|
3048 | 827df9f3 | balrog | break;
|
3049 | 827df9f3 | balrog | |
3050 | 827df9f3 | balrog | case 0x28c: /* CONTROL_EMU_SUPPORT */ |
3051 | 827df9f3 | balrog | break;
|
3052 | 827df9f3 | balrog | |
3053 | 827df9f3 | balrog | case 0x290: /* CONTROL_MSUSPENDMUX_0 */ |
3054 | 827df9f3 | balrog | s->msuspendmux[0] = value & 0x3fffffff; |
3055 | 827df9f3 | balrog | break;
|
3056 | 827df9f3 | balrog | case 0x294: /* CONTROL_MSUSPENDMUX_1 */ |
3057 | 827df9f3 | balrog | s->msuspendmux[1] = value & 0x3fffffff; |
3058 | 827df9f3 | balrog | break;
|
3059 | 827df9f3 | balrog | case 0x298: /* CONTROL_MSUSPENDMUX_2 */ |
3060 | 827df9f3 | balrog | s->msuspendmux[2] = value & 0x3fffffff; |
3061 | 827df9f3 | balrog | break;
|
3062 | 827df9f3 | balrog | case 0x29c: /* CONTROL_MSUSPENDMUX_3 */ |
3063 | 827df9f3 | balrog | s->msuspendmux[3] = value & 0x3fffffff; |
3064 | 827df9f3 | balrog | break;
|
3065 | 827df9f3 | balrog | case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */ |
3066 | 827df9f3 | balrog | s->msuspendmux[4] = value & 0x3fffffff; |
3067 | 827df9f3 | balrog | break;
|
3068 | 827df9f3 | balrog | |
3069 | 827df9f3 | balrog | case 0x2b8: /* CONTROL_PSA_CTRL */ |
3070 | 827df9f3 | balrog | s->psaconfig = value & 0x1c;
|
3071 | 827df9f3 | balrog | s->psaconfig |= (value & 0x20) ? 2 : 1; |
3072 | 827df9f3 | balrog | break;
|
3073 | 827df9f3 | balrog | case 0x2bc: /* CONTROL_PSA_CMD */ |
3074 | 827df9f3 | balrog | break;
|
3075 | 827df9f3 | balrog | |
3076 | 827df9f3 | balrog | case 0x2b0: /* CONTROL_SEC_CTRL */ |
3077 | 827df9f3 | balrog | case 0x2b4: /* CONTROL_SEC_TEST */ |
3078 | 827df9f3 | balrog | case 0x2d0: /* CONTROL_SEC_EMU */ |
3079 | 827df9f3 | balrog | case 0x2d4: /* CONTROL_SEC_TAP */ |
3080 | 827df9f3 | balrog | case 0x2d8: /* CONTROL_OCM_RAM_PERM */ |
3081 | 827df9f3 | balrog | case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */ |
3082 | 827df9f3 | balrog | case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */ |
3083 | 827df9f3 | balrog | case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */ |
3084 | 827df9f3 | balrog | case 0x2f0: /* CONTROL_SEC_STATUS */ |
3085 | 827df9f3 | balrog | case 0x2f4: /* CONTROL_SEC_ERR_STATUS */ |
3086 | 827df9f3 | balrog | break;
|
3087 | 827df9f3 | balrog | |
3088 | 827df9f3 | balrog | default:
|
3089 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
3090 | 827df9f3 | balrog | return;
|
3091 | 827df9f3 | balrog | } |
3092 | 827df9f3 | balrog | } |
3093 | 827df9f3 | balrog | |
3094 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap_sysctl_readfn[] = {
|
3095 | 827df9f3 | balrog | omap_badwidth_read32, /* TODO */
|
3096 | 827df9f3 | balrog | omap_badwidth_read32, /* TODO */
|
3097 | 827df9f3 | balrog | omap_sysctl_read, |
3098 | 827df9f3 | balrog | }; |
3099 | 827df9f3 | balrog | |
3100 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap_sysctl_writefn[] = {
|
3101 | 827df9f3 | balrog | omap_badwidth_write32, /* TODO */
|
3102 | 827df9f3 | balrog | omap_badwidth_write32, /* TODO */
|
3103 | 827df9f3 | balrog | omap_sysctl_write, |
3104 | 827df9f3 | balrog | }; |
3105 | 827df9f3 | balrog | |
3106 | 827df9f3 | balrog | static void omap_sysctl_reset(struct omap_sysctl_s *s) |
3107 | 827df9f3 | balrog | { |
3108 | 827df9f3 | balrog | /* (power-on reset) */
|
3109 | 827df9f3 | balrog | s->sysconfig = 0;
|
3110 | 827df9f3 | balrog | s->obs = 0;
|
3111 | 827df9f3 | balrog | s->devconfig = 0x0c000000;
|
3112 | 827df9f3 | balrog | s->msuspendmux[0] = 0x00000000; |
3113 | 827df9f3 | balrog | s->msuspendmux[1] = 0x00000000; |
3114 | 827df9f3 | balrog | s->msuspendmux[2] = 0x00000000; |
3115 | 827df9f3 | balrog | s->msuspendmux[3] = 0x00000000; |
3116 | 827df9f3 | balrog | s->msuspendmux[4] = 0x00000000; |
3117 | 827df9f3 | balrog | s->psaconfig = 1;
|
3118 | 827df9f3 | balrog | |
3119 | 827df9f3 | balrog | s->padconf[0x00] = 0x000f0f0f; |
3120 | 827df9f3 | balrog | s->padconf[0x01] = 0x00000000; |
3121 | 827df9f3 | balrog | s->padconf[0x02] = 0x00000000; |
3122 | 827df9f3 | balrog | s->padconf[0x03] = 0x00000000; |
3123 | 827df9f3 | balrog | s->padconf[0x04] = 0x00000000; |
3124 | 827df9f3 | balrog | s->padconf[0x05] = 0x00000000; |
3125 | 827df9f3 | balrog | s->padconf[0x06] = 0x00000000; |
3126 | 827df9f3 | balrog | s->padconf[0x07] = 0x00000000; |
3127 | 827df9f3 | balrog | s->padconf[0x08] = 0x08080800; |
3128 | 827df9f3 | balrog | s->padconf[0x09] = 0x08080808; |
3129 | 827df9f3 | balrog | s->padconf[0x0a] = 0x08080808; |
3130 | 827df9f3 | balrog | s->padconf[0x0b] = 0x08080808; |
3131 | 827df9f3 | balrog | s->padconf[0x0c] = 0x08080808; |
3132 | 827df9f3 | balrog | s->padconf[0x0d] = 0x08080800; |
3133 | 827df9f3 | balrog | s->padconf[0x0e] = 0x08080808; |
3134 | 827df9f3 | balrog | s->padconf[0x0f] = 0x08080808; |
3135 | 827df9f3 | balrog | s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */ |
3136 | 827df9f3 | balrog | s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */ |
3137 | 827df9f3 | balrog | s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */ |
3138 | 827df9f3 | balrog | s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */ |
3139 | 827df9f3 | balrog | s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */ |
3140 | 827df9f3 | balrog | s->padconf[0x15] = 0x18181818; |
3141 | 827df9f3 | balrog | s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */ |
3142 | 827df9f3 | balrog | s->padconf[0x17] = 0x1f001f00; |
3143 | 827df9f3 | balrog | s->padconf[0x18] = 0x1f1f1f1f; |
3144 | 827df9f3 | balrog | s->padconf[0x19] = 0x00000000; |
3145 | 827df9f3 | balrog | s->padconf[0x1a] = 0x1f180000; |
3146 | 827df9f3 | balrog | s->padconf[0x1b] = 0x00001f1f; |
3147 | 827df9f3 | balrog | s->padconf[0x1c] = 0x1f001f00; |
3148 | 827df9f3 | balrog | s->padconf[0x1d] = 0x00000000; |
3149 | 827df9f3 | balrog | s->padconf[0x1e] = 0x00000000; |
3150 | 827df9f3 | balrog | s->padconf[0x1f] = 0x08000000; |
3151 | 827df9f3 | balrog | s->padconf[0x20] = 0x08080808; |
3152 | 827df9f3 | balrog | s->padconf[0x21] = 0x08080808; |
3153 | 827df9f3 | balrog | s->padconf[0x22] = 0x0f080808; |
3154 | 827df9f3 | balrog | s->padconf[0x23] = 0x0f0f0f0f; |
3155 | 827df9f3 | balrog | s->padconf[0x24] = 0x000f0f0f; |
3156 | 827df9f3 | balrog | s->padconf[0x25] = 0x1f1f1f0f; |
3157 | 827df9f3 | balrog | s->padconf[0x26] = 0x080f0f1f; |
3158 | 827df9f3 | balrog | s->padconf[0x27] = 0x070f1808; |
3159 | 827df9f3 | balrog | s->padconf[0x28] = 0x0f070707; |
3160 | 827df9f3 | balrog | s->padconf[0x29] = 0x000f0f1f; |
3161 | 827df9f3 | balrog | s->padconf[0x2a] = 0x0f0f0f1f; |
3162 | 827df9f3 | balrog | s->padconf[0x2b] = 0x08000000; |
3163 | 827df9f3 | balrog | s->padconf[0x2c] = 0x0000001f; |
3164 | 827df9f3 | balrog | s->padconf[0x2d] = 0x0f0f1f00; |
3165 | 827df9f3 | balrog | s->padconf[0x2e] = 0x1f1f0f0f; |
3166 | 827df9f3 | balrog | s->padconf[0x2f] = 0x0f1f1f1f; |
3167 | 827df9f3 | balrog | s->padconf[0x30] = 0x0f0f0f0f; |
3168 | 827df9f3 | balrog | s->padconf[0x31] = 0x0f1f0f1f; |
3169 | 827df9f3 | balrog | s->padconf[0x32] = 0x0f0f0f0f; |
3170 | 827df9f3 | balrog | s->padconf[0x33] = 0x0f1f0f1f; |
3171 | 827df9f3 | balrog | s->padconf[0x34] = 0x1f1f0f0f; |
3172 | 827df9f3 | balrog | s->padconf[0x35] = 0x0f0f1f1f; |
3173 | 827df9f3 | balrog | s->padconf[0x36] = 0x0f0f1f0f; |
3174 | 827df9f3 | balrog | s->padconf[0x37] = 0x0f0f0f0f; |
3175 | 827df9f3 | balrog | s->padconf[0x38] = 0x1f18180f; |
3176 | 827df9f3 | balrog | s->padconf[0x39] = 0x1f1f1f1f; |
3177 | 827df9f3 | balrog | s->padconf[0x3a] = 0x00001f1f; |
3178 | 827df9f3 | balrog | s->padconf[0x3b] = 0x00000000; |
3179 | 827df9f3 | balrog | s->padconf[0x3c] = 0x00000000; |
3180 | 827df9f3 | balrog | s->padconf[0x3d] = 0x0f0f0f0f; |
3181 | 827df9f3 | balrog | s->padconf[0x3e] = 0x18000f0f; |
3182 | 827df9f3 | balrog | s->padconf[0x3f] = 0x00070000; |
3183 | 827df9f3 | balrog | s->padconf[0x40] = 0x00000707; |
3184 | 827df9f3 | balrog | s->padconf[0x41] = 0x0f1f0700; |
3185 | 827df9f3 | balrog | s->padconf[0x42] = 0x1f1f070f; |
3186 | 827df9f3 | balrog | s->padconf[0x43] = 0x0008081f; |
3187 | 827df9f3 | balrog | s->padconf[0x44] = 0x00000800; |
3188 | 827df9f3 | balrog | } |
3189 | 827df9f3 | balrog | |
3190 | 827df9f3 | balrog | struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta, |
3191 | 827df9f3 | balrog | omap_clk iclk, struct omap_mpu_state_s *mpu)
|
3192 | 827df9f3 | balrog | { |
3193 | 827df9f3 | balrog | int iomemtype;
|
3194 | 827df9f3 | balrog | struct omap_sysctl_s *s = (struct omap_sysctl_s *) |
3195 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_sysctl_s)); |
3196 | 827df9f3 | balrog | |
3197 | 827df9f3 | balrog | s->mpu = mpu; |
3198 | 827df9f3 | balrog | omap_sysctl_reset(s); |
3199 | 827df9f3 | balrog | |
3200 | c66fb5bc | balrog | iomemtype = l4_register_io_memory(0, omap_sysctl_readfn,
|
3201 | 827df9f3 | balrog | omap_sysctl_writefn, s); |
3202 | 827df9f3 | balrog | s->base = omap_l4_attach(ta, 0, iomemtype);
|
3203 | 827df9f3 | balrog | omap_l4_attach(ta, 0, iomemtype);
|
3204 | 827df9f3 | balrog | |
3205 | 827df9f3 | balrog | return s;
|
3206 | 827df9f3 | balrog | } |
3207 | 827df9f3 | balrog | |
3208 | 827df9f3 | balrog | /* SDRAM Controller Subsystem */
|
3209 | 827df9f3 | balrog | struct omap_sdrc_s {
|
3210 | 827df9f3 | balrog | target_phys_addr_t base; |
3211 | 827df9f3 | balrog | |
3212 | 827df9f3 | balrog | uint8_t config; |
3213 | 827df9f3 | balrog | }; |
3214 | 827df9f3 | balrog | |
3215 | 827df9f3 | balrog | static void omap_sdrc_reset(struct omap_sdrc_s *s) |
3216 | 827df9f3 | balrog | { |
3217 | 827df9f3 | balrog | s->config = 0x10;
|
3218 | 827df9f3 | balrog | } |
3219 | 827df9f3 | balrog | |
3220 | 827df9f3 | balrog | static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr) |
3221 | 827df9f3 | balrog | { |
3222 | 827df9f3 | balrog | struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque; |
3223 | 827df9f3 | balrog | int offset = addr - s->base;
|
3224 | 827df9f3 | balrog | |
3225 | 827df9f3 | balrog | switch (offset) {
|
3226 | 827df9f3 | balrog | case 0x00: /* SDRC_REVISION */ |
3227 | 827df9f3 | balrog | return 0x20; |
3228 | 827df9f3 | balrog | |
3229 | 827df9f3 | balrog | case 0x10: /* SDRC_SYSCONFIG */ |
3230 | 827df9f3 | balrog | return s->config;
|
3231 | 827df9f3 | balrog | |
3232 | 827df9f3 | balrog | case 0x14: /* SDRC_SYSSTATUS */ |
3233 | 827df9f3 | balrog | return 1; /* RESETDONE */ |
3234 | 827df9f3 | balrog | |
3235 | 827df9f3 | balrog | case 0x40: /* SDRC_CS_CFG */ |
3236 | 827df9f3 | balrog | case 0x44: /* SDRC_SHARING */ |
3237 | 827df9f3 | balrog | case 0x48: /* SDRC_ERR_ADDR */ |
3238 | 827df9f3 | balrog | case 0x4c: /* SDRC_ERR_TYPE */ |
3239 | 827df9f3 | balrog | case 0x60: /* SDRC_DLLA_SCTRL */ |
3240 | 827df9f3 | balrog | case 0x64: /* SDRC_DLLA_STATUS */ |
3241 | 827df9f3 | balrog | case 0x68: /* SDRC_DLLB_CTRL */ |
3242 | 827df9f3 | balrog | case 0x6c: /* SDRC_DLLB_STATUS */ |
3243 | 827df9f3 | balrog | case 0x70: /* SDRC_POWER */ |
3244 | 827df9f3 | balrog | case 0x80: /* SDRC_MCFG_0 */ |
3245 | 827df9f3 | balrog | case 0x84: /* SDRC_MR_0 */ |
3246 | 827df9f3 | balrog | case 0x88: /* SDRC_EMR1_0 */ |
3247 | 827df9f3 | balrog | case 0x8c: /* SDRC_EMR2_0 */ |
3248 | 827df9f3 | balrog | case 0x90: /* SDRC_EMR3_0 */ |
3249 | 827df9f3 | balrog | case 0x94: /* SDRC_DCDL1_CTRL */ |
3250 | 827df9f3 | balrog | case 0x98: /* SDRC_DCDL2_CTRL */ |
3251 | 827df9f3 | balrog | case 0x9c: /* SDRC_ACTIM_CTRLA_0 */ |
3252 | 827df9f3 | balrog | case 0xa0: /* SDRC_ACTIM_CTRLB_0 */ |
3253 | 827df9f3 | balrog | case 0xa4: /* SDRC_RFR_CTRL_0 */ |
3254 | 827df9f3 | balrog | case 0xa8: /* SDRC_MANUAL_0 */ |
3255 | 827df9f3 | balrog | case 0xb0: /* SDRC_MCFG_1 */ |
3256 | 827df9f3 | balrog | case 0xb4: /* SDRC_MR_1 */ |
3257 | 827df9f3 | balrog | case 0xb8: /* SDRC_EMR1_1 */ |
3258 | 827df9f3 | balrog | case 0xbc: /* SDRC_EMR2_1 */ |
3259 | 827df9f3 | balrog | case 0xc0: /* SDRC_EMR3_1 */ |
3260 | 827df9f3 | balrog | case 0xc4: /* SDRC_ACTIM_CTRLA_1 */ |
3261 | 827df9f3 | balrog | case 0xc8: /* SDRC_ACTIM_CTRLB_1 */ |
3262 | 827df9f3 | balrog | case 0xd4: /* SDRC_RFR_CTRL_1 */ |
3263 | 827df9f3 | balrog | case 0xd8: /* SDRC_MANUAL_1 */ |
3264 | 827df9f3 | balrog | return 0x00; |
3265 | 827df9f3 | balrog | } |
3266 | 827df9f3 | balrog | |
3267 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
3268 | 827df9f3 | balrog | return 0; |
3269 | 827df9f3 | balrog | } |
3270 | 827df9f3 | balrog | |
3271 | 827df9f3 | balrog | static void omap_sdrc_write(void *opaque, target_phys_addr_t addr, |
3272 | 827df9f3 | balrog | uint32_t value) |
3273 | 827df9f3 | balrog | { |
3274 | 827df9f3 | balrog | struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque; |
3275 | 827df9f3 | balrog | int offset = addr - s->base;
|
3276 | 827df9f3 | balrog | |
3277 | 827df9f3 | balrog | switch (offset) {
|
3278 | 827df9f3 | balrog | case 0x00: /* SDRC_REVISION */ |
3279 | 827df9f3 | balrog | case 0x14: /* SDRC_SYSSTATUS */ |
3280 | 827df9f3 | balrog | case 0x48: /* SDRC_ERR_ADDR */ |
3281 | 827df9f3 | balrog | case 0x64: /* SDRC_DLLA_STATUS */ |
3282 | 827df9f3 | balrog | case 0x6c: /* SDRC_DLLB_STATUS */ |
3283 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
3284 | 827df9f3 | balrog | return;
|
3285 | 827df9f3 | balrog | |
3286 | 827df9f3 | balrog | case 0x10: /* SDRC_SYSCONFIG */ |
3287 | 827df9f3 | balrog | if ((value >> 3) != 0x2) |
3288 | 827df9f3 | balrog | fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
|
3289 | 827df9f3 | balrog | __FUNCTION__, value >> 3);
|
3290 | 827df9f3 | balrog | if (value & 2) |
3291 | 827df9f3 | balrog | omap_sdrc_reset(s); |
3292 | 827df9f3 | balrog | s->config = value & 0x18;
|
3293 | 827df9f3 | balrog | break;
|
3294 | 827df9f3 | balrog | |
3295 | 827df9f3 | balrog | case 0x40: /* SDRC_CS_CFG */ |
3296 | 827df9f3 | balrog | case 0x44: /* SDRC_SHARING */ |
3297 | 827df9f3 | balrog | case 0x4c: /* SDRC_ERR_TYPE */ |
3298 | 827df9f3 | balrog | case 0x60: /* SDRC_DLLA_SCTRL */ |
3299 | 827df9f3 | balrog | case 0x68: /* SDRC_DLLB_CTRL */ |
3300 | 827df9f3 | balrog | case 0x70: /* SDRC_POWER */ |
3301 | 827df9f3 | balrog | case 0x80: /* SDRC_MCFG_0 */ |
3302 | 827df9f3 | balrog | case 0x84: /* SDRC_MR_0 */ |
3303 | 827df9f3 | balrog | case 0x88: /* SDRC_EMR1_0 */ |
3304 | 827df9f3 | balrog | case 0x8c: /* SDRC_EMR2_0 */ |
3305 | 827df9f3 | balrog | case 0x90: /* SDRC_EMR3_0 */ |
3306 | 827df9f3 | balrog | case 0x94: /* SDRC_DCDL1_CTRL */ |
3307 | 827df9f3 | balrog | case 0x98: /* SDRC_DCDL2_CTRL */ |
3308 | 827df9f3 | balrog | case 0x9c: /* SDRC_ACTIM_CTRLA_0 */ |
3309 | 827df9f3 | balrog | case 0xa0: /* SDRC_ACTIM_CTRLB_0 */ |
3310 | 827df9f3 | balrog | case 0xa4: /* SDRC_RFR_CTRL_0 */ |
3311 | 827df9f3 | balrog | case 0xa8: /* SDRC_MANUAL_0 */ |
3312 | 827df9f3 | balrog | case 0xb0: /* SDRC_MCFG_1 */ |
3313 | 827df9f3 | balrog | case 0xb4: /* SDRC_MR_1 */ |
3314 | 827df9f3 | balrog | case 0xb8: /* SDRC_EMR1_1 */ |
3315 | 827df9f3 | balrog | case 0xbc: /* SDRC_EMR2_1 */ |
3316 | 827df9f3 | balrog | case 0xc0: /* SDRC_EMR3_1 */ |
3317 | 827df9f3 | balrog | case 0xc4: /* SDRC_ACTIM_CTRLA_1 */ |
3318 | 827df9f3 | balrog | case 0xc8: /* SDRC_ACTIM_CTRLB_1 */ |
3319 | 827df9f3 | balrog | case 0xd4: /* SDRC_RFR_CTRL_1 */ |
3320 | 827df9f3 | balrog | case 0xd8: /* SDRC_MANUAL_1 */ |
3321 | 827df9f3 | balrog | break;
|
3322 | 827df9f3 | balrog | |
3323 | 827df9f3 | balrog | default:
|
3324 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
3325 | 827df9f3 | balrog | return;
|
3326 | 827df9f3 | balrog | } |
3327 | 827df9f3 | balrog | } |
3328 | 827df9f3 | balrog | |
3329 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap_sdrc_readfn[] = {
|
3330 | 827df9f3 | balrog | omap_badwidth_read32, |
3331 | 827df9f3 | balrog | omap_badwidth_read32, |
3332 | 827df9f3 | balrog | omap_sdrc_read, |
3333 | 827df9f3 | balrog | }; |
3334 | 827df9f3 | balrog | |
3335 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap_sdrc_writefn[] = {
|
3336 | 827df9f3 | balrog | omap_badwidth_write32, |
3337 | 827df9f3 | balrog | omap_badwidth_write32, |
3338 | 827df9f3 | balrog | omap_sdrc_write, |
3339 | 827df9f3 | balrog | }; |
3340 | 827df9f3 | balrog | |
3341 | 827df9f3 | balrog | struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base)
|
3342 | 827df9f3 | balrog | { |
3343 | 827df9f3 | balrog | int iomemtype;
|
3344 | 827df9f3 | balrog | struct omap_sdrc_s *s = (struct omap_sdrc_s *) |
3345 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_sdrc_s)); |
3346 | 827df9f3 | balrog | |
3347 | 827df9f3 | balrog | s->base = base; |
3348 | 827df9f3 | balrog | omap_sdrc_reset(s); |
3349 | 827df9f3 | balrog | |
3350 | 827df9f3 | balrog | iomemtype = cpu_register_io_memory(0, omap_sdrc_readfn,
|
3351 | 827df9f3 | balrog | omap_sdrc_writefn, s); |
3352 | 827df9f3 | balrog | cpu_register_physical_memory(s->base, 0x1000, iomemtype);
|
3353 | 827df9f3 | balrog | |
3354 | 827df9f3 | balrog | return s;
|
3355 | 827df9f3 | balrog | } |
3356 | 827df9f3 | balrog | |
3357 | 827df9f3 | balrog | /* General-Purpose Memory Controller */
|
3358 | 827df9f3 | balrog | struct omap_gpmc_s {
|
3359 | 827df9f3 | balrog | target_phys_addr_t base; |
3360 | 827df9f3 | balrog | qemu_irq irq; |
3361 | 827df9f3 | balrog | |
3362 | 827df9f3 | balrog | uint8_t sysconfig; |
3363 | 827df9f3 | balrog | uint16_t irqst; |
3364 | 827df9f3 | balrog | uint16_t irqen; |
3365 | 827df9f3 | balrog | uint16_t timeout; |
3366 | 827df9f3 | balrog | uint16_t config; |
3367 | 827df9f3 | balrog | uint32_t prefconfig[2];
|
3368 | 827df9f3 | balrog | int prefcontrol;
|
3369 | 827df9f3 | balrog | int preffifo;
|
3370 | 827df9f3 | balrog | int prefcount;
|
3371 | 827df9f3 | balrog | struct omap_gpmc_cs_file_s {
|
3372 | 827df9f3 | balrog | uint32_t config[7];
|
3373 | 827df9f3 | balrog | target_phys_addr_t base; |
3374 | 827df9f3 | balrog | size_t size; |
3375 | 827df9f3 | balrog | int iomemtype;
|
3376 | 827df9f3 | balrog | void (*base_update)(void *opaque, target_phys_addr_t new); |
3377 | 827df9f3 | balrog | void (*unmap)(void *opaque); |
3378 | 827df9f3 | balrog | void *opaque;
|
3379 | 827df9f3 | balrog | } cs_file[8];
|
3380 | 827df9f3 | balrog | int ecc_cs;
|
3381 | 827df9f3 | balrog | int ecc_ptr;
|
3382 | 827df9f3 | balrog | uint32_t ecc_cfg; |
3383 | 827df9f3 | balrog | struct ecc_state_s ecc[9]; |
3384 | 827df9f3 | balrog | }; |
3385 | 827df9f3 | balrog | |
3386 | 827df9f3 | balrog | static void omap_gpmc_int_update(struct omap_gpmc_s *s) |
3387 | 827df9f3 | balrog | { |
3388 | 827df9f3 | balrog | qemu_set_irq(s->irq, s->irqen & s->irqst); |
3389 | 827df9f3 | balrog | } |
3390 | 827df9f3 | balrog | |
3391 | 827df9f3 | balrog | static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask) |
3392 | 827df9f3 | balrog | { |
3393 | 827df9f3 | balrog | /* TODO: check for overlapping regions and report access errors */
|
3394 | 827df9f3 | balrog | if ((mask != 0x8 && mask != 0xc && mask != 0xe && mask != 0xf) || |
3395 | 827df9f3 | balrog | (base < 0 || base >= 0x40) || |
3396 | 827df9f3 | balrog | (base & 0x0f & ~mask)) {
|
3397 | 827df9f3 | balrog | fprintf(stderr, "%s: wrong cs address mapping/decoding!\n",
|
3398 | 827df9f3 | balrog | __FUNCTION__); |
3399 | 827df9f3 | balrog | return;
|
3400 | 827df9f3 | balrog | } |
3401 | 827df9f3 | balrog | |
3402 | 827df9f3 | balrog | if (!f->opaque)
|
3403 | 827df9f3 | balrog | return;
|
3404 | 827df9f3 | balrog | |
3405 | 827df9f3 | balrog | f->base = base << 24;
|
3406 | 827df9f3 | balrog | f->size = (0x0fffffff & ~(mask << 24)) + 1; |
3407 | 827df9f3 | balrog | /* TODO: rather than setting the size of the mapping (which should be
|
3408 | 827df9f3 | balrog | * constant), the mask should cause wrapping of the address space, so
|
3409 | 827df9f3 | balrog | * that the same memory becomes accessible at every <i>size</i> bytes
|
3410 | 827df9f3 | balrog | * starting from <i>base</i>. */
|
3411 | 827df9f3 | balrog | if (f->iomemtype)
|
3412 | 827df9f3 | balrog | cpu_register_physical_memory(f->base, f->size, f->iomemtype); |
3413 | 827df9f3 | balrog | |
3414 | 827df9f3 | balrog | if (f->base_update)
|
3415 | 827df9f3 | balrog | f->base_update(f->opaque, f->base); |
3416 | 827df9f3 | balrog | } |
3417 | 827df9f3 | balrog | |
3418 | 827df9f3 | balrog | static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f) |
3419 | 827df9f3 | balrog | { |
3420 | 827df9f3 | balrog | if (f->size) {
|
3421 | 827df9f3 | balrog | if (f->unmap)
|
3422 | 827df9f3 | balrog | f->unmap(f->opaque); |
3423 | 827df9f3 | balrog | if (f->iomemtype)
|
3424 | 827df9f3 | balrog | cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED); |
3425 | 827df9f3 | balrog | f->base = 0;
|
3426 | 827df9f3 | balrog | f->size = 0;
|
3427 | 827df9f3 | balrog | } |
3428 | 827df9f3 | balrog | } |
3429 | 827df9f3 | balrog | |
3430 | 827df9f3 | balrog | static void omap_gpmc_reset(struct omap_gpmc_s *s) |
3431 | 827df9f3 | balrog | { |
3432 | 827df9f3 | balrog | int i;
|
3433 | 827df9f3 | balrog | |
3434 | 827df9f3 | balrog | s->sysconfig = 0;
|
3435 | 827df9f3 | balrog | s->irqst = 0;
|
3436 | 827df9f3 | balrog | s->irqen = 0;
|
3437 | 827df9f3 | balrog | omap_gpmc_int_update(s); |
3438 | 827df9f3 | balrog | s->timeout = 0;
|
3439 | 827df9f3 | balrog | s->config = 0xa00;
|
3440 | 827df9f3 | balrog | s->prefconfig[0] = 0x00004000; |
3441 | 827df9f3 | balrog | s->prefconfig[1] = 0x00000000; |
3442 | 827df9f3 | balrog | s->prefcontrol = 0;
|
3443 | 827df9f3 | balrog | s->preffifo = 0;
|
3444 | 827df9f3 | balrog | s->prefcount = 0;
|
3445 | 827df9f3 | balrog | for (i = 0; i < 8; i ++) { |
3446 | 827df9f3 | balrog | if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */ |
3447 | 827df9f3 | balrog | omap_gpmc_cs_unmap(s->cs_file + i); |
3448 | 827df9f3 | balrog | s->cs_file[i].config[0] = i ? 1 << 12 : 0; |
3449 | 827df9f3 | balrog | s->cs_file[i].config[1] = 0x101001; |
3450 | 827df9f3 | balrog | s->cs_file[i].config[2] = 0x020201; |
3451 | 827df9f3 | balrog | s->cs_file[i].config[3] = 0x10031003; |
3452 | 827df9f3 | balrog | s->cs_file[i].config[4] = 0x10f1111; |
3453 | 827df9f3 | balrog | s->cs_file[i].config[5] = 0; |
3454 | 827df9f3 | balrog | s->cs_file[i].config[6] = 0xf00 | (i ? 0 : 1 << 6); |
3455 | 827df9f3 | balrog | if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */ |
3456 | 827df9f3 | balrog | omap_gpmc_cs_map(&s->cs_file[i], |
3457 | 827df9f3 | balrog | s->cs_file[i].config[6] & 0x1f, /* MASKADDR */ |
3458 | 827df9f3 | balrog | (s->cs_file[i].config[6] >> 8 & 0xf)); /* BASEADDR */ |
3459 | 827df9f3 | balrog | } |
3460 | 827df9f3 | balrog | omap_gpmc_cs_map(s->cs_file, 0, 0xf); |
3461 | 827df9f3 | balrog | s->ecc_cs = 0;
|
3462 | 827df9f3 | balrog | s->ecc_ptr = 0;
|
3463 | 827df9f3 | balrog | s->ecc_cfg = 0x3fcff000;
|
3464 | 827df9f3 | balrog | for (i = 0; i < 9; i ++) |
3465 | 827df9f3 | balrog | ecc_reset(&s->ecc[i]); |
3466 | 827df9f3 | balrog | } |
3467 | 827df9f3 | balrog | |
3468 | 827df9f3 | balrog | static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr) |
3469 | 827df9f3 | balrog | { |
3470 | 827df9f3 | balrog | struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque; |
3471 | 827df9f3 | balrog | int offset = addr - s->base;
|
3472 | 827df9f3 | balrog | int cs;
|
3473 | 827df9f3 | balrog | struct omap_gpmc_cs_file_s *f;
|
3474 | 827df9f3 | balrog | |
3475 | 827df9f3 | balrog | switch (offset) {
|
3476 | 827df9f3 | balrog | case 0x000: /* GPMC_REVISION */ |
3477 | 827df9f3 | balrog | return 0x20; |
3478 | 827df9f3 | balrog | |
3479 | 827df9f3 | balrog | case 0x010: /* GPMC_SYSCONFIG */ |
3480 | 827df9f3 | balrog | return s->sysconfig;
|
3481 | 827df9f3 | balrog | |
3482 | 827df9f3 | balrog | case 0x014: /* GPMC_SYSSTATUS */ |
3483 | 827df9f3 | balrog | return 1; /* RESETDONE */ |
3484 | 827df9f3 | balrog | |
3485 | 827df9f3 | balrog | case 0x018: /* GPMC_IRQSTATUS */ |
3486 | 827df9f3 | balrog | return s->irqst;
|
3487 | 827df9f3 | balrog | |
3488 | 827df9f3 | balrog | case 0x01c: /* GPMC_IRQENABLE */ |
3489 | 827df9f3 | balrog | return s->irqen;
|
3490 | 827df9f3 | balrog | |
3491 | 827df9f3 | balrog | case 0x040: /* GPMC_TIMEOUT_CONTROL */ |
3492 | 827df9f3 | balrog | return s->timeout;
|
3493 | 827df9f3 | balrog | |
3494 | 827df9f3 | balrog | case 0x044: /* GPMC_ERR_ADDRESS */ |
3495 | 827df9f3 | balrog | case 0x048: /* GPMC_ERR_TYPE */ |
3496 | 827df9f3 | balrog | return 0; |
3497 | 827df9f3 | balrog | |
3498 | 827df9f3 | balrog | case 0x050: /* GPMC_CONFIG */ |
3499 | 827df9f3 | balrog | return s->config;
|
3500 | 827df9f3 | balrog | |
3501 | 827df9f3 | balrog | case 0x054: /* GPMC_STATUS */ |
3502 | 827df9f3 | balrog | return 0x001; |
3503 | 827df9f3 | balrog | |
3504 | 827df9f3 | balrog | case 0x060 ... 0x1d4: |
3505 | 827df9f3 | balrog | cs = (offset - 0x060) / 0x30; |
3506 | 827df9f3 | balrog | offset -= cs * 0x30;
|
3507 | 827df9f3 | balrog | f = s->cs_file + cs; |
3508 | 827df9f3 | balrog | switch (offset - cs * 0x30) { |
3509 | 827df9f3 | balrog | case 0x60: /* GPMC_CONFIG1 */ |
3510 | 827df9f3 | balrog | return f->config[0]; |
3511 | 827df9f3 | balrog | case 0x64: /* GPMC_CONFIG2 */ |
3512 | 827df9f3 | balrog | return f->config[1]; |
3513 | 827df9f3 | balrog | case 0x68: /* GPMC_CONFIG3 */ |
3514 | 827df9f3 | balrog | return f->config[2]; |
3515 | 827df9f3 | balrog | case 0x6c: /* GPMC_CONFIG4 */ |
3516 | 827df9f3 | balrog | return f->config[3]; |
3517 | 827df9f3 | balrog | case 0x70: /* GPMC_CONFIG5 */ |
3518 | 827df9f3 | balrog | return f->config[4]; |
3519 | 827df9f3 | balrog | case 0x74: /* GPMC_CONFIG6 */ |
3520 | 827df9f3 | balrog | return f->config[5]; |
3521 | 827df9f3 | balrog | case 0x78: /* GPMC_CONFIG7 */ |
3522 | 827df9f3 | balrog | return f->config[6]; |
3523 | 827df9f3 | balrog | case 0x84: /* GPMC_NAND_DATA */ |
3524 | 827df9f3 | balrog | return 0; |
3525 | 827df9f3 | balrog | } |
3526 | 827df9f3 | balrog | break;
|
3527 | 827df9f3 | balrog | |
3528 | 827df9f3 | balrog | case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */ |
3529 | 827df9f3 | balrog | return s->prefconfig[0]; |
3530 | 827df9f3 | balrog | case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */ |
3531 | 827df9f3 | balrog | return s->prefconfig[1]; |
3532 | 827df9f3 | balrog | case 0x1ec: /* GPMC_PREFETCH_CONTROL */ |
3533 | 827df9f3 | balrog | return s->prefcontrol;
|
3534 | 827df9f3 | balrog | case 0x1f0: /* GPMC_PREFETCH_STATUS */ |
3535 | 827df9f3 | balrog | return (s->preffifo << 24) | |
3536 | 827df9f3 | balrog | ((s->preffifo > |
3537 | 827df9f3 | balrog | ((s->prefconfig[0] >> 8) & 0x7f) ? 1 : 0) << 16) | |
3538 | 827df9f3 | balrog | s->prefcount; |
3539 | 827df9f3 | balrog | |
3540 | 827df9f3 | balrog | case 0x1f4: /* GPMC_ECC_CONFIG */ |
3541 | 827df9f3 | balrog | return s->ecc_cs;
|
3542 | 827df9f3 | balrog | case 0x1f8: /* GPMC_ECC_CONTROL */ |
3543 | 827df9f3 | balrog | return s->ecc_ptr;
|
3544 | 827df9f3 | balrog | case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */ |
3545 | 827df9f3 | balrog | return s->ecc_cfg;
|
3546 | 827df9f3 | balrog | case 0x200 ... 0x220: /* GPMC_ECC_RESULT */ |
3547 | 827df9f3 | balrog | cs = (offset & 0x1f) >> 2; |
3548 | 827df9f3 | balrog | /* TODO: check correctness */
|
3549 | 827df9f3 | balrog | return
|
3550 | 827df9f3 | balrog | ((s->ecc[cs].cp & 0x07) << 0) | |
3551 | 827df9f3 | balrog | ((s->ecc[cs].cp & 0x38) << 13) | |
3552 | 827df9f3 | balrog | ((s->ecc[cs].lp[0] & 0x1ff) << 3) | |
3553 | 827df9f3 | balrog | ((s->ecc[cs].lp[1] & 0x1ff) << 19); |
3554 | 827df9f3 | balrog | |
3555 | 827df9f3 | balrog | case 0x230: /* GPMC_TESTMODE_CTRL */ |
3556 | 827df9f3 | balrog | return 0; |
3557 | 827df9f3 | balrog | case 0x234: /* GPMC_PSA_LSB */ |
3558 | 827df9f3 | balrog | case 0x238: /* GPMC_PSA_MSB */ |
3559 | 827df9f3 | balrog | return 0x00000000; |
3560 | 827df9f3 | balrog | } |
3561 | 827df9f3 | balrog | |
3562 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
3563 | 827df9f3 | balrog | return 0; |
3564 | 827df9f3 | balrog | } |
3565 | 827df9f3 | balrog | |
3566 | 827df9f3 | balrog | static void omap_gpmc_write(void *opaque, target_phys_addr_t addr, |
3567 | 827df9f3 | balrog | uint32_t value) |
3568 | 827df9f3 | balrog | { |
3569 | 827df9f3 | balrog | struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque; |
3570 | 827df9f3 | balrog | int offset = addr - s->base;
|
3571 | 827df9f3 | balrog | int cs;
|
3572 | 827df9f3 | balrog | struct omap_gpmc_cs_file_s *f;
|
3573 | 827df9f3 | balrog | |
3574 | 827df9f3 | balrog | switch (offset) {
|
3575 | 827df9f3 | balrog | case 0x000: /* GPMC_REVISION */ |
3576 | 827df9f3 | balrog | case 0x014: /* GPMC_SYSSTATUS */ |
3577 | 827df9f3 | balrog | case 0x054: /* GPMC_STATUS */ |
3578 | 827df9f3 | balrog | case 0x1f0: /* GPMC_PREFETCH_STATUS */ |
3579 | 827df9f3 | balrog | case 0x200 ... 0x220: /* GPMC_ECC_RESULT */ |
3580 | 827df9f3 | balrog | case 0x234: /* GPMC_PSA_LSB */ |
3581 | 827df9f3 | balrog | case 0x238: /* GPMC_PSA_MSB */ |
3582 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
3583 | 827df9f3 | balrog | break;
|
3584 | 827df9f3 | balrog | |
3585 | 827df9f3 | balrog | case 0x010: /* GPMC_SYSCONFIG */ |
3586 | 827df9f3 | balrog | if ((value >> 3) == 0x3) |
3587 | 827df9f3 | balrog | fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
|
3588 | 827df9f3 | balrog | __FUNCTION__, value >> 3);
|
3589 | 827df9f3 | balrog | if (value & 2) |
3590 | 827df9f3 | balrog | omap_gpmc_reset(s); |
3591 | 827df9f3 | balrog | s->sysconfig = value & 0x19;
|
3592 | 827df9f3 | balrog | break;
|
3593 | 827df9f3 | balrog | |
3594 | 827df9f3 | balrog | case 0x018: /* GPMC_IRQSTATUS */ |
3595 | 827df9f3 | balrog | s->irqen = ~value; |
3596 | 827df9f3 | balrog | omap_gpmc_int_update(s); |
3597 | 827df9f3 | balrog | break;
|
3598 | 827df9f3 | balrog | |
3599 | 827df9f3 | balrog | case 0x01c: /* GPMC_IRQENABLE */ |
3600 | 827df9f3 | balrog | s->irqen = value & 0xf03;
|
3601 | 827df9f3 | balrog | omap_gpmc_int_update(s); |
3602 | 827df9f3 | balrog | break;
|
3603 | 827df9f3 | balrog | |
3604 | 827df9f3 | balrog | case 0x040: /* GPMC_TIMEOUT_CONTROL */ |
3605 | 827df9f3 | balrog | s->timeout = value & 0x1ff1;
|
3606 | 827df9f3 | balrog | break;
|
3607 | 827df9f3 | balrog | |
3608 | 827df9f3 | balrog | case 0x044: /* GPMC_ERR_ADDRESS */ |
3609 | 827df9f3 | balrog | case 0x048: /* GPMC_ERR_TYPE */ |
3610 | 827df9f3 | balrog | break;
|
3611 | 827df9f3 | balrog | |
3612 | 827df9f3 | balrog | case 0x050: /* GPMC_CONFIG */ |
3613 | 827df9f3 | balrog | s->config = value & 0xf13;
|
3614 | 827df9f3 | balrog | break;
|
3615 | 827df9f3 | balrog | |
3616 | 827df9f3 | balrog | case 0x060 ... 0x1d4: |
3617 | 827df9f3 | balrog | cs = (offset - 0x060) / 0x30; |
3618 | 827df9f3 | balrog | offset -= cs * 0x30;
|
3619 | 827df9f3 | balrog | f = s->cs_file + cs; |
3620 | 827df9f3 | balrog | switch (offset) {
|
3621 | 827df9f3 | balrog | case 0x60: /* GPMC_CONFIG1 */ |
3622 | 827df9f3 | balrog | f->config[0] = value & 0xffef3e13; |
3623 | 827df9f3 | balrog | break;
|
3624 | 827df9f3 | balrog | case 0x64: /* GPMC_CONFIG2 */ |
3625 | 827df9f3 | balrog | f->config[1] = value & 0x001f1f8f; |
3626 | 827df9f3 | balrog | break;
|
3627 | 827df9f3 | balrog | case 0x68: /* GPMC_CONFIG3 */ |
3628 | 827df9f3 | balrog | f->config[2] = value & 0x001f1f8f; |
3629 | 827df9f3 | balrog | break;
|
3630 | 827df9f3 | balrog | case 0x6c: /* GPMC_CONFIG4 */ |
3631 | 827df9f3 | balrog | f->config[3] = value & 0x1f8f1f8f; |
3632 | 827df9f3 | balrog | break;
|
3633 | 827df9f3 | balrog | case 0x70: /* GPMC_CONFIG5 */ |
3634 | 827df9f3 | balrog | f->config[4] = value & 0x0f1f1f1f; |
3635 | 827df9f3 | balrog | break;
|
3636 | 827df9f3 | balrog | case 0x74: /* GPMC_CONFIG6 */ |
3637 | 827df9f3 | balrog | f->config[5] = value & 0x00000fcf; |
3638 | 827df9f3 | balrog | break;
|
3639 | 827df9f3 | balrog | case 0x78: /* GPMC_CONFIG7 */ |
3640 | 827df9f3 | balrog | if ((f->config[6] ^ value) & 0xf7f) { |
3641 | 827df9f3 | balrog | if (f->config[6] & (1 << 6)) /* CSVALID */ |
3642 | 827df9f3 | balrog | omap_gpmc_cs_unmap(f); |
3643 | 827df9f3 | balrog | if (value & (1 << 6)) /* CSVALID */ |
3644 | 827df9f3 | balrog | omap_gpmc_cs_map(f, value & 0x1f, /* MASKADDR */ |
3645 | 827df9f3 | balrog | (value >> 8 & 0xf)); /* BASEADDR */ |
3646 | 827df9f3 | balrog | } |
3647 | 827df9f3 | balrog | f->config[6] = value & 0x00000f7f; |
3648 | 827df9f3 | balrog | break;
|
3649 | 827df9f3 | balrog | case 0x7c: /* GPMC_NAND_COMMAND */ |
3650 | 827df9f3 | balrog | case 0x80: /* GPMC_NAND_ADDRESS */ |
3651 | 827df9f3 | balrog | case 0x84: /* GPMC_NAND_DATA */ |
3652 | 827df9f3 | balrog | break;
|
3653 | 827df9f3 | balrog | |
3654 | 827df9f3 | balrog | default:
|
3655 | 827df9f3 | balrog | goto bad_reg;
|
3656 | 827df9f3 | balrog | } |
3657 | 827df9f3 | balrog | break;
|
3658 | 827df9f3 | balrog | |
3659 | 827df9f3 | balrog | case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */ |
3660 | 827df9f3 | balrog | s->prefconfig[0] = value & 0x7f8f7fbf; |
3661 | 827df9f3 | balrog | /* TODO: update interrupts, fifos, dmas */
|
3662 | 827df9f3 | balrog | break;
|
3663 | 827df9f3 | balrog | |
3664 | 827df9f3 | balrog | case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */ |
3665 | 827df9f3 | balrog | s->prefconfig[1] = value & 0x3fff; |
3666 | 827df9f3 | balrog | break;
|
3667 | 827df9f3 | balrog | |
3668 | 827df9f3 | balrog | case 0x1ec: /* GPMC_PREFETCH_CONTROL */ |
3669 | 827df9f3 | balrog | s->prefcontrol = value & 1;
|
3670 | 827df9f3 | balrog | if (s->prefcontrol) {
|
3671 | 827df9f3 | balrog | if (s->prefconfig[0] & 1) |
3672 | 827df9f3 | balrog | s->preffifo = 0x40;
|
3673 | 827df9f3 | balrog | else
|
3674 | 827df9f3 | balrog | s->preffifo = 0x00;
|
3675 | 827df9f3 | balrog | } |
3676 | 827df9f3 | balrog | /* TODO: start */
|
3677 | 827df9f3 | balrog | break;
|
3678 | 827df9f3 | balrog | |
3679 | 827df9f3 | balrog | case 0x1f4: /* GPMC_ECC_CONFIG */ |
3680 | 827df9f3 | balrog | s->ecc_cs = 0x8f;
|
3681 | 827df9f3 | balrog | break;
|
3682 | 827df9f3 | balrog | case 0x1f8: /* GPMC_ECC_CONTROL */ |
3683 | 827df9f3 | balrog | if (value & (1 << 8)) |
3684 | 827df9f3 | balrog | for (cs = 0; cs < 9; cs ++) |
3685 | 827df9f3 | balrog | ecc_reset(&s->ecc[cs]); |
3686 | 827df9f3 | balrog | s->ecc_ptr = value & 0xf;
|
3687 | 827df9f3 | balrog | if (s->ecc_ptr == 0 || s->ecc_ptr > 9) { |
3688 | 827df9f3 | balrog | s->ecc_ptr = 0;
|
3689 | 827df9f3 | balrog | s->ecc_cs &= ~1;
|
3690 | 827df9f3 | balrog | } |
3691 | 827df9f3 | balrog | break;
|
3692 | 827df9f3 | balrog | case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */ |
3693 | 827df9f3 | balrog | s->ecc_cfg = value & 0x3fcff1ff;
|
3694 | 827df9f3 | balrog | break;
|
3695 | 827df9f3 | balrog | case 0x230: /* GPMC_TESTMODE_CTRL */ |
3696 | 827df9f3 | balrog | if (value & 7) |
3697 | 827df9f3 | balrog | fprintf(stderr, "%s: test mode enable attempt\n", __FUNCTION__);
|
3698 | 827df9f3 | balrog | break;
|
3699 | 827df9f3 | balrog | |
3700 | 827df9f3 | balrog | default:
|
3701 | 827df9f3 | balrog | bad_reg:
|
3702 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
3703 | 827df9f3 | balrog | return;
|
3704 | 827df9f3 | balrog | } |
3705 | 827df9f3 | balrog | } |
3706 | 827df9f3 | balrog | |
3707 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap_gpmc_readfn[] = {
|
3708 | 827df9f3 | balrog | omap_badwidth_read32, /* TODO */
|
3709 | 827df9f3 | balrog | omap_badwidth_read32, /* TODO */
|
3710 | 827df9f3 | balrog | omap_gpmc_read, |
3711 | 827df9f3 | balrog | }; |
3712 | 827df9f3 | balrog | |
3713 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap_gpmc_writefn[] = {
|
3714 | 827df9f3 | balrog | omap_badwidth_write32, /* TODO */
|
3715 | 827df9f3 | balrog | omap_badwidth_write32, /* TODO */
|
3716 | 827df9f3 | balrog | omap_gpmc_write, |
3717 | 827df9f3 | balrog | }; |
3718 | 827df9f3 | balrog | |
3719 | 827df9f3 | balrog | struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
|
3720 | 827df9f3 | balrog | { |
3721 | 827df9f3 | balrog | int iomemtype;
|
3722 | 827df9f3 | balrog | struct omap_gpmc_s *s = (struct omap_gpmc_s *) |
3723 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_gpmc_s)); |
3724 | 827df9f3 | balrog | |
3725 | 827df9f3 | balrog | s->base = base; |
3726 | 827df9f3 | balrog | omap_gpmc_reset(s); |
3727 | 827df9f3 | balrog | |
3728 | 827df9f3 | balrog | iomemtype = cpu_register_io_memory(0, omap_gpmc_readfn,
|
3729 | 827df9f3 | balrog | omap_gpmc_writefn, s); |
3730 | 827df9f3 | balrog | cpu_register_physical_memory(s->base, 0x1000, iomemtype);
|
3731 | 827df9f3 | balrog | |
3732 | 827df9f3 | balrog | return s;
|
3733 | 827df9f3 | balrog | } |
3734 | 827df9f3 | balrog | |
3735 | 827df9f3 | balrog | void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype, |
3736 | 827df9f3 | balrog | void (*base_upd)(void *opaque, target_phys_addr_t new), |
3737 | 827df9f3 | balrog | void (*unmap)(void *opaque), void *opaque) |
3738 | 827df9f3 | balrog | { |
3739 | 827df9f3 | balrog | struct omap_gpmc_cs_file_s *f;
|
3740 | 827df9f3 | balrog | |
3741 | 827df9f3 | balrog | if (cs < 0 || cs >= 8) { |
3742 | 827df9f3 | balrog | fprintf(stderr, "%s: bad chip-select %i\n", __FUNCTION__, cs);
|
3743 | 827df9f3 | balrog | exit(-1);
|
3744 | 827df9f3 | balrog | } |
3745 | 827df9f3 | balrog | f = &s->cs_file[cs]; |
3746 | 827df9f3 | balrog | |
3747 | 827df9f3 | balrog | f->iomemtype = iomemtype; |
3748 | 827df9f3 | balrog | f->base_update = base_upd; |
3749 | 827df9f3 | balrog | f->unmap = unmap; |
3750 | 827df9f3 | balrog | f->opaque = opaque; |
3751 | 827df9f3 | balrog | |
3752 | 827df9f3 | balrog | if (f->config[6] & (1 << 6)) /* CSVALID */ |
3753 | 827df9f3 | balrog | omap_gpmc_cs_map(f, f->config[6] & 0x1f, /* MASKADDR */ |
3754 | 827df9f3 | balrog | (f->config[6] >> 8 & 0xf)); /* BASEADDR */ |
3755 | 827df9f3 | balrog | } |
3756 | 827df9f3 | balrog | |
3757 | 827df9f3 | balrog | /* General chip reset */
|
3758 | 827df9f3 | balrog | static void omap2_mpu_reset(void *opaque) |
3759 | 827df9f3 | balrog | { |
3760 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
3761 | 827df9f3 | balrog | |
3762 | 827df9f3 | balrog | omap_inth_reset(mpu->ih[0]);
|
3763 | 827df9f3 | balrog | omap_dma_reset(mpu->dma); |
3764 | 827df9f3 | balrog | omap_prcm_reset(mpu->prcm); |
3765 | 827df9f3 | balrog | omap_sysctl_reset(mpu->sysc); |
3766 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[0]);
|
3767 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[1]);
|
3768 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[2]);
|
3769 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[3]);
|
3770 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[4]);
|
3771 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[5]);
|
3772 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[6]);
|
3773 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[7]);
|
3774 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[8]);
|
3775 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[9]);
|
3776 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[10]);
|
3777 | 827df9f3 | balrog | omap_gp_timer_reset(mpu->gptimer[11]);
|
3778 | 827df9f3 | balrog | omap_synctimer_reset(&mpu->synctimer); |
3779 | 827df9f3 | balrog | omap_sdrc_reset(mpu->sdrc); |
3780 | 827df9f3 | balrog | omap_gpmc_reset(mpu->gpmc); |
3781 | 827df9f3 | balrog | omap_dss_reset(mpu->dss); |
3782 | 827df9f3 | balrog | omap_uart_reset(mpu->uart[0]);
|
3783 | 827df9f3 | balrog | omap_uart_reset(mpu->uart[1]);
|
3784 | 827df9f3 | balrog | omap_uart_reset(mpu->uart[2]);
|
3785 | 827df9f3 | balrog | omap_mmc_reset(mpu->mmc); |
3786 | 827df9f3 | balrog | omap_gpif_reset(mpu->gpif); |
3787 | 827df9f3 | balrog | omap_mcspi_reset(mpu->mcspi[0]);
|
3788 | 827df9f3 | balrog | omap_mcspi_reset(mpu->mcspi[1]);
|
3789 | 827df9f3 | balrog | omap_i2c_reset(mpu->i2c[0]);
|
3790 | 827df9f3 | balrog | omap_i2c_reset(mpu->i2c[1]);
|
3791 | 827df9f3 | balrog | cpu_reset(mpu->env); |
3792 | 827df9f3 | balrog | } |
3793 | 827df9f3 | balrog | |
3794 | 827df9f3 | balrog | static int omap2_validate_addr(struct omap_mpu_state_s *s, |
3795 | 827df9f3 | balrog | target_phys_addr_t addr) |
3796 | 827df9f3 | balrog | { |
3797 | 827df9f3 | balrog | return 1; |
3798 | 827df9f3 | balrog | } |
3799 | 827df9f3 | balrog | |
3800 | 827df9f3 | balrog | static const struct dma_irq_map omap2_dma_irq_map[] = { |
3801 | 827df9f3 | balrog | { 0, OMAP_INT_24XX_SDMA_IRQ0 },
|
3802 | 827df9f3 | balrog | { 0, OMAP_INT_24XX_SDMA_IRQ1 },
|
3803 | 827df9f3 | balrog | { 0, OMAP_INT_24XX_SDMA_IRQ2 },
|
3804 | 827df9f3 | balrog | { 0, OMAP_INT_24XX_SDMA_IRQ3 },
|
3805 | 827df9f3 | balrog | }; |
3806 | 827df9f3 | balrog | |
3807 | 827df9f3 | balrog | struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size, |
3808 | 827df9f3 | balrog | DisplayState *ds, const char *core) |
3809 | 827df9f3 | balrog | { |
3810 | 827df9f3 | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) |
3811 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_mpu_state_s)); |
3812 | 7e7c5e4c | balrog | ram_addr_t sram_base, q2_base; |
3813 | 827df9f3 | balrog | qemu_irq *cpu_irq; |
3814 | 827df9f3 | balrog | qemu_irq dma_irqs[4];
|
3815 | 827df9f3 | balrog | omap_clk gpio_clks[4];
|
3816 | 827df9f3 | balrog | int sdindex;
|
3817 | 827df9f3 | balrog | int i;
|
3818 | 827df9f3 | balrog | |
3819 | 827df9f3 | balrog | /* Core */
|
3820 | 827df9f3 | balrog | s->mpu_model = omap2420; |
3821 | 827df9f3 | balrog | s->env = cpu_init(core ?: "arm1136-r2");
|
3822 | 827df9f3 | balrog | if (!s->env) {
|
3823 | 827df9f3 | balrog | fprintf(stderr, "Unable to find CPU definition\n");
|
3824 | 827df9f3 | balrog | exit(1);
|
3825 | 827df9f3 | balrog | } |
3826 | 827df9f3 | balrog | s->sdram_size = sdram_size; |
3827 | 827df9f3 | balrog | s->sram_size = OMAP242X_SRAM_SIZE; |
3828 | 827df9f3 | balrog | |
3829 | 827df9f3 | balrog | s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0]; |
3830 | 827df9f3 | balrog | |
3831 | 827df9f3 | balrog | /* Clocks */
|
3832 | 827df9f3 | balrog | omap_clk_init(s); |
3833 | 827df9f3 | balrog | |
3834 | 827df9f3 | balrog | /* Memory-mapped stuff */
|
3835 | 827df9f3 | balrog | cpu_register_physical_memory(OMAP2_Q2_BASE, s->sdram_size, |
3836 | 7e7c5e4c | balrog | (q2_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM); |
3837 | 827df9f3 | balrog | cpu_register_physical_memory(OMAP2_SRAM_BASE, s->sram_size, |
3838 | 827df9f3 | balrog | (sram_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM); |
3839 | 827df9f3 | balrog | |
3840 | 827df9f3 | balrog | s->l4 = omap_l4_init(OMAP2_L4_BASE, 54);
|
3841 | 827df9f3 | balrog | |
3842 | 827df9f3 | balrog | /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
|
3843 | 827df9f3 | balrog | cpu_irq = arm_pic_init_cpu(s->env); |
3844 | 827df9f3 | balrog | s->ih[0] = omap2_inth_init(0x480fe000, 0x1000, 3, &s->irq[0], |
3845 | 827df9f3 | balrog | cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ], |
3846 | 827df9f3 | balrog | omap_findclk(s, "mpu_intc_fclk"),
|
3847 | 827df9f3 | balrog | omap_findclk(s, "mpu_intc_iclk"));
|
3848 | 827df9f3 | balrog | |
3849 | 827df9f3 | balrog | s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
|
3850 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_PRCM_MPU_IRQ], NULL, NULL, s); |
3851 | 827df9f3 | balrog | |
3852 | 827df9f3 | balrog | s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
|
3853 | 827df9f3 | balrog | omap_findclk(s, "omapctrl_iclk"), s);
|
3854 | 827df9f3 | balrog | |
3855 | 827df9f3 | balrog | for (i = 0; i < 4; i ++) |
3856 | 827df9f3 | balrog | dma_irqs[i] = |
3857 | 827df9f3 | balrog | s->irq[omap2_dma_irq_map[i].ih][omap2_dma_irq_map[i].intr]; |
3858 | 827df9f3 | balrog | s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32, |
3859 | 827df9f3 | balrog | omap_findclk(s, "sdma_iclk"),
|
3860 | 827df9f3 | balrog | omap_findclk(s, "sdma_fclk"));
|
3861 | 827df9f3 | balrog | s->port->addr_valid = omap2_validate_addr; |
3862 | 827df9f3 | balrog | |
3863 | 827df9f3 | balrog | s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19), |
3864 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_UART1_IRQ],
|
3865 | 827df9f3 | balrog | omap_findclk(s, "uart1_fclk"),
|
3866 | 827df9f3 | balrog | omap_findclk(s, "uart1_iclk"),
|
3867 | 827df9f3 | balrog | s->drq[OMAP24XX_DMA_UART1_TX], |
3868 | 827df9f3 | balrog | s->drq[OMAP24XX_DMA_UART1_RX], serial_hds[0]);
|
3869 | 827df9f3 | balrog | s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20), |
3870 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_UART2_IRQ],
|
3871 | 827df9f3 | balrog | omap_findclk(s, "uart2_fclk"),
|
3872 | 827df9f3 | balrog | omap_findclk(s, "uart2_iclk"),
|
3873 | 827df9f3 | balrog | s->drq[OMAP24XX_DMA_UART2_TX], |
3874 | 827df9f3 | balrog | s->drq[OMAP24XX_DMA_UART2_RX], |
3875 | 827df9f3 | balrog | serial_hds[0] ? serial_hds[1] : 0); |
3876 | 827df9f3 | balrog | s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21), |
3877 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_UART3_IRQ],
|
3878 | 827df9f3 | balrog | omap_findclk(s, "uart3_fclk"),
|
3879 | 827df9f3 | balrog | omap_findclk(s, "uart3_iclk"),
|
3880 | 827df9f3 | balrog | s->drq[OMAP24XX_DMA_UART3_TX], |
3881 | 827df9f3 | balrog | s->drq[OMAP24XX_DMA_UART3_RX], |
3882 | 827df9f3 | balrog | serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0); |
3883 | 827df9f3 | balrog | |
3884 | 827df9f3 | balrog | s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7), |
3885 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER1],
|
3886 | 827df9f3 | balrog | omap_findclk(s, "wu_gpt1_clk"),
|
3887 | 827df9f3 | balrog | omap_findclk(s, "wu_l4_iclk"));
|
3888 | 827df9f3 | balrog | s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8), |
3889 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER2],
|
3890 | 827df9f3 | balrog | omap_findclk(s, "core_gpt2_clk"),
|
3891 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3892 | 827df9f3 | balrog | s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22), |
3893 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER3],
|
3894 | 827df9f3 | balrog | omap_findclk(s, "core_gpt3_clk"),
|
3895 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3896 | 827df9f3 | balrog | s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23), |
3897 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER4],
|
3898 | 827df9f3 | balrog | omap_findclk(s, "core_gpt4_clk"),
|
3899 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3900 | 827df9f3 | balrog | s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24), |
3901 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER5],
|
3902 | 827df9f3 | balrog | omap_findclk(s, "core_gpt5_clk"),
|
3903 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3904 | 827df9f3 | balrog | s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25), |
3905 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER6],
|
3906 | 827df9f3 | balrog | omap_findclk(s, "core_gpt6_clk"),
|
3907 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3908 | 827df9f3 | balrog | s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26), |
3909 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER7],
|
3910 | 827df9f3 | balrog | omap_findclk(s, "core_gpt7_clk"),
|
3911 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3912 | 827df9f3 | balrog | s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27), |
3913 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER8],
|
3914 | 827df9f3 | balrog | omap_findclk(s, "core_gpt8_clk"),
|
3915 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3916 | 827df9f3 | balrog | s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28), |
3917 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER9],
|
3918 | 827df9f3 | balrog | omap_findclk(s, "core_gpt9_clk"),
|
3919 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3920 | 827df9f3 | balrog | s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29), |
3921 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER10],
|
3922 | 827df9f3 | balrog | omap_findclk(s, "core_gpt10_clk"),
|
3923 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3924 | 827df9f3 | balrog | s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30), |
3925 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER11],
|
3926 | 827df9f3 | balrog | omap_findclk(s, "core_gpt11_clk"),
|
3927 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3928 | 827df9f3 | balrog | s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31), |
3929 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_GPTIMER12],
|
3930 | 827df9f3 | balrog | omap_findclk(s, "core_gpt12_clk"),
|
3931 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3932 | 827df9f3 | balrog | |
3933 | 827df9f3 | balrog | omap_tap_init(omap_l4ta(s->l4, 2), s);
|
3934 | 827df9f3 | balrog | |
3935 | 827df9f3 | balrog | omap_synctimer_init(omap_l4tao(s->l4, 2), s,
|
3936 | 827df9f3 | balrog | omap_findclk(s, "clk32-kHz"),
|
3937 | 827df9f3 | balrog | omap_findclk(s, "core_l4_iclk"));
|
3938 | 827df9f3 | balrog | |
3939 | 827df9f3 | balrog | s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5), |
3940 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_I2C1_IRQ],
|
3941 | 827df9f3 | balrog | &s->drq[OMAP24XX_DMA_I2C1_TX], |
3942 | 827df9f3 | balrog | omap_findclk(s, "i2c1.fclk"),
|
3943 | 827df9f3 | balrog | omap_findclk(s, "i2c1.iclk"));
|
3944 | 827df9f3 | balrog | s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6), |
3945 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_I2C2_IRQ],
|
3946 | 827df9f3 | balrog | &s->drq[OMAP24XX_DMA_I2C2_TX], |
3947 | 827df9f3 | balrog | omap_findclk(s, "i2c2.fclk"),
|
3948 | 827df9f3 | balrog | omap_findclk(s, "i2c2.iclk"));
|
3949 | 827df9f3 | balrog | |
3950 | 827df9f3 | balrog | gpio_clks[0] = omap_findclk(s, "gpio1_dbclk"); |
3951 | 827df9f3 | balrog | gpio_clks[1] = omap_findclk(s, "gpio2_dbclk"); |
3952 | 827df9f3 | balrog | gpio_clks[2] = omap_findclk(s, "gpio3_dbclk"); |
3953 | 827df9f3 | balrog | gpio_clks[3] = omap_findclk(s, "gpio4_dbclk"); |
3954 | 827df9f3 | balrog | s->gpif = omap2_gpio_init(omap_l4ta(s->l4, 3),
|
3955 | 827df9f3 | balrog | &s->irq[0][OMAP_INT_24XX_GPIO_BANK1],
|
3956 | 827df9f3 | balrog | gpio_clks, omap_findclk(s, "gpio_iclk"), 4); |
3957 | 827df9f3 | balrog | |
3958 | 827df9f3 | balrog | s->sdrc = omap_sdrc_init(0x68009000);
|
3959 | 827df9f3 | balrog | s->gpmc = omap_gpmc_init(0x6800a000, s->irq[0][OMAP_INT_24XX_GPMC_IRQ]); |
3960 | 827df9f3 | balrog | |
3961 | 827df9f3 | balrog | sdindex = drive_get_index(IF_SD, 0, 0); |
3962 | 827df9f3 | balrog | if (sdindex == -1) { |
3963 | 827df9f3 | balrog | fprintf(stderr, "qemu: missing SecureDigital device\n");
|
3964 | 827df9f3 | balrog | exit(1);
|
3965 | 827df9f3 | balrog | } |
3966 | 827df9f3 | balrog | s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), drives_table[sdindex].bdrv,
|
3967 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_MMC_IRQ],
|
3968 | 827df9f3 | balrog | &s->drq[OMAP24XX_DMA_MMC1_TX], |
3969 | 827df9f3 | balrog | omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk")); |
3970 | 827df9f3 | balrog | |
3971 | 827df9f3 | balrog | s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4, |
3972 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ],
|
3973 | 827df9f3 | balrog | &s->drq[OMAP24XX_DMA_SPI1_TX0], |
3974 | 827df9f3 | balrog | omap_findclk(s, "spi1_fclk"),
|
3975 | 827df9f3 | balrog | omap_findclk(s, "spi1_iclk"));
|
3976 | 827df9f3 | balrog | s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2, |
3977 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ],
|
3978 | 827df9f3 | balrog | &s->drq[OMAP24XX_DMA_SPI2_TX0], |
3979 | 827df9f3 | balrog | omap_findclk(s, "spi2_fclk"),
|
3980 | 827df9f3 | balrog | omap_findclk(s, "spi2_iclk"));
|
3981 | 827df9f3 | balrog | |
3982 | 827df9f3 | balrog | s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800, ds, |
3983 | 827df9f3 | balrog | /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
|
3984 | 827df9f3 | balrog | s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
|
3985 | 827df9f3 | balrog | omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"), |
3986 | 827df9f3 | balrog | omap_findclk(s, "dss_54m_clk"),
|
3987 | 827df9f3 | balrog | omap_findclk(s, "dss_l3_iclk"),
|
3988 | 827df9f3 | balrog | omap_findclk(s, "dss_l4_iclk"));
|
3989 | 827df9f3 | balrog | |
3990 | 54585ffe | balrog | omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000, |
3991 | 54585ffe | balrog | s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"), |
3992 | 54585ffe | balrog | serial_hds[0] && serial_hds[1] && serial_hds[2] ? |
3993 | 54585ffe | balrog | serial_hds[3] : 0); |
3994 | 54585ffe | balrog | |
3995 | 827df9f3 | balrog | /* All register mappings (includin those not currenlty implemented):
|
3996 | 827df9f3 | balrog | * SystemControlMod 48000000 - 48000fff
|
3997 | 827df9f3 | balrog | * SystemControlL4 48001000 - 48001fff
|
3998 | 827df9f3 | balrog | * 32kHz Timer Mod 48004000 - 48004fff
|
3999 | 827df9f3 | balrog | * 32kHz Timer L4 48005000 - 48005fff
|
4000 | 827df9f3 | balrog | * PRCM ModA 48008000 - 480087ff
|
4001 | 827df9f3 | balrog | * PRCM ModB 48008800 - 48008fff
|
4002 | 827df9f3 | balrog | * PRCM L4 48009000 - 48009fff
|
4003 | 827df9f3 | balrog | * TEST-BCM Mod 48012000 - 48012fff
|
4004 | 827df9f3 | balrog | * TEST-BCM L4 48013000 - 48013fff
|
4005 | 827df9f3 | balrog | * TEST-TAP Mod 48014000 - 48014fff
|
4006 | 827df9f3 | balrog | * TEST-TAP L4 48015000 - 48015fff
|
4007 | 827df9f3 | balrog | * GPIO1 Mod 48018000 - 48018fff
|
4008 | 827df9f3 | balrog | * GPIO Top 48019000 - 48019fff
|
4009 | 827df9f3 | balrog | * GPIO2 Mod 4801a000 - 4801afff
|
4010 | 827df9f3 | balrog | * GPIO L4 4801b000 - 4801bfff
|
4011 | 827df9f3 | balrog | * GPIO3 Mod 4801c000 - 4801cfff
|
4012 | 827df9f3 | balrog | * GPIO4 Mod 4801e000 - 4801efff
|
4013 | 827df9f3 | balrog | * WDTIMER1 Mod 48020000 - 48010fff
|
4014 | 827df9f3 | balrog | * WDTIMER Top 48021000 - 48011fff
|
4015 | 827df9f3 | balrog | * WDTIMER2 Mod 48022000 - 48012fff
|
4016 | 827df9f3 | balrog | * WDTIMER L4 48023000 - 48013fff
|
4017 | 827df9f3 | balrog | * WDTIMER3 Mod 48024000 - 48014fff
|
4018 | 827df9f3 | balrog | * WDTIMER3 L4 48025000 - 48015fff
|
4019 | 827df9f3 | balrog | * WDTIMER4 Mod 48026000 - 48016fff
|
4020 | 827df9f3 | balrog | * WDTIMER4 L4 48027000 - 48017fff
|
4021 | 827df9f3 | balrog | * GPTIMER1 Mod 48028000 - 48018fff
|
4022 | 827df9f3 | balrog | * GPTIMER1 L4 48029000 - 48019fff
|
4023 | 827df9f3 | balrog | * GPTIMER2 Mod 4802a000 - 4801afff
|
4024 | 827df9f3 | balrog | * GPTIMER2 L4 4802b000 - 4801bfff
|
4025 | 827df9f3 | balrog | * L4-Config AP 48040000 - 480407ff
|
4026 | 827df9f3 | balrog | * L4-Config IP 48040800 - 48040fff
|
4027 | 827df9f3 | balrog | * L4-Config LA 48041000 - 48041fff
|
4028 | 827df9f3 | balrog | * ARM11ETB Mod 48048000 - 48049fff
|
4029 | 827df9f3 | balrog | * ARM11ETB L4 4804a000 - 4804afff
|
4030 | 827df9f3 | balrog | * DISPLAY Top 48050000 - 480503ff
|
4031 | 827df9f3 | balrog | * DISPLAY DISPC 48050400 - 480507ff
|
4032 | 827df9f3 | balrog | * DISPLAY RFBI 48050800 - 48050bff
|
4033 | 827df9f3 | balrog | * DISPLAY VENC 48050c00 - 48050fff
|
4034 | 827df9f3 | balrog | * DISPLAY L4 48051000 - 48051fff
|
4035 | 827df9f3 | balrog | * CAMERA Top 48052000 - 480523ff
|
4036 | 827df9f3 | balrog | * CAMERA core 48052400 - 480527ff
|
4037 | 827df9f3 | balrog | * CAMERA DMA 48052800 - 48052bff
|
4038 | 827df9f3 | balrog | * CAMERA MMU 48052c00 - 48052fff
|
4039 | 827df9f3 | balrog | * CAMERA L4 48053000 - 48053fff
|
4040 | 827df9f3 | balrog | * SDMA Mod 48056000 - 48056fff
|
4041 | 827df9f3 | balrog | * SDMA L4 48057000 - 48057fff
|
4042 | 827df9f3 | balrog | * SSI Top 48058000 - 48058fff
|
4043 | 827df9f3 | balrog | * SSI GDD 48059000 - 48059fff
|
4044 | 827df9f3 | balrog | * SSI Port1 4805a000 - 4805afff
|
4045 | 827df9f3 | balrog | * SSI Port2 4805b000 - 4805bfff
|
4046 | 827df9f3 | balrog | * SSI L4 4805c000 - 4805cfff
|
4047 | 827df9f3 | balrog | * USB Mod 4805e000 - 480fefff
|
4048 | 827df9f3 | balrog | * USB L4 4805f000 - 480fffff
|
4049 | 827df9f3 | balrog | * WIN_TRACER1 Mod 48060000 - 48060fff
|
4050 | 827df9f3 | balrog | * WIN_TRACER1 L4 48061000 - 48061fff
|
4051 | 827df9f3 | balrog | * WIN_TRACER2 Mod 48062000 - 48062fff
|
4052 | 827df9f3 | balrog | * WIN_TRACER2 L4 48063000 - 48063fff
|
4053 | 827df9f3 | balrog | * WIN_TRACER3 Mod 48064000 - 48064fff
|
4054 | 827df9f3 | balrog | * WIN_TRACER3 L4 48065000 - 48065fff
|
4055 | 827df9f3 | balrog | * WIN_TRACER4 Top 48066000 - 480660ff
|
4056 | 827df9f3 | balrog | * WIN_TRACER4 ETT 48066100 - 480661ff
|
4057 | 827df9f3 | balrog | * WIN_TRACER4 WT 48066200 - 480662ff
|
4058 | 827df9f3 | balrog | * WIN_TRACER4 L4 48067000 - 48067fff
|
4059 | 827df9f3 | balrog | * XTI Mod 48068000 - 48068fff
|
4060 | 827df9f3 | balrog | * XTI L4 48069000 - 48069fff
|
4061 | 827df9f3 | balrog | * UART1 Mod 4806a000 - 4806afff
|
4062 | 827df9f3 | balrog | * UART1 L4 4806b000 - 4806bfff
|
4063 | 827df9f3 | balrog | * UART2 Mod 4806c000 - 4806cfff
|
4064 | 827df9f3 | balrog | * UART2 L4 4806d000 - 4806dfff
|
4065 | 827df9f3 | balrog | * UART3 Mod 4806e000 - 4806efff
|
4066 | 827df9f3 | balrog | * UART3 L4 4806f000 - 4806ffff
|
4067 | 827df9f3 | balrog | * I2C1 Mod 48070000 - 48070fff
|
4068 | 827df9f3 | balrog | * I2C1 L4 48071000 - 48071fff
|
4069 | 827df9f3 | balrog | * I2C2 Mod 48072000 - 48072fff
|
4070 | 827df9f3 | balrog | * I2C2 L4 48073000 - 48073fff
|
4071 | 827df9f3 | balrog | * McBSP1 Mod 48074000 - 48074fff
|
4072 | 827df9f3 | balrog | * McBSP1 L4 48075000 - 48075fff
|
4073 | 827df9f3 | balrog | * McBSP2 Mod 48076000 - 48076fff
|
4074 | 827df9f3 | balrog | * McBSP2 L4 48077000 - 48077fff
|
4075 | 827df9f3 | balrog | * GPTIMER3 Mod 48078000 - 48078fff
|
4076 | 827df9f3 | balrog | * GPTIMER3 L4 48079000 - 48079fff
|
4077 | 827df9f3 | balrog | * GPTIMER4 Mod 4807a000 - 4807afff
|
4078 | 827df9f3 | balrog | * GPTIMER4 L4 4807b000 - 4807bfff
|
4079 | 827df9f3 | balrog | * GPTIMER5 Mod 4807c000 - 4807cfff
|
4080 | 827df9f3 | balrog | * GPTIMER5 L4 4807d000 - 4807dfff
|
4081 | 827df9f3 | balrog | * GPTIMER6 Mod 4807e000 - 4807efff
|
4082 | 827df9f3 | balrog | * GPTIMER6 L4 4807f000 - 4807ffff
|
4083 | 827df9f3 | balrog | * GPTIMER7 Mod 48080000 - 48080fff
|
4084 | 827df9f3 | balrog | * GPTIMER7 L4 48081000 - 48081fff
|
4085 | 827df9f3 | balrog | * GPTIMER8 Mod 48082000 - 48082fff
|
4086 | 827df9f3 | balrog | * GPTIMER8 L4 48083000 - 48083fff
|
4087 | 827df9f3 | balrog | * GPTIMER9 Mod 48084000 - 48084fff
|
4088 | 827df9f3 | balrog | * GPTIMER9 L4 48085000 - 48085fff
|
4089 | 827df9f3 | balrog | * GPTIMER10 Mod 48086000 - 48086fff
|
4090 | 827df9f3 | balrog | * GPTIMER10 L4 48087000 - 48087fff
|
4091 | 827df9f3 | balrog | * GPTIMER11 Mod 48088000 - 48088fff
|
4092 | 827df9f3 | balrog | * GPTIMER11 L4 48089000 - 48089fff
|
4093 | 827df9f3 | balrog | * GPTIMER12 Mod 4808a000 - 4808afff
|
4094 | 827df9f3 | balrog | * GPTIMER12 L4 4808b000 - 4808bfff
|
4095 | 827df9f3 | balrog | * EAC Mod 48090000 - 48090fff
|
4096 | 827df9f3 | balrog | * EAC L4 48091000 - 48091fff
|
4097 | 827df9f3 | balrog | * FAC Mod 48092000 - 48092fff
|
4098 | 827df9f3 | balrog | * FAC L4 48093000 - 48093fff
|
4099 | 827df9f3 | balrog | * MAILBOX Mod 48094000 - 48094fff
|
4100 | 827df9f3 | balrog | * MAILBOX L4 48095000 - 48095fff
|
4101 | 827df9f3 | balrog | * SPI1 Mod 48098000 - 48098fff
|
4102 | 827df9f3 | balrog | * SPI1 L4 48099000 - 48099fff
|
4103 | 827df9f3 | balrog | * SPI2 Mod 4809a000 - 4809afff
|
4104 | 827df9f3 | balrog | * SPI2 L4 4809b000 - 4809bfff
|
4105 | 827df9f3 | balrog | * MMC/SDIO Mod 4809c000 - 4809cfff
|
4106 | 827df9f3 | balrog | * MMC/SDIO L4 4809d000 - 4809dfff
|
4107 | 827df9f3 | balrog | * MS_PRO Mod 4809e000 - 4809efff
|
4108 | 827df9f3 | balrog | * MS_PRO L4 4809f000 - 4809ffff
|
4109 | 827df9f3 | balrog | * RNG Mod 480a0000 - 480a0fff
|
4110 | 827df9f3 | balrog | * RNG L4 480a1000 - 480a1fff
|
4111 | 827df9f3 | balrog | * DES3DES Mod 480a2000 - 480a2fff
|
4112 | 827df9f3 | balrog | * DES3DES L4 480a3000 - 480a3fff
|
4113 | 827df9f3 | balrog | * SHA1MD5 Mod 480a4000 - 480a4fff
|
4114 | 827df9f3 | balrog | * SHA1MD5 L4 480a5000 - 480a5fff
|
4115 | 827df9f3 | balrog | * AES Mod 480a6000 - 480a6fff
|
4116 | 827df9f3 | balrog | * AES L4 480a7000 - 480a7fff
|
4117 | 827df9f3 | balrog | * PKA Mod 480a8000 - 480a9fff
|
4118 | 827df9f3 | balrog | * PKA L4 480aa000 - 480aafff
|
4119 | 827df9f3 | balrog | * MG Mod 480b0000 - 480b0fff
|
4120 | 827df9f3 | balrog | * MG L4 480b1000 - 480b1fff
|
4121 | 827df9f3 | balrog | * HDQ/1-wire Mod 480b2000 - 480b2fff
|
4122 | 827df9f3 | balrog | * HDQ/1-wire L4 480b3000 - 480b3fff
|
4123 | 827df9f3 | balrog | * MPU interrupt 480fe000 - 480fefff
|
4124 | 54585ffe | balrog | * STI channel base 54000000 - 5400ffff
|
4125 | 827df9f3 | balrog | * IVA RAM 5c000000 - 5c01ffff
|
4126 | 827df9f3 | balrog | * IVA ROM 5c020000 - 5c027fff
|
4127 | 827df9f3 | balrog | * IMG_BUF_A 5c040000 - 5c040fff
|
4128 | 827df9f3 | balrog | * IMG_BUF_B 5c042000 - 5c042fff
|
4129 | 827df9f3 | balrog | * VLCDS 5c048000 - 5c0487ff
|
4130 | 827df9f3 | balrog | * IMX_COEF 5c049000 - 5c04afff
|
4131 | 827df9f3 | balrog | * IMX_CMD 5c051000 - 5c051fff
|
4132 | 827df9f3 | balrog | * VLCDQ 5c053000 - 5c0533ff
|
4133 | 827df9f3 | balrog | * VLCDH 5c054000 - 5c054fff
|
4134 | 827df9f3 | balrog | * SEQ_CMD 5c055000 - 5c055fff
|
4135 | 827df9f3 | balrog | * IMX_REG 5c056000 - 5c0560ff
|
4136 | 827df9f3 | balrog | * VLCD_REG 5c056100 - 5c0561ff
|
4137 | 827df9f3 | balrog | * SEQ_REG 5c056200 - 5c0562ff
|
4138 | 827df9f3 | balrog | * IMG_BUF_REG 5c056300 - 5c0563ff
|
4139 | 827df9f3 | balrog | * SEQIRQ_REG 5c056400 - 5c0564ff
|
4140 | 827df9f3 | balrog | * OCP_REG 5c060000 - 5c060fff
|
4141 | 827df9f3 | balrog | * SYSC_REG 5c070000 - 5c070fff
|
4142 | 827df9f3 | balrog | * MMU_REG 5d000000 - 5d000fff
|
4143 | 827df9f3 | balrog | * sDMA R 68000400 - 680005ff
|
4144 | 827df9f3 | balrog | * sDMA W 68000600 - 680007ff
|
4145 | 827df9f3 | balrog | * Display Control 68000800 - 680009ff
|
4146 | 827df9f3 | balrog | * DSP subsystem 68000a00 - 68000bff
|
4147 | 827df9f3 | balrog | * MPU subsystem 68000c00 - 68000dff
|
4148 | 827df9f3 | balrog | * IVA subsystem 68001000 - 680011ff
|
4149 | 827df9f3 | balrog | * USB 68001200 - 680013ff
|
4150 | 827df9f3 | balrog | * Camera 68001400 - 680015ff
|
4151 | 827df9f3 | balrog | * VLYNQ (firewall) 68001800 - 68001bff
|
4152 | 827df9f3 | balrog | * VLYNQ 68001e00 - 68001fff
|
4153 | 827df9f3 | balrog | * SSI 68002000 - 680021ff
|
4154 | 827df9f3 | balrog | * L4 68002400 - 680025ff
|
4155 | 827df9f3 | balrog | * DSP (firewall) 68002800 - 68002bff
|
4156 | 827df9f3 | balrog | * DSP subsystem 68002e00 - 68002fff
|
4157 | 827df9f3 | balrog | * IVA (firewall) 68003000 - 680033ff
|
4158 | 827df9f3 | balrog | * IVA 68003600 - 680037ff
|
4159 | 827df9f3 | balrog | * GFX 68003a00 - 68003bff
|
4160 | 827df9f3 | balrog | * CMDWR emulation 68003c00 - 68003dff
|
4161 | 827df9f3 | balrog | * SMS 68004000 - 680041ff
|
4162 | 827df9f3 | balrog | * OCM 68004200 - 680043ff
|
4163 | 827df9f3 | balrog | * GPMC 68004400 - 680045ff
|
4164 | 827df9f3 | balrog | * RAM (firewall) 68005000 - 680053ff
|
4165 | 827df9f3 | balrog | * RAM (err login) 68005400 - 680057ff
|
4166 | 827df9f3 | balrog | * ROM (firewall) 68005800 - 68005bff
|
4167 | 827df9f3 | balrog | * ROM (err login) 68005c00 - 68005fff
|
4168 | 827df9f3 | balrog | * GPMC (firewall) 68006000 - 680063ff
|
4169 | 827df9f3 | balrog | * GPMC (err login) 68006400 - 680067ff
|
4170 | 827df9f3 | balrog | * SMS (err login) 68006c00 - 68006fff
|
4171 | 827df9f3 | balrog | * SMS registers 68008000 - 68008fff
|
4172 | 827df9f3 | balrog | * SDRC registers 68009000 - 68009fff
|
4173 | 827df9f3 | balrog | * GPMC registers 6800a000 6800afff
|
4174 | 827df9f3 | balrog | */
|
4175 | 827df9f3 | balrog | |
4176 | 827df9f3 | balrog | qemu_register_reset(omap2_mpu_reset, s); |
4177 | 827df9f3 | balrog | |
4178 | 827df9f3 | balrog | return s;
|
4179 | 827df9f3 | balrog | } |