root / tcg / tcg-opc.h @ c596defd
History | View | Annotate | Download (7.5 kB)
1 | c896fe29 | bellard | /*
|
---|---|---|---|
2 | c896fe29 | bellard | * Tiny Code Generator for QEMU
|
3 | c896fe29 | bellard | *
|
4 | c896fe29 | bellard | * Copyright (c) 2008 Fabrice Bellard
|
5 | c896fe29 | bellard | *
|
6 | c896fe29 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | c896fe29 | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | c896fe29 | bellard | * in the Software without restriction, including without limitation the rights
|
9 | c896fe29 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | c896fe29 | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | c896fe29 | bellard | * furnished to do so, subject to the following conditions:
|
12 | c896fe29 | bellard | *
|
13 | c896fe29 | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | c896fe29 | bellard | * all copies or substantial portions of the Software.
|
15 | c896fe29 | bellard | *
|
16 | c896fe29 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | c896fe29 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | c896fe29 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | c896fe29 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | c896fe29 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | c896fe29 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | c896fe29 | bellard | * THE SOFTWARE.
|
23 | c896fe29 | bellard | */
|
24 | bf6247fb | blueswir1 | #ifdef CONFIG_DYNGEN_OP
|
25 | c896fe29 | bellard | #include "dyngen-opc.h" |
26 | cf2be984 | blueswir1 | #endif
|
27 | c896fe29 | bellard | |
28 | c896fe29 | bellard | #ifndef DEF2
|
29 | c896fe29 | bellard | #define DEF2(name, oargs, iargs, cargs, flags) DEF(name, oargs + iargs + cargs, 0) |
30 | c896fe29 | bellard | #endif
|
31 | c896fe29 | bellard | |
32 | c896fe29 | bellard | /* predefined ops */
|
33 | c896fe29 | bellard | DEF2(end, 0, 0, 0, 0) /* must be kept first */ |
34 | c896fe29 | bellard | DEF2(nop, 0, 0, 0, 0) |
35 | c896fe29 | bellard | DEF2(nop1, 0, 0, 1, 0) |
36 | c896fe29 | bellard | DEF2(nop2, 0, 0, 2, 0) |
37 | c896fe29 | bellard | DEF2(nop3, 0, 0, 3, 0) |
38 | c896fe29 | bellard | DEF2(nopn, 0, 0, 1, 0) /* variable number of parameters */ |
39 | c896fe29 | bellard | |
40 | 5ff9d6a4 | bellard | DEF2(discard, 1, 0, 0, 0) |
41 | 5ff9d6a4 | bellard | |
42 | c896fe29 | bellard | DEF2(set_label, 0, 0, 1, 0) |
43 | 5ff9d6a4 | bellard | DEF2(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */ |
44 | 5ff9d6a4 | bellard | DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
45 | 5ff9d6a4 | bellard | DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
46 | c896fe29 | bellard | |
47 | c896fe29 | bellard | DEF2(mov_i32, 1, 1, 0, 0) |
48 | c896fe29 | bellard | DEF2(movi_i32, 1, 0, 1, 0) |
49 | c896fe29 | bellard | /* load/store */
|
50 | c896fe29 | bellard | DEF2(ld8u_i32, 1, 1, 1, 0) |
51 | c896fe29 | bellard | DEF2(ld8s_i32, 1, 1, 1, 0) |
52 | c896fe29 | bellard | DEF2(ld16u_i32, 1, 1, 1, 0) |
53 | c896fe29 | bellard | DEF2(ld16s_i32, 1, 1, 1, 0) |
54 | c896fe29 | bellard | DEF2(ld_i32, 1, 1, 1, 0) |
55 | 5ff9d6a4 | bellard | DEF2(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
56 | 5ff9d6a4 | bellard | DEF2(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
57 | 5ff9d6a4 | bellard | DEF2(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
58 | c896fe29 | bellard | /* arith */
|
59 | c896fe29 | bellard | DEF2(add_i32, 1, 2, 0, 0) |
60 | c896fe29 | bellard | DEF2(sub_i32, 1, 2, 0, 0) |
61 | c896fe29 | bellard | DEF2(mul_i32, 1, 2, 0, 0) |
62 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_div_i32
|
63 | c896fe29 | bellard | DEF2(div_i32, 1, 2, 0, 0) |
64 | c896fe29 | bellard | DEF2(divu_i32, 1, 2, 0, 0) |
65 | c896fe29 | bellard | DEF2(rem_i32, 1, 2, 0, 0) |
66 | c896fe29 | bellard | DEF2(remu_i32, 1, 2, 0, 0) |
67 | c896fe29 | bellard | #else
|
68 | c896fe29 | bellard | DEF2(div2_i32, 2, 3, 0, 0) |
69 | c896fe29 | bellard | DEF2(divu2_i32, 2, 3, 0, 0) |
70 | c896fe29 | bellard | #endif
|
71 | c896fe29 | bellard | DEF2(and_i32, 1, 2, 0, 0) |
72 | c896fe29 | bellard | DEF2(or_i32, 1, 2, 0, 0) |
73 | c896fe29 | bellard | DEF2(xor_i32, 1, 2, 0, 0) |
74 | c896fe29 | bellard | /* shifts */
|
75 | c896fe29 | bellard | DEF2(shl_i32, 1, 2, 0, 0) |
76 | c896fe29 | bellard | DEF2(shr_i32, 1, 2, 0, 0) |
77 | c896fe29 | bellard | DEF2(sar_i32, 1, 2, 0, 0) |
78 | c896fe29 | bellard | |
79 | 5ff9d6a4 | bellard | DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
80 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 32 |
81 | c896fe29 | bellard | DEF2(add2_i32, 2, 4, 0, 0) |
82 | c896fe29 | bellard | DEF2(sub2_i32, 2, 4, 0, 0) |
83 | 5ff9d6a4 | bellard | DEF2(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
84 | c896fe29 | bellard | DEF2(mulu2_i32, 2, 2, 0, 0) |
85 | c896fe29 | bellard | #endif
|
86 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext8s_i32
|
87 | c896fe29 | bellard | DEF2(ext8s_i32, 1, 1, 0, 0) |
88 | c896fe29 | bellard | #endif
|
89 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext16s_i32
|
90 | c896fe29 | bellard | DEF2(ext16s_i32, 1, 1, 0, 0) |
91 | c896fe29 | bellard | #endif
|
92 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_bswap_i32
|
93 | c896fe29 | bellard | DEF2(bswap_i32, 1, 1, 0, 0) |
94 | c896fe29 | bellard | #endif
|
95 | c896fe29 | bellard | |
96 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 64 |
97 | c896fe29 | bellard | DEF2(mov_i64, 1, 1, 0, 0) |
98 | c896fe29 | bellard | DEF2(movi_i64, 1, 0, 1, 0) |
99 | c896fe29 | bellard | /* load/store */
|
100 | c896fe29 | bellard | DEF2(ld8u_i64, 1, 1, 1, 0) |
101 | c896fe29 | bellard | DEF2(ld8s_i64, 1, 1, 1, 0) |
102 | c896fe29 | bellard | DEF2(ld16u_i64, 1, 1, 1, 0) |
103 | c896fe29 | bellard | DEF2(ld16s_i64, 1, 1, 1, 0) |
104 | c896fe29 | bellard | DEF2(ld32u_i64, 1, 1, 1, 0) |
105 | c896fe29 | bellard | DEF2(ld32s_i64, 1, 1, 1, 0) |
106 | c896fe29 | bellard | DEF2(ld_i64, 1, 1, 1, 0) |
107 | 5ff9d6a4 | bellard | DEF2(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
108 | 5ff9d6a4 | bellard | DEF2(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
109 | 5ff9d6a4 | bellard | DEF2(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
110 | 5ff9d6a4 | bellard | DEF2(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
111 | c896fe29 | bellard | /* arith */
|
112 | c896fe29 | bellard | DEF2(add_i64, 1, 2, 0, 0) |
113 | c896fe29 | bellard | DEF2(sub_i64, 1, 2, 0, 0) |
114 | c896fe29 | bellard | DEF2(mul_i64, 1, 2, 0, 0) |
115 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_div_i64
|
116 | c896fe29 | bellard | DEF2(div_i64, 1, 2, 0, 0) |
117 | c896fe29 | bellard | DEF2(divu_i64, 1, 2, 0, 0) |
118 | c896fe29 | bellard | DEF2(rem_i64, 1, 2, 0, 0) |
119 | c896fe29 | bellard | DEF2(remu_i64, 1, 2, 0, 0) |
120 | c896fe29 | bellard | #else
|
121 | c896fe29 | bellard | DEF2(div2_i64, 2, 3, 0, 0) |
122 | c896fe29 | bellard | DEF2(divu2_i64, 2, 3, 0, 0) |
123 | c896fe29 | bellard | #endif
|
124 | c896fe29 | bellard | DEF2(and_i64, 1, 2, 0, 0) |
125 | c896fe29 | bellard | DEF2(or_i64, 1, 2, 0, 0) |
126 | c896fe29 | bellard | DEF2(xor_i64, 1, 2, 0, 0) |
127 | c896fe29 | bellard | /* shifts */
|
128 | c896fe29 | bellard | DEF2(shl_i64, 1, 2, 0, 0) |
129 | c896fe29 | bellard | DEF2(shr_i64, 1, 2, 0, 0) |
130 | c896fe29 | bellard | DEF2(sar_i64, 1, 2, 0, 0) |
131 | c896fe29 | bellard | |
132 | 5ff9d6a4 | bellard | DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
133 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext8s_i64
|
134 | c896fe29 | bellard | DEF2(ext8s_i64, 1, 1, 0, 0) |
135 | c896fe29 | bellard | #endif
|
136 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext16s_i64
|
137 | c896fe29 | bellard | DEF2(ext16s_i64, 1, 1, 0, 0) |
138 | c896fe29 | bellard | #endif
|
139 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext32s_i64
|
140 | c896fe29 | bellard | DEF2(ext32s_i64, 1, 1, 0, 0) |
141 | c896fe29 | bellard | #endif
|
142 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_bswap_i64
|
143 | c896fe29 | bellard | DEF2(bswap_i64, 1, 1, 0, 0) |
144 | c896fe29 | bellard | #endif
|
145 | c896fe29 | bellard | #endif
|
146 | 390efc54 | pbrook | #ifdef TCG_TARGET_HAS_neg_i32
|
147 | 390efc54 | pbrook | DEF2(neg_i32, 1, 1, 0, 0) |
148 | 390efc54 | pbrook | #endif
|
149 | 390efc54 | pbrook | #ifdef TCG_TARGET_HAS_neg_i64
|
150 | 390efc54 | pbrook | DEF2(neg_i64, 1, 1, 0, 0) |
151 | 390efc54 | pbrook | #endif
|
152 | c896fe29 | bellard | |
153 | c896fe29 | bellard | /* QEMU specific */
|
154 | 7e4597d7 | bellard | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
155 | 7e4597d7 | bellard | DEF2(debug_insn_start, 0, 0, 2, 0) |
156 | 7e4597d7 | bellard | #else
|
157 | 7e4597d7 | bellard | DEF2(debug_insn_start, 0, 0, 1, 0) |
158 | 7e4597d7 | bellard | #endif
|
159 | 5ff9d6a4 | bellard | DEF2(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
160 | 5ff9d6a4 | bellard | DEF2(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
161 | c896fe29 | bellard | /* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
|
162 | c896fe29 | bellard | constants must be defined */
|
163 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 32 |
164 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
165 | 5ff9d6a4 | bellard | DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
166 | c896fe29 | bellard | #else
|
167 | 5ff9d6a4 | bellard | DEF2(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
168 | c896fe29 | bellard | #endif
|
169 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
170 | 5ff9d6a4 | bellard | DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
171 | c896fe29 | bellard | #else
|
172 | 5ff9d6a4 | bellard | DEF2(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
173 | c896fe29 | bellard | #endif
|
174 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
175 | 5ff9d6a4 | bellard | DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
176 | c896fe29 | bellard | #else
|
177 | 5ff9d6a4 | bellard | DEF2(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
178 | c896fe29 | bellard | #endif
|
179 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
180 | 5ff9d6a4 | bellard | DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
181 | c896fe29 | bellard | #else
|
182 | 5ff9d6a4 | bellard | DEF2(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
183 | c896fe29 | bellard | #endif
|
184 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
185 | 5ff9d6a4 | bellard | DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
186 | c896fe29 | bellard | #else
|
187 | 5ff9d6a4 | bellard | DEF2(qemu_ld32u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
188 | c896fe29 | bellard | #endif
|
189 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
190 | 5ff9d6a4 | bellard | DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
191 | c896fe29 | bellard | #else
|
192 | 5ff9d6a4 | bellard | DEF2(qemu_ld32s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
193 | c896fe29 | bellard | #endif
|
194 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
195 | 5ff9d6a4 | bellard | DEF2(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
196 | c896fe29 | bellard | #else
|
197 | 5ff9d6a4 | bellard | DEF2(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
198 | c896fe29 | bellard | #endif
|
199 | c896fe29 | bellard | |
200 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
201 | 5ff9d6a4 | bellard | DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
202 | c896fe29 | bellard | #else
|
203 | 5ff9d6a4 | bellard | DEF2(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
204 | c896fe29 | bellard | #endif
|
205 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
206 | 5ff9d6a4 | bellard | DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
207 | c896fe29 | bellard | #else
|
208 | 5ff9d6a4 | bellard | DEF2(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
209 | c896fe29 | bellard | #endif
|
210 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
211 | 5ff9d6a4 | bellard | DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
212 | c896fe29 | bellard | #else
|
213 | 5ff9d6a4 | bellard | DEF2(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
214 | c896fe29 | bellard | #endif
|
215 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
216 | 5ff9d6a4 | bellard | DEF2(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
217 | c896fe29 | bellard | #else
|
218 | 5ff9d6a4 | bellard | DEF2(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
219 | c896fe29 | bellard | #endif
|
220 | c896fe29 | bellard | |
221 | c896fe29 | bellard | #else /* TCG_TARGET_REG_BITS == 32 */ |
222 | c896fe29 | bellard | |
223 | 5ff9d6a4 | bellard | DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
224 | 5ff9d6a4 | bellard | DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
225 | 5ff9d6a4 | bellard | DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
226 | 5ff9d6a4 | bellard | DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
227 | 5ff9d6a4 | bellard | DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
228 | 5ff9d6a4 | bellard | DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
229 | 5ff9d6a4 | bellard | DEF2(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
230 | c896fe29 | bellard | |
231 | 5ff9d6a4 | bellard | DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
232 | 5ff9d6a4 | bellard | DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
233 | 5ff9d6a4 | bellard | DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
234 | 5ff9d6a4 | bellard | DEF2(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
235 | c896fe29 | bellard | |
236 | c896fe29 | bellard | #endif /* TCG_TARGET_REG_BITS != 32 */ |
237 | c896fe29 | bellard | |
238 | c896fe29 | bellard | #undef DEF2 |