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/*
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* QEMU ESP/NCR53C9x emulation
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*
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* Copyright (c) 2005-2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "scsi-disk.h" |
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#include "scsi.h" |
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/* debug ESP card */
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//#define DEBUG_ESP
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/*
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* On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
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* also produced as NCR89C100. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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* and
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
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*/
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#ifdef DEBUG_ESP
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#define DPRINTF(fmt, args...) \
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do { printf("ESP: " fmt , ##args); } while (0) |
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#else
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#define DPRINTF(fmt, args...) do {} while (0) |
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#endif
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#define ESP_REGS 16 |
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#define TI_BUFSZ 32 |
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typedef struct ESPState ESPState; |
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struct ESPState {
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uint32_t it_shift; |
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qemu_irq irq; |
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uint8_t rregs[ESP_REGS]; |
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uint8_t wregs[ESP_REGS]; |
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int32_t ti_size; |
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uint32_t ti_rptr, ti_wptr; |
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uint8_t ti_buf[TI_BUFSZ]; |
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uint32_t sense; |
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uint32_t dma; |
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SCSIDevice *scsi_dev[ESP_MAX_DEVS]; |
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SCSIDevice *current_dev; |
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uint8_t cmdbuf[TI_BUFSZ]; |
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uint32_t cmdlen; |
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uint32_t do_cmd; |
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/* The amount of data left in the current DMA transfer. */
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uint32_t dma_left; |
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/* The size of the current DMA transfer. Zero if no transfer is in
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progress. */
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uint32_t dma_counter; |
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uint8_t *async_buf; |
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uint32_t async_len; |
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espdma_memory_read_write dma_memory_read; |
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espdma_memory_read_write dma_memory_write; |
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void *dma_opaque;
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}; |
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#define ESP_TCLO 0x0 |
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#define ESP_TCMID 0x1 |
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#define ESP_FIFO 0x2 |
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#define ESP_CMD 0x3 |
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#define ESP_RSTAT 0x4 |
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#define ESP_WBUSID 0x4 |
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#define ESP_RINTR 0x5 |
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#define ESP_WSEL 0x5 |
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#define ESP_RSEQ 0x6 |
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#define ESP_WSYNTP 0x6 |
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#define ESP_RFLAGS 0x7 |
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#define ESP_WSYNO 0x7 |
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#define ESP_CFG1 0x8 |
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#define ESP_RRES1 0x9 |
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#define ESP_WCCF 0x9 |
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#define ESP_RRES2 0xa |
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#define ESP_WTEST 0xa |
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#define ESP_CFG2 0xb |
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#define ESP_CFG3 0xc |
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#define ESP_RES3 0xd |
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#define ESP_TCHI 0xe |
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#define ESP_RES4 0xf |
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|
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#define CMD_DMA 0x80 |
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#define CMD_CMD 0x7f |
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|
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#define CMD_NOP 0x00 |
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#define CMD_FLUSH 0x01 |
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#define CMD_RESET 0x02 |
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#define CMD_BUSRESET 0x03 |
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#define CMD_TI 0x10 |
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#define CMD_ICCS 0x11 |
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#define CMD_MSGACC 0x12 |
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#define CMD_SATN 0x1a |
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#define CMD_SELATN 0x42 |
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#define CMD_SELATNS 0x43 |
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#define CMD_ENSEL 0x44 |
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#define STAT_DO 0x00 |
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#define STAT_DI 0x01 |
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#define STAT_CD 0x02 |
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#define STAT_ST 0x03 |
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#define STAT_MI 0x06 |
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#define STAT_MO 0x07 |
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#define STAT_PIO_MASK 0x06 |
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#define STAT_TC 0x10 |
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#define STAT_PE 0x20 |
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#define STAT_GE 0x40 |
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#define STAT_INT 0x80 |
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#define INTR_FC 0x08 |
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#define INTR_BS 0x10 |
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#define INTR_DC 0x20 |
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#define INTR_RST 0x80 |
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#define SEQ_0 0x0 |
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#define SEQ_CD 0x4 |
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#define CFG1_RESREPT 0x40 |
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#define CFG2_MASK 0x15 |
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#define TCHI_FAS100A 0x4 |
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static void esp_raise_irq(ESPState *s) |
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{ |
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if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
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s->rregs[ESP_RSTAT] |= STAT_INT; |
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qemu_irq_raise(s->irq); |
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} |
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} |
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static void esp_lower_irq(ESPState *s) |
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{ |
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if (s->rregs[ESP_RSTAT] & STAT_INT) {
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s->rregs[ESP_RSTAT] &= ~STAT_INT; |
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qemu_irq_lower(s->irq); |
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} |
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} |
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static uint32_t get_cmd(ESPState *s, uint8_t *buf)
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{ |
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uint32_t dmalen; |
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int target;
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dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
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target = s->wregs[ESP_WBUSID] & 7;
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DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
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if (s->dma) {
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s->dma_memory_read(s->dma_opaque, buf, dmalen); |
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} else {
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buf[0] = 0; |
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memcpy(&buf[1], s->ti_buf, dmalen);
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dmalen++; |
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} |
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s->ti_size = 0;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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if (s->current_dev) {
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/* Started a new command before the old one finished. Cancel it. */
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s->current_dev->cancel_io(s->current_dev, 0);
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s->async_len = 0;
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} |
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if (target >= ESP_MAX_DEVS || !s->scsi_dev[target]) {
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// No such drive
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s->rregs[ESP_RSTAT] = 0;
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s->rregs[ESP_RINTR] = INTR_DC; |
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s->rregs[ESP_RSEQ] = SEQ_0; |
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esp_raise_irq(s); |
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return 0; |
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} |
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s->current_dev = s->scsi_dev[target]; |
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return dmalen;
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} |
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static void do_cmd(ESPState *s, uint8_t *buf) |
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{ |
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int32_t datalen; |
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int lun;
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DPRINTF("do_cmd: busid 0x%x\n", buf[0]); |
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lun = buf[0] & 7; |
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datalen = s->current_dev->send_command(s->current_dev, 0, &buf[1], lun); |
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s->ti_size = datalen; |
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if (datalen != 0) { |
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s->rregs[ESP_RSTAT] = STAT_TC; |
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s->dma_left = 0;
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s->dma_counter = 0;
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if (datalen > 0) { |
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s->rregs[ESP_RSTAT] |= STAT_DI; |
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s->current_dev->read_data(s->current_dev, 0);
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} else {
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s->rregs[ESP_RSTAT] |= STAT_DO; |
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s->current_dev->write_data(s->current_dev, 0);
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} |
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} |
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
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s->rregs[ESP_RSEQ] = SEQ_CD; |
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esp_raise_irq(s); |
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} |
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static void handle_satn(ESPState *s) |
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{ |
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uint8_t buf[32];
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int len;
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len = get_cmd(s, buf); |
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if (len)
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do_cmd(s, buf); |
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} |
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static void handle_satn_stop(ESPState *s) |
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{ |
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s->cmdlen = get_cmd(s, s->cmdbuf); |
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if (s->cmdlen) {
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DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
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s->do_cmd = 1;
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s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
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s->rregs[ESP_RSEQ] = SEQ_CD; |
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esp_raise_irq(s); |
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} |
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} |
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static void write_response(ESPState *s) |
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{ |
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DPRINTF("Transfer status (sense=%d)\n", s->sense);
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s->ti_buf[0] = s->sense;
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s->ti_buf[1] = 0; |
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if (s->dma) {
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s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
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s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; |
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
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s->rregs[ESP_RSEQ] = SEQ_CD; |
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} else {
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s->ti_size = 2;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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s->rregs[ESP_RFLAGS] = 2;
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} |
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esp_raise_irq(s); |
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} |
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static void esp_dma_done(ESPState *s) |
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{ |
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s->rregs[ESP_RSTAT] |= STAT_TC; |
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s->rregs[ESP_RINTR] = INTR_BS; |
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s->rregs[ESP_RSEQ] = 0;
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s->rregs[ESP_RFLAGS] = 0;
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s->rregs[ESP_TCLO] = 0;
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s->rregs[ESP_TCMID] = 0;
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esp_raise_irq(s); |
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} |
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static void esp_do_dma(ESPState *s) |
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{ |
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uint32_t len; |
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int to_device;
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to_device = (s->ti_size < 0);
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len = s->dma_left; |
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if (s->do_cmd) {
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DPRINTF("command len %d + %d\n", s->cmdlen, len);
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s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); |
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s->ti_size = 0;
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s->cmdlen = 0;
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s->do_cmd = 0;
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do_cmd(s, s->cmdbuf); |
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return;
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} |
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if (s->async_len == 0) { |
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/* Defer until data is available. */
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return;
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} |
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if (len > s->async_len) {
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len = s->async_len; |
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} |
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if (to_device) {
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s->dma_memory_read(s->dma_opaque, s->async_buf, len); |
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} else {
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s->dma_memory_write(s->dma_opaque, s->async_buf, len); |
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} |
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s->dma_left -= len; |
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s->async_buf += len; |
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s->async_len -= len; |
310 |
if (to_device)
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s->ti_size += len; |
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else
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s->ti_size -= len; |
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if (s->async_len == 0) { |
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if (to_device) {
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// ti_size is negative
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s->current_dev->write_data(s->current_dev, 0);
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} else {
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s->current_dev->read_data(s->current_dev, 0);
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/* If there is still data to be read from the device then
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complete the DMA operation immeriately. Otherwise defer
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until the scsi layer has completed. */
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if (s->dma_left == 0 && s->ti_size > 0) { |
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esp_dma_done(s); |
325 |
} |
326 |
} |
327 |
} else {
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/* Partially filled a scsi buffer. Complete immediately. */
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esp_dma_done(s); |
330 |
} |
331 |
} |
332 |
|
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static void esp_command_complete(void *opaque, int reason, uint32_t tag, |
334 |
uint32_t arg) |
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{ |
336 |
ESPState *s = (ESPState *)opaque; |
337 |
|
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if (reason == SCSI_REASON_DONE) {
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DPRINTF("SCSI Command complete\n");
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if (s->ti_size != 0) |
341 |
DPRINTF("SCSI command completed unexpectedly\n");
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s->ti_size = 0;
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s->dma_left = 0;
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s->async_len = 0;
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if (arg)
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DPRINTF("Command failed\n");
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s->sense = arg; |
348 |
s->rregs[ESP_RSTAT] = STAT_ST; |
349 |
esp_dma_done(s); |
350 |
s->current_dev = NULL;
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} else {
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DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
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s->async_len = arg; |
354 |
s->async_buf = s->current_dev->get_buf(s->current_dev, 0);
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355 |
if (s->dma_left) {
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356 |
esp_do_dma(s); |
357 |
} else if (s->dma_counter != 0 && s->ti_size <= 0) { |
358 |
/* If this was the last part of a DMA transfer then the
|
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completion interrupt is deferred to here. */
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360 |
esp_dma_done(s); |
361 |
} |
362 |
} |
363 |
} |
364 |
|
365 |
static void handle_ti(ESPState *s) |
366 |
{ |
367 |
uint32_t dmalen, minlen; |
368 |
|
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dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
|
370 |
if (dmalen==0) { |
371 |
dmalen=0x10000;
|
372 |
} |
373 |
s->dma_counter = dmalen; |
374 |
|
375 |
if (s->do_cmd)
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376 |
minlen = (dmalen < 32) ? dmalen : 32; |
377 |
else if (s->ti_size < 0) |
378 |
minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; |
379 |
else
|
380 |
minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; |
381 |
DPRINTF("Transfer Information len %d\n", minlen);
|
382 |
if (s->dma) {
|
383 |
s->dma_left = minlen; |
384 |
s->rregs[ESP_RSTAT] &= ~STAT_TC; |
385 |
esp_do_dma(s); |
386 |
} else if (s->do_cmd) { |
387 |
DPRINTF("command len %d\n", s->cmdlen);
|
388 |
s->ti_size = 0;
|
389 |
s->cmdlen = 0;
|
390 |
s->do_cmd = 0;
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391 |
do_cmd(s, s->cmdbuf); |
392 |
return;
|
393 |
} |
394 |
} |
395 |
|
396 |
static void esp_reset(void *opaque) |
397 |
{ |
398 |
ESPState *s = opaque; |
399 |
|
400 |
esp_lower_irq(s); |
401 |
|
402 |
memset(s->rregs, 0, ESP_REGS);
|
403 |
memset(s->wregs, 0, ESP_REGS);
|
404 |
s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a
|
405 |
s->ti_size = 0;
|
406 |
s->ti_rptr = 0;
|
407 |
s->ti_wptr = 0;
|
408 |
s->dma = 0;
|
409 |
s->do_cmd = 0;
|
410 |
} |
411 |
|
412 |
static void parent_esp_reset(void *opaque, int irq, int level) |
413 |
{ |
414 |
if (level)
|
415 |
esp_reset(opaque); |
416 |
} |
417 |
|
418 |
static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
419 |
{ |
420 |
ESPState *s = opaque; |
421 |
uint32_t saddr; |
422 |
|
423 |
saddr = (addr >> s->it_shift) & (ESP_REGS - 1);
|
424 |
DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
|
425 |
switch (saddr) {
|
426 |
case ESP_FIFO:
|
427 |
if (s->ti_size > 0) { |
428 |
s->ti_size--; |
429 |
if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { |
430 |
/* Data in/out. */
|
431 |
fprintf(stderr, "esp: PIO data read not implemented\n");
|
432 |
s->rregs[ESP_FIFO] = 0;
|
433 |
} else {
|
434 |
s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; |
435 |
} |
436 |
esp_raise_irq(s); |
437 |
} |
438 |
if (s->ti_size == 0) { |
439 |
s->ti_rptr = 0;
|
440 |
s->ti_wptr = 0;
|
441 |
} |
442 |
break;
|
443 |
case ESP_RINTR:
|
444 |
// Clear interrupt/error status bits
|
445 |
s->rregs[ESP_RSTAT] &= ~(STAT_GE | STAT_PE); |
446 |
esp_lower_irq(s); |
447 |
break;
|
448 |
default:
|
449 |
break;
|
450 |
} |
451 |
return s->rregs[saddr];
|
452 |
} |
453 |
|
454 |
static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
455 |
{ |
456 |
ESPState *s = opaque; |
457 |
uint32_t saddr; |
458 |
|
459 |
saddr = (addr >> s->it_shift) & (ESP_REGS - 1);
|
460 |
DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
|
461 |
val); |
462 |
switch (saddr) {
|
463 |
case ESP_TCLO:
|
464 |
case ESP_TCMID:
|
465 |
s->rregs[ESP_RSTAT] &= ~STAT_TC; |
466 |
break;
|
467 |
case ESP_FIFO:
|
468 |
if (s->do_cmd) {
|
469 |
s->cmdbuf[s->cmdlen++] = val & 0xff;
|
470 |
} else if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { |
471 |
uint8_t buf; |
472 |
buf = val & 0xff;
|
473 |
s->ti_size--; |
474 |
fprintf(stderr, "esp: PIO data write not implemented\n");
|
475 |
} else {
|
476 |
s->ti_size++; |
477 |
s->ti_buf[s->ti_wptr++] = val & 0xff;
|
478 |
} |
479 |
break;
|
480 |
case ESP_CMD:
|
481 |
s->rregs[saddr] = val; |
482 |
if (val & CMD_DMA) {
|
483 |
s->dma = 1;
|
484 |
/* Reload DMA counter. */
|
485 |
s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO]; |
486 |
s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID]; |
487 |
} else {
|
488 |
s->dma = 0;
|
489 |
} |
490 |
switch(val & CMD_CMD) {
|
491 |
case CMD_NOP:
|
492 |
DPRINTF("NOP (%2.2x)\n", val);
|
493 |
break;
|
494 |
case CMD_FLUSH:
|
495 |
DPRINTF("Flush FIFO (%2.2x)\n", val);
|
496 |
//s->ti_size = 0;
|
497 |
s->rregs[ESP_RINTR] = INTR_FC; |
498 |
s->rregs[ESP_RSEQ] = 0;
|
499 |
break;
|
500 |
case CMD_RESET:
|
501 |
DPRINTF("Chip reset (%2.2x)\n", val);
|
502 |
esp_reset(s); |
503 |
break;
|
504 |
case CMD_BUSRESET:
|
505 |
DPRINTF("Bus reset (%2.2x)\n", val);
|
506 |
s->rregs[ESP_RINTR] = INTR_RST; |
507 |
if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
|
508 |
esp_raise_irq(s); |
509 |
} |
510 |
break;
|
511 |
case CMD_TI:
|
512 |
handle_ti(s); |
513 |
break;
|
514 |
case CMD_ICCS:
|
515 |
DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
|
516 |
write_response(s); |
517 |
break;
|
518 |
case CMD_MSGACC:
|
519 |
DPRINTF("Message Accepted (%2.2x)\n", val);
|
520 |
write_response(s); |
521 |
s->rregs[ESP_RINTR] = INTR_DC; |
522 |
s->rregs[ESP_RSEQ] = 0;
|
523 |
break;
|
524 |
case CMD_SATN:
|
525 |
DPRINTF("Set ATN (%2.2x)\n", val);
|
526 |
break;
|
527 |
case CMD_SELATN:
|
528 |
DPRINTF("Set ATN (%2.2x)\n", val);
|
529 |
handle_satn(s); |
530 |
break;
|
531 |
case CMD_SELATNS:
|
532 |
DPRINTF("Set ATN & stop (%2.2x)\n", val);
|
533 |
handle_satn_stop(s); |
534 |
break;
|
535 |
case CMD_ENSEL:
|
536 |
DPRINTF("Enable selection (%2.2x)\n", val);
|
537 |
break;
|
538 |
default:
|
539 |
DPRINTF("Unhandled ESP command (%2.2x)\n", val);
|
540 |
break;
|
541 |
} |
542 |
break;
|
543 |
case ESP_WBUSID ... ESP_WSYNO:
|
544 |
break;
|
545 |
case ESP_CFG1:
|
546 |
s->rregs[saddr] = val; |
547 |
break;
|
548 |
case ESP_WCCF ... ESP_WTEST:
|
549 |
break;
|
550 |
case ESP_CFG2:
|
551 |
s->rregs[saddr] = val & CFG2_MASK; |
552 |
break;
|
553 |
case ESP_CFG3 ... ESP_RES4:
|
554 |
s->rregs[saddr] = val; |
555 |
break;
|
556 |
default:
|
557 |
break;
|
558 |
} |
559 |
s->wregs[saddr] = val; |
560 |
} |
561 |
|
562 |
static CPUReadMemoryFunc *esp_mem_read[3] = { |
563 |
esp_mem_readb, |
564 |
NULL,
|
565 |
NULL,
|
566 |
}; |
567 |
|
568 |
static CPUWriteMemoryFunc *esp_mem_write[3] = { |
569 |
esp_mem_writeb, |
570 |
NULL,
|
571 |
NULL,
|
572 |
}; |
573 |
|
574 |
static void esp_save(QEMUFile *f, void *opaque) |
575 |
{ |
576 |
ESPState *s = opaque; |
577 |
|
578 |
qemu_put_buffer(f, s->rregs, ESP_REGS); |
579 |
qemu_put_buffer(f, s->wregs, ESP_REGS); |
580 |
qemu_put_be32s(f, (uint32_t *)&s->ti_size); |
581 |
qemu_put_be32s(f, &s->ti_rptr); |
582 |
qemu_put_be32s(f, &s->ti_wptr); |
583 |
qemu_put_buffer(f, s->ti_buf, TI_BUFSZ); |
584 |
qemu_put_be32s(f, &s->sense); |
585 |
qemu_put_be32s(f, &s->dma); |
586 |
qemu_put_buffer(f, s->cmdbuf, TI_BUFSZ); |
587 |
qemu_put_be32s(f, &s->cmdlen); |
588 |
qemu_put_be32s(f, &s->do_cmd); |
589 |
qemu_put_be32s(f, &s->dma_left); |
590 |
// There should be no transfers in progress, so dma_counter is not saved
|
591 |
} |
592 |
|
593 |
static int esp_load(QEMUFile *f, void *opaque, int version_id) |
594 |
{ |
595 |
ESPState *s = opaque; |
596 |
|
597 |
if (version_id != 3) |
598 |
return -EINVAL; // Cannot emulate 2 |
599 |
|
600 |
qemu_get_buffer(f, s->rregs, ESP_REGS); |
601 |
qemu_get_buffer(f, s->wregs, ESP_REGS); |
602 |
qemu_get_be32s(f, (uint32_t *)&s->ti_size); |
603 |
qemu_get_be32s(f, &s->ti_rptr); |
604 |
qemu_get_be32s(f, &s->ti_wptr); |
605 |
qemu_get_buffer(f, s->ti_buf, TI_BUFSZ); |
606 |
qemu_get_be32s(f, &s->sense); |
607 |
qemu_get_be32s(f, &s->dma); |
608 |
qemu_get_buffer(f, s->cmdbuf, TI_BUFSZ); |
609 |
qemu_get_be32s(f, &s->cmdlen); |
610 |
qemu_get_be32s(f, &s->do_cmd); |
611 |
qemu_get_be32s(f, &s->dma_left); |
612 |
|
613 |
return 0; |
614 |
} |
615 |
|
616 |
void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id) |
617 |
{ |
618 |
ESPState *s = (ESPState *)opaque; |
619 |
|
620 |
if (id < 0) { |
621 |
for (id = 0; id < ESP_MAX_DEVS; id++) { |
622 |
if (s->scsi_dev[id] == NULL) |
623 |
break;
|
624 |
} |
625 |
} |
626 |
if (id >= ESP_MAX_DEVS) {
|
627 |
DPRINTF("Bad Device ID %d\n", id);
|
628 |
return;
|
629 |
} |
630 |
if (s->scsi_dev[id]) {
|
631 |
DPRINTF("Destroying device %d\n", id);
|
632 |
s->scsi_dev[id]->destroy(s->scsi_dev[id]); |
633 |
} |
634 |
DPRINTF("Attaching block device %d\n", id);
|
635 |
/* Command queueing is not implemented. */
|
636 |
s->scsi_dev[id] = scsi_generic_init(bd, 0, esp_command_complete, s);
|
637 |
if (s->scsi_dev[id] == NULL) |
638 |
s->scsi_dev[id] = scsi_disk_init(bd, 0, esp_command_complete, s);
|
639 |
} |
640 |
|
641 |
void *esp_init(target_phys_addr_t espaddr, int it_shift, |
642 |
espdma_memory_read_write dma_memory_read, |
643 |
espdma_memory_read_write dma_memory_write, |
644 |
void *dma_opaque, qemu_irq irq, qemu_irq *reset)
|
645 |
{ |
646 |
ESPState *s; |
647 |
int esp_io_memory;
|
648 |
|
649 |
s = qemu_mallocz(sizeof(ESPState));
|
650 |
if (!s)
|
651 |
return NULL; |
652 |
|
653 |
s->irq = irq; |
654 |
s->it_shift = it_shift; |
655 |
s->dma_memory_read = dma_memory_read; |
656 |
s->dma_memory_write = dma_memory_write; |
657 |
s->dma_opaque = dma_opaque; |
658 |
|
659 |
esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
|
660 |
cpu_register_physical_memory(espaddr, ESP_REGS << it_shift, esp_io_memory); |
661 |
|
662 |
esp_reset(s); |
663 |
|
664 |
register_savevm("esp", espaddr, 3, esp_save, esp_load, s); |
665 |
qemu_register_reset(esp_reset, s); |
666 |
|
667 |
*reset = *qemu_allocate_irqs(parent_esp_reset, s, 1);
|
668 |
|
669 |
return s;
|
670 |
} |