root / hw / mips_r4k.c @ c5d6edc3
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1 | 6af0bf9c | bellard | #include "vl.h" |
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2 | 6af0bf9c | bellard | |
3 | 6af0bf9c | bellard | #define BIOS_FILENAME "mips_bios.bin" |
4 | 6af0bf9c | bellard | //#define BIOS_FILENAME "system.bin"
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5 | 6af0bf9c | bellard | #define KERNEL_LOAD_ADDR 0x80010000 |
6 | 6af0bf9c | bellard | #define INITRD_LOAD_ADDR 0x80800000 |
7 | 6af0bf9c | bellard | |
8 | 66a93e0f | bellard | #define VIRT_TO_PHYS_ADDEND (-0x80000000LL) |
9 | 66a93e0f | bellard | |
10 | 6af0bf9c | bellard | extern FILE *logfile;
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11 | 6af0bf9c | bellard | |
12 | 697584ab | bellard | static PITState *pit;
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13 | 697584ab | bellard | |
14 | 73133662 | bellard | static void pic_irq_request(void *opaque, int level) |
15 | 6af0bf9c | bellard | { |
16 | c68ea704 | bellard | CPUState *env = first_cpu; |
17 | 73133662 | bellard | if (level) {
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18 | c68ea704 | bellard | env->CP0_Cause |= 0x00000400;
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19 | c68ea704 | bellard | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
20 | 6af0bf9c | bellard | } else {
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21 | c68ea704 | bellard | env->CP0_Cause &= ~0x00000400;
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22 | c68ea704 | bellard | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
23 | 6af0bf9c | bellard | } |
24 | 6af0bf9c | bellard | } |
25 | 6af0bf9c | bellard | |
26 | 6af0bf9c | bellard | void cpu_mips_irqctrl_init (void) |
27 | 6af0bf9c | bellard | { |
28 | 6af0bf9c | bellard | } |
29 | 6af0bf9c | bellard | |
30 | f5d2a381 | bellard | /* XXX: do not use a global */
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31 | 6af0bf9c | bellard | uint32_t cpu_mips_get_random (CPUState *env) |
32 | 6af0bf9c | bellard | { |
33 | f5d2a381 | bellard | static uint32_t seed = 0; |
34 | f5d2a381 | bellard | uint32_t idx; |
35 | f5d2a381 | bellard | seed = seed * 314159 + 1; |
36 | f5d2a381 | bellard | idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
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37 | f5d2a381 | bellard | return idx;
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38 | 6af0bf9c | bellard | } |
39 | 6af0bf9c | bellard | |
40 | 899abcf5 | bellard | /* MIPS R4K timer */
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41 | 6af0bf9c | bellard | uint32_t cpu_mips_get_count (CPUState *env) |
42 | 6af0bf9c | bellard | { |
43 | 6af0bf9c | bellard | return env->CP0_Count +
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44 | 6af0bf9c | bellard | (uint32_t)muldiv64(qemu_get_clock(vm_clock), |
45 | 6af0bf9c | bellard | 100 * 1000 * 1000, ticks_per_sec); |
46 | 6af0bf9c | bellard | } |
47 | 6af0bf9c | bellard | |
48 | 6af0bf9c | bellard | static void cpu_mips_update_count (CPUState *env, uint32_t count, |
49 | 6af0bf9c | bellard | uint32_t compare) |
50 | 6af0bf9c | bellard | { |
51 | 6af0bf9c | bellard | uint64_t now, next; |
52 | 6af0bf9c | bellard | uint32_t tmp; |
53 | 6af0bf9c | bellard | |
54 | 6af0bf9c | bellard | tmp = count; |
55 | 6af0bf9c | bellard | if (count == compare)
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56 | 6af0bf9c | bellard | tmp++; |
57 | 6af0bf9c | bellard | now = qemu_get_clock(vm_clock); |
58 | 6af0bf9c | bellard | next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000); |
59 | 6af0bf9c | bellard | if (next == now)
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60 | 6af0bf9c | bellard | next++; |
61 | 2d7272a5 | bellard | #if 0
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62 | 6af0bf9c | bellard | if (logfile) {
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63 | 6af0bf9c | bellard | fprintf(logfile, "%s: 0x%08llx %08x %08x => 0x%08llx\n",
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64 | 6af0bf9c | bellard | __func__, now, count, compare, next - now);
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65 | 6af0bf9c | bellard | }
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66 | 6af0bf9c | bellard | #endif
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67 | 6af0bf9c | bellard | /* Store new count and compare registers */
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68 | 6af0bf9c | bellard | env->CP0_Compare = compare; |
69 | 6af0bf9c | bellard | env->CP0_Count = |
70 | 6af0bf9c | bellard | count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec); |
71 | 6af0bf9c | bellard | /* Adjust timer */
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72 | 6af0bf9c | bellard | qemu_mod_timer(env->timer, next); |
73 | 6af0bf9c | bellard | } |
74 | 6af0bf9c | bellard | |
75 | 6af0bf9c | bellard | void cpu_mips_store_count (CPUState *env, uint32_t value)
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76 | 6af0bf9c | bellard | { |
77 | 6af0bf9c | bellard | cpu_mips_update_count(env, value, env->CP0_Compare); |
78 | 6af0bf9c | bellard | } |
79 | 6af0bf9c | bellard | |
80 | 6af0bf9c | bellard | void cpu_mips_store_compare (CPUState *env, uint32_t value)
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81 | 6af0bf9c | bellard | { |
82 | 6af0bf9c | bellard | cpu_mips_update_count(env, cpu_mips_get_count(env), value); |
83 | c68ea704 | bellard | env->CP0_Cause &= ~0x00008000;
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84 | c68ea704 | bellard | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
85 | 6af0bf9c | bellard | } |
86 | 6af0bf9c | bellard | |
87 | 6af0bf9c | bellard | static void mips_timer_cb (void *opaque) |
88 | 6af0bf9c | bellard | { |
89 | 6af0bf9c | bellard | CPUState *env; |
90 | 6af0bf9c | bellard | |
91 | 6af0bf9c | bellard | env = opaque; |
92 | 2d7272a5 | bellard | #if 0
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93 | 6af0bf9c | bellard | if (logfile) {
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94 | 6af0bf9c | bellard | fprintf(logfile, "%s\n", __func__);
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95 | 6af0bf9c | bellard | }
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96 | 6af0bf9c | bellard | #endif
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97 | 6af0bf9c | bellard | cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare); |
98 | c68ea704 | bellard | env->CP0_Cause |= 0x00008000;
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99 | c68ea704 | bellard | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
100 | 6af0bf9c | bellard | } |
101 | 6af0bf9c | bellard | |
102 | 6af0bf9c | bellard | void cpu_mips_clock_init (CPUState *env)
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103 | 6af0bf9c | bellard | { |
104 | 6af0bf9c | bellard | env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env); |
105 | 6af0bf9c | bellard | env->CP0_Compare = 0;
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106 | 6af0bf9c | bellard | cpu_mips_update_count(env, 1, 0); |
107 | 6af0bf9c | bellard | } |
108 | 6af0bf9c | bellard | |
109 | 66a93e0f | bellard | |
110 | 6af0bf9c | bellard | static void io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
111 | 6af0bf9c | bellard | { |
112 | 2d7272a5 | bellard | #if 0
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113 | 6af0bf9c | bellard | if (logfile)
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114 | 6af0bf9c | bellard | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
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115 | 2d7272a5 | bellard | #endif
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116 | 6af0bf9c | bellard | cpu_outb(NULL, addr & 0xffff, value); |
117 | 6af0bf9c | bellard | } |
118 | 6af0bf9c | bellard | |
119 | 6af0bf9c | bellard | static uint32_t io_readb (void *opaque, target_phys_addr_t addr) |
120 | 6af0bf9c | bellard | { |
121 | 6af0bf9c | bellard | uint32_t ret = cpu_inb(NULL, addr & 0xffff); |
122 | 2d7272a5 | bellard | #if 0
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123 | 6af0bf9c | bellard | if (logfile)
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124 | 6af0bf9c | bellard | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
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125 | 2d7272a5 | bellard | #endif
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126 | 6af0bf9c | bellard | return ret;
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127 | 6af0bf9c | bellard | } |
128 | 6af0bf9c | bellard | |
129 | 6af0bf9c | bellard | static void io_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
130 | 6af0bf9c | bellard | { |
131 | 2d7272a5 | bellard | #if 0
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132 | 6af0bf9c | bellard | if (logfile)
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133 | 6af0bf9c | bellard | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
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134 | 2d7272a5 | bellard | #endif
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135 | 6af0bf9c | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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136 | 6af0bf9c | bellard | value = bswap16(value); |
137 | 6af0bf9c | bellard | #endif
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138 | 6af0bf9c | bellard | cpu_outw(NULL, addr & 0xffff, value); |
139 | 6af0bf9c | bellard | } |
140 | 6af0bf9c | bellard | |
141 | 6af0bf9c | bellard | static uint32_t io_readw (void *opaque, target_phys_addr_t addr) |
142 | 6af0bf9c | bellard | { |
143 | 6af0bf9c | bellard | uint32_t ret = cpu_inw(NULL, addr & 0xffff); |
144 | 6af0bf9c | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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145 | 6af0bf9c | bellard | ret = bswap16(ret); |
146 | 6af0bf9c | bellard | #endif
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147 | 2d7272a5 | bellard | #if 0
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148 | 6af0bf9c | bellard | if (logfile)
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149 | 6af0bf9c | bellard | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
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150 | 2d7272a5 | bellard | #endif
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151 | 6af0bf9c | bellard | return ret;
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152 | 6af0bf9c | bellard | } |
153 | 6af0bf9c | bellard | |
154 | 6af0bf9c | bellard | static void io_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
155 | 6af0bf9c | bellard | { |
156 | 2d7272a5 | bellard | #if 0
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157 | 6af0bf9c | bellard | if (logfile)
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158 | 6af0bf9c | bellard | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
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159 | 2d7272a5 | bellard | #endif
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160 | 6af0bf9c | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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161 | 6af0bf9c | bellard | value = bswap32(value); |
162 | 6af0bf9c | bellard | #endif
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163 | 6af0bf9c | bellard | cpu_outl(NULL, addr & 0xffff, value); |
164 | 6af0bf9c | bellard | } |
165 | 6af0bf9c | bellard | |
166 | 6af0bf9c | bellard | static uint32_t io_readl (void *opaque, target_phys_addr_t addr) |
167 | 6af0bf9c | bellard | { |
168 | 6af0bf9c | bellard | uint32_t ret = cpu_inl(NULL, addr & 0xffff); |
169 | 6af0bf9c | bellard | |
170 | 6af0bf9c | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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171 | 6af0bf9c | bellard | ret = bswap32(ret); |
172 | 6af0bf9c | bellard | #endif
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173 | 2d7272a5 | bellard | #if 0
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174 | 6af0bf9c | bellard | if (logfile)
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175 | 6af0bf9c | bellard | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
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176 | 2d7272a5 | bellard | #endif
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177 | 6af0bf9c | bellard | return ret;
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178 | 6af0bf9c | bellard | } |
179 | 6af0bf9c | bellard | |
180 | 6af0bf9c | bellard | CPUWriteMemoryFunc *io_write[] = { |
181 | 6af0bf9c | bellard | &io_writeb, |
182 | 6af0bf9c | bellard | &io_writew, |
183 | 6af0bf9c | bellard | &io_writel, |
184 | 6af0bf9c | bellard | }; |
185 | 6af0bf9c | bellard | |
186 | 6af0bf9c | bellard | CPUReadMemoryFunc *io_read[] = { |
187 | 6af0bf9c | bellard | &io_readb, |
188 | 6af0bf9c | bellard | &io_readw, |
189 | 6af0bf9c | bellard | &io_readl, |
190 | 6af0bf9c | bellard | }; |
191 | 6af0bf9c | bellard | |
192 | 6af0bf9c | bellard | void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, |
193 | 6af0bf9c | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
194 | 6af0bf9c | bellard | const char *kernel_filename, const char *kernel_cmdline, |
195 | 6af0bf9c | bellard | const char *initrd_filename) |
196 | 6af0bf9c | bellard | { |
197 | 6af0bf9c | bellard | char buf[1024]; |
198 | 66a93e0f | bellard | int64_t entry = 0;
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199 | 6af0bf9c | bellard | unsigned long bios_offset; |
200 | 6af0bf9c | bellard | int io_memory;
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201 | 6af0bf9c | bellard | int ret;
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202 | c68ea704 | bellard | CPUState *env; |
203 | 66a93e0f | bellard | long kernel_size;
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204 | c68ea704 | bellard | |
205 | c68ea704 | bellard | env = cpu_init(); |
206 | c68ea704 | bellard | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
207 | c68ea704 | bellard | |
208 | 6af0bf9c | bellard | /* allocate RAM */
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209 | 6af0bf9c | bellard | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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210 | 66a93e0f | bellard | |
211 | 66a93e0f | bellard | /* Try to load a BIOS image. If this fails, we continue regardless,
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212 | 66a93e0f | bellard | but initialize the hardware ourselves. When a kernel gets
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213 | 66a93e0f | bellard | preloaded we also initialize the hardware, since the BIOS wasn't
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214 | 66a93e0f | bellard | run. */
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215 | 6af0bf9c | bellard | bios_offset = ram_size + vga_ram_size; |
216 | 6af0bf9c | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
217 | 6af0bf9c | bellard | ret = load_image(buf, phys_ram_base + bios_offset); |
218 | 66a93e0f | bellard | if (ret == BIOS_SIZE) {
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219 | 66a93e0f | bellard | cpu_register_physical_memory((uint32_t)(0x1fc00000),
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220 | 66a93e0f | bellard | BIOS_SIZE, bios_offset | IO_MEM_ROM); |
221 | 66a93e0f | bellard | } else {
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222 | 66a93e0f | bellard | /* not fatal */
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223 | 66a93e0f | bellard | fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
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224 | 66a93e0f | bellard | buf); |
225 | 6af0bf9c | bellard | } |
226 | 66a93e0f | bellard | |
227 | 66a93e0f | bellard | kernel_size = 0;
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228 | 66a93e0f | bellard | if (kernel_filename) {
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229 | 66a93e0f | bellard | kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry); |
230 | 66a93e0f | bellard | if (kernel_size >= 0) |
231 | 66a93e0f | bellard | env->PC = entry; |
232 | 66a93e0f | bellard | else {
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233 | 66a93e0f | bellard | kernel_size = load_image(kernel_filename, |
234 | 66a93e0f | bellard | phys_ram_base + KERNEL_LOAD_ADDR + VIRT_TO_PHYS_ADDEND); |
235 | 66a93e0f | bellard | if (kernel_size < 0) { |
236 | 66a93e0f | bellard | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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237 | 66a93e0f | bellard | kernel_filename); |
238 | 66a93e0f | bellard | exit(1);
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239 | 66a93e0f | bellard | } |
240 | 66a93e0f | bellard | env->PC = KERNEL_LOAD_ADDR; |
241 | 66a93e0f | bellard | } |
242 | 66a93e0f | bellard | |
243 | 6af0bf9c | bellard | /* load initrd */
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244 | 6af0bf9c | bellard | if (initrd_filename) {
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245 | 66a93e0f | bellard | if (load_image(initrd_filename,
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246 | 66a93e0f | bellard | phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND) |
247 | 66a93e0f | bellard | == (target_ulong) -1) {
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248 | 6af0bf9c | bellard | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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249 | 6af0bf9c | bellard | initrd_filename); |
250 | 6af0bf9c | bellard | exit(1);
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251 | 6af0bf9c | bellard | } |
252 | 6af0bf9c | bellard | } |
253 | 66a93e0f | bellard | |
254 | 2d7272a5 | bellard | /* Store command line. */
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255 | 2d7272a5 | bellard | strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline); |
256 | 2d7272a5 | bellard | /* FIXME: little endian support */
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257 | 2d7272a5 | bellard | *(int *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678); |
258 | 2d7272a5 | bellard | *(int *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size); |
259 | 6af0bf9c | bellard | } |
260 | 6af0bf9c | bellard | |
261 | 6af0bf9c | bellard | /* Init internal devices */
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262 | c68ea704 | bellard | cpu_mips_clock_init(env); |
263 | 6af0bf9c | bellard | cpu_mips_irqctrl_init(); |
264 | 6af0bf9c | bellard | |
265 | 0699b548 | bellard | /* Register 64 KB of ISA IO space at 0x14000000 */
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266 | 6af0bf9c | bellard | io_memory = cpu_register_io_memory(0, io_read, io_write, NULL); |
267 | 0699b548 | bellard | cpu_register_physical_memory(0x14000000, 0x00010000, io_memory); |
268 | 0699b548 | bellard | isa_mem_base = 0x10000000;
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269 | 0699b548 | bellard | |
270 | c68ea704 | bellard | isa_pic = pic_init(pic_irq_request, env); |
271 | 697584ab | bellard | pit = pit_init(0x40, 0); |
272 | e5d13e2f | bellard | serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]); |
273 | 0699b548 | bellard | vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size,
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274 | d5295253 | bellard | vga_ram_size, 0, 0); |
275 | 9827e95c | bellard | |
276 | a41b2ff2 | pbrook | if (nd_table[0].vlan) { |
277 | a41b2ff2 | pbrook | if (nd_table[0].model == NULL |
278 | a41b2ff2 | pbrook | || strcmp(nd_table[0].model, "ne2k_isa") == 0) { |
279 | a41b2ff2 | pbrook | isa_ne2000_init(0x300, 9, &nd_table[0]); |
280 | a41b2ff2 | pbrook | } else {
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281 | a41b2ff2 | pbrook | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
282 | a41b2ff2 | pbrook | exit (1);
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283 | a41b2ff2 | pbrook | } |
284 | a41b2ff2 | pbrook | } |
285 | 6af0bf9c | bellard | } |
286 | 6af0bf9c | bellard | |
287 | 6af0bf9c | bellard | QEMUMachine mips_machine = { |
288 | 6af0bf9c | bellard | "mips",
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289 | 6af0bf9c | bellard | "mips r4k platform",
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290 | 6af0bf9c | bellard | mips_r4k_init, |
291 | 6af0bf9c | bellard | }; |