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1 | 420557e8 | bellard | /*
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2 | 6f7e9aec | bellard | * QEMU TCX Frame buffer
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3 | 420557e8 | bellard | *
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4 | 6f7e9aec | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 420557e8 | bellard | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 420557e8 | bellard | #include "vl.h" |
25 | 420557e8 | bellard | |
26 | 420557e8 | bellard | #define MAXX 1024 |
27 | 420557e8 | bellard | #define MAXY 768 |
28 | 6f7e9aec | bellard | #define TCX_DAC_NREGS 16 |
29 | 420557e8 | bellard | |
30 | 420557e8 | bellard | typedef struct TCXState { |
31 | 8d5f07fa | bellard | uint32_t addr; |
32 | 420557e8 | bellard | DisplayState *ds; |
33 | 8d5f07fa | bellard | uint8_t *vram; |
34 | e80cfcfc | bellard | unsigned long vram_offset; |
35 | 6f7e9aec | bellard | uint16_t width, height; |
36 | e80cfcfc | bellard | uint8_t r[256], g[256], b[256]; |
37 | 6f7e9aec | bellard | uint8_t dac_index, dac_state; |
38 | 420557e8 | bellard | } TCXState; |
39 | 420557e8 | bellard | |
40 | 95219897 | pbrook | static void tcx_screen_dump(void *opaque, const char *filename); |
41 | 95219897 | pbrook | |
42 | e80cfcfc | bellard | static void tcx_draw_line32(TCXState *s1, uint8_t *d, |
43 | e80cfcfc | bellard | const uint8_t *s, int width) |
44 | 420557e8 | bellard | { |
45 | e80cfcfc | bellard | int x;
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46 | e80cfcfc | bellard | uint8_t val; |
47 | e80cfcfc | bellard | |
48 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
49 | e80cfcfc | bellard | val = *s++; |
50 | e80cfcfc | bellard | *d++ = s1->b[val]; |
51 | 6f7e9aec | bellard | *d++ = s1->g[val]; |
52 | 6f7e9aec | bellard | *d++ = s1->r[val]; |
53 | e80cfcfc | bellard | d++; |
54 | e80cfcfc | bellard | } |
55 | 420557e8 | bellard | } |
56 | 420557e8 | bellard | |
57 | e80cfcfc | bellard | static void tcx_draw_line24(TCXState *s1, uint8_t *d, |
58 | e80cfcfc | bellard | const uint8_t *s, int width) |
59 | e80cfcfc | bellard | { |
60 | e80cfcfc | bellard | int x;
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61 | e80cfcfc | bellard | uint8_t val; |
62 | 8d5f07fa | bellard | |
63 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
64 | e80cfcfc | bellard | val = *s++; |
65 | e80cfcfc | bellard | *d++ = s1->b[val]; |
66 | 6f7e9aec | bellard | *d++ = s1->g[val]; |
67 | 6f7e9aec | bellard | *d++ = s1->r[val]; |
68 | e80cfcfc | bellard | } |
69 | e80cfcfc | bellard | } |
70 | e80cfcfc | bellard | |
71 | e80cfcfc | bellard | static void tcx_draw_line8(TCXState *s1, uint8_t *d, |
72 | e80cfcfc | bellard | const uint8_t *s, int width) |
73 | 420557e8 | bellard | { |
74 | e80cfcfc | bellard | int x;
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75 | e80cfcfc | bellard | uint8_t val; |
76 | e80cfcfc | bellard | |
77 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
78 | e80cfcfc | bellard | val = *s++; |
79 | e80cfcfc | bellard | /* XXX translate between palettes? */
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80 | e80cfcfc | bellard | *d++ = val; |
81 | 420557e8 | bellard | } |
82 | 420557e8 | bellard | } |
83 | 420557e8 | bellard | |
84 | e80cfcfc | bellard | /* Fixed line length 1024 allows us to do nice tricks not possible on
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85 | e80cfcfc | bellard | VGA... */
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86 | 95219897 | pbrook | static void tcx_update_display(void *opaque) |
87 | 420557e8 | bellard | { |
88 | e80cfcfc | bellard | TCXState *ts = opaque; |
89 | e80cfcfc | bellard | uint32_t page; |
90 | e80cfcfc | bellard | int y, page_min, page_max, y_start, dd, ds;
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91 | e80cfcfc | bellard | uint8_t *d, *s; |
92 | e80cfcfc | bellard | void (*f)(TCXState *s1, uint8_t *d, const uint8_t *s, int width); |
93 | e80cfcfc | bellard | |
94 | e80cfcfc | bellard | if (ts->ds->depth == 0) |
95 | e80cfcfc | bellard | return;
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96 | 6f7e9aec | bellard | page = ts->vram_offset; |
97 | e80cfcfc | bellard | y_start = -1;
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98 | e80cfcfc | bellard | page_min = 0x7fffffff;
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99 | e80cfcfc | bellard | page_max = -1;
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100 | e80cfcfc | bellard | d = ts->ds->data; |
101 | 6f7e9aec | bellard | s = ts->vram; |
102 | e80cfcfc | bellard | dd = ts->ds->linesize; |
103 | e80cfcfc | bellard | ds = 1024;
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104 | e80cfcfc | bellard | |
105 | e80cfcfc | bellard | switch (ts->ds->depth) {
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106 | e80cfcfc | bellard | case 32: |
107 | e80cfcfc | bellard | f = tcx_draw_line32; |
108 | e80cfcfc | bellard | break;
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109 | e80cfcfc | bellard | case 24: |
110 | e80cfcfc | bellard | f = tcx_draw_line24; |
111 | e80cfcfc | bellard | break;
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112 | e80cfcfc | bellard | default:
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113 | e80cfcfc | bellard | case 8: |
114 | e80cfcfc | bellard | f = tcx_draw_line8; |
115 | e80cfcfc | bellard | break;
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116 | e80cfcfc | bellard | case 0: |
117 | e80cfcfc | bellard | return;
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118 | e80cfcfc | bellard | } |
119 | 662f3c86 | bellard | |
120 | 6f7e9aec | bellard | for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { |
121 | 0a962c02 | bellard | if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
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122 | e80cfcfc | bellard | if (y_start < 0) |
123 | e80cfcfc | bellard | y_start = y; |
124 | e80cfcfc | bellard | if (page < page_min)
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125 | e80cfcfc | bellard | page_min = page; |
126 | e80cfcfc | bellard | if (page > page_max)
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127 | e80cfcfc | bellard | page_max = page; |
128 | 6f7e9aec | bellard | f(ts, d, s, ts->width); |
129 | e80cfcfc | bellard | d += dd; |
130 | e80cfcfc | bellard | s += ds; |
131 | 6f7e9aec | bellard | f(ts, d, s, ts->width); |
132 | e80cfcfc | bellard | d += dd; |
133 | e80cfcfc | bellard | s += ds; |
134 | 6f7e9aec | bellard | f(ts, d, s, ts->width); |
135 | e80cfcfc | bellard | d += dd; |
136 | e80cfcfc | bellard | s += ds; |
137 | 6f7e9aec | bellard | f(ts, d, s, ts->width); |
138 | e80cfcfc | bellard | d += dd; |
139 | e80cfcfc | bellard | s += ds; |
140 | e80cfcfc | bellard | } else {
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141 | e80cfcfc | bellard | if (y_start >= 0) { |
142 | e80cfcfc | bellard | /* flush to display */
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143 | e80cfcfc | bellard | dpy_update(ts->ds, 0, y_start,
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144 | 6f7e9aec | bellard | ts->width, y - y_start); |
145 | e80cfcfc | bellard | y_start = -1;
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146 | e80cfcfc | bellard | } |
147 | e80cfcfc | bellard | d += dd * 4;
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148 | e80cfcfc | bellard | s += ds * 4;
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149 | e80cfcfc | bellard | } |
150 | e80cfcfc | bellard | } |
151 | e80cfcfc | bellard | if (y_start >= 0) { |
152 | e80cfcfc | bellard | /* flush to display */
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153 | e80cfcfc | bellard | dpy_update(ts->ds, 0, y_start,
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154 | 6f7e9aec | bellard | ts->width, y - y_start); |
155 | e80cfcfc | bellard | } |
156 | e80cfcfc | bellard | /* reset modified pages */
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157 | e80cfcfc | bellard | if (page_max != -1) { |
158 | 0a962c02 | bellard | cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
159 | 0a962c02 | bellard | VGA_DIRTY_FLAG); |
160 | e80cfcfc | bellard | } |
161 | 420557e8 | bellard | } |
162 | 420557e8 | bellard | |
163 | 95219897 | pbrook | static void tcx_invalidate_display(void *opaque) |
164 | 420557e8 | bellard | { |
165 | e80cfcfc | bellard | TCXState *s = opaque; |
166 | e80cfcfc | bellard | int i;
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167 | e80cfcfc | bellard | |
168 | e80cfcfc | bellard | for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) { |
169 | e80cfcfc | bellard | cpu_physical_memory_set_dirty(s->vram_offset + i); |
170 | e80cfcfc | bellard | } |
171 | 420557e8 | bellard | } |
172 | 420557e8 | bellard | |
173 | e80cfcfc | bellard | static void tcx_save(QEMUFile *f, void *opaque) |
174 | 420557e8 | bellard | { |
175 | 420557e8 | bellard | TCXState *s = opaque; |
176 | e80cfcfc | bellard | |
177 | e80cfcfc | bellard | qemu_put_be32s(f, (uint32_t *)&s->addr); |
178 | e80cfcfc | bellard | qemu_put_be32s(f, (uint32_t *)&s->vram); |
179 | 6f7e9aec | bellard | qemu_put_be16s(f, (uint16_t *)&s->height); |
180 | 6f7e9aec | bellard | qemu_put_be16s(f, (uint16_t *)&s->width); |
181 | e80cfcfc | bellard | qemu_put_buffer(f, s->r, 256);
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182 | e80cfcfc | bellard | qemu_put_buffer(f, s->g, 256);
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183 | e80cfcfc | bellard | qemu_put_buffer(f, s->b, 256);
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184 | 6f7e9aec | bellard | qemu_put_8s(f, &s->dac_index); |
185 | 6f7e9aec | bellard | qemu_put_8s(f, &s->dac_state); |
186 | 420557e8 | bellard | } |
187 | 420557e8 | bellard | |
188 | e80cfcfc | bellard | static int tcx_load(QEMUFile *f, void *opaque, int version_id) |
189 | 420557e8 | bellard | { |
190 | e80cfcfc | bellard | TCXState *s = opaque; |
191 | e80cfcfc | bellard | |
192 | e80cfcfc | bellard | if (version_id != 1) |
193 | e80cfcfc | bellard | return -EINVAL;
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194 | e80cfcfc | bellard | |
195 | e80cfcfc | bellard | qemu_get_be32s(f, (uint32_t *)&s->addr); |
196 | e80cfcfc | bellard | qemu_get_be32s(f, (uint32_t *)&s->vram); |
197 | 6f7e9aec | bellard | qemu_get_be16s(f, (uint16_t *)&s->height); |
198 | 6f7e9aec | bellard | qemu_get_be16s(f, (uint16_t *)&s->width); |
199 | e80cfcfc | bellard | qemu_get_buffer(f, s->r, 256);
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200 | e80cfcfc | bellard | qemu_get_buffer(f, s->g, 256);
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201 | e80cfcfc | bellard | qemu_get_buffer(f, s->b, 256);
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202 | 6f7e9aec | bellard | qemu_get_8s(f, &s->dac_index); |
203 | 6f7e9aec | bellard | qemu_get_8s(f, &s->dac_state); |
204 | e80cfcfc | bellard | return 0; |
205 | 420557e8 | bellard | } |
206 | 420557e8 | bellard | |
207 | e80cfcfc | bellard | static void tcx_reset(void *opaque) |
208 | 420557e8 | bellard | { |
209 | e80cfcfc | bellard | TCXState *s = opaque; |
210 | e80cfcfc | bellard | |
211 | e80cfcfc | bellard | /* Initialize palette */
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212 | e80cfcfc | bellard | memset(s->r, 0, 256); |
213 | e80cfcfc | bellard | memset(s->g, 0, 256); |
214 | e80cfcfc | bellard | memset(s->b, 0, 256); |
215 | e80cfcfc | bellard | s->r[255] = s->g[255] = s->b[255] = 255; |
216 | e80cfcfc | bellard | memset(s->vram, 0, MAXX*MAXY);
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217 | 0a962c02 | bellard | cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset + MAXX*MAXY, |
218 | 0a962c02 | bellard | VGA_DIRTY_FLAG); |
219 | 6f7e9aec | bellard | s->dac_index = 0;
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220 | 6f7e9aec | bellard | s->dac_state = 0;
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221 | 6f7e9aec | bellard | } |
222 | 6f7e9aec | bellard | |
223 | 6f7e9aec | bellard | static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr) |
224 | 6f7e9aec | bellard | { |
225 | 6f7e9aec | bellard | return 0; |
226 | 6f7e9aec | bellard | } |
227 | 6f7e9aec | bellard | |
228 | 6f7e9aec | bellard | static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
229 | 6f7e9aec | bellard | { |
230 | 6f7e9aec | bellard | TCXState *s = opaque; |
231 | 6f7e9aec | bellard | uint32_t saddr; |
232 | 6f7e9aec | bellard | |
233 | 6f7e9aec | bellard | saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2; |
234 | 6f7e9aec | bellard | switch (saddr) {
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235 | 6f7e9aec | bellard | case 0: |
236 | 6f7e9aec | bellard | s->dac_index = val >> 24;
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237 | 6f7e9aec | bellard | s->dac_state = 0;
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238 | 6f7e9aec | bellard | break;
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239 | 6f7e9aec | bellard | case 1: |
240 | 6f7e9aec | bellard | switch (s->dac_state) {
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241 | 6f7e9aec | bellard | case 0: |
242 | 6f7e9aec | bellard | s->r[s->dac_index] = val >> 24;
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243 | 6f7e9aec | bellard | s->dac_state++; |
244 | 6f7e9aec | bellard | break;
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245 | 6f7e9aec | bellard | case 1: |
246 | 6f7e9aec | bellard | s->g[s->dac_index] = val >> 24;
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247 | 6f7e9aec | bellard | s->dac_state++; |
248 | 6f7e9aec | bellard | break;
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249 | 6f7e9aec | bellard | case 2: |
250 | 6f7e9aec | bellard | s->b[s->dac_index] = val >> 24;
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251 | 6f7e9aec | bellard | default:
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252 | 6f7e9aec | bellard | s->dac_state = 0;
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253 | 6f7e9aec | bellard | break;
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254 | 6f7e9aec | bellard | } |
255 | 6f7e9aec | bellard | break;
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256 | 6f7e9aec | bellard | default:
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257 | 6f7e9aec | bellard | break;
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258 | 6f7e9aec | bellard | } |
259 | 6f7e9aec | bellard | return;
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260 | 420557e8 | bellard | } |
261 | 420557e8 | bellard | |
262 | 6f7e9aec | bellard | static CPUReadMemoryFunc *tcx_dac_read[3] = { |
263 | 6f7e9aec | bellard | tcx_dac_readl, |
264 | 6f7e9aec | bellard | tcx_dac_readl, |
265 | 6f7e9aec | bellard | tcx_dac_readl, |
266 | 6f7e9aec | bellard | }; |
267 | 6f7e9aec | bellard | |
268 | 6f7e9aec | bellard | static CPUWriteMemoryFunc *tcx_dac_write[3] = { |
269 | 6f7e9aec | bellard | tcx_dac_writel, |
270 | 6f7e9aec | bellard | tcx_dac_writel, |
271 | 6f7e9aec | bellard | tcx_dac_writel, |
272 | 6f7e9aec | bellard | }; |
273 | 6f7e9aec | bellard | |
274 | 95219897 | pbrook | void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
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275 | 95219897 | pbrook | unsigned long vram_offset, int vram_size, int width, int height) |
276 | 420557e8 | bellard | { |
277 | 420557e8 | bellard | TCXState *s; |
278 | 6f7e9aec | bellard | int io_memory;
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279 | 420557e8 | bellard | |
280 | 420557e8 | bellard | s = qemu_mallocz(sizeof(TCXState));
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281 | 420557e8 | bellard | if (!s)
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282 | 95219897 | pbrook | return;
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283 | 420557e8 | bellard | s->ds = ds; |
284 | 8d5f07fa | bellard | s->addr = addr; |
285 | e80cfcfc | bellard | s->vram = vram_base; |
286 | e80cfcfc | bellard | s->vram_offset = vram_offset; |
287 | 6f7e9aec | bellard | s->width = width; |
288 | 6f7e9aec | bellard | s->height = height; |
289 | e80cfcfc | bellard | |
290 | 6f7e9aec | bellard | cpu_register_physical_memory(addr + 0x800000, vram_size, vram_offset);
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291 | 6f7e9aec | bellard | io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
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292 | 6f7e9aec | bellard | cpu_register_physical_memory(addr + 0x200000, TCX_DAC_NREGS, io_memory);
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293 | e80cfcfc | bellard | |
294 | 95219897 | pbrook | graphic_console_init(s->ds, tcx_update_display, tcx_invalidate_display, |
295 | 95219897 | pbrook | tcx_screen_dump, s); |
296 | e80cfcfc | bellard | register_savevm("tcx", addr, 1, tcx_save, tcx_load, s); |
297 | e80cfcfc | bellard | qemu_register_reset(tcx_reset, s); |
298 | e80cfcfc | bellard | tcx_reset(s); |
299 | 6f7e9aec | bellard | dpy_resize(s->ds, width, height); |
300 | 420557e8 | bellard | } |
301 | 420557e8 | bellard | |
302 | 95219897 | pbrook | static void tcx_screen_dump(void *opaque, const char *filename) |
303 | 8d5f07fa | bellard | { |
304 | e80cfcfc | bellard | TCXState *s = opaque; |
305 | 8d5f07fa | bellard | FILE *f; |
306 | e80cfcfc | bellard | uint8_t *d, *d1, v; |
307 | 8d5f07fa | bellard | int y, x;
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308 | 8d5f07fa | bellard | |
309 | 8d5f07fa | bellard | f = fopen(filename, "wb");
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310 | 8d5f07fa | bellard | if (!f)
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311 | e80cfcfc | bellard | return;
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312 | 6f7e9aec | bellard | fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
313 | 6f7e9aec | bellard | d1 = s->vram; |
314 | 6f7e9aec | bellard | for(y = 0; y < s->height; y++) { |
315 | 8d5f07fa | bellard | d = d1; |
316 | 6f7e9aec | bellard | for(x = 0; x < s->width; x++) { |
317 | 8d5f07fa | bellard | v = *d; |
318 | e80cfcfc | bellard | fputc(s->r[v], f); |
319 | e80cfcfc | bellard | fputc(s->g[v], f); |
320 | e80cfcfc | bellard | fputc(s->b[v], f); |
321 | 8d5f07fa | bellard | d++; |
322 | 8d5f07fa | bellard | } |
323 | e80cfcfc | bellard | d1 += MAXX; |
324 | 8d5f07fa | bellard | } |
325 | 8d5f07fa | bellard | fclose(f); |
326 | 8d5f07fa | bellard | return;
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327 | 8d5f07fa | bellard | } |
328 | 8d5f07fa | bellard | |
329 | 8d5f07fa | bellard |