root / target-i386 / opreg_template.h @ c5d6edc3
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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * i386 micro operations (templates for various register related
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3 | 2c0262af | bellard | * operations)
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4 | 2c0262af | bellard | *
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5 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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6 | 2c0262af | bellard | *
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7 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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8 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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9 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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10 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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11 | 2c0262af | bellard | *
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12 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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13 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 2c0262af | bellard | * Lesser General Public License for more details.
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16 | 2c0262af | bellard | *
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17 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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18 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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19 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 2c0262af | bellard | */
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21 | 2c0262af | bellard | void OPPROTO glue(op_movl_A0,REGNAME)(void) |
22 | 2c0262af | bellard | { |
23 | 14ce26e7 | bellard | A0 = (uint32_t)REG; |
24 | 2c0262af | bellard | } |
25 | 2c0262af | bellard | |
26 | 2c0262af | bellard | void OPPROTO glue(op_addl_A0,REGNAME)(void) |
27 | 2c0262af | bellard | { |
28 | 14ce26e7 | bellard | A0 = (uint32_t)(A0 + REG); |
29 | 2c0262af | bellard | } |
30 | 2c0262af | bellard | |
31 | 2c0262af | bellard | void OPPROTO glue(glue(op_addl_A0,REGNAME),_s1)(void) |
32 | 2c0262af | bellard | { |
33 | 14ce26e7 | bellard | A0 = (uint32_t)(A0 + (REG << 1));
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34 | 2c0262af | bellard | } |
35 | 2c0262af | bellard | |
36 | 2c0262af | bellard | void OPPROTO glue(glue(op_addl_A0,REGNAME),_s2)(void) |
37 | 2c0262af | bellard | { |
38 | 14ce26e7 | bellard | A0 = (uint32_t)(A0 + (REG << 2));
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39 | 2c0262af | bellard | } |
40 | 2c0262af | bellard | |
41 | 2c0262af | bellard | void OPPROTO glue(glue(op_addl_A0,REGNAME),_s3)(void) |
42 | 2c0262af | bellard | { |
43 | 14ce26e7 | bellard | A0 = (uint32_t)(A0 + (REG << 3));
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44 | 14ce26e7 | bellard | } |
45 | 14ce26e7 | bellard | |
46 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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47 | 14ce26e7 | bellard | void OPPROTO glue(op_movq_A0,REGNAME)(void) |
48 | 14ce26e7 | bellard | { |
49 | 14ce26e7 | bellard | A0 = REG; |
50 | 14ce26e7 | bellard | } |
51 | 14ce26e7 | bellard | |
52 | 14ce26e7 | bellard | void OPPROTO glue(op_addq_A0,REGNAME)(void) |
53 | 14ce26e7 | bellard | { |
54 | 14ce26e7 | bellard | A0 = (A0 + REG); |
55 | 14ce26e7 | bellard | } |
56 | 14ce26e7 | bellard | |
57 | 14ce26e7 | bellard | void OPPROTO glue(glue(op_addq_A0,REGNAME),_s1)(void) |
58 | 14ce26e7 | bellard | { |
59 | 14ce26e7 | bellard | A0 = (A0 + (REG << 1));
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60 | 14ce26e7 | bellard | } |
61 | 14ce26e7 | bellard | |
62 | 14ce26e7 | bellard | void OPPROTO glue(glue(op_addq_A0,REGNAME),_s2)(void) |
63 | 14ce26e7 | bellard | { |
64 | 14ce26e7 | bellard | A0 = (A0 + (REG << 2));
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65 | 2c0262af | bellard | } |
66 | 2c0262af | bellard | |
67 | 14ce26e7 | bellard | void OPPROTO glue(glue(op_addq_A0,REGNAME),_s3)(void) |
68 | 14ce26e7 | bellard | { |
69 | 14ce26e7 | bellard | A0 = (A0 + (REG << 3));
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70 | 14ce26e7 | bellard | } |
71 | 14ce26e7 | bellard | #endif
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72 | 14ce26e7 | bellard | |
73 | 2c0262af | bellard | void OPPROTO glue(op_movl_T0,REGNAME)(void) |
74 | 2c0262af | bellard | { |
75 | 2c0262af | bellard | T0 = REG; |
76 | 2c0262af | bellard | } |
77 | 2c0262af | bellard | |
78 | 2c0262af | bellard | void OPPROTO glue(op_movl_T1,REGNAME)(void) |
79 | 2c0262af | bellard | { |
80 | 2c0262af | bellard | T1 = REG; |
81 | 2c0262af | bellard | } |
82 | 2c0262af | bellard | |
83 | 2c0262af | bellard | void OPPROTO glue(op_movh_T0,REGNAME)(void) |
84 | 2c0262af | bellard | { |
85 | 2c0262af | bellard | T0 = REG >> 8;
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86 | 2c0262af | bellard | } |
87 | 2c0262af | bellard | |
88 | 2c0262af | bellard | void OPPROTO glue(op_movh_T1,REGNAME)(void) |
89 | 2c0262af | bellard | { |
90 | 2c0262af | bellard | T1 = REG >> 8;
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91 | 2c0262af | bellard | } |
92 | 2c0262af | bellard | |
93 | 2c0262af | bellard | void OPPROTO glue(glue(op_movl,REGNAME),_T0)(void) |
94 | 2c0262af | bellard | { |
95 | 14ce26e7 | bellard | REG = (uint32_t)T0; |
96 | 2c0262af | bellard | } |
97 | 2c0262af | bellard | |
98 | 2c0262af | bellard | void OPPROTO glue(glue(op_movl,REGNAME),_T1)(void) |
99 | 2c0262af | bellard | { |
100 | 14ce26e7 | bellard | REG = (uint32_t)T1; |
101 | 2c0262af | bellard | } |
102 | 2c0262af | bellard | |
103 | 2c0262af | bellard | void OPPROTO glue(glue(op_movl,REGNAME),_A0)(void) |
104 | 2c0262af | bellard | { |
105 | 14ce26e7 | bellard | REG = (uint32_t)A0; |
106 | 14ce26e7 | bellard | } |
107 | 14ce26e7 | bellard | |
108 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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109 | 14ce26e7 | bellard | void OPPROTO glue(glue(op_movq,REGNAME),_T0)(void) |
110 | 14ce26e7 | bellard | { |
111 | 14ce26e7 | bellard | REG = T0; |
112 | 14ce26e7 | bellard | } |
113 | 14ce26e7 | bellard | |
114 | 14ce26e7 | bellard | void OPPROTO glue(glue(op_movq,REGNAME),_T1)(void) |
115 | 14ce26e7 | bellard | { |
116 | 14ce26e7 | bellard | REG = T1; |
117 | 14ce26e7 | bellard | } |
118 | 14ce26e7 | bellard | |
119 | 14ce26e7 | bellard | void OPPROTO glue(glue(op_movq,REGNAME),_A0)(void) |
120 | 14ce26e7 | bellard | { |
121 | 2c0262af | bellard | REG = A0; |
122 | 2c0262af | bellard | } |
123 | 14ce26e7 | bellard | #endif
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124 | 2c0262af | bellard | |
125 | 2c0262af | bellard | /* mov T1 to REG if T0 is true */
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126 | 2c0262af | bellard | void OPPROTO glue(glue(op_cmovw,REGNAME),_T1_T0)(void) |
127 | 2c0262af | bellard | { |
128 | 2c0262af | bellard | if (T0)
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129 | 14ce26e7 | bellard | REG = (REG & ~0xffff) | (T1 & 0xffff); |
130 | 128b346e | bellard | FORCE_RET(); |
131 | 2c0262af | bellard | } |
132 | 2c0262af | bellard | |
133 | 2c0262af | bellard | void OPPROTO glue(glue(op_cmovl,REGNAME),_T1_T0)(void) |
134 | 2c0262af | bellard | { |
135 | 2c0262af | bellard | if (T0)
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136 | 14ce26e7 | bellard | REG = (uint32_t)T1; |
137 | 14ce26e7 | bellard | FORCE_RET(); |
138 | 14ce26e7 | bellard | } |
139 | 14ce26e7 | bellard | |
140 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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141 | 14ce26e7 | bellard | void OPPROTO glue(glue(op_cmovq,REGNAME),_T1_T0)(void) |
142 | 14ce26e7 | bellard | { |
143 | 14ce26e7 | bellard | if (T0)
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144 | 2c0262af | bellard | REG = T1; |
145 | 128b346e | bellard | FORCE_RET(); |
146 | 2c0262af | bellard | } |
147 | 14ce26e7 | bellard | #endif
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148 | 2c0262af | bellard | |
149 | 2c0262af | bellard | /* NOTE: T0 high order bits are ignored */
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150 | 2c0262af | bellard | void OPPROTO glue(glue(op_movw,REGNAME),_T0)(void) |
151 | 2c0262af | bellard | { |
152 | 14ce26e7 | bellard | REG = (REG & ~0xffff) | (T0 & 0xffff); |
153 | 2c0262af | bellard | } |
154 | 2c0262af | bellard | |
155 | 2c0262af | bellard | /* NOTE: T0 high order bits are ignored */
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156 | 2c0262af | bellard | void OPPROTO glue(glue(op_movw,REGNAME),_T1)(void) |
157 | 2c0262af | bellard | { |
158 | 14ce26e7 | bellard | REG = (REG & ~0xffff) | (T1 & 0xffff); |
159 | 2c0262af | bellard | } |
160 | 2c0262af | bellard | |
161 | 2c0262af | bellard | /* NOTE: A0 high order bits are ignored */
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162 | 2c0262af | bellard | void OPPROTO glue(glue(op_movw,REGNAME),_A0)(void) |
163 | 2c0262af | bellard | { |
164 | 14ce26e7 | bellard | REG = (REG & ~0xffff) | (A0 & 0xffff); |
165 | 2c0262af | bellard | } |
166 | 2c0262af | bellard | |
167 | 2c0262af | bellard | /* NOTE: T0 high order bits are ignored */
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168 | 2c0262af | bellard | void OPPROTO glue(glue(op_movb,REGNAME),_T0)(void) |
169 | 2c0262af | bellard | { |
170 | 14ce26e7 | bellard | REG = (REG & ~0xff) | (T0 & 0xff); |
171 | 2c0262af | bellard | } |
172 | 2c0262af | bellard | |
173 | 2c0262af | bellard | /* NOTE: T0 high order bits are ignored */
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174 | 2c0262af | bellard | void OPPROTO glue(glue(op_movh,REGNAME),_T0)(void) |
175 | 2c0262af | bellard | { |
176 | 14ce26e7 | bellard | REG = (REG & ~0xff00) | ((T0 & 0xff) << 8); |
177 | 2c0262af | bellard | } |
178 | 2c0262af | bellard | |
179 | 2c0262af | bellard | /* NOTE: T1 high order bits are ignored */
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180 | 2c0262af | bellard | void OPPROTO glue(glue(op_movb,REGNAME),_T1)(void) |
181 | 2c0262af | bellard | { |
182 | 14ce26e7 | bellard | REG = (REG & ~0xff) | (T1 & 0xff); |
183 | 2c0262af | bellard | } |
184 | 2c0262af | bellard | |
185 | 2c0262af | bellard | /* NOTE: T1 high order bits are ignored */
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186 | 2c0262af | bellard | void OPPROTO glue(glue(op_movh,REGNAME),_T1)(void) |
187 | 2c0262af | bellard | { |
188 | 14ce26e7 | bellard | REG = (REG & ~0xff00) | ((T1 & 0xff) << 8); |
189 | 2c0262af | bellard | } |