| 6 |
6 |
/* If we want to use host float regs... */
|
| 7 |
7 |
//#define USE_HOST_FLOAT_REGS
|
| 8 |
8 |
|
| 9 |
|
enum {
|
| 10 |
|
MIPS_R4Kc = 0x00018000,
|
| 11 |
|
MIPS_R4Kp = 0x00018300,
|
| 12 |
|
};
|
|
9 |
#define MIPS_R4Kc 0x00018000
|
|
10 |
#define MIPS_R4Kp 0x00018300
|
| 13 |
11 |
|
| 14 |
12 |
/* Emulate MIPS R4Kc for now */
|
| 15 |
13 |
#define MIPS_CPU MIPS_R4Kc
|
| ... | ... | |
| 19 |
17 |
#define TARGET_LONG_BITS 32
|
| 20 |
18 |
/* real pages are variable size... */
|
| 21 |
19 |
#define TARGET_PAGE_BITS 12
|
| 22 |
|
/* Uses MIPS R4Kx ehancements to MIPS32 architecture */
|
|
20 |
/* Uses MIPS R4Kx enhancements to MIPS32 architecture */
|
| 23 |
21 |
#define MIPS_USES_R4K_EXT
|
| 24 |
22 |
/* Uses MIPS R4Kc TLB model */
|
| 25 |
23 |
#define MIPS_USES_R4K_TLB
|
| ... | ... | |
| 30 |
28 |
* Define a major version 1, minor version 0.
|
| 31 |
29 |
*/
|
| 32 |
30 |
#define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0)
|
| 33 |
|
/* Have config1, runs in big-endian mode, uses TLB */
|
| 34 |
|
#define MIPS_CONFIG0 \
|
| 35 |
|
((1 << CP0C0_M) | (0x000 << CP0C0_K23) | (0x000 << CP0C0_KU) | \
|
| 36 |
|
(1 << CP0C0_BE) | (0x001 << CP0C0_MT) | (0x010 << CP0C0_K0))
|
|
31 |
/* Have config1, uses TLB */
|
|
32 |
#define MIPS_CONFIG0_1 \
|
|
33 |
((1 << CP0C0_M) | (0 << CP0C0_K23) | (0 << CP0C0_KU) | \
|
|
34 |
(1 << CP0C0_MT) | (2 << CP0C0_K0))
|
|
35 |
#ifdef TARGET_WORDS_BIGENDIAN
|
|
36 |
#define MIPS_CONFIG0 (MIPS_CONFIG0_1 | (1 << CP0C0_BE))
|
|
37 |
#else
|
|
38 |
#define MIPS_CONFIG0 MIPS_CONFIG0_1
|
|
39 |
#endif
|
| 37 |
40 |
/* 16 TLBs, 64 sets Icache, 16 bytes Icache line, 2-way Icache,
|
| 38 |
41 |
* 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
|
| 39 |
42 |
* no performance counters, watch registers present, no code compression,
|
| ... | ... | |
| 45 |
48 |
(0x000 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x01 << CP0C1_DA) | \
|
| 46 |
49 |
(0 << CP0C1_PC) | (1 << CP0C1_WR) | (0 << CP0C1_CA) | \
|
| 47 |
50 |
(1 << CP0C1_EP) | (MIPS_USES_FPU << CP0C1_FP))
|
| 48 |
|
#elif defined (MIPS_CPU == MIPS_R4Kp)
|
|
51 |
#elif (MIPS_CPU == MIPS_R4Kp)
|
| 49 |
52 |
/* 32 bits target */
|
| 50 |
53 |
#define TARGET_LONG_BITS 32
|
| 51 |
54 |
/* real pages are variable size... */
|
| 52 |
55 |
#define TARGET_PAGE_BITS 12
|
| 53 |
|
/* Uses MIPS R4Kx ehancements to MIPS32 architecture */
|
|
56 |
/* Uses MIPS R4Kx enhancements to MIPS32 architecture */
|
| 54 |
57 |
#define MIPS_USES_R4K_EXT
|
| 55 |
58 |
/* Uses MIPS R4Km FPM MMU model */
|
| 56 |
59 |
#define MIPS_USES_R4K_FPM
|