Revision c5d6edc3 target-mips/mips-defs.h
b/target-mips/mips-defs.h | ||
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/* If we want to use host float regs... */ |
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//#define USE_HOST_FLOAT_REGS |
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enum { |
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MIPS_R4Kc = 0x00018000, |
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MIPS_R4Kp = 0x00018300, |
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}; |
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#define MIPS_R4Kc 0x00018000 |
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#define MIPS_R4Kp 0x00018300 |
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/* Emulate MIPS R4Kc for now */ |
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#define MIPS_CPU MIPS_R4Kc |
... | ... | |
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#define TARGET_LONG_BITS 32 |
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/* real pages are variable size... */ |
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#define TARGET_PAGE_BITS 12 |
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/* Uses MIPS R4Kx ehancements to MIPS32 architecture */ |
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/* Uses MIPS R4Kx enhancements to MIPS32 architecture */
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#define MIPS_USES_R4K_EXT |
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/* Uses MIPS R4Kc TLB model */ |
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#define MIPS_USES_R4K_TLB |
... | ... | |
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* Define a major version 1, minor version 0. |
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*/ |
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#define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0) |
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/* Have config1, runs in big-endian mode, uses TLB */ |
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#define MIPS_CONFIG0 \ |
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((1 << CP0C0_M) | (0x000 << CP0C0_K23) | (0x000 << CP0C0_KU) | \ |
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(1 << CP0C0_BE) | (0x001 << CP0C0_MT) | (0x010 << CP0C0_K0)) |
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/* Have config1, uses TLB */ |
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#define MIPS_CONFIG0_1 \ |
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((1 << CP0C0_M) | (0 << CP0C0_K23) | (0 << CP0C0_KU) | \ |
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(1 << CP0C0_MT) | (2 << CP0C0_K0)) |
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#ifdef TARGET_WORDS_BIGENDIAN |
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#define MIPS_CONFIG0 (MIPS_CONFIG0_1 | (1 << CP0C0_BE)) |
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#else |
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#define MIPS_CONFIG0 MIPS_CONFIG0_1 |
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#endif |
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/* 16 TLBs, 64 sets Icache, 16 bytes Icache line, 2-way Icache, |
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* 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache, |
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* no performance counters, watch registers present, no code compression, |
... | ... | |
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(0x000 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x01 << CP0C1_DA) | \ |
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(0 << CP0C1_PC) | (1 << CP0C1_WR) | (0 << CP0C1_CA) | \ |
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(1 << CP0C1_EP) | (MIPS_USES_FPU << CP0C1_FP)) |
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#elif defined (MIPS_CPU == MIPS_R4Kp)
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#elif (MIPS_CPU == MIPS_R4Kp) |
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/* 32 bits target */ |
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#define TARGET_LONG_BITS 32 |
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/* real pages are variable size... */ |
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#define TARGET_PAGE_BITS 12 |
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/* Uses MIPS R4Kx ehancements to MIPS32 architecture */ |
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/* Uses MIPS R4Kx enhancements to MIPS32 architecture */
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#define MIPS_USES_R4K_EXT |
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/* Uses MIPS R4Km FPM MMU model */ |
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#define MIPS_USES_R4K_FPM |
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