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/*
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* QEMU Sun4u/Sun4v System Emulator
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "pci.h" |
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#include "apb_pci.h" |
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#include "pc.h" |
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#include "nvram.h" |
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#include "fdc.h" |
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#include "net.h" |
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#include "qemu-timer.h" |
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#include "sysemu.h" |
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#include "boards.h" |
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#include "firmware_abi.h" |
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#include "fw_cfg.h" |
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#include "sysbus.h" |
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#include "ide.h" |
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#include "loader.h" |
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#include "elf.h" |
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#include "blockdev.h" |
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|
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//#define DEBUG_IRQ
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//#define DEBUG_EBUS
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//#define DEBUG_TIMER
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|
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#ifdef DEBUG_IRQ
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#define CPUIRQ_DPRINTF(fmt, ...) \
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do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define CPUIRQ_DPRINTF(fmt, ...)
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#endif
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|
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#ifdef DEBUG_EBUS
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#define EBUS_DPRINTF(fmt, ...) \
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do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define EBUS_DPRINTF(fmt, ...)
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#endif
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|
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#ifdef DEBUG_TIMER
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#define TIMER_DPRINTF(fmt, ...) \
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do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define TIMER_DPRINTF(fmt, ...)
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#endif
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|
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#define KERNEL_LOAD_ADDR 0x00404000 |
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#define CMDLINE_ADDR 0x003ff000 |
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#define INITRD_LOAD_ADDR 0x00300000 |
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#define PROM_SIZE_MAX (4 * 1024 * 1024) |
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#define PROM_VADDR 0x000ffd00000ULL |
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#define APB_SPECIAL_BASE 0x1fe00000000ULL |
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#define APB_MEM_BASE 0x1ff00000000ULL |
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#define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) |
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#define PROM_FILENAME "openbios-sparc64" |
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#define NVRAM_SIZE 0x2000 |
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#define MAX_IDE_BUS 2 |
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#define BIOS_CFG_IOPORT 0x510 |
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#define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
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#define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) |
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#define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) |
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|
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#define MAX_PILS 16 |
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|
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#define TICK_MAX 0x7fffffffffffffffULL |
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|
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struct hwdef {
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const char * const default_cpu_model; |
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uint16_t machine_id; |
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uint64_t prom_addr; |
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uint64_t console_serial_base; |
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}; |
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|
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typedef struct EbusState { |
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PCIDevice pci_dev; |
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MemoryRegion bar0; |
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MemoryRegion bar1; |
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} EbusState; |
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|
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int DMA_get_channel_mode (int nchan) |
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{ |
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return 0; |
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} |
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int DMA_read_memory (int nchan, void *buf, int pos, int size) |
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{ |
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return 0; |
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} |
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int DMA_write_memory (int nchan, void *buf, int pos, int size) |
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{ |
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return 0; |
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} |
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void DMA_hold_DREQ (int nchan) {} |
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void DMA_release_DREQ (int nchan) {} |
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void DMA_schedule(int nchan) {} |
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|
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void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) |
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{ |
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} |
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|
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void DMA_register_channel (int nchan, |
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DMA_transfer_handler transfer_handler, |
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void *opaque)
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{ |
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} |
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|
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static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
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{ |
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fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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return 0; |
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} |
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|
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static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size, |
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const char *arch, ram_addr_t RAM_size, |
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const char *boot_devices, |
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uint32_t kernel_image, uint32_t kernel_size, |
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const char *cmdline, |
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uint32_t initrd_image, uint32_t initrd_size, |
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uint32_t NVRAM_image, |
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int width, int height, int depth, |
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const uint8_t *macaddr)
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{ |
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unsigned int i; |
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uint32_t start, end; |
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uint8_t image[0x1ff0];
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struct OpenBIOS_nvpart_v1 *part_header;
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memset(image, '\0', sizeof(image)); |
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start = 0;
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// OpenBIOS nvram variables
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// Variable partition
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_SYSTEM; |
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pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
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end = start + sizeof(struct OpenBIOS_nvpart_v1); |
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for (i = 0; i < nb_prom_envs; i++) |
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end = OpenBIOS_set_var(image, end, prom_envs[i]); |
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// End marker
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image[end++] = '\0';
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end = start + ((end - start + 15) & ~15); |
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OpenBIOS_finish_partition(part_header, end - start); |
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// free partition
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start = end; |
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_FREE; |
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pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
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end = 0x1fd0;
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OpenBIOS_finish_partition(part_header, end - start); |
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Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
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for (i = 0; i < sizeof(image); i++) |
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m48t59_write(nvram, i, image[i]); |
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return 0; |
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} |
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static unsigned long sun4u_load_kernel(const char *kernel_filename, |
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const char *initrd_filename, |
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ram_addr_t RAM_size, long *initrd_size)
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{ |
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int linux_boot;
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unsigned int i; |
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long kernel_size;
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uint8_t *ptr; |
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linux_boot = (kernel_filename != NULL);
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kernel_size = 0;
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if (linux_boot) {
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int bswap_needed;
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#ifdef BSWAP_NEEDED
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bswap_needed = 1;
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#else
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bswap_needed = 0;
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#endif
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kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, |
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NULL, NULL, 1, ELF_MACHINE, 0); |
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if (kernel_size < 0) |
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kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
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RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
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TARGET_PAGE_SIZE); |
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if (kernel_size < 0) |
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kernel_size = load_image_targphys(kernel_filename, |
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KERNEL_LOAD_ADDR, |
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RAM_size - KERNEL_LOAD_ADDR); |
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if (kernel_size < 0) { |
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename); |
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exit(1);
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} |
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/* load initrd */
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*initrd_size = 0;
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if (initrd_filename) {
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*initrd_size = load_image_targphys(initrd_filename, |
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INITRD_LOAD_ADDR, |
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RAM_size - INITRD_LOAD_ADDR); |
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if (*initrd_size < 0) { |
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename); |
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exit(1);
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} |
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} |
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if (*initrd_size > 0) { |
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for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
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ptr = rom_ptr(KERNEL_LOAD_ADDR + i); |
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if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ |
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stl_p(ptr + 24, INITRD_LOAD_ADDR + KERNEL_LOAD_ADDR - 0x4000); |
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stl_p(ptr + 28, *initrd_size);
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break;
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} |
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} |
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} |
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} |
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return kernel_size;
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} |
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|
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void pic_info(Monitor *mon)
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{ |
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} |
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|
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void irq_info(Monitor *mon)
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{ |
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} |
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|
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void cpu_check_irqs(CPUState *env)
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{ |
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uint32_t pil = env->pil_in | |
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(env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); |
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/* check if TM or SM in SOFTINT are set
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setting these also causes interrupt 14 */
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if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
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pil |= 1 << 14; |
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} |
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|
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if (!pil) {
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if (env->interrupt_request & CPU_INTERRUPT_HARD) {
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CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
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env->interrupt_index); |
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env->interrupt_index = 0;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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return;
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} |
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|
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if (cpu_interrupts_enabled(env)) {
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|
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unsigned int i; |
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for (i = 15; i > env->psrpil; i--) { |
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if (pil & (1 << i)) { |
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int old_interrupt = env->interrupt_index;
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int new_interrupt = TT_EXTINT | i;
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|
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if (env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt) { |
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CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
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"current %x >= pending %x\n",
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env->tl, cpu_tsptr(env)->tt, new_interrupt); |
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} else if (old_interrupt != new_interrupt) { |
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env->interrupt_index = new_interrupt; |
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CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
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old_interrupt, new_interrupt); |
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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break;
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} |
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} |
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} else {
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CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
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"current interrupt %x\n",
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pil, env->pil_in, env->softint, env->interrupt_index); |
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} |
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} |
302 |
|
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static void cpu_kick_irq(CPUState *env) |
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{ |
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env->halted = 0;
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cpu_check_irqs(env); |
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qemu_cpu_kick(env); |
308 |
} |
309 |
|
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static void cpu_set_irq(void *opaque, int irq, int level) |
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{ |
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CPUState *env = opaque; |
313 |
|
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if (level) {
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CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq);
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env->pil_in |= 1 << irq;
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cpu_kick_irq(env); |
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} else {
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CPUIRQ_DPRINTF("Lower CPU IRQ %d\n", irq);
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env->pil_in &= ~(1 << irq);
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cpu_check_irqs(env); |
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} |
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} |
324 |
|
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typedef struct ResetData { |
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CPUState *env; |
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uint64_t prom_addr; |
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} ResetData; |
329 |
|
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void cpu_put_timer(QEMUFile *f, CPUTimer *s)
|
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{ |
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qemu_put_be32s(f, &s->frequency); |
333 |
qemu_put_be32s(f, &s->disabled); |
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qemu_put_be64s(f, &s->disabled_mask); |
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qemu_put_sbe64s(f, &s->clock_offset); |
336 |
|
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qemu_put_timer(f, s->qtimer); |
338 |
} |
339 |
|
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void cpu_get_timer(QEMUFile *f, CPUTimer *s)
|
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{ |
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qemu_get_be32s(f, &s->frequency); |
343 |
qemu_get_be32s(f, &s->disabled); |
344 |
qemu_get_be64s(f, &s->disabled_mask); |
345 |
qemu_get_sbe64s(f, &s->clock_offset); |
346 |
|
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qemu_get_timer(f, s->qtimer); |
348 |
} |
349 |
|
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static CPUTimer* cpu_timer_create(const char* name, CPUState *env, |
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QEMUBHFunc *cb, uint32_t frequency, |
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uint64_t disabled_mask) |
353 |
{ |
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CPUTimer *timer = qemu_mallocz(sizeof (CPUTimer));
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|
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timer->name = name; |
357 |
timer->frequency = frequency; |
358 |
timer->disabled_mask = disabled_mask; |
359 |
|
360 |
timer->disabled = 1;
|
361 |
timer->clock_offset = qemu_get_clock_ns(vm_clock); |
362 |
|
363 |
timer->qtimer = qemu_new_timer_ns(vm_clock, cb, env); |
364 |
|
365 |
return timer;
|
366 |
} |
367 |
|
368 |
static void cpu_timer_reset(CPUTimer *timer) |
369 |
{ |
370 |
timer->disabled = 1;
|
371 |
timer->clock_offset = qemu_get_clock_ns(vm_clock); |
372 |
|
373 |
qemu_del_timer(timer->qtimer); |
374 |
} |
375 |
|
376 |
static void main_cpu_reset(void *opaque) |
377 |
{ |
378 |
ResetData *s = (ResetData *)opaque; |
379 |
CPUState *env = s->env; |
380 |
static unsigned int nr_resets; |
381 |
|
382 |
cpu_reset(env); |
383 |
|
384 |
cpu_timer_reset(env->tick); |
385 |
cpu_timer_reset(env->stick); |
386 |
cpu_timer_reset(env->hstick); |
387 |
|
388 |
env->gregs[1] = 0; // Memory start |
389 |
env->gregs[2] = ram_size; // Memory size |
390 |
env->gregs[3] = 0; // Machine description XXX |
391 |
if (nr_resets++ == 0) { |
392 |
/* Power on reset */
|
393 |
env->pc = s->prom_addr + 0x20ULL;
|
394 |
} else {
|
395 |
env->pc = s->prom_addr + 0x40ULL;
|
396 |
} |
397 |
env->npc = env->pc + 4;
|
398 |
} |
399 |
|
400 |
static void tick_irq(void *opaque) |
401 |
{ |
402 |
CPUState *env = opaque; |
403 |
|
404 |
CPUTimer* timer = env->tick; |
405 |
|
406 |
if (timer->disabled) {
|
407 |
CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
|
408 |
return;
|
409 |
} else {
|
410 |
CPUIRQ_DPRINTF("tick: fire\n");
|
411 |
} |
412 |
|
413 |
env->softint |= SOFTINT_TIMER; |
414 |
cpu_kick_irq(env); |
415 |
} |
416 |
|
417 |
static void stick_irq(void *opaque) |
418 |
{ |
419 |
CPUState *env = opaque; |
420 |
|
421 |
CPUTimer* timer = env->stick; |
422 |
|
423 |
if (timer->disabled) {
|
424 |
CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
|
425 |
return;
|
426 |
} else {
|
427 |
CPUIRQ_DPRINTF("stick: fire\n");
|
428 |
} |
429 |
|
430 |
env->softint |= SOFTINT_STIMER; |
431 |
cpu_kick_irq(env); |
432 |
} |
433 |
|
434 |
static void hstick_irq(void *opaque) |
435 |
{ |
436 |
CPUState *env = opaque; |
437 |
|
438 |
CPUTimer* timer = env->hstick; |
439 |
|
440 |
if (timer->disabled) {
|
441 |
CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
|
442 |
return;
|
443 |
} else {
|
444 |
CPUIRQ_DPRINTF("hstick: fire\n");
|
445 |
} |
446 |
|
447 |
env->softint |= SOFTINT_STIMER; |
448 |
cpu_kick_irq(env); |
449 |
} |
450 |
|
451 |
static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
|
452 |
{ |
453 |
return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency);
|
454 |
} |
455 |
|
456 |
static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
|
457 |
{ |
458 |
return muldiv64(timer_ticks, frequency, get_ticks_per_sec());
|
459 |
} |
460 |
|
461 |
void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
|
462 |
{ |
463 |
uint64_t real_count = count & ~timer->disabled_mask; |
464 |
uint64_t disabled_bit = count & timer->disabled_mask; |
465 |
|
466 |
int64_t vm_clock_offset = qemu_get_clock_ns(vm_clock) - |
467 |
cpu_to_timer_ticks(real_count, timer->frequency); |
468 |
|
469 |
TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
|
470 |
timer->name, real_count, |
471 |
timer->disabled?"disabled":"enabled", timer); |
472 |
|
473 |
timer->disabled = disabled_bit ? 1 : 0; |
474 |
timer->clock_offset = vm_clock_offset; |
475 |
} |
476 |
|
477 |
uint64_t cpu_tick_get_count(CPUTimer *timer) |
478 |
{ |
479 |
uint64_t real_count = timer_to_cpu_ticks( |
480 |
qemu_get_clock_ns(vm_clock) - timer->clock_offset, |
481 |
timer->frequency); |
482 |
|
483 |
TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
|
484 |
timer->name, real_count, |
485 |
timer->disabled?"disabled":"enabled", timer); |
486 |
|
487 |
if (timer->disabled)
|
488 |
real_count |= timer->disabled_mask; |
489 |
|
490 |
return real_count;
|
491 |
} |
492 |
|
493 |
void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
|
494 |
{ |
495 |
int64_t now = qemu_get_clock_ns(vm_clock); |
496 |
|
497 |
uint64_t real_limit = limit & ~timer->disabled_mask; |
498 |
timer->disabled = (limit & timer->disabled_mask) ? 1 : 0; |
499 |
|
500 |
int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) + |
501 |
timer->clock_offset; |
502 |
|
503 |
if (expires < now) {
|
504 |
expires = now + 1;
|
505 |
} |
506 |
|
507 |
TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
|
508 |
"called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
|
509 |
timer->name, real_limit, |
510 |
timer->disabled?"disabled":"enabled", |
511 |
timer, limit, |
512 |
timer_to_cpu_ticks(now - timer->clock_offset, |
513 |
timer->frequency), |
514 |
timer_to_cpu_ticks(expires - now, timer->frequency)); |
515 |
|
516 |
if (!real_limit) {
|
517 |
TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
|
518 |
timer->name); |
519 |
qemu_del_timer(timer->qtimer); |
520 |
} else if (timer->disabled) { |
521 |
qemu_del_timer(timer->qtimer); |
522 |
} else {
|
523 |
qemu_mod_timer(timer->qtimer, expires); |
524 |
} |
525 |
} |
526 |
|
527 |
static void dummy_isa_irq_handler(void *opaque, int n, int level) |
528 |
{ |
529 |
} |
530 |
|
531 |
/* EBUS (Eight bit bus) bridge */
|
532 |
static void |
533 |
pci_ebus_init(PCIBus *bus, int devfn)
|
534 |
{ |
535 |
qemu_irq *isa_irq; |
536 |
|
537 |
pci_create_simple(bus, devfn, "ebus");
|
538 |
isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16); |
539 |
isa_bus_irqs(isa_irq); |
540 |
} |
541 |
|
542 |
static int |
543 |
pci_ebus_init1(PCIDevice *pci_dev) |
544 |
{ |
545 |
EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev); |
546 |
|
547 |
isa_bus_new(&pci_dev->qdev); |
548 |
|
549 |
pci_dev->config[0x04] = 0x06; // command = bus master, pci mem |
550 |
pci_dev->config[0x05] = 0x00; |
551 |
pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
552 |
pci_dev->config[0x07] = 0x03; // status = medium devsel |
553 |
pci_dev->config[0x09] = 0x00; // programming i/f |
554 |
pci_dev->config[0x0D] = 0x0a; // latency_timer |
555 |
|
556 |
isa_mmio_setup(&s->bar0, 0x1000000);
|
557 |
pci_register_bar_region(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
|
558 |
&s->bar0); |
559 |
isa_mmio_setup(&s->bar1, 0x800000);
|
560 |
pci_register_bar_region(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY,
|
561 |
&s->bar1); |
562 |
return 0; |
563 |
} |
564 |
|
565 |
static PCIDeviceInfo ebus_info = {
|
566 |
.qdev.name = "ebus",
|
567 |
.qdev.size = sizeof(EbusState),
|
568 |
.init = pci_ebus_init1, |
569 |
.vendor_id = PCI_VENDOR_ID_SUN, |
570 |
.device_id = PCI_DEVICE_ID_SUN_EBUS, |
571 |
.revision = 0x01,
|
572 |
.class_id = PCI_CLASS_BRIDGE_OTHER, |
573 |
}; |
574 |
|
575 |
static void pci_ebus_register(void) |
576 |
{ |
577 |
pci_qdev_register(&ebus_info); |
578 |
} |
579 |
|
580 |
device_init(pci_ebus_register); |
581 |
|
582 |
static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
583 |
{ |
584 |
target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque; |
585 |
return addr + *base_addr - PROM_VADDR;
|
586 |
} |
587 |
|
588 |
/* Boot PROM (OpenBIOS) */
|
589 |
static void prom_init(target_phys_addr_t addr, const char *bios_name) |
590 |
{ |
591 |
DeviceState *dev; |
592 |
SysBusDevice *s; |
593 |
char *filename;
|
594 |
int ret;
|
595 |
|
596 |
dev = qdev_create(NULL, "openprom"); |
597 |
qdev_init_nofail(dev); |
598 |
s = sysbus_from_qdev(dev); |
599 |
|
600 |
sysbus_mmio_map(s, 0, addr);
|
601 |
|
602 |
/* load boot prom */
|
603 |
if (bios_name == NULL) { |
604 |
bios_name = PROM_FILENAME; |
605 |
} |
606 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
607 |
if (filename) {
|
608 |
ret = load_elf(filename, translate_prom_address, &addr, |
609 |
NULL, NULL, NULL, 1, ELF_MACHINE, 0); |
610 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
611 |
ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); |
612 |
} |
613 |
qemu_free(filename); |
614 |
} else {
|
615 |
ret = -1;
|
616 |
} |
617 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
618 |
fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
619 |
exit(1);
|
620 |
} |
621 |
} |
622 |
|
623 |
static int prom_init1(SysBusDevice *dev) |
624 |
{ |
625 |
ram_addr_t prom_offset; |
626 |
|
627 |
prom_offset = qemu_ram_alloc(NULL, "sun4u.prom", PROM_SIZE_MAX); |
628 |
sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); |
629 |
return 0; |
630 |
} |
631 |
|
632 |
static SysBusDeviceInfo prom_info = {
|
633 |
.init = prom_init1, |
634 |
.qdev.name = "openprom",
|
635 |
.qdev.size = sizeof(SysBusDevice),
|
636 |
.qdev.props = (Property[]) { |
637 |
{/* end of property list */}
|
638 |
} |
639 |
}; |
640 |
|
641 |
static void prom_register_devices(void) |
642 |
{ |
643 |
sysbus_register_withprop(&prom_info); |
644 |
} |
645 |
|
646 |
device_init(prom_register_devices); |
647 |
|
648 |
|
649 |
typedef struct RamDevice |
650 |
{ |
651 |
SysBusDevice busdev; |
652 |
uint64_t size; |
653 |
} RamDevice; |
654 |
|
655 |
/* System RAM */
|
656 |
static int ram_init1(SysBusDevice *dev) |
657 |
{ |
658 |
ram_addr_t RAM_size, ram_offset; |
659 |
RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
660 |
|
661 |
RAM_size = d->size; |
662 |
|
663 |
ram_offset = qemu_ram_alloc(NULL, "sun4u.ram", RAM_size); |
664 |
sysbus_init_mmio(dev, RAM_size, ram_offset); |
665 |
return 0; |
666 |
} |
667 |
|
668 |
static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size) |
669 |
{ |
670 |
DeviceState *dev; |
671 |
SysBusDevice *s; |
672 |
RamDevice *d; |
673 |
|
674 |
/* allocate RAM */
|
675 |
dev = qdev_create(NULL, "memory"); |
676 |
s = sysbus_from_qdev(dev); |
677 |
|
678 |
d = FROM_SYSBUS(RamDevice, s); |
679 |
d->size = RAM_size; |
680 |
qdev_init_nofail(dev); |
681 |
|
682 |
sysbus_mmio_map(s, 0, addr);
|
683 |
} |
684 |
|
685 |
static SysBusDeviceInfo ram_info = {
|
686 |
.init = ram_init1, |
687 |
.qdev.name = "memory",
|
688 |
.qdev.size = sizeof(RamDevice),
|
689 |
.qdev.props = (Property[]) { |
690 |
DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
691 |
DEFINE_PROP_END_OF_LIST(), |
692 |
} |
693 |
}; |
694 |
|
695 |
static void ram_register_devices(void) |
696 |
{ |
697 |
sysbus_register_withprop(&ram_info); |
698 |
} |
699 |
|
700 |
device_init(ram_register_devices); |
701 |
|
702 |
static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) |
703 |
{ |
704 |
CPUState *env; |
705 |
ResetData *reset_info; |
706 |
|
707 |
uint32_t tick_frequency = 100*1000000; |
708 |
uint32_t stick_frequency = 100*1000000; |
709 |
uint32_t hstick_frequency = 100*1000000; |
710 |
|
711 |
if (!cpu_model)
|
712 |
cpu_model = hwdef->default_cpu_model; |
713 |
env = cpu_init(cpu_model); |
714 |
if (!env) {
|
715 |
fprintf(stderr, "Unable to find Sparc CPU definition\n");
|
716 |
exit(1);
|
717 |
} |
718 |
|
719 |
env->tick = cpu_timer_create("tick", env, tick_irq,
|
720 |
tick_frequency, TICK_NPT_MASK); |
721 |
|
722 |
env->stick = cpu_timer_create("stick", env, stick_irq,
|
723 |
stick_frequency, TICK_INT_DIS); |
724 |
|
725 |
env->hstick = cpu_timer_create("hstick", env, hstick_irq,
|
726 |
hstick_frequency, TICK_INT_DIS); |
727 |
|
728 |
reset_info = qemu_mallocz(sizeof(ResetData));
|
729 |
reset_info->env = env; |
730 |
reset_info->prom_addr = hwdef->prom_addr; |
731 |
qemu_register_reset(main_cpu_reset, reset_info); |
732 |
|
733 |
return env;
|
734 |
} |
735 |
|
736 |
static void sun4uv_init(ram_addr_t RAM_size, |
737 |
const char *boot_devices, |
738 |
const char *kernel_filename, const char *kernel_cmdline, |
739 |
const char *initrd_filename, const char *cpu_model, |
740 |
const struct hwdef *hwdef) |
741 |
{ |
742 |
CPUState *env; |
743 |
M48t59State *nvram; |
744 |
unsigned int i; |
745 |
long initrd_size, kernel_size;
|
746 |
PCIBus *pci_bus, *pci_bus2, *pci_bus3; |
747 |
qemu_irq *irq; |
748 |
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
749 |
DriveInfo *fd[MAX_FD]; |
750 |
void *fw_cfg;
|
751 |
|
752 |
/* init CPUs */
|
753 |
env = cpu_devinit(cpu_model, hwdef); |
754 |
|
755 |
/* set up devices */
|
756 |
ram_init(0, RAM_size);
|
757 |
|
758 |
prom_init(hwdef->prom_addr, bios_name); |
759 |
|
760 |
|
761 |
irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
762 |
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2, |
763 |
&pci_bus3); |
764 |
isa_mem_base = APB_PCI_IO_BASE; |
765 |
pci_vga_init(pci_bus); |
766 |
|
767 |
// XXX Should be pci_bus3
|
768 |
pci_ebus_init(pci_bus, -1);
|
769 |
|
770 |
i = 0;
|
771 |
if (hwdef->console_serial_base) {
|
772 |
serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200, |
773 |
serial_hds[i], 1, 1); |
774 |
i++; |
775 |
} |
776 |
for(; i < MAX_SERIAL_PORTS; i++) {
|
777 |
if (serial_hds[i]) {
|
778 |
serial_isa_init(i, serial_hds[i]); |
779 |
} |
780 |
} |
781 |
|
782 |
for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
783 |
if (parallel_hds[i]) {
|
784 |
parallel_init(i, parallel_hds[i]); |
785 |
} |
786 |
} |
787 |
|
788 |
for(i = 0; i < nb_nics; i++) |
789 |
pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); |
790 |
|
791 |
ide_drive_get(hd, MAX_IDE_BUS); |
792 |
|
793 |
pci_cmd646_ide_init(pci_bus, hd, 1);
|
794 |
|
795 |
isa_create_simple("i8042");
|
796 |
for(i = 0; i < MAX_FD; i++) { |
797 |
fd[i] = drive_get(IF_FLOPPY, 0, i);
|
798 |
} |
799 |
fdctrl_init_isa(fd); |
800 |
nvram = m48t59_init_isa(0x0074, NVRAM_SIZE, 59); |
801 |
|
802 |
initrd_size = 0;
|
803 |
kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename, |
804 |
ram_size, &initrd_size); |
805 |
|
806 |
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
|
807 |
KERNEL_LOAD_ADDR, kernel_size, |
808 |
kernel_cmdline, |
809 |
INITRD_LOAD_ADDR, initrd_size, |
810 |
/* XXX: need an option to load a NVRAM image */
|
811 |
0,
|
812 |
graphic_width, graphic_height, graphic_depth, |
813 |
(uint8_t *)&nd_table[0].macaddr);
|
814 |
|
815 |
fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
816 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
817 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
818 |
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
819 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
820 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
821 |
if (kernel_cmdline) {
|
822 |
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
823 |
strlen(kernel_cmdline) + 1);
|
824 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
825 |
(uint8_t*)strdup(kernel_cmdline), |
826 |
strlen(kernel_cmdline) + 1);
|
827 |
} else {
|
828 |
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
|
829 |
} |
830 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
831 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
832 |
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
|
833 |
|
834 |
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); |
835 |
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); |
836 |
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); |
837 |
|
838 |
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
839 |
} |
840 |
|
841 |
enum {
|
842 |
sun4u_id = 0,
|
843 |
sun4v_id = 64,
|
844 |
niagara_id, |
845 |
}; |
846 |
|
847 |
static const struct hwdef hwdefs[] = { |
848 |
/* Sun4u generic PC-like machine */
|
849 |
{ |
850 |
.default_cpu_model = "TI UltraSparc IIi",
|
851 |
.machine_id = sun4u_id, |
852 |
.prom_addr = 0x1fff0000000ULL,
|
853 |
.console_serial_base = 0,
|
854 |
}, |
855 |
/* Sun4v generic PC-like machine */
|
856 |
{ |
857 |
.default_cpu_model = "Sun UltraSparc T1",
|
858 |
.machine_id = sun4v_id, |
859 |
.prom_addr = 0x1fff0000000ULL,
|
860 |
.console_serial_base = 0,
|
861 |
}, |
862 |
/* Sun4v generic Niagara machine */
|
863 |
{ |
864 |
.default_cpu_model = "Sun UltraSparc T1",
|
865 |
.machine_id = niagara_id, |
866 |
.prom_addr = 0xfff0000000ULL,
|
867 |
.console_serial_base = 0xfff0c2c000ULL,
|
868 |
}, |
869 |
}; |
870 |
|
871 |
/* Sun4u hardware initialisation */
|
872 |
static void sun4u_init(ram_addr_t RAM_size, |
873 |
const char *boot_devices, |
874 |
const char *kernel_filename, const char *kernel_cmdline, |
875 |
const char *initrd_filename, const char *cpu_model) |
876 |
{ |
877 |
sun4uv_init(RAM_size, boot_devices, kernel_filename, |
878 |
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
|
879 |
} |
880 |
|
881 |
/* Sun4v hardware initialisation */
|
882 |
static void sun4v_init(ram_addr_t RAM_size, |
883 |
const char *boot_devices, |
884 |
const char *kernel_filename, const char *kernel_cmdline, |
885 |
const char *initrd_filename, const char *cpu_model) |
886 |
{ |
887 |
sun4uv_init(RAM_size, boot_devices, kernel_filename, |
888 |
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
|
889 |
} |
890 |
|
891 |
/* Niagara hardware initialisation */
|
892 |
static void niagara_init(ram_addr_t RAM_size, |
893 |
const char *boot_devices, |
894 |
const char *kernel_filename, const char *kernel_cmdline, |
895 |
const char *initrd_filename, const char *cpu_model) |
896 |
{ |
897 |
sun4uv_init(RAM_size, boot_devices, kernel_filename, |
898 |
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
|
899 |
} |
900 |
|
901 |
static QEMUMachine sun4u_machine = {
|
902 |
.name = "sun4u",
|
903 |
.desc = "Sun4u platform",
|
904 |
.init = sun4u_init, |
905 |
.max_cpus = 1, // XXX for now |
906 |
.is_default = 1,
|
907 |
}; |
908 |
|
909 |
static QEMUMachine sun4v_machine = {
|
910 |
.name = "sun4v",
|
911 |
.desc = "Sun4v platform",
|
912 |
.init = sun4v_init, |
913 |
.max_cpus = 1, // XXX for now |
914 |
}; |
915 |
|
916 |
static QEMUMachine niagara_machine = {
|
917 |
.name = "Niagara",
|
918 |
.desc = "Sun4v platform, Niagara",
|
919 |
.init = niagara_init, |
920 |
.max_cpus = 1, // XXX for now |
921 |
}; |
922 |
|
923 |
static void sun4u_machine_init(void) |
924 |
{ |
925 |
qemu_register_machine(&sun4u_machine); |
926 |
qemu_register_machine(&sun4v_machine); |
927 |
qemu_register_machine(&niagara_machine); |
928 |
} |
929 |
|
930 |
machine_init(sun4u_machine_init); |