root / hw / mst_fpga.c @ c60e08d9
History | View | Annotate | Download (5.2 kB)
1 | 7233b355 | ths | /*
|
---|---|---|---|
2 | 7233b355 | ths | * PXA270-based Intel Mainstone platforms.
|
3 | 7233b355 | ths | * FPGA driver
|
4 | 7233b355 | ths | *
|
5 | 7233b355 | ths | * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
|
6 | 7233b355 | ths | * <akuster@mvista.com>
|
7 | 7233b355 | ths | *
|
8 | 7233b355 | ths | * This code is licensed under the GNU GPL v2.
|
9 | 7233b355 | ths | */
|
10 | 7233b355 | ths | #include "hw.h" |
11 | 7233b355 | ths | #include "pxa.h" |
12 | 7233b355 | ths | #include "mainstone.h" |
13 | 7233b355 | ths | |
14 | 7233b355 | ths | /* Mainstone FPGA for extern irqs */
|
15 | 7233b355 | ths | #define FPGA_GPIO_PIN 0 |
16 | 7233b355 | ths | #define MST_NUM_IRQS 16 |
17 | 7233b355 | ths | #define MST_BASE MST_FPGA_PHYS
|
18 | 7233b355 | ths | #define MST_LEDDAT1 0x10 |
19 | 7233b355 | ths | #define MST_LEDDAT2 0x14 |
20 | 7233b355 | ths | #define MST_LEDCTRL 0x40 |
21 | 7233b355 | ths | #define MST_GPSWR 0x60 |
22 | 7233b355 | ths | #define MST_MSCWR1 0x80 |
23 | 7233b355 | ths | #define MST_MSCWR2 0x84 |
24 | 7233b355 | ths | #define MST_MSCWR3 0x88 |
25 | 7233b355 | ths | #define MST_MSCRD 0x90 |
26 | 7233b355 | ths | #define MST_INTMSKENA 0xc0 |
27 | 7233b355 | ths | #define MST_INTSETCLR 0xd0 |
28 | 7233b355 | ths | #define MST_PCMCIA0 0xe0 |
29 | 7233b355 | ths | #define MST_PCMCIA1 0xe4 |
30 | 7233b355 | ths | |
31 | 7233b355 | ths | typedef struct mst_irq_state{ |
32 | 7233b355 | ths | target_phys_addr_t target_base; |
33 | 7233b355 | ths | qemu_irq *parent; |
34 | 7233b355 | ths | qemu_irq *pins; |
35 | 7233b355 | ths | |
36 | 7233b355 | ths | uint32_t prev_level; |
37 | 7233b355 | ths | uint32_t leddat1; |
38 | 7233b355 | ths | uint32_t leddat2; |
39 | 7233b355 | ths | uint32_t ledctrl; |
40 | 7233b355 | ths | uint32_t gpswr; |
41 | 7233b355 | ths | uint32_t mscwr1; |
42 | 7233b355 | ths | uint32_t mscwr2; |
43 | 7233b355 | ths | uint32_t mscwr3; |
44 | 7233b355 | ths | uint32_t mscrd; |
45 | 7233b355 | ths | uint32_t intmskena; |
46 | 7233b355 | ths | uint32_t intsetclr; |
47 | 7233b355 | ths | uint32_t pcmcia0; |
48 | 7233b355 | ths | uint32_t pcmcia1; |
49 | 7233b355 | ths | }mst_irq_state; |
50 | 7233b355 | ths | |
51 | 7233b355 | ths | static void |
52 | 7233b355 | ths | mst_fpga_update_gpio(mst_irq_state *s) |
53 | 7233b355 | ths | { |
54 | 7233b355 | ths | uint32_t level, diff; |
55 | 7233b355 | ths | int bit;
|
56 | 7233b355 | ths | level = s->prev_level ^ s->intsetclr; |
57 | 7233b355 | ths | |
58 | 7233b355 | ths | for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { |
59 | 7233b355 | ths | bit = ffs(diff) - 1;
|
60 | 7233b355 | ths | qemu_set_irq(s->pins[bit], (level >> bit) & 1 );
|
61 | 7233b355 | ths | } |
62 | 7233b355 | ths | s->prev_level = level; |
63 | 7233b355 | ths | } |
64 | 7233b355 | ths | |
65 | 7233b355 | ths | static void |
66 | 7233b355 | ths | mst_fpga_set_irq(void *opaque, int irq, int level) |
67 | 7233b355 | ths | { |
68 | 7233b355 | ths | mst_irq_state *s = (mst_irq_state *)opaque; |
69 | 7233b355 | ths | |
70 | 7233b355 | ths | if (level)
|
71 | 7233b355 | ths | s->prev_level |= 1u << irq;
|
72 | 7233b355 | ths | else
|
73 | 7233b355 | ths | s->prev_level &= ~(1u << irq);
|
74 | 7233b355 | ths | |
75 | 7233b355 | ths | if(s->intmskena & (1u << irq)) { |
76 | 7233b355 | ths | s->intsetclr = 1u << irq;
|
77 | 7233b355 | ths | qemu_set_irq(s->parent[0], level);
|
78 | 7233b355 | ths | } |
79 | 7233b355 | ths | } |
80 | 7233b355 | ths | |
81 | 7233b355 | ths | |
82 | 7233b355 | ths | static uint32_t
|
83 | 7233b355 | ths | mst_fpga_readb(void *opaque, target_phys_addr_t addr)
|
84 | 7233b355 | ths | { |
85 | 7233b355 | ths | mst_irq_state *s = (mst_irq_state *) opaque; |
86 | 7233b355 | ths | addr -= s->target_base; |
87 | 7233b355 | ths | |
88 | 7233b355 | ths | switch (addr) {
|
89 | 7233b355 | ths | case MST_LEDDAT1:
|
90 | 7233b355 | ths | return s->leddat1;
|
91 | 7233b355 | ths | case MST_LEDDAT2:
|
92 | 7233b355 | ths | return s->leddat2;
|
93 | 7233b355 | ths | case MST_LEDCTRL:
|
94 | 7233b355 | ths | return s->ledctrl;
|
95 | 7233b355 | ths | case MST_GPSWR:
|
96 | 7233b355 | ths | return s->gpswr;
|
97 | 7233b355 | ths | case MST_MSCWR1:
|
98 | 7233b355 | ths | return s->mscwr1;
|
99 | 7233b355 | ths | case MST_MSCWR2:
|
100 | 7233b355 | ths | return s->mscwr2;
|
101 | 7233b355 | ths | case MST_MSCWR3:
|
102 | 7233b355 | ths | return s->mscwr3;
|
103 | 7233b355 | ths | case MST_MSCRD:
|
104 | 7233b355 | ths | return s->mscrd;
|
105 | 7233b355 | ths | case MST_INTMSKENA:
|
106 | 7233b355 | ths | return s->intmskena;
|
107 | 7233b355 | ths | case MST_INTSETCLR:
|
108 | 7233b355 | ths | return s->intsetclr;
|
109 | 7233b355 | ths | case MST_PCMCIA0:
|
110 | 7233b355 | ths | return s->pcmcia0;
|
111 | 7233b355 | ths | case MST_PCMCIA1:
|
112 | 7233b355 | ths | return s->pcmcia1;
|
113 | 7233b355 | ths | default:
|
114 | 7233b355 | ths | printf("Mainstone - mst_fpga_readb: Bad register offset "
|
115 | 7233b355 | ths | REG_FMT " \n", addr);
|
116 | 7233b355 | ths | } |
117 | 7233b355 | ths | return 0; |
118 | 7233b355 | ths | } |
119 | 7233b355 | ths | |
120 | 7233b355 | ths | static void |
121 | 7233b355 | ths | mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
|
122 | 7233b355 | ths | { |
123 | 7233b355 | ths | mst_irq_state *s = (mst_irq_state *) opaque; |
124 | 7233b355 | ths | addr -= s->target_base; |
125 | 7233b355 | ths | value &= 0xffffffff;
|
126 | 7233b355 | ths | |
127 | 7233b355 | ths | switch (addr) {
|
128 | 7233b355 | ths | case MST_LEDDAT1:
|
129 | 7233b355 | ths | s->leddat1 = value; |
130 | 7233b355 | ths | break;
|
131 | 7233b355 | ths | case MST_LEDDAT2:
|
132 | 7233b355 | ths | s->leddat2 = value; |
133 | 7233b355 | ths | break;
|
134 | 7233b355 | ths | case MST_LEDCTRL:
|
135 | 7233b355 | ths | s->ledctrl = value; |
136 | 7233b355 | ths | break;
|
137 | 7233b355 | ths | case MST_GPSWR:
|
138 | 7233b355 | ths | s->gpswr = value; |
139 | 7233b355 | ths | break;
|
140 | 7233b355 | ths | case MST_MSCWR1:
|
141 | 7233b355 | ths | s->mscwr1 = value; |
142 | 7233b355 | ths | break;
|
143 | 7233b355 | ths | case MST_MSCWR2:
|
144 | 7233b355 | ths | s->mscwr2 = value; |
145 | 7233b355 | ths | break;
|
146 | 7233b355 | ths | case MST_MSCWR3:
|
147 | 7233b355 | ths | s->mscwr3 = value; |
148 | 7233b355 | ths | break;
|
149 | 7233b355 | ths | case MST_MSCRD:
|
150 | 7233b355 | ths | s->mscrd = value; |
151 | 7233b355 | ths | break;
|
152 | 7233b355 | ths | case MST_INTMSKENA: /* Mask interupt */ |
153 | 7233b355 | ths | s->intmskena = (value & 0xFEEFF);
|
154 | 7233b355 | ths | mst_fpga_update_gpio(s); |
155 | 7233b355 | ths | break;
|
156 | 7233b355 | ths | case MST_INTSETCLR: /* clear or set interrupt */ |
157 | 7233b355 | ths | s->intsetclr = (value & 0xFEEFF);
|
158 | 7233b355 | ths | break;
|
159 | 7233b355 | ths | case MST_PCMCIA0:
|
160 | 7233b355 | ths | s->pcmcia0 = value; |
161 | 7233b355 | ths | break;
|
162 | 7233b355 | ths | case MST_PCMCIA1:
|
163 | 7233b355 | ths | s->pcmcia1 = value; |
164 | 7233b355 | ths | break;
|
165 | 7233b355 | ths | default:
|
166 | 7233b355 | ths | printf("Mainstone - mst_fpga_writeb: Bad register offset "
|
167 | 7233b355 | ths | REG_FMT " \n", addr);
|
168 | 7233b355 | ths | } |
169 | 7233b355 | ths | } |
170 | 7233b355 | ths | |
171 | 7233b355 | ths | CPUReadMemoryFunc *mst_fpga_readfn[] = { |
172 | 7233b355 | ths | mst_fpga_readb, |
173 | 7233b355 | ths | mst_fpga_readb, |
174 | 7233b355 | ths | mst_fpga_readb, |
175 | 7233b355 | ths | }; |
176 | 7233b355 | ths | CPUWriteMemoryFunc *mst_fpga_writefn[] = { |
177 | 7233b355 | ths | mst_fpga_writeb, |
178 | 7233b355 | ths | mst_fpga_writeb, |
179 | 7233b355 | ths | mst_fpga_writeb, |
180 | 7233b355 | ths | }; |
181 | 7233b355 | ths | |
182 | 7233b355 | ths | static void |
183 | 7233b355 | ths | mst_fpga_save(QEMUFile *f, void *opaque)
|
184 | 7233b355 | ths | { |
185 | 7233b355 | ths | struct mst_irq_state *s = (mst_irq_state *) opaque;
|
186 | 7233b355 | ths | |
187 | 7233b355 | ths | qemu_put_be32s(f, &s->prev_level); |
188 | 7233b355 | ths | qemu_put_be32s(f, &s->leddat1); |
189 | 7233b355 | ths | qemu_put_be32s(f, &s->leddat2); |
190 | 7233b355 | ths | qemu_put_be32s(f, &s->ledctrl); |
191 | 7233b355 | ths | qemu_put_be32s(f, &s->gpswr); |
192 | 7233b355 | ths | qemu_put_be32s(f, &s->mscwr1); |
193 | 7233b355 | ths | qemu_put_be32s(f, &s->mscwr2); |
194 | 7233b355 | ths | qemu_put_be32s(f, &s->mscwr3); |
195 | 7233b355 | ths | qemu_put_be32s(f, &s->mscrd); |
196 | 7233b355 | ths | qemu_put_be32s(f, &s->intmskena); |
197 | 7233b355 | ths | qemu_put_be32s(f, &s->intsetclr); |
198 | 7233b355 | ths | qemu_put_be32s(f, &s->pcmcia0); |
199 | 7233b355 | ths | qemu_put_be32s(f, &s->pcmcia1); |
200 | 7233b355 | ths | } |
201 | 7233b355 | ths | |
202 | 7233b355 | ths | static int |
203 | 7233b355 | ths | mst_fpga_load(QEMUFile *f, void *opaque, int version_id) |
204 | 7233b355 | ths | { |
205 | 7233b355 | ths | mst_irq_state *s = (mst_irq_state *) opaque; |
206 | 7233b355 | ths | |
207 | 7233b355 | ths | qemu_get_be32s(f, &s->prev_level); |
208 | 7233b355 | ths | qemu_get_be32s(f, &s->leddat1); |
209 | 7233b355 | ths | qemu_get_be32s(f, &s->leddat2); |
210 | 7233b355 | ths | qemu_get_be32s(f, &s->ledctrl); |
211 | 7233b355 | ths | qemu_get_be32s(f, &s->gpswr); |
212 | 7233b355 | ths | qemu_get_be32s(f, &s->mscwr1); |
213 | 7233b355 | ths | qemu_get_be32s(f, &s->mscwr2); |
214 | 7233b355 | ths | qemu_get_be32s(f, &s->mscwr3); |
215 | 7233b355 | ths | qemu_get_be32s(f, &s->mscrd); |
216 | 7233b355 | ths | qemu_get_be32s(f, &s->intmskena); |
217 | 7233b355 | ths | qemu_get_be32s(f, &s->intsetclr); |
218 | 7233b355 | ths | qemu_get_be32s(f, &s->pcmcia0); |
219 | 7233b355 | ths | qemu_get_be32s(f, &s->pcmcia1); |
220 | 7233b355 | ths | return 0; |
221 | 7233b355 | ths | } |
222 | 7233b355 | ths | |
223 | 7233b355 | ths | qemu_irq *mst_irq_init(struct pxa2xx_state_s *cpu, uint32_t base, int irq) |
224 | 7233b355 | ths | { |
225 | 7233b355 | ths | mst_irq_state *s; |
226 | 7233b355 | ths | int iomemtype;
|
227 | 7233b355 | ths | qemu_irq *qi; |
228 | 7233b355 | ths | |
229 | 7233b355 | ths | s = (mst_irq_state *) |
230 | 7233b355 | ths | qemu_mallocz(sizeof(mst_irq_state));
|
231 | 7233b355 | ths | |
232 | 7233b355 | ths | if (!s)
|
233 | 7233b355 | ths | return NULL; |
234 | 7233b355 | ths | s->target_base = base; |
235 | 7233b355 | ths | s->parent = &cpu->pic[irq]; |
236 | 7233b355 | ths | |
237 | 7233b355 | ths | /* alloc the external 16 irqs */
|
238 | 7233b355 | ths | qi = qemu_allocate_irqs(mst_fpga_set_irq, s, MST_NUM_IRQS); |
239 | 7233b355 | ths | s->pins = qi; |
240 | 7233b355 | ths | |
241 | 7233b355 | ths | iomemtype = cpu_register_io_memory(0, mst_fpga_readfn,
|
242 | 7233b355 | ths | mst_fpga_writefn, s); |
243 | 7233b355 | ths | cpu_register_physical_memory(MST_BASE, 0x00100000, iomemtype);
|
244 | 7233b355 | ths | register_savevm("mainstone_fpga", 0, 0, mst_fpga_save, mst_fpga_load, s); |
245 | 7233b355 | ths | return qi;
|
246 | 7233b355 | ths | } |