root / hw / etraxfs_dma.c @ c65fc1df
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1 | 1ba13a5d | edgar_igl | /*
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2 | 1ba13a5d | edgar_igl | * QEMU ETRAX DMA Controller.
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3 | 1ba13a5d | edgar_igl | *
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4 | 1ba13a5d | edgar_igl | * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
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5 | 1ba13a5d | edgar_igl | *
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6 | 1ba13a5d | edgar_igl | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 1ba13a5d | edgar_igl | * of this software and associated documentation files (the "Software"), to deal
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8 | 1ba13a5d | edgar_igl | * in the Software without restriction, including without limitation the rights
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9 | 1ba13a5d | edgar_igl | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 1ba13a5d | edgar_igl | * copies of the Software, and to permit persons to whom the Software is
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11 | 1ba13a5d | edgar_igl | * furnished to do so, subject to the following conditions:
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12 | 1ba13a5d | edgar_igl | *
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13 | 1ba13a5d | edgar_igl | * The above copyright notice and this permission notice shall be included in
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14 | 1ba13a5d | edgar_igl | * all copies or substantial portions of the Software.
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15 | 1ba13a5d | edgar_igl | *
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16 | 1ba13a5d | edgar_igl | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 1ba13a5d | edgar_igl | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 1ba13a5d | edgar_igl | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 1ba13a5d | edgar_igl | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 1ba13a5d | edgar_igl | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 1ba13a5d | edgar_igl | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 1ba13a5d | edgar_igl | * THE SOFTWARE.
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23 | 1ba13a5d | edgar_igl | */
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24 | 1ba13a5d | edgar_igl | #include <stdio.h> |
25 | 1ba13a5d | edgar_igl | #include <sys/time.h> |
26 | 1ba13a5d | edgar_igl | #include "hw.h" |
27 | 9dcb06ce | Edgar E. Iglesias | #include "exec-memory.h" |
28 | 492c30af | aliguori | #include "qemu-common.h" |
29 | 492c30af | aliguori | #include "sysemu.h" |
30 | 1ba13a5d | edgar_igl | |
31 | 1ba13a5d | edgar_igl | #include "etraxfs_dma.h" |
32 | 1ba13a5d | edgar_igl | |
33 | 1ba13a5d | edgar_igl | #define D(x)
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34 | 1ba13a5d | edgar_igl | |
35 | c01c07bb | edgar_igl | #define RW_DATA (0x0 / 4) |
36 | c01c07bb | edgar_igl | #define RW_SAVED_DATA (0x58 / 4) |
37 | c01c07bb | edgar_igl | #define RW_SAVED_DATA_BUF (0x5c / 4) |
38 | c01c07bb | edgar_igl | #define RW_GROUP (0x60 / 4) |
39 | c01c07bb | edgar_igl | #define RW_GROUP_DOWN (0x7c / 4) |
40 | c01c07bb | edgar_igl | #define RW_CMD (0x80 / 4) |
41 | c01c07bb | edgar_igl | #define RW_CFG (0x84 / 4) |
42 | c01c07bb | edgar_igl | #define RW_STAT (0x88 / 4) |
43 | c01c07bb | edgar_igl | #define RW_INTR_MASK (0x8c / 4) |
44 | c01c07bb | edgar_igl | #define RW_ACK_INTR (0x90 / 4) |
45 | c01c07bb | edgar_igl | #define R_INTR (0x94 / 4) |
46 | c01c07bb | edgar_igl | #define R_MASKED_INTR (0x98 / 4) |
47 | c01c07bb | edgar_igl | #define RW_STREAM_CMD (0x9c / 4) |
48 | c01c07bb | edgar_igl | |
49 | c01c07bb | edgar_igl | #define DMA_REG_MAX (0x100 / 4) |
50 | 1ba13a5d | edgar_igl | |
51 | 1ba13a5d | edgar_igl | /* descriptors */
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52 | 1ba13a5d | edgar_igl | |
53 | 1ba13a5d | edgar_igl | // ------------------------------------------------------------ dma_descr_group
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54 | 1ba13a5d | edgar_igl | typedef struct dma_descr_group { |
55 | 41107bcb | Edgar E. Iglesias | uint32_t next; |
56 | 1ba13a5d | edgar_igl | unsigned eol : 1; |
57 | 1ba13a5d | edgar_igl | unsigned tol : 1; |
58 | 1ba13a5d | edgar_igl | unsigned bol : 1; |
59 | 1ba13a5d | edgar_igl | unsigned : 1; |
60 | 1ba13a5d | edgar_igl | unsigned intr : 1; |
61 | 1ba13a5d | edgar_igl | unsigned : 2; |
62 | 1ba13a5d | edgar_igl | unsigned en : 1; |
63 | 1ba13a5d | edgar_igl | unsigned : 7; |
64 | 1ba13a5d | edgar_igl | unsigned dis : 1; |
65 | 1ba13a5d | edgar_igl | unsigned md : 16; |
66 | 1ba13a5d | edgar_igl | struct dma_descr_group *up;
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67 | 1ba13a5d | edgar_igl | union {
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68 | 1ba13a5d | edgar_igl | struct dma_descr_context *context;
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69 | 1ba13a5d | edgar_igl | struct dma_descr_group *group;
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70 | 1ba13a5d | edgar_igl | } down; |
71 | 1ba13a5d | edgar_igl | } dma_descr_group; |
72 | 1ba13a5d | edgar_igl | |
73 | 1ba13a5d | edgar_igl | // ---------------------------------------------------------- dma_descr_context
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74 | 1ba13a5d | edgar_igl | typedef struct dma_descr_context { |
75 | 41107bcb | Edgar E. Iglesias | uint32_t next; |
76 | 1ba13a5d | edgar_igl | unsigned eol : 1; |
77 | 1ba13a5d | edgar_igl | unsigned : 3; |
78 | 1ba13a5d | edgar_igl | unsigned intr : 1; |
79 | 1ba13a5d | edgar_igl | unsigned : 1; |
80 | 1ba13a5d | edgar_igl | unsigned store_mode : 1; |
81 | 1ba13a5d | edgar_igl | unsigned en : 1; |
82 | 1ba13a5d | edgar_igl | unsigned : 7; |
83 | 1ba13a5d | edgar_igl | unsigned dis : 1; |
84 | 1ba13a5d | edgar_igl | unsigned md0 : 16; |
85 | 1ba13a5d | edgar_igl | unsigned md1;
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86 | 1ba13a5d | edgar_igl | unsigned md2;
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87 | 1ba13a5d | edgar_igl | unsigned md3;
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88 | 1ba13a5d | edgar_igl | unsigned md4;
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89 | 41107bcb | Edgar E. Iglesias | uint32_t saved_data; |
90 | 41107bcb | Edgar E. Iglesias | uint32_t saved_data_buf; |
91 | 1ba13a5d | edgar_igl | } dma_descr_context; |
92 | 1ba13a5d | edgar_igl | |
93 | 1ba13a5d | edgar_igl | // ------------------------------------------------------------- dma_descr_data
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94 | 1ba13a5d | edgar_igl | typedef struct dma_descr_data { |
95 | 41107bcb | Edgar E. Iglesias | uint32_t next; |
96 | 41107bcb | Edgar E. Iglesias | uint32_t buf; |
97 | 1ba13a5d | edgar_igl | unsigned eol : 1; |
98 | 1ba13a5d | edgar_igl | unsigned : 2; |
99 | 1ba13a5d | edgar_igl | unsigned out_eop : 1; |
100 | 1ba13a5d | edgar_igl | unsigned intr : 1; |
101 | 1ba13a5d | edgar_igl | unsigned wait : 1; |
102 | 1ba13a5d | edgar_igl | unsigned : 2; |
103 | 1ba13a5d | edgar_igl | unsigned : 3; |
104 | 1ba13a5d | edgar_igl | unsigned in_eop : 1; |
105 | 1ba13a5d | edgar_igl | unsigned : 4; |
106 | 1ba13a5d | edgar_igl | unsigned md : 16; |
107 | 41107bcb | Edgar E. Iglesias | uint32_t after; |
108 | 1ba13a5d | edgar_igl | } dma_descr_data; |
109 | 1ba13a5d | edgar_igl | |
110 | 1ba13a5d | edgar_igl | /* Constants */
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111 | 1ba13a5d | edgar_igl | enum {
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112 | 1ba13a5d | edgar_igl | regk_dma_ack_pkt = 0x00000100,
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113 | 1ba13a5d | edgar_igl | regk_dma_anytime = 0x00000001,
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114 | 1ba13a5d | edgar_igl | regk_dma_array = 0x00000008,
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115 | 1ba13a5d | edgar_igl | regk_dma_burst = 0x00000020,
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116 | 1ba13a5d | edgar_igl | regk_dma_client = 0x00000002,
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117 | 1ba13a5d | edgar_igl | regk_dma_copy_next = 0x00000010,
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118 | 1ba13a5d | edgar_igl | regk_dma_copy_up = 0x00000020,
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119 | 1ba13a5d | edgar_igl | regk_dma_data_at_eol = 0x00000001,
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120 | 1ba13a5d | edgar_igl | regk_dma_dis_c = 0x00000010,
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121 | 1ba13a5d | edgar_igl | regk_dma_dis_g = 0x00000020,
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122 | 1ba13a5d | edgar_igl | regk_dma_idle = 0x00000001,
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123 | 1ba13a5d | edgar_igl | regk_dma_intern = 0x00000004,
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124 | 1ba13a5d | edgar_igl | regk_dma_load_c = 0x00000200,
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125 | 1ba13a5d | edgar_igl | regk_dma_load_c_n = 0x00000280,
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126 | 1ba13a5d | edgar_igl | regk_dma_load_c_next = 0x00000240,
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127 | 1ba13a5d | edgar_igl | regk_dma_load_d = 0x00000140,
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128 | 1ba13a5d | edgar_igl | regk_dma_load_g = 0x00000300,
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129 | 1ba13a5d | edgar_igl | regk_dma_load_g_down = 0x000003c0,
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130 | 1ba13a5d | edgar_igl | regk_dma_load_g_next = 0x00000340,
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131 | 1ba13a5d | edgar_igl | regk_dma_load_g_up = 0x00000380,
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132 | 1ba13a5d | edgar_igl | regk_dma_next_en = 0x00000010,
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133 | 1ba13a5d | edgar_igl | regk_dma_next_pkt = 0x00000010,
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134 | 1ba13a5d | edgar_igl | regk_dma_no = 0x00000000,
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135 | 1ba13a5d | edgar_igl | regk_dma_only_at_wait = 0x00000000,
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136 | 1ba13a5d | edgar_igl | regk_dma_restore = 0x00000020,
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137 | 1ba13a5d | edgar_igl | regk_dma_rst = 0x00000001,
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138 | 1ba13a5d | edgar_igl | regk_dma_running = 0x00000004,
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139 | 1ba13a5d | edgar_igl | regk_dma_rw_cfg_default = 0x00000000,
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140 | 1ba13a5d | edgar_igl | regk_dma_rw_cmd_default = 0x00000000,
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141 | 1ba13a5d | edgar_igl | regk_dma_rw_intr_mask_default = 0x00000000,
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142 | 1ba13a5d | edgar_igl | regk_dma_rw_stat_default = 0x00000101,
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143 | 1ba13a5d | edgar_igl | regk_dma_rw_stream_cmd_default = 0x00000000,
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144 | 1ba13a5d | edgar_igl | regk_dma_save_down = 0x00000020,
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145 | 1ba13a5d | edgar_igl | regk_dma_save_up = 0x00000020,
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146 | 1ba13a5d | edgar_igl | regk_dma_set_reg = 0x00000050,
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147 | 1ba13a5d | edgar_igl | regk_dma_set_w_size1 = 0x00000190,
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148 | 1ba13a5d | edgar_igl | regk_dma_set_w_size2 = 0x000001a0,
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149 | 1ba13a5d | edgar_igl | regk_dma_set_w_size4 = 0x000001c0,
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150 | 1ba13a5d | edgar_igl | regk_dma_stopped = 0x00000002,
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151 | 1ba13a5d | edgar_igl | regk_dma_store_c = 0x00000002,
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152 | 1ba13a5d | edgar_igl | regk_dma_store_descr = 0x00000000,
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153 | 1ba13a5d | edgar_igl | regk_dma_store_g = 0x00000004,
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154 | 1ba13a5d | edgar_igl | regk_dma_store_md = 0x00000001,
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155 | 1ba13a5d | edgar_igl | regk_dma_sw = 0x00000008,
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156 | 1ba13a5d | edgar_igl | regk_dma_update_down = 0x00000020,
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157 | 1ba13a5d | edgar_igl | regk_dma_yes = 0x00000001
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158 | 1ba13a5d | edgar_igl | }; |
159 | 1ba13a5d | edgar_igl | |
160 | 1ba13a5d | edgar_igl | enum dma_ch_state
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161 | 1ba13a5d | edgar_igl | { |
162 | 4487fd34 | edgar_igl | RST = 1,
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163 | 1ba13a5d | edgar_igl | STOPPED = 2,
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164 | 1ba13a5d | edgar_igl | RUNNING = 4
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165 | 1ba13a5d | edgar_igl | }; |
166 | 1ba13a5d | edgar_igl | |
167 | 1ba13a5d | edgar_igl | struct fs_dma_channel
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168 | 1ba13a5d | edgar_igl | { |
169 | 96d7ddde | Edgar E. Iglesias | qemu_irq irq; |
170 | 1ba13a5d | edgar_igl | struct etraxfs_dma_client *client;
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171 | 1ba13a5d | edgar_igl | |
172 | 1ba13a5d | edgar_igl | /* Internal status. */
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173 | 1ba13a5d | edgar_igl | int stream_cmd_src;
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174 | 1ba13a5d | edgar_igl | enum dma_ch_state state;
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175 | 1ba13a5d | edgar_igl | |
176 | 1ba13a5d | edgar_igl | unsigned int input : 1; |
177 | 1ba13a5d | edgar_igl | unsigned int eol : 1; |
178 | 1ba13a5d | edgar_igl | |
179 | 1ba13a5d | edgar_igl | struct dma_descr_group current_g;
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180 | 1ba13a5d | edgar_igl | struct dma_descr_context current_c;
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181 | 1ba13a5d | edgar_igl | struct dma_descr_data current_d;
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182 | 1ba13a5d | edgar_igl | |
183 | 1ba13a5d | edgar_igl | /* Controll registers. */
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184 | 1ba13a5d | edgar_igl | uint32_t regs[DMA_REG_MAX]; |
185 | 1ba13a5d | edgar_igl | }; |
186 | 1ba13a5d | edgar_igl | |
187 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl
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188 | 1ba13a5d | edgar_igl | { |
189 | 9dcb06ce | Edgar E. Iglesias | MemoryRegion mmio; |
190 | 1ba13a5d | edgar_igl | int nr_channels;
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191 | 1ba13a5d | edgar_igl | struct fs_dma_channel *channels;
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192 | 492c30af | aliguori | |
193 | 492c30af | aliguori | QEMUBH *bh; |
194 | 1ba13a5d | edgar_igl | }; |
195 | 1ba13a5d | edgar_igl | |
196 | c01c07bb | edgar_igl | static void DMA_run(void *opaque); |
197 | c01c07bb | edgar_igl | static int channel_out_run(struct fs_dma_ctrl *ctrl, int c); |
198 | c01c07bb | edgar_igl | |
199 | 1ba13a5d | edgar_igl | static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg) |
200 | 1ba13a5d | edgar_igl | { |
201 | 1ba13a5d | edgar_igl | return ctrl->channels[c].regs[reg];
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202 | 1ba13a5d | edgar_igl | } |
203 | 1ba13a5d | edgar_igl | |
204 | 1ba13a5d | edgar_igl | static inline int channel_stopped(struct fs_dma_ctrl *ctrl, int c) |
205 | 1ba13a5d | edgar_igl | { |
206 | 1ba13a5d | edgar_igl | return channel_reg(ctrl, c, RW_CFG) & 2; |
207 | 1ba13a5d | edgar_igl | } |
208 | 1ba13a5d | edgar_igl | |
209 | 1ba13a5d | edgar_igl | static inline int channel_en(struct fs_dma_ctrl *ctrl, int c) |
210 | 1ba13a5d | edgar_igl | { |
211 | 1ba13a5d | edgar_igl | return (channel_reg(ctrl, c, RW_CFG) & 1) |
212 | 1ba13a5d | edgar_igl | && ctrl->channels[c].client; |
213 | 1ba13a5d | edgar_igl | } |
214 | 1ba13a5d | edgar_igl | |
215 | c227f099 | Anthony Liguori | static inline int fs_channel(target_phys_addr_t addr) |
216 | 1ba13a5d | edgar_igl | { |
217 | 1ba13a5d | edgar_igl | /* Every channel has a 0x2000 ctrl register map. */
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218 | 8da3ff18 | pbrook | return addr >> 13; |
219 | 1ba13a5d | edgar_igl | } |
220 | 1ba13a5d | edgar_igl | |
221 | d297f464 | edgar_igl | #ifdef USE_THIS_DEAD_CODE
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222 | 1ba13a5d | edgar_igl | static void channel_load_g(struct fs_dma_ctrl *ctrl, int c) |
223 | 1ba13a5d | edgar_igl | { |
224 | c227f099 | Anthony Liguori | target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP); |
225 | 1ba13a5d | edgar_igl | |
226 | 1ba13a5d | edgar_igl | /* Load and decode. FIXME: handle endianness. */
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227 | 1ba13a5d | edgar_igl | cpu_physical_memory_read (addr, |
228 | 1ba13a5d | edgar_igl | (void *) &ctrl->channels[c].current_g,
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229 | 1ba13a5d | edgar_igl | sizeof ctrl->channels[c].current_g);
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230 | 1ba13a5d | edgar_igl | } |
231 | 1ba13a5d | edgar_igl | |
232 | 1ba13a5d | edgar_igl | static void dump_c(int ch, struct dma_descr_context *c) |
233 | 1ba13a5d | edgar_igl | { |
234 | 1ba13a5d | edgar_igl | printf("%s ch=%d\n", __func__, ch);
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235 | 41107bcb | Edgar E. Iglesias | printf("next=%x\n", c->next);
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236 | 41107bcb | Edgar E. Iglesias | printf("saved_data=%x\n", c->saved_data);
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237 | 41107bcb | Edgar E. Iglesias | printf("saved_data_buf=%x\n", c->saved_data_buf);
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238 | 1ba13a5d | edgar_igl | printf("eol=%x\n", (uint32_t) c->eol);
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239 | 1ba13a5d | edgar_igl | } |
240 | 1ba13a5d | edgar_igl | |
241 | 1ba13a5d | edgar_igl | static void dump_d(int ch, struct dma_descr_data *d) |
242 | 1ba13a5d | edgar_igl | { |
243 | 1ba13a5d | edgar_igl | printf("%s ch=%d\n", __func__, ch);
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244 | 41107bcb | Edgar E. Iglesias | printf("next=%x\n", d->next);
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245 | 41107bcb | Edgar E. Iglesias | printf("buf=%x\n", d->buf);
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246 | 41107bcb | Edgar E. Iglesias | printf("after=%x\n", d->after);
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247 | 1ba13a5d | edgar_igl | printf("intr=%x\n", (uint32_t) d->intr);
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248 | 1ba13a5d | edgar_igl | printf("out_eop=%x\n", (uint32_t) d->out_eop);
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249 | 1ba13a5d | edgar_igl | printf("in_eop=%x\n", (uint32_t) d->in_eop);
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250 | 1ba13a5d | edgar_igl | printf("eol=%x\n", (uint32_t) d->eol);
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251 | 1ba13a5d | edgar_igl | } |
252 | d297f464 | edgar_igl | #endif
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253 | 1ba13a5d | edgar_igl | |
254 | 1ba13a5d | edgar_igl | static void channel_load_c(struct fs_dma_ctrl *ctrl, int c) |
255 | 1ba13a5d | edgar_igl | { |
256 | c227f099 | Anthony Liguori | target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN); |
257 | 1ba13a5d | edgar_igl | |
258 | 1ba13a5d | edgar_igl | /* Load and decode. FIXME: handle endianness. */
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259 | 1ba13a5d | edgar_igl | cpu_physical_memory_read (addr, |
260 | 1ba13a5d | edgar_igl | (void *) &ctrl->channels[c].current_c,
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261 | 1ba13a5d | edgar_igl | sizeof ctrl->channels[c].current_c);
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262 | 1ba13a5d | edgar_igl | |
263 | 1ba13a5d | edgar_igl | D(dump_c(c, &ctrl->channels[c].current_c)); |
264 | 1ba13a5d | edgar_igl | /* I guess this should update the current pos. */
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265 | d297f464 | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA] = |
266 | d297f464 | edgar_igl | (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data; |
267 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
268 | d297f464 | edgar_igl | (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data_buf; |
269 | 1ba13a5d | edgar_igl | } |
270 | 1ba13a5d | edgar_igl | |
271 | 1ba13a5d | edgar_igl | static void channel_load_d(struct fs_dma_ctrl *ctrl, int c) |
272 | 1ba13a5d | edgar_igl | { |
273 | c227f099 | Anthony Liguori | target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA); |
274 | 1ba13a5d | edgar_igl | |
275 | 1ba13a5d | edgar_igl | /* Load and decode. FIXME: handle endianness. */
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276 | 41107bcb | Edgar E. Iglesias | D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); |
277 | 1ba13a5d | edgar_igl | cpu_physical_memory_read (addr, |
278 | 1ba13a5d | edgar_igl | (void *) &ctrl->channels[c].current_d,
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279 | 1ba13a5d | edgar_igl | sizeof ctrl->channels[c].current_d);
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280 | 1ba13a5d | edgar_igl | |
281 | 1ba13a5d | edgar_igl | D(dump_d(c, &ctrl->channels[c].current_d)); |
282 | fa1bdde4 | edgar_igl | ctrl->channels[c].regs[RW_DATA] = addr; |
283 | a8303d18 | edgar_igl | } |
284 | a8303d18 | edgar_igl | |
285 | a8303d18 | edgar_igl | static void channel_store_c(struct fs_dma_ctrl *ctrl, int c) |
286 | a8303d18 | edgar_igl | { |
287 | c227f099 | Anthony Liguori | target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN); |
288 | a8303d18 | edgar_igl | |
289 | a8303d18 | edgar_igl | /* Encode and store. FIXME: handle endianness. */
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290 | 41107bcb | Edgar E. Iglesias | D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); |
291 | a8303d18 | edgar_igl | D(dump_d(c, &ctrl->channels[c].current_d)); |
292 | a8303d18 | edgar_igl | cpu_physical_memory_write (addr, |
293 | a8303d18 | edgar_igl | (void *) &ctrl->channels[c].current_c,
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294 | a8303d18 | edgar_igl | sizeof ctrl->channels[c].current_c);
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295 | 1ba13a5d | edgar_igl | } |
296 | 1ba13a5d | edgar_igl | |
297 | 1ba13a5d | edgar_igl | static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) |
298 | 1ba13a5d | edgar_igl | { |
299 | c227f099 | Anthony Liguori | target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA); |
300 | 1ba13a5d | edgar_igl | |
301 | a8303d18 | edgar_igl | /* Encode and store. FIXME: handle endianness. */
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302 | 41107bcb | Edgar E. Iglesias | D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); |
303 | 1ba13a5d | edgar_igl | cpu_physical_memory_write (addr, |
304 | 1ba13a5d | edgar_igl | (void *) &ctrl->channels[c].current_d,
|
305 | 1ba13a5d | edgar_igl | sizeof ctrl->channels[c].current_d);
|
306 | 1ba13a5d | edgar_igl | } |
307 | 1ba13a5d | edgar_igl | |
308 | 1ba13a5d | edgar_igl | static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c) |
309 | 1ba13a5d | edgar_igl | { |
310 | 1ba13a5d | edgar_igl | /* FIXME: */
|
311 | 1ba13a5d | edgar_igl | } |
312 | 1ba13a5d | edgar_igl | |
313 | 1ba13a5d | edgar_igl | static inline void channel_start(struct fs_dma_ctrl *ctrl, int c) |
314 | 1ba13a5d | edgar_igl | { |
315 | 1ba13a5d | edgar_igl | if (ctrl->channels[c].client)
|
316 | 1ba13a5d | edgar_igl | { |
317 | 1ba13a5d | edgar_igl | ctrl->channels[c].eol = 0;
|
318 | 1ba13a5d | edgar_igl | ctrl->channels[c].state = RUNNING; |
319 | c01c07bb | edgar_igl | if (!ctrl->channels[c].input)
|
320 | c01c07bb | edgar_igl | channel_out_run(ctrl, c); |
321 | 1ba13a5d | edgar_igl | } else
|
322 | 1ba13a5d | edgar_igl | printf("WARNING: starting DMA ch %d with no client\n", c);
|
323 | 1ab5f75c | edgar_igl | |
324 | 1ab5f75c | edgar_igl | qemu_bh_schedule_idle(ctrl->bh); |
325 | 1ba13a5d | edgar_igl | } |
326 | 1ba13a5d | edgar_igl | |
327 | 1ba13a5d | edgar_igl | static void channel_continue(struct fs_dma_ctrl *ctrl, int c) |
328 | 1ba13a5d | edgar_igl | { |
329 | 1ba13a5d | edgar_igl | if (!channel_en(ctrl, c)
|
330 | 1ba13a5d | edgar_igl | || channel_stopped(ctrl, c) |
331 | 1ba13a5d | edgar_igl | || ctrl->channels[c].state != RUNNING |
332 | 1ba13a5d | edgar_igl | /* Only reload the current data descriptor if it has eol set. */
|
333 | 1ba13a5d | edgar_igl | || !ctrl->channels[c].current_d.eol) { |
334 | 1ba13a5d | edgar_igl | D(printf("continue failed ch=%d state=%d stopped=%d en=%d eol=%d\n",
|
335 | 1ba13a5d | edgar_igl | c, ctrl->channels[c].state, |
336 | 1ba13a5d | edgar_igl | channel_stopped(ctrl, c), |
337 | 1ba13a5d | edgar_igl | channel_en(ctrl,c), |
338 | 1ba13a5d | edgar_igl | ctrl->channels[c].eol)); |
339 | 1ba13a5d | edgar_igl | D(dump_d(c, &ctrl->channels[c].current_d)); |
340 | 1ba13a5d | edgar_igl | return;
|
341 | 1ba13a5d | edgar_igl | } |
342 | 1ba13a5d | edgar_igl | |
343 | 1ba13a5d | edgar_igl | /* Reload the current descriptor. */
|
344 | 1ba13a5d | edgar_igl | channel_load_d(ctrl, c); |
345 | 1ba13a5d | edgar_igl | |
346 | 1ba13a5d | edgar_igl | /* If the current descriptor cleared the eol flag and we had already
|
347 | 1ba13a5d | edgar_igl | reached eol state, do the continue. */
|
348 | 1ba13a5d | edgar_igl | if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) {
|
349 | 41107bcb | Edgar E. Iglesias | D(printf("continue %d ok %x\n", c,
|
350 | 1ba13a5d | edgar_igl | ctrl->channels[c].current_d.next)); |
351 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA] = |
352 | d297f464 | edgar_igl | (uint32_t)(unsigned long)ctrl->channels[c].current_d.next; |
353 | 1ba13a5d | edgar_igl | channel_load_d(ctrl, c); |
354 | c01c07bb | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
355 | c01c07bb | edgar_igl | (uint32_t)(unsigned long)ctrl->channels[c].current_d.buf; |
356 | c01c07bb | edgar_igl | |
357 | 1ba13a5d | edgar_igl | channel_start(ctrl, c); |
358 | 1ba13a5d | edgar_igl | } |
359 | a8303d18 | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
360 | d297f464 | edgar_igl | (uint32_t)(unsigned long)ctrl->channels[c].current_d.buf; |
361 | 1ba13a5d | edgar_igl | } |
362 | 1ba13a5d | edgar_igl | |
363 | 1ba13a5d | edgar_igl | static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v) |
364 | 1ba13a5d | edgar_igl | { |
365 | 1ba13a5d | edgar_igl | unsigned int cmd = v & ((1 << 10) - 1); |
366 | 1ba13a5d | edgar_igl | |
367 | d27b2e50 | edgar_igl | D(printf("%s ch=%d cmd=%x\n",
|
368 | d27b2e50 | edgar_igl | __func__, c, cmd)); |
369 | 1ba13a5d | edgar_igl | if (cmd & regk_dma_load_d) {
|
370 | 1ba13a5d | edgar_igl | channel_load_d(ctrl, c); |
371 | 1ba13a5d | edgar_igl | if (cmd & regk_dma_burst)
|
372 | 1ba13a5d | edgar_igl | channel_start(ctrl, c); |
373 | 1ba13a5d | edgar_igl | } |
374 | 1ba13a5d | edgar_igl | |
375 | 1ba13a5d | edgar_igl | if (cmd & regk_dma_load_c) {
|
376 | 1ba13a5d | edgar_igl | channel_load_c(ctrl, c); |
377 | 1ba13a5d | edgar_igl | } |
378 | 1ba13a5d | edgar_igl | } |
379 | 1ba13a5d | edgar_igl | |
380 | 1ba13a5d | edgar_igl | static void channel_update_irq(struct fs_dma_ctrl *ctrl, int c) |
381 | 1ba13a5d | edgar_igl | { |
382 | 1ba13a5d | edgar_igl | D(printf("%s %d\n", __func__, c));
|
383 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[R_INTR] &= |
384 | 1ba13a5d | edgar_igl | ~(ctrl->channels[c].regs[RW_ACK_INTR]); |
385 | 1ba13a5d | edgar_igl | |
386 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[R_MASKED_INTR] = |
387 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[R_INTR] |
388 | 1ba13a5d | edgar_igl | & ctrl->channels[c].regs[RW_INTR_MASK]; |
389 | 1ba13a5d | edgar_igl | |
390 | 1ba13a5d | edgar_igl | D(printf("%s: chan=%d masked_intr=%x\n", __func__,
|
391 | 1ba13a5d | edgar_igl | c, |
392 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[R_MASKED_INTR])); |
393 | 1ba13a5d | edgar_igl | |
394 | 96d7ddde | Edgar E. Iglesias | qemu_set_irq(ctrl->channels[c].irq, |
395 | 7a3161ba | Edgar E. Iglesias | !!ctrl->channels[c].regs[R_MASKED_INTR]); |
396 | 1ba13a5d | edgar_igl | } |
397 | 1ba13a5d | edgar_igl | |
398 | 1ab5f75c | edgar_igl | static int channel_out_run(struct fs_dma_ctrl *ctrl, int c) |
399 | 1ba13a5d | edgar_igl | { |
400 | 1ba13a5d | edgar_igl | uint32_t len; |
401 | 1ba13a5d | edgar_igl | uint32_t saved_data_buf; |
402 | 1ba13a5d | edgar_igl | unsigned char buf[2 * 1024]; |
403 | 1ba13a5d | edgar_igl | |
404 | 1ab5f75c | edgar_igl | if (ctrl->channels[c].eol)
|
405 | 1ab5f75c | edgar_igl | return 0; |
406 | 1ab5f75c | edgar_igl | |
407 | 1ab5f75c | edgar_igl | do {
|
408 | 41107bcb | Edgar E. Iglesias | D(printf("ch=%d buf=%x after=%x\n",
|
409 | c968ef8d | edgar_igl | c, |
410 | c968ef8d | edgar_igl | (uint32_t)ctrl->channels[c].current_d.buf, |
411 | 41107bcb | Edgar E. Iglesias | (uint32_t)ctrl->channels[c].current_d.after)); |
412 | c968ef8d | edgar_igl | |
413 | c01c07bb | edgar_igl | channel_load_d(ctrl, c); |
414 | c01c07bb | edgar_igl | saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF); |
415 | ea0f49a7 | edgar_igl | len = (uint32_t)(unsigned long) |
416 | ea0f49a7 | edgar_igl | ctrl->channels[c].current_d.after; |
417 | c968ef8d | edgar_igl | len -= saved_data_buf; |
418 | c968ef8d | edgar_igl | |
419 | c968ef8d | edgar_igl | if (len > sizeof buf) |
420 | c968ef8d | edgar_igl | len = sizeof buf;
|
421 | c968ef8d | edgar_igl | cpu_physical_memory_read (saved_data_buf, buf, len); |
422 | c968ef8d | edgar_igl | |
423 | c968ef8d | edgar_igl | D(printf("channel %d pushes %x %u bytes\n", c,
|
424 | c968ef8d | edgar_igl | saved_data_buf, len)); |
425 | c968ef8d | edgar_igl | |
426 | c968ef8d | edgar_igl | if (ctrl->channels[c].client->client.push)
|
427 | c968ef8d | edgar_igl | ctrl->channels[c].client->client.push( |
428 | c968ef8d | edgar_igl | ctrl->channels[c].client->client.opaque, |
429 | c968ef8d | edgar_igl | buf, len); |
430 | c968ef8d | edgar_igl | else
|
431 | c968ef8d | edgar_igl | printf("WARNING: DMA ch%d dataloss,"
|
432 | c968ef8d | edgar_igl | " no attached client.\n", c);
|
433 | c968ef8d | edgar_igl | |
434 | c968ef8d | edgar_igl | saved_data_buf += len; |
435 | c968ef8d | edgar_igl | |
436 | ea0f49a7 | edgar_igl | if (saved_data_buf == (uint32_t)(unsigned long) |
437 | ea0f49a7 | edgar_igl | ctrl->channels[c].current_d.after) { |
438 | c968ef8d | edgar_igl | /* Done. Step to next. */
|
439 | c968ef8d | edgar_igl | if (ctrl->channels[c].current_d.out_eop) {
|
440 | c968ef8d | edgar_igl | /* TODO: signal eop to the client. */
|
441 | c968ef8d | edgar_igl | D(printf("signal eop\n"));
|
442 | c968ef8d | edgar_igl | } |
443 | c968ef8d | edgar_igl | if (ctrl->channels[c].current_d.intr) {
|
444 | c968ef8d | edgar_igl | /* TODO: signal eop to the client. */
|
445 | c968ef8d | edgar_igl | /* data intr. */
|
446 | c01c07bb | edgar_igl | D(printf("signal intr %d eol=%d\n",
|
447 | c01c07bb | edgar_igl | len, ctrl->channels[c].current_d.eol)); |
448 | c968ef8d | edgar_igl | ctrl->channels[c].regs[R_INTR] |= (1 << 2); |
449 | c968ef8d | edgar_igl | channel_update_irq(ctrl, c); |
450 | c968ef8d | edgar_igl | } |
451 | c01c07bb | edgar_igl | channel_store_d(ctrl, c); |
452 | c968ef8d | edgar_igl | if (ctrl->channels[c].current_d.eol) {
|
453 | c968ef8d | edgar_igl | D(printf("channel %d EOL\n", c));
|
454 | c968ef8d | edgar_igl | ctrl->channels[c].eol = 1;
|
455 | c968ef8d | edgar_igl | |
456 | c968ef8d | edgar_igl | /* Mark the context as disabled. */
|
457 | c968ef8d | edgar_igl | ctrl->channels[c].current_c.dis = 1;
|
458 | c968ef8d | edgar_igl | channel_store_c(ctrl, c); |
459 | c968ef8d | edgar_igl | |
460 | c968ef8d | edgar_igl | channel_stop(ctrl, c); |
461 | c968ef8d | edgar_igl | } else {
|
462 | c968ef8d | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA] = |
463 | ea0f49a7 | edgar_igl | (uint32_t)(unsigned long)ctrl-> |
464 | ea0f49a7 | edgar_igl | channels[c].current_d.next; |
465 | c968ef8d | edgar_igl | /* Load new descriptor. */
|
466 | c968ef8d | edgar_igl | channel_load_d(ctrl, c); |
467 | c968ef8d | edgar_igl | saved_data_buf = (uint32_t)(unsigned long) |
468 | c968ef8d | edgar_igl | ctrl->channels[c].current_d.buf; |
469 | c968ef8d | edgar_igl | } |
470 | c968ef8d | edgar_igl | |
471 | c968ef8d | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
472 | c968ef8d | edgar_igl | saved_data_buf; |
473 | c968ef8d | edgar_igl | D(dump_d(c, &ctrl->channels[c].current_d)); |
474 | 1ba13a5d | edgar_igl | } |
475 | a8303d18 | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf; |
476 | 1ab5f75c | edgar_igl | } while (!ctrl->channels[c].eol);
|
477 | 1ab5f75c | edgar_igl | return 1; |
478 | 1ba13a5d | edgar_igl | } |
479 | 1ba13a5d | edgar_igl | |
480 | 1ba13a5d | edgar_igl | static int channel_in_process(struct fs_dma_ctrl *ctrl, int c, |
481 | 1ba13a5d | edgar_igl | unsigned char *buf, int buflen, int eop) |
482 | 1ba13a5d | edgar_igl | { |
483 | 1ba13a5d | edgar_igl | uint32_t len; |
484 | 1ba13a5d | edgar_igl | uint32_t saved_data_buf; |
485 | 1ba13a5d | edgar_igl | |
486 | 1ba13a5d | edgar_igl | if (ctrl->channels[c].eol == 1) |
487 | 1ba13a5d | edgar_igl | return 0; |
488 | 1ba13a5d | edgar_igl | |
489 | c01c07bb | edgar_igl | channel_load_d(ctrl, c); |
490 | 1ba13a5d | edgar_igl | saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF); |
491 | ea0f49a7 | edgar_igl | len = (uint32_t)(unsigned long)ctrl->channels[c].current_d.after; |
492 | 1ba13a5d | edgar_igl | len -= saved_data_buf; |
493 | 1ba13a5d | edgar_igl | |
494 | 1ba13a5d | edgar_igl | if (len > buflen)
|
495 | 1ba13a5d | edgar_igl | len = buflen; |
496 | 1ba13a5d | edgar_igl | |
497 | 1ba13a5d | edgar_igl | cpu_physical_memory_write (saved_data_buf, buf, len); |
498 | 1ba13a5d | edgar_igl | saved_data_buf += len; |
499 | 1ba13a5d | edgar_igl | |
500 | d297f464 | edgar_igl | if (saved_data_buf ==
|
501 | ea0f49a7 | edgar_igl | (uint32_t)(unsigned long)ctrl->channels[c].current_d.after |
502 | 1ba13a5d | edgar_igl | || eop) { |
503 | 1ba13a5d | edgar_igl | uint32_t r_intr = ctrl->channels[c].regs[R_INTR]; |
504 | 1ba13a5d | edgar_igl | |
505 | 1ba13a5d | edgar_igl | D(printf("in dscr end len=%d\n",
|
506 | 1ba13a5d | edgar_igl | ctrl->channels[c].current_d.after |
507 | 1ba13a5d | edgar_igl | - ctrl->channels[c].current_d.buf)); |
508 | 41107bcb | Edgar E. Iglesias | ctrl->channels[c].current_d.after = saved_data_buf; |
509 | 1ba13a5d | edgar_igl | |
510 | 1ba13a5d | edgar_igl | /* Done. Step to next. */
|
511 | 1ba13a5d | edgar_igl | if (ctrl->channels[c].current_d.intr) {
|
512 | 1ba13a5d | edgar_igl | /* TODO: signal eop to the client. */
|
513 | 1ba13a5d | edgar_igl | /* data intr. */
|
514 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[R_INTR] |= 3;
|
515 | 1ba13a5d | edgar_igl | } |
516 | 1ba13a5d | edgar_igl | if (eop) {
|
517 | 1ba13a5d | edgar_igl | ctrl->channels[c].current_d.in_eop = 1;
|
518 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[R_INTR] |= 8;
|
519 | 1ba13a5d | edgar_igl | } |
520 | 1ba13a5d | edgar_igl | if (r_intr != ctrl->channels[c].regs[R_INTR])
|
521 | 1ba13a5d | edgar_igl | channel_update_irq(ctrl, c); |
522 | 1ba13a5d | edgar_igl | |
523 | 1ba13a5d | edgar_igl | channel_store_d(ctrl, c); |
524 | 1ba13a5d | edgar_igl | D(dump_d(c, &ctrl->channels[c].current_d)); |
525 | 1ba13a5d | edgar_igl | |
526 | 1ba13a5d | edgar_igl | if (ctrl->channels[c].current_d.eol) {
|
527 | 1ba13a5d | edgar_igl | D(printf("channel %d EOL\n", c));
|
528 | 1ba13a5d | edgar_igl | ctrl->channels[c].eol = 1;
|
529 | a8303d18 | edgar_igl | |
530 | a8303d18 | edgar_igl | /* Mark the context as disabled. */
|
531 | a8303d18 | edgar_igl | ctrl->channels[c].current_c.dis = 1;
|
532 | a8303d18 | edgar_igl | channel_store_c(ctrl, c); |
533 | a8303d18 | edgar_igl | |
534 | 1ba13a5d | edgar_igl | channel_stop(ctrl, c); |
535 | 1ba13a5d | edgar_igl | } else {
|
536 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA] = |
537 | ea0f49a7 | edgar_igl | (uint32_t)(unsigned long)ctrl-> |
538 | ea0f49a7 | edgar_igl | channels[c].current_d.next; |
539 | 1ba13a5d | edgar_igl | /* Load new descriptor. */
|
540 | 1ba13a5d | edgar_igl | channel_load_d(ctrl, c); |
541 | ea0f49a7 | edgar_igl | saved_data_buf = (uint32_t)(unsigned long) |
542 | a8303d18 | edgar_igl | ctrl->channels[c].current_d.buf; |
543 | 1ba13a5d | edgar_igl | } |
544 | 1ba13a5d | edgar_igl | } |
545 | 1ba13a5d | edgar_igl | |
546 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf; |
547 | 1ba13a5d | edgar_igl | return len;
|
548 | 1ba13a5d | edgar_igl | } |
549 | 1ba13a5d | edgar_igl | |
550 | 1ab5f75c | edgar_igl | static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c) |
551 | 1ba13a5d | edgar_igl | { |
552 | 1ab5f75c | edgar_igl | if (ctrl->channels[c].client->client.pull) {
|
553 | 1ba13a5d | edgar_igl | ctrl->channels[c].client->client.pull( |
554 | 1ba13a5d | edgar_igl | ctrl->channels[c].client->client.opaque); |
555 | 1ab5f75c | edgar_igl | return 1; |
556 | 1ab5f75c | edgar_igl | } else
|
557 | 1ab5f75c | edgar_igl | return 0; |
558 | 1ba13a5d | edgar_igl | } |
559 | 1ba13a5d | edgar_igl | |
560 | c227f099 | Anthony Liguori | static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr) |
561 | 1ba13a5d | edgar_igl | { |
562 | 41107bcb | Edgar E. Iglesias | hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr); |
563 | 1ba13a5d | edgar_igl | return 0; |
564 | 1ba13a5d | edgar_igl | } |
565 | 1ba13a5d | edgar_igl | |
566 | 9dcb06ce | Edgar E. Iglesias | static uint64_t
|
567 | 9dcb06ce | Edgar E. Iglesias | dma_read(void *opaque, target_phys_addr_t addr, unsigned int size) |
568 | 1ba13a5d | edgar_igl | { |
569 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = opaque;
|
570 | 1ba13a5d | edgar_igl | int c;
|
571 | 1ba13a5d | edgar_igl | uint32_t r = 0;
|
572 | 1ba13a5d | edgar_igl | |
573 | 9dcb06ce | Edgar E. Iglesias | if (size != 4) { |
574 | 9dcb06ce | Edgar E. Iglesias | dma_rinvalid(opaque, addr); |
575 | 9dcb06ce | Edgar E. Iglesias | } |
576 | 9dcb06ce | Edgar E. Iglesias | |
577 | e6320485 | edgar_igl | /* Make addr relative to this channel and bounded to nr regs. */
|
578 | 8da3ff18 | pbrook | c = fs_channel(addr); |
579 | e6320485 | edgar_igl | addr &= 0xff;
|
580 | c01c07bb | edgar_igl | addr >>= 2;
|
581 | 1ba13a5d | edgar_igl | switch (addr)
|
582 | a8303d18 | edgar_igl | { |
583 | 1ba13a5d | edgar_igl | case RW_STAT:
|
584 | 1ba13a5d | edgar_igl | r = ctrl->channels[c].state & 7;
|
585 | 1ba13a5d | edgar_igl | r |= ctrl->channels[c].eol << 5;
|
586 | 1ba13a5d | edgar_igl | r |= ctrl->channels[c].stream_cmd_src << 8;
|
587 | 1ba13a5d | edgar_igl | break;
|
588 | 1ba13a5d | edgar_igl | |
589 | a8303d18 | edgar_igl | default:
|
590 | 1ba13a5d | edgar_igl | r = ctrl->channels[c].regs[addr]; |
591 | 41107bcb | Edgar E. Iglesias | D(printf ("%s c=%d addr=" TARGET_FMT_plx "\n", |
592 | d27b2e50 | edgar_igl | __func__, c, addr)); |
593 | a8303d18 | edgar_igl | break;
|
594 | a8303d18 | edgar_igl | } |
595 | 1ba13a5d | edgar_igl | return r;
|
596 | 1ba13a5d | edgar_igl | } |
597 | 1ba13a5d | edgar_igl | |
598 | 1ba13a5d | edgar_igl | static void |
599 | c227f099 | Anthony Liguori | dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
|
600 | 1ba13a5d | edgar_igl | { |
601 | 41107bcb | Edgar E. Iglesias | hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr); |
602 | 1ba13a5d | edgar_igl | } |
603 | 1ba13a5d | edgar_igl | |
604 | 1ba13a5d | edgar_igl | static void |
605 | 4487fd34 | edgar_igl | dma_update_state(struct fs_dma_ctrl *ctrl, int c) |
606 | 4487fd34 | edgar_igl | { |
607 | d11cf8cc | Edgar E. Iglesias | if (ctrl->channels[c].regs[RW_CFG] & 2) |
608 | d11cf8cc | Edgar E. Iglesias | ctrl->channels[c].state = STOPPED; |
609 | d11cf8cc | Edgar E. Iglesias | if (!(ctrl->channels[c].regs[RW_CFG] & 1)) |
610 | d11cf8cc | Edgar E. Iglesias | ctrl->channels[c].state = RST; |
611 | 4487fd34 | edgar_igl | } |
612 | 4487fd34 | edgar_igl | |
613 | 4487fd34 | edgar_igl | static void |
614 | 9dcb06ce | Edgar E. Iglesias | dma_write(void *opaque, target_phys_addr_t addr,
|
615 | 9dcb06ce | Edgar E. Iglesias | uint64_t val64, unsigned int size) |
616 | 1ba13a5d | edgar_igl | { |
617 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = opaque;
|
618 | 9dcb06ce | Edgar E. Iglesias | uint32_t value = val64; |
619 | 1ba13a5d | edgar_igl | int c;
|
620 | 1ba13a5d | edgar_igl | |
621 | 9dcb06ce | Edgar E. Iglesias | if (size != 4) { |
622 | 9dcb06ce | Edgar E. Iglesias | dma_winvalid(opaque, addr, value); |
623 | 9dcb06ce | Edgar E. Iglesias | } |
624 | 9dcb06ce | Edgar E. Iglesias | |
625 | e6320485 | edgar_igl | /* Make addr relative to this channel and bounded to nr regs. */
|
626 | 8da3ff18 | pbrook | c = fs_channel(addr); |
627 | e6320485 | edgar_igl | addr &= 0xff;
|
628 | c01c07bb | edgar_igl | addr >>= 2;
|
629 | 1ba13a5d | edgar_igl | switch (addr)
|
630 | a8303d18 | edgar_igl | { |
631 | 1ba13a5d | edgar_igl | case RW_DATA:
|
632 | fa1bdde4 | edgar_igl | ctrl->channels[c].regs[addr] = value; |
633 | 1ba13a5d | edgar_igl | break;
|
634 | 1ba13a5d | edgar_igl | |
635 | 1ba13a5d | edgar_igl | case RW_CFG:
|
636 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[addr] = value; |
637 | 4487fd34 | edgar_igl | dma_update_state(ctrl, c); |
638 | 1ba13a5d | edgar_igl | break;
|
639 | 1ba13a5d | edgar_igl | case RW_CMD:
|
640 | 1ba13a5d | edgar_igl | /* continue. */
|
641 | 4487fd34 | edgar_igl | if (value & ~1) |
642 | 4487fd34 | edgar_igl | printf("Invalid store to ch=%d RW_CMD %x\n",
|
643 | 4487fd34 | edgar_igl | c, value); |
644 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[addr] = value; |
645 | 1ba13a5d | edgar_igl | channel_continue(ctrl, c); |
646 | 1ba13a5d | edgar_igl | break;
|
647 | 1ba13a5d | edgar_igl | |
648 | 1ba13a5d | edgar_igl | case RW_SAVED_DATA:
|
649 | 1ba13a5d | edgar_igl | case RW_SAVED_DATA_BUF:
|
650 | 1ba13a5d | edgar_igl | case RW_GROUP:
|
651 | 1ba13a5d | edgar_igl | case RW_GROUP_DOWN:
|
652 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[addr] = value; |
653 | 1ba13a5d | edgar_igl | break;
|
654 | 1ba13a5d | edgar_igl | |
655 | 1ba13a5d | edgar_igl | case RW_ACK_INTR:
|
656 | 1ba13a5d | edgar_igl | case RW_INTR_MASK:
|
657 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[addr] = value; |
658 | 1ba13a5d | edgar_igl | channel_update_irq(ctrl, c); |
659 | 1ba13a5d | edgar_igl | if (addr == RW_ACK_INTR)
|
660 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[RW_ACK_INTR] = 0;
|
661 | 1ba13a5d | edgar_igl | break;
|
662 | 1ba13a5d | edgar_igl | |
663 | 1ba13a5d | edgar_igl | case RW_STREAM_CMD:
|
664 | 4487fd34 | edgar_igl | if (value & ~1023) |
665 | 4487fd34 | edgar_igl | printf("Invalid store to ch=%d "
|
666 | 4487fd34 | edgar_igl | "RW_STREAMCMD %x\n",
|
667 | 4487fd34 | edgar_igl | c, value); |
668 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[addr] = value; |
669 | d27b2e50 | edgar_igl | D(printf("stream_cmd ch=%d\n", c));
|
670 | 1ba13a5d | edgar_igl | channel_stream_cmd(ctrl, c, value); |
671 | 1ba13a5d | edgar_igl | break;
|
672 | 1ba13a5d | edgar_igl | |
673 | a8303d18 | edgar_igl | default:
|
674 | 41107bcb | Edgar E. Iglesias | D(printf ("%s c=%d " TARGET_FMT_plx "\n", |
675 | 41107bcb | Edgar E. Iglesias | __func__, c, addr)); |
676 | a8303d18 | edgar_igl | break;
|
677 | 1ba13a5d | edgar_igl | } |
678 | 1ba13a5d | edgar_igl | } |
679 | 1ba13a5d | edgar_igl | |
680 | 9dcb06ce | Edgar E. Iglesias | static const MemoryRegionOps dma_ops = { |
681 | 9dcb06ce | Edgar E. Iglesias | .read = dma_read, |
682 | 9dcb06ce | Edgar E. Iglesias | .write = dma_write, |
683 | 9dcb06ce | Edgar E. Iglesias | .endianness = DEVICE_NATIVE_ENDIAN, |
684 | 9dcb06ce | Edgar E. Iglesias | .valid = { |
685 | 9dcb06ce | Edgar E. Iglesias | .min_access_size = 1,
|
686 | 9dcb06ce | Edgar E. Iglesias | .max_access_size = 4
|
687 | 9dcb06ce | Edgar E. Iglesias | } |
688 | 1ba13a5d | edgar_igl | }; |
689 | 1ba13a5d | edgar_igl | |
690 | 1ab5f75c | edgar_igl | static int etraxfs_dmac_run(void *opaque) |
691 | 1ba13a5d | edgar_igl | { |
692 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = opaque;
|
693 | 1ba13a5d | edgar_igl | int i;
|
694 | 1ba13a5d | edgar_igl | int p = 0; |
695 | 1ba13a5d | edgar_igl | |
696 | 1ba13a5d | edgar_igl | for (i = 0; |
697 | 1ba13a5d | edgar_igl | i < ctrl->nr_channels; |
698 | 1ba13a5d | edgar_igl | i++) |
699 | 1ba13a5d | edgar_igl | { |
700 | 1ba13a5d | edgar_igl | if (ctrl->channels[i].state == RUNNING)
|
701 | 1ba13a5d | edgar_igl | { |
702 | 1ab5f75c | edgar_igl | if (ctrl->channels[i].input) {
|
703 | 1ab5f75c | edgar_igl | p += channel_in_run(ctrl, i); |
704 | 1ab5f75c | edgar_igl | } else {
|
705 | 1ab5f75c | edgar_igl | p += channel_out_run(ctrl, i); |
706 | 1ab5f75c | edgar_igl | } |
707 | 1ba13a5d | edgar_igl | } |
708 | 1ba13a5d | edgar_igl | } |
709 | 1ab5f75c | edgar_igl | return p;
|
710 | 1ba13a5d | edgar_igl | } |
711 | 1ba13a5d | edgar_igl | |
712 | 1ba13a5d | edgar_igl | int etraxfs_dmac_input(struct etraxfs_dma_client *client, |
713 | 1ba13a5d | edgar_igl | void *buf, int len, int eop) |
714 | 1ba13a5d | edgar_igl | { |
715 | 1ba13a5d | edgar_igl | return channel_in_process(client->ctrl, client->channel,
|
716 | 1ba13a5d | edgar_igl | buf, len, eop); |
717 | 1ba13a5d | edgar_igl | } |
718 | 1ba13a5d | edgar_igl | |
719 | 1ba13a5d | edgar_igl | /* Connect an IRQ line with a channel. */
|
720 | 1ba13a5d | edgar_igl | void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input) |
721 | 1ba13a5d | edgar_igl | { |
722 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = opaque;
|
723 | 96d7ddde | Edgar E. Iglesias | ctrl->channels[c].irq = *line; |
724 | 1ba13a5d | edgar_igl | ctrl->channels[c].input = input; |
725 | 1ba13a5d | edgar_igl | } |
726 | 1ba13a5d | edgar_igl | |
727 | 1ba13a5d | edgar_igl | void etraxfs_dmac_connect_client(void *opaque, int c, |
728 | 1ba13a5d | edgar_igl | struct etraxfs_dma_client *cl)
|
729 | 1ba13a5d | edgar_igl | { |
730 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = opaque;
|
731 | 1ba13a5d | edgar_igl | cl->ctrl = ctrl; |
732 | 1ba13a5d | edgar_igl | cl->channel = c; |
733 | 1ba13a5d | edgar_igl | ctrl->channels[c].client = cl; |
734 | 1ba13a5d | edgar_igl | } |
735 | 1ba13a5d | edgar_igl | |
736 | 1ba13a5d | edgar_igl | |
737 | 492c30af | aliguori | static void DMA_run(void *opaque) |
738 | fa1bdde4 | edgar_igl | { |
739 | 492c30af | aliguori | struct fs_dma_ctrl *etraxfs_dmac = opaque;
|
740 | 1ab5f75c | edgar_igl | int p = 1; |
741 | 1ab5f75c | edgar_igl | |
742 | 1354869c | Luiz Capitulino | if (runstate_is_running())
|
743 | 1ab5f75c | edgar_igl | p = etraxfs_dmac_run(etraxfs_dmac); |
744 | 1ab5f75c | edgar_igl | |
745 | 1ab5f75c | edgar_igl | if (p)
|
746 | 1ab5f75c | edgar_igl | qemu_bh_schedule_idle(etraxfs_dmac->bh); |
747 | fa1bdde4 | edgar_igl | } |
748 | fa1bdde4 | edgar_igl | |
749 | c227f099 | Anthony Liguori | void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels) |
750 | 1ba13a5d | edgar_igl | { |
751 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = NULL; |
752 | 1ba13a5d | edgar_igl | |
753 | 7267c094 | Anthony Liguori | ctrl = g_malloc0(sizeof *ctrl);
|
754 | 1ba13a5d | edgar_igl | |
755 | 492c30af | aliguori | ctrl->bh = qemu_bh_new(DMA_run, ctrl); |
756 | 492c30af | aliguori | |
757 | 1ba13a5d | edgar_igl | ctrl->nr_channels = nr_channels; |
758 | 7267c094 | Anthony Liguori | ctrl->channels = g_malloc0(sizeof ctrl->channels[0] * nr_channels); |
759 | 1ba13a5d | edgar_igl | |
760 | 9dcb06ce | Edgar E. Iglesias | memory_region_init_io(&ctrl->mmio, &dma_ops, ctrl, "etraxfs-dma",
|
761 | 9dcb06ce | Edgar E. Iglesias | nr_channels * 0x2000);
|
762 | 9dcb06ce | Edgar E. Iglesias | memory_region_add_subregion(get_system_memory(), base, &ctrl->mmio); |
763 | 9dcb06ce | Edgar E. Iglesias | |
764 | 1ba13a5d | edgar_igl | return ctrl;
|
765 | 1ba13a5d | edgar_igl | } |