| 1391 |
1391 |
store_reg(r1, tmp2);
|
| 1392 |
1392 |
tcg_temp_free_i64(tmp2);
|
| 1393 |
1393 |
break;
|
| 1394 |
|
case 0x15: /* LGH R1,D2(X2,B2) [RXY] */
|
| 1395 |
|
tmp2 = tcg_temp_new_i64();
|
| 1396 |
|
tcg_gen_qemu_ld16s(tmp2, addr, get_mem_index(s));
|
| 1397 |
|
store_reg(r1, tmp2);
|
| 1398 |
|
tcg_temp_free_i64(tmp2);
|
| 1399 |
|
break;
|
| 1400 |
1394 |
case 0x17: /* LLGT R1,D2(X2,B2) [RXY] */
|
| 1401 |
1395 |
tmp2 = tcg_temp_new_i64();
|
| 1402 |
1396 |
tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
|
| ... | ... | |
| 1458 |
1452 |
store_reg8(r1, tmp3);
|
| 1459 |
1453 |
tcg_temp_free_i64(tmp3);
|
| 1460 |
1454 |
break;
|
| 1461 |
|
case 0x76: /* LB R1,D2(X2,B2) [RXY] */
|
| 1462 |
|
case 0x77: /* LGB R1,D2(X2,B2) [RXY] */
|
| 1463 |
|
tmp2 = tcg_temp_new_i64();
|
| 1464 |
|
tcg_gen_qemu_ld8s(tmp2, addr, get_mem_index(s));
|
| 1465 |
|
switch (op) {
|
| 1466 |
|
case 0x76:
|
| 1467 |
|
tcg_gen_ext8s_i64(tmp2, tmp2);
|
| 1468 |
|
store_reg32_i64(r1, tmp2);
|
| 1469 |
|
break;
|
| 1470 |
|
case 0x77:
|
| 1471 |
|
tcg_gen_ext8s_i64(tmp2, tmp2);
|
| 1472 |
|
store_reg(r1, tmp2);
|
| 1473 |
|
break;
|
| 1474 |
|
default:
|
| 1475 |
|
tcg_abort();
|
| 1476 |
|
}
|
| 1477 |
|
tcg_temp_free_i64(tmp2);
|
| 1478 |
|
break;
|
| 1479 |
|
case 0x78: /* LHY R1,D2(X2,B2) [RXY] */
|
| 1480 |
|
tmp2 = tcg_temp_new_i64();
|
| 1481 |
|
tcg_gen_qemu_ld16s(tmp2, addr, get_mem_index(s));
|
| 1482 |
|
store_reg32_i64(r1, tmp2);
|
| 1483 |
|
tcg_temp_free_i64(tmp2);
|
| 1484 |
|
break;
|
| 1485 |
1455 |
case 0x87: /* DLG R1,D2(X2,B2) [RXY] */
|
| 1486 |
1456 |
tmp2 = tcg_temp_new_i64();
|
| 1487 |
1457 |
tmp32_1 = tcg_const_i32(r1);
|
| ... | ... | |
| 1517 |
1487 |
tcg_temp_free_i64(tmp2);
|
| 1518 |
1488 |
tcg_temp_free_i32(tmp32_1);
|
| 1519 |
1489 |
break;
|
| 1520 |
|
case 0x90: /* LLGC R1,D2(X2,B2) [RXY] */
|
| 1521 |
|
tcg_gen_qemu_ld8u(regs[r1], addr, get_mem_index(s));
|
| 1522 |
|
break;
|
| 1523 |
|
case 0x91: /* LLGH R1,D2(X2,B2) [RXY] */
|
| 1524 |
|
tcg_gen_qemu_ld16u(regs[r1], addr, get_mem_index(s));
|
| 1525 |
|
break;
|
| 1526 |
|
case 0x94: /* LLC R1,D2(X2,B2) [RXY] */
|
| 1527 |
|
tmp2 = tcg_temp_new_i64();
|
| 1528 |
|
tcg_gen_qemu_ld8u(tmp2, addr, get_mem_index(s));
|
| 1529 |
|
store_reg32_i64(r1, tmp2);
|
| 1530 |
|
tcg_temp_free_i64(tmp2);
|
| 1531 |
|
break;
|
| 1532 |
|
case 0x95: /* LLH R1,D2(X2,B2) [RXY] */
|
| 1533 |
|
tmp2 = tcg_temp_new_i64();
|
| 1534 |
|
tcg_gen_qemu_ld16u(tmp2, addr, get_mem_index(s));
|
| 1535 |
|
store_reg32_i64(r1, tmp2);
|
| 1536 |
|
tcg_temp_free_i64(tmp2);
|
| 1537 |
|
break;
|
| 1538 |
1490 |
case 0x97: /* DL R1,D2(X2,B2) [RXY] */
|
| 1539 |
1491 |
/* reg(r1) = reg(r1, r1+1) % ld32(addr) */
|
| 1540 |
1492 |
/* reg(r1+1) = reg(r1, r1+1) / ld32(addr) */
|
| ... | ... | |
| 2194 |
2146 |
s->is_jmp = DISAS_TB_JUMP;
|
| 2195 |
2147 |
tcg_temp_free_i64(tmp);
|
| 2196 |
2148 |
break;
|
| 2197 |
|
case 0x8: /* lhi r1, i2 */
|
| 2198 |
|
tmp32_1 = tcg_const_i32(i2);
|
| 2199 |
|
store_reg32(r1, tmp32_1);
|
| 2200 |
|
tcg_temp_free_i32(tmp32_1);
|
| 2201 |
|
break;
|
| 2202 |
|
case 0x9: /* lghi r1, i2 */
|
| 2203 |
|
tmp = tcg_const_i64(i2);
|
| 2204 |
|
store_reg(r1, tmp);
|
| 2205 |
|
tcg_temp_free_i64(tmp);
|
| 2206 |
|
break;
|
| 2207 |
2149 |
default:
|
| 2208 |
2150 |
LOG_DISAS("illegal a7 operation 0x%x\n", op);
|
| 2209 |
2151 |
gen_illegal_opcode(s);
|
| ... | ... | |
| 2911 |
2853 |
}
|
| 2912 |
2854 |
tcg_temp_free_i64(tmp);
|
| 2913 |
2855 |
break;
|
| 2914 |
|
case 0x6: /* LGBR R1,R2 [RRE] */
|
| 2915 |
|
tmp2 = load_reg(r2);
|
| 2916 |
|
tcg_gen_ext8s_i64(tmp2, tmp2);
|
| 2917 |
|
store_reg(r1, tmp2);
|
| 2918 |
|
tcg_temp_free_i64(tmp2);
|
| 2919 |
|
break;
|
| 2920 |
2856 |
case 0xd: /* DSGR R1,R2 [RRE] */
|
| 2921 |
2857 |
case 0x1d: /* DSGFR R1,R2 [RRE] */
|
| 2922 |
2858 |
tmp = load_reg(r1 + 1);
|
| ... | ... | |
| 2955 |
2891 |
store_reg32(r1, tmp32_1);
|
| 2956 |
2892 |
tcg_temp_free_i32(tmp32_1);
|
| 2957 |
2893 |
break;
|
| 2958 |
|
case 0x26: /* LBR R1,R2 [RRE] */
|
| 2959 |
|
tmp32_1 = load_reg32(r2);
|
| 2960 |
|
tcg_gen_ext8s_i32(tmp32_1, tmp32_1);
|
| 2961 |
|
store_reg32(r1, tmp32_1);
|
| 2962 |
|
tcg_temp_free_i32(tmp32_1);
|
| 2963 |
|
break;
|
| 2964 |
|
case 0x27: /* LHR R1,R2 [RRE] */
|
| 2965 |
|
tmp32_1 = load_reg32(r2);
|
| 2966 |
|
tcg_gen_ext16s_i32(tmp32_1, tmp32_1);
|
| 2967 |
|
store_reg32(r1, tmp32_1);
|
| 2968 |
|
tcg_temp_free_i32(tmp32_1);
|
| 2969 |
|
break;
|
| 2970 |
2894 |
case 0x83: /* FLOGR R1,R2 [RRE] */
|
| 2971 |
2895 |
tmp = load_reg(r2);
|
| 2972 |
2896 |
tmp32_1 = tcg_const_i32(r1);
|
| ... | ... | |
| 2975 |
2899 |
tcg_temp_free_i64(tmp);
|
| 2976 |
2900 |
tcg_temp_free_i32(tmp32_1);
|
| 2977 |
2901 |
break;
|
| 2978 |
|
case 0x84: /* LLGCR R1,R2 [RRE] */
|
| 2979 |
|
tmp = load_reg(r2);
|
| 2980 |
|
tcg_gen_andi_i64(tmp, tmp, 0xff);
|
| 2981 |
|
store_reg(r1, tmp);
|
| 2982 |
|
tcg_temp_free_i64(tmp);
|
| 2983 |
|
break;
|
| 2984 |
|
case 0x85: /* LLGHR R1,R2 [RRE] */
|
| 2985 |
|
tmp = load_reg(r2);
|
| 2986 |
|
tcg_gen_andi_i64(tmp, tmp, 0xffff);
|
| 2987 |
|
store_reg(r1, tmp);
|
| 2988 |
|
tcg_temp_free_i64(tmp);
|
| 2989 |
|
break;
|
| 2990 |
2902 |
case 0x87: /* DLGR R1,R2 [RRE] */
|
| 2991 |
2903 |
tmp32_1 = tcg_const_i32(r1);
|
| 2992 |
2904 |
tmp = load_reg(r2);
|
| ... | ... | |
| 3021 |
2933 |
tcg_temp_free_i64(tmp2);
|
| 3022 |
2934 |
tcg_temp_free_i32(tmp32_1);
|
| 3023 |
2935 |
break;
|
| 3024 |
|
case 0x94: /* LLCR R1,R2 [RRE] */
|
| 3025 |
|
tmp32_1 = load_reg32(r2);
|
| 3026 |
|
tcg_gen_andi_i32(tmp32_1, tmp32_1, 0xff);
|
| 3027 |
|
store_reg32(r1, tmp32_1);
|
| 3028 |
|
tcg_temp_free_i32(tmp32_1);
|
| 3029 |
|
break;
|
| 3030 |
|
case 0x95: /* LLHR R1,R2 [RRE] */
|
| 3031 |
|
tmp32_1 = load_reg32(r2);
|
| 3032 |
|
tcg_gen_andi_i32(tmp32_1, tmp32_1, 0xffff);
|
| 3033 |
|
store_reg32(r1, tmp32_1);
|
| 3034 |
|
tcg_temp_free_i32(tmp32_1);
|
| 3035 |
|
break;
|
| 3036 |
2936 |
case 0x97: /* DLR R1,R2 [RRE] */
|
| 3037 |
2937 |
/* reg(r1) = reg(r1, r1+1) % reg(r2) */
|
| 3038 |
2938 |
/* reg(r1+1) = reg(r1, r1+1) / reg(r2) */
|
| ... | ... | |
| 3429 |
3329 |
tcg_temp_free_i64(tmp);
|
| 3430 |
3330 |
s->is_jmp = DISAS_TB_JUMP;
|
| 3431 |
3331 |
break;
|
| 3432 |
|
case 0x48: /* LH R1,D2(X2,B2) [RX] */
|
| 3433 |
|
insn = ld_code4(env, s->pc);
|
| 3434 |
|
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
|
| 3435 |
|
tmp2 = tcg_temp_new_i64();
|
| 3436 |
|
tcg_gen_qemu_ld16s(tmp2, tmp, get_mem_index(s));
|
| 3437 |
|
store_reg32_i64(r1, tmp2);
|
| 3438 |
|
tcg_temp_free_i64(tmp);
|
| 3439 |
|
tcg_temp_free_i64(tmp2);
|
| 3440 |
|
break;
|
| 3441 |
3332 |
case 0x4d: /* BAS R1,D2(X2,B2) [RX] */
|
| 3442 |
3333 |
insn = ld_code4(env, s->pc);
|
| 3443 |
3334 |
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
|
| ... | ... | |
| 4366 |
4257 |
return NO_EXIT;
|
| 4367 |
4258 |
}
|
| 4368 |
4259 |
|
|
4260 |
static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
|
|
4261 |
{
|
|
4262 |
tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
|
|
4263 |
return NO_EXIT;
|
|
4264 |
}
|
|
4265 |
|
|
4266 |
static ExitStatus op_ld8u(DisasContext *s, DisasOps *o)
|
|
4267 |
{
|
|
4268 |
tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
|
|
4269 |
return NO_EXIT;
|
|
4270 |
}
|
|
4271 |
|
|
4272 |
static ExitStatus op_ld16s(DisasContext *s, DisasOps *o)
|
|
4273 |
{
|
|
4274 |
tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
|
|
4275 |
return NO_EXIT;
|
|
4276 |
}
|
|
4277 |
|
|
4278 |
static ExitStatus op_ld16u(DisasContext *s, DisasOps *o)
|
|
4279 |
{
|
|
4280 |
tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
|
|
4281 |
return NO_EXIT;
|
|
4282 |
}
|
|
4283 |
|
| 4369 |
4284 |
static ExitStatus op_ld32s(DisasContext *s, DisasOps *o)
|
| 4370 |
4285 |
{
|
| 4371 |
4286 |
tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
|
| ... | ... | |
| 4676 |
4591 |
o->g_in2 = true;
|
| 4677 |
4592 |
}
|
| 4678 |
4593 |
|
|
4594 |
static void in2_r2_8s(DisasContext *s, DisasFields *f, DisasOps *o)
|
|
4595 |
{
|
|
4596 |
o->in2 = tcg_temp_new_i64();
|
|
4597 |
tcg_gen_ext8s_i64(o->in2, regs[get_field(f, r2)]);
|
|
4598 |
}
|
|
4599 |
|
|
4600 |
static void in2_r2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
|
|
4601 |
{
|
|
4602 |
o->in2 = tcg_temp_new_i64();
|
|
4603 |
tcg_gen_ext8u_i64(o->in2, regs[get_field(f, r2)]);
|
|
4604 |
}
|
|
4605 |
|
|
4606 |
static void in2_r2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
|
|
4607 |
{
|
|
4608 |
o->in2 = tcg_temp_new_i64();
|
|
4609 |
tcg_gen_ext16s_i64(o->in2, regs[get_field(f, r2)]);
|
|
4610 |
}
|
|
4611 |
|
|
4612 |
static void in2_r2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
|
|
4613 |
{
|
|
4614 |
o->in2 = tcg_temp_new_i64();
|
|
4615 |
tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r2)]);
|
|
4616 |
}
|
|
4617 |
|
| 4679 |
4618 |
static void in2_r3(DisasContext *s, DisasFields *f, DisasOps *o)
|
| 4680 |
4619 |
{
|
| 4681 |
4620 |
o->in2 = load_reg(get_field(f, r3));
|