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1 | 81ea0e13 | Michael Walle | /*
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2 | 81ea0e13 | Michael Walle | * LatticeMico32 virtual CPU header.
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3 | 81ea0e13 | Michael Walle | *
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4 | 81ea0e13 | Michael Walle | * Copyright (c) 2010 Michael Walle <michael@walle.cc>
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5 | 81ea0e13 | Michael Walle | *
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6 | 81ea0e13 | Michael Walle | * This library is free software; you can redistribute it and/or
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7 | 81ea0e13 | Michael Walle | * modify it under the terms of the GNU Lesser General Public
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8 | 81ea0e13 | Michael Walle | * License as published by the Free Software Foundation; either
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9 | 81ea0e13 | Michael Walle | * version 2 of the License, or (at your option) any later version.
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10 | 81ea0e13 | Michael Walle | *
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11 | 81ea0e13 | Michael Walle | * This library is distributed in the hope that it will be useful,
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12 | 81ea0e13 | Michael Walle | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 81ea0e13 | Michael Walle | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 81ea0e13 | Michael Walle | * Lesser General Public License for more details.
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15 | 81ea0e13 | Michael Walle | *
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16 | 81ea0e13 | Michael Walle | * You should have received a copy of the GNU Lesser General Public
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17 | 81ea0e13 | Michael Walle | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 81ea0e13 | Michael Walle | */
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19 | 81ea0e13 | Michael Walle | |
20 | 81ea0e13 | Michael Walle | #ifndef CPU_LM32_H
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21 | 81ea0e13 | Michael Walle | #define CPU_LM32_H
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22 | 81ea0e13 | Michael Walle | |
23 | 81ea0e13 | Michael Walle | #define TARGET_LONG_BITS 32 |
24 | 81ea0e13 | Michael Walle | |
25 | 81ea0e13 | Michael Walle | #define CPUState struct CPULM32State |
26 | 81ea0e13 | Michael Walle | |
27 | 81ea0e13 | Michael Walle | #include "qemu-common.h" |
28 | 81ea0e13 | Michael Walle | #include "cpu-defs.h" |
29 | 81ea0e13 | Michael Walle | struct CPULM32State;
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30 | 81ea0e13 | Michael Walle | |
31 | 81ea0e13 | Michael Walle | #define TARGET_HAS_ICE 1 |
32 | 81ea0e13 | Michael Walle | |
33 | 81ea0e13 | Michael Walle | #define ELF_MACHINE EM_LATTICEMICO32
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34 | 81ea0e13 | Michael Walle | |
35 | 81ea0e13 | Michael Walle | #define NB_MMU_MODES 1 |
36 | 81ea0e13 | Michael Walle | #define TARGET_PAGE_BITS 12 |
37 | 81ea0e13 | Michael Walle | static inline int cpu_mmu_index(CPUState *env) |
38 | 81ea0e13 | Michael Walle | { |
39 | 81ea0e13 | Michael Walle | return 0; |
40 | 81ea0e13 | Michael Walle | } |
41 | 81ea0e13 | Michael Walle | |
42 | 81ea0e13 | Michael Walle | #define TARGET_PHYS_ADDR_SPACE_BITS 32 |
43 | 81ea0e13 | Michael Walle | #define TARGET_VIRT_ADDR_SPACE_BITS 32 |
44 | 81ea0e13 | Michael Walle | |
45 | 81ea0e13 | Michael Walle | /* Exceptions indices */
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46 | 81ea0e13 | Michael Walle | enum {
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47 | 81ea0e13 | Michael Walle | EXCP_RESET = 0,
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48 | 81ea0e13 | Michael Walle | EXCP_BREAKPOINT, |
49 | 81ea0e13 | Michael Walle | EXCP_INSN_BUS_ERROR, |
50 | 81ea0e13 | Michael Walle | EXCP_WATCHPOINT, |
51 | 81ea0e13 | Michael Walle | EXCP_DATA_BUS_ERROR, |
52 | 81ea0e13 | Michael Walle | EXCP_DIVIDE_BY_ZERO, |
53 | 81ea0e13 | Michael Walle | EXCP_IRQ, |
54 | 81ea0e13 | Michael Walle | EXCP_SYSTEMCALL |
55 | 81ea0e13 | Michael Walle | }; |
56 | 81ea0e13 | Michael Walle | |
57 | 81ea0e13 | Michael Walle | /* Registers */
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58 | 81ea0e13 | Michael Walle | enum {
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59 | 81ea0e13 | Michael Walle | R_R0 = 0, R_R1, R_R2, R_R3, R_R4, R_R5, R_R6, R_R7, R_R8, R_R9, R_R10,
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60 | 81ea0e13 | Michael Walle | R_R11, R_R12, R_R13, R_R14, R_R15, R_R16, R_R17, R_R18, R_R19, R_R20, |
61 | 81ea0e13 | Michael Walle | R_R21, R_R22, R_R23, R_R24, R_R25, R_R26, R_R27, R_R28, R_R29, R_R30, |
62 | 81ea0e13 | Michael Walle | R_R31 |
63 | 81ea0e13 | Michael Walle | }; |
64 | 81ea0e13 | Michael Walle | |
65 | 81ea0e13 | Michael Walle | /* Register aliases */
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66 | 81ea0e13 | Michael Walle | enum {
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67 | 81ea0e13 | Michael Walle | R_GP = R_R26, |
68 | 81ea0e13 | Michael Walle | R_FP = R_R27, |
69 | 81ea0e13 | Michael Walle | R_SP = R_R28, |
70 | 81ea0e13 | Michael Walle | R_RA = R_R29, |
71 | 81ea0e13 | Michael Walle | R_EA = R_R30, |
72 | 81ea0e13 | Michael Walle | R_BA = R_R31 |
73 | 81ea0e13 | Michael Walle | }; |
74 | 81ea0e13 | Michael Walle | |
75 | 81ea0e13 | Michael Walle | /* IE flags */
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76 | 81ea0e13 | Michael Walle | enum {
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77 | 81ea0e13 | Michael Walle | IE_IE = (1<<0), |
78 | 81ea0e13 | Michael Walle | IE_EIE = (1<<1), |
79 | 81ea0e13 | Michael Walle | IE_BIE = (1<<2), |
80 | 81ea0e13 | Michael Walle | }; |
81 | 81ea0e13 | Michael Walle | |
82 | 81ea0e13 | Michael Walle | /* DC flags */
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83 | 81ea0e13 | Michael Walle | enum {
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84 | 81ea0e13 | Michael Walle | DC_SS = (1<<0), |
85 | 81ea0e13 | Michael Walle | DC_RE = (1<<1), |
86 | 81ea0e13 | Michael Walle | DC_C0 = (1<<2), |
87 | 81ea0e13 | Michael Walle | DC_C1 = (1<<3), |
88 | 81ea0e13 | Michael Walle | DC_C2 = (1<<4), |
89 | 81ea0e13 | Michael Walle | DC_C3 = (1<<5), |
90 | 81ea0e13 | Michael Walle | }; |
91 | 81ea0e13 | Michael Walle | |
92 | 81ea0e13 | Michael Walle | /* CFG mask */
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93 | 81ea0e13 | Michael Walle | enum {
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94 | 81ea0e13 | Michael Walle | CFG_M = (1<<0), |
95 | 81ea0e13 | Michael Walle | CFG_D = (1<<1), |
96 | 81ea0e13 | Michael Walle | CFG_S = (1<<2), |
97 | 81ea0e13 | Michael Walle | CFG_U = (1<<3), |
98 | 81ea0e13 | Michael Walle | CFG_X = (1<<4), |
99 | 81ea0e13 | Michael Walle | CFG_CC = (1<<5), |
100 | 81ea0e13 | Michael Walle | CFG_IC = (1<<6), |
101 | 81ea0e13 | Michael Walle | CFG_DC = (1<<7), |
102 | 81ea0e13 | Michael Walle | CFG_G = (1<<8), |
103 | 81ea0e13 | Michael Walle | CFG_H = (1<<9), |
104 | 81ea0e13 | Michael Walle | CFG_R = (1<<10), |
105 | 81ea0e13 | Michael Walle | CFG_J = (1<<11), |
106 | 81ea0e13 | Michael Walle | CFG_INT_SHIFT = 12,
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107 | 81ea0e13 | Michael Walle | CFG_BP_SHIFT = 18,
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108 | 81ea0e13 | Michael Walle | CFG_WP_SHIFT = 22,
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109 | 81ea0e13 | Michael Walle | CFG_REV_SHIFT = 26,
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110 | 81ea0e13 | Michael Walle | }; |
111 | 81ea0e13 | Michael Walle | |
112 | 81ea0e13 | Michael Walle | /* CSRs */
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113 | 81ea0e13 | Michael Walle | enum {
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114 | 81ea0e13 | Michael Walle | CSR_IE = 0x00,
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115 | 81ea0e13 | Michael Walle | CSR_IM = 0x01,
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116 | 81ea0e13 | Michael Walle | CSR_IP = 0x02,
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117 | 81ea0e13 | Michael Walle | CSR_ICC = 0x03,
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118 | 81ea0e13 | Michael Walle | CSR_DCC = 0x04,
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119 | 81ea0e13 | Michael Walle | CSR_CC = 0x05,
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120 | 81ea0e13 | Michael Walle | CSR_CFG = 0x06,
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121 | 81ea0e13 | Michael Walle | CSR_EBA = 0x07,
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122 | 81ea0e13 | Michael Walle | CSR_DC = 0x08,
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123 | 81ea0e13 | Michael Walle | CSR_DEBA = 0x09,
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124 | 81ea0e13 | Michael Walle | CSR_JTX = 0x0e,
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125 | 81ea0e13 | Michael Walle | CSR_JRX = 0x0f,
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126 | 81ea0e13 | Michael Walle | CSR_BP0 = 0x10,
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127 | 81ea0e13 | Michael Walle | CSR_BP1 = 0x11,
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128 | 81ea0e13 | Michael Walle | CSR_BP2 = 0x12,
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129 | 81ea0e13 | Michael Walle | CSR_BP3 = 0x13,
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130 | 81ea0e13 | Michael Walle | CSR_WP0 = 0x18,
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131 | 81ea0e13 | Michael Walle | CSR_WP1 = 0x19,
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132 | 81ea0e13 | Michael Walle | CSR_WP2 = 0x1a,
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133 | 81ea0e13 | Michael Walle | CSR_WP3 = 0x1b,
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134 | 81ea0e13 | Michael Walle | }; |
135 | 81ea0e13 | Michael Walle | |
136 | 81ea0e13 | Michael Walle | enum {
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137 | 81ea0e13 | Michael Walle | LM32_FEATURE_MULTIPLY = 1,
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138 | 81ea0e13 | Michael Walle | LM32_FEATURE_DIVIDE = 2,
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139 | 81ea0e13 | Michael Walle | LM32_FEATURE_SHIFT = 4,
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140 | 81ea0e13 | Michael Walle | LM32_FEATURE_SIGN_EXTEND = 8,
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141 | 81ea0e13 | Michael Walle | LM32_FEATURE_I_CACHE = 16,
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142 | 81ea0e13 | Michael Walle | LM32_FEATURE_D_CACHE = 32,
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143 | 81ea0e13 | Michael Walle | LM32_FEATURE_CYCLE_COUNT = 64,
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144 | 81ea0e13 | Michael Walle | }; |
145 | 81ea0e13 | Michael Walle | |
146 | 81ea0e13 | Michael Walle | enum {
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147 | 81ea0e13 | Michael Walle | LM32_FLAG_IGNORE_MSB = 1,
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148 | 81ea0e13 | Michael Walle | }; |
149 | 81ea0e13 | Michael Walle | |
150 | 81ea0e13 | Michael Walle | typedef struct CPULM32State { |
151 | 81ea0e13 | Michael Walle | /* general registers */
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152 | 81ea0e13 | Michael Walle | uint32_t regs[32];
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153 | 81ea0e13 | Michael Walle | |
154 | 81ea0e13 | Michael Walle | /* special registers */
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155 | 81ea0e13 | Michael Walle | uint32_t pc; /* program counter */
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156 | 81ea0e13 | Michael Walle | uint32_t ie; /* interrupt enable */
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157 | 81ea0e13 | Michael Walle | uint32_t icc; /* instruction cache control */
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158 | 81ea0e13 | Michael Walle | uint32_t dcc; /* data cache control */
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159 | 81ea0e13 | Michael Walle | uint32_t cc; /* cycle counter */
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160 | 81ea0e13 | Michael Walle | uint32_t cfg; /* configuration */
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161 | 81ea0e13 | Michael Walle | |
162 | 81ea0e13 | Michael Walle | /* debug registers */
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163 | 81ea0e13 | Michael Walle | uint32_t dc; /* debug control */
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164 | 81ea0e13 | Michael Walle | uint32_t bp[4]; /* breakpoint addresses */ |
165 | 81ea0e13 | Michael Walle | uint32_t wp[4]; /* watchpoint addresses */ |
166 | 81ea0e13 | Michael Walle | |
167 | 81ea0e13 | Michael Walle | CPU_COMMON |
168 | 81ea0e13 | Michael Walle | |
169 | 81ea0e13 | Michael Walle | uint32_t eba; /* exception base address */
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170 | 81ea0e13 | Michael Walle | uint32_t deba; /* debug exception base address */
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171 | 81ea0e13 | Michael Walle | |
172 | 81ea0e13 | Michael Walle | /* interrupt controller handle for callbacks */
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173 | 81ea0e13 | Michael Walle | DeviceState *pic_state; |
174 | 81ea0e13 | Michael Walle | /* JTAG UART handle for callbacks */
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175 | 81ea0e13 | Michael Walle | DeviceState *juart_state; |
176 | 81ea0e13 | Michael Walle | |
177 | 81ea0e13 | Michael Walle | /* processor core features */
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178 | 81ea0e13 | Michael Walle | uint32_t features; |
179 | 81ea0e13 | Michael Walle | uint32_t flags; |
180 | 81ea0e13 | Michael Walle | uint8_t num_bps; |
181 | 81ea0e13 | Michael Walle | uint8_t num_wps; |
182 | 81ea0e13 | Michael Walle | |
183 | 81ea0e13 | Michael Walle | } CPULM32State; |
184 | 81ea0e13 | Michael Walle | |
185 | 81ea0e13 | Michael Walle | |
186 | 81ea0e13 | Michael Walle | CPUState *cpu_lm32_init(const char *cpu_model); |
187 | 81ea0e13 | Michael Walle | void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf);
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188 | 81ea0e13 | Michael Walle | int cpu_lm32_exec(CPUState *s);
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189 | 81ea0e13 | Michael Walle | void cpu_lm32_close(CPUState *s);
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190 | 81ea0e13 | Michael Walle | void do_interrupt(CPUState *env);
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191 | 81ea0e13 | Michael Walle | /* you can call this signal handler from your SIGBUS and SIGSEGV
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192 | 81ea0e13 | Michael Walle | signal handlers to inform the virtual CPU of exceptions. non zero
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193 | 81ea0e13 | Michael Walle | is returned if the signal was handled by the virtual CPU. */
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194 | 81ea0e13 | Michael Walle | int cpu_lm32_signal_handler(int host_signum, void *pinfo, |
195 | 81ea0e13 | Michael Walle | void *puc);
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196 | 81ea0e13 | Michael Walle | void lm32_translate_init(void); |
197 | 81ea0e13 | Michael Walle | void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value); |
198 | 81ea0e13 | Michael Walle | |
199 | 81ea0e13 | Michael Walle | #define cpu_list cpu_lm32_list
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200 | 81ea0e13 | Michael Walle | #define cpu_init cpu_lm32_init
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201 | 81ea0e13 | Michael Walle | #define cpu_exec cpu_lm32_exec
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202 | 81ea0e13 | Michael Walle | #define cpu_gen_code cpu_lm32_gen_code
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203 | 81ea0e13 | Michael Walle | #define cpu_signal_handler cpu_lm32_signal_handler
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204 | 81ea0e13 | Michael Walle | |
205 | 81ea0e13 | Michael Walle | #define CPU_SAVE_VERSION 1 |
206 | 81ea0e13 | Michael Walle | |
207 | 81ea0e13 | Michael Walle | int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
208 | 81ea0e13 | Michael Walle | int mmu_idx, int is_softmmu); |
209 | 81ea0e13 | Michael Walle | #define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault
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210 | 81ea0e13 | Michael Walle | |
211 | 81ea0e13 | Michael Walle | #if defined(CONFIG_USER_ONLY)
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212 | 81ea0e13 | Michael Walle | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
213 | 81ea0e13 | Michael Walle | { |
214 | 81ea0e13 | Michael Walle | if (newsp) {
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215 | 81ea0e13 | Michael Walle | env->regs[R_SP] = newsp; |
216 | 81ea0e13 | Michael Walle | } |
217 | 81ea0e13 | Michael Walle | env->regs[R_R1] = 0;
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218 | 81ea0e13 | Michael Walle | } |
219 | 81ea0e13 | Michael Walle | #endif
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220 | 81ea0e13 | Michael Walle | |
221 | 81ea0e13 | Michael Walle | static inline void cpu_set_tls(CPUState *env, target_ulong newtls) |
222 | 81ea0e13 | Michael Walle | { |
223 | 81ea0e13 | Michael Walle | } |
224 | 81ea0e13 | Michael Walle | |
225 | 81ea0e13 | Michael Walle | static inline int cpu_interrupts_enabled(CPUState *env) |
226 | 81ea0e13 | Michael Walle | { |
227 | 81ea0e13 | Michael Walle | return env->ie & IE_IE;
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228 | 81ea0e13 | Michael Walle | } |
229 | 81ea0e13 | Michael Walle | |
230 | 81ea0e13 | Michael Walle | #include "cpu-all.h" |
231 | 81ea0e13 | Michael Walle | |
232 | 81ea0e13 | Michael Walle | static inline target_ulong cpu_get_pc(CPUState *env) |
233 | 81ea0e13 | Michael Walle | { |
234 | 81ea0e13 | Michael Walle | return env->pc;
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235 | 81ea0e13 | Michael Walle | } |
236 | 81ea0e13 | Michael Walle | |
237 | 81ea0e13 | Michael Walle | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
238 | 81ea0e13 | Michael Walle | target_ulong *cs_base, int *flags)
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239 | 81ea0e13 | Michael Walle | { |
240 | 81ea0e13 | Michael Walle | *pc = env->pc; |
241 | 81ea0e13 | Michael Walle | *cs_base = 0;
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242 | 81ea0e13 | Michael Walle | *flags = 0;
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243 | 81ea0e13 | Michael Walle | } |
244 | 81ea0e13 | Michael Walle | #endif |