Statistics
| Branch: | Revision:

root / hw / etraxfs_dma.c @ c6d86a33

History | View | Annotate | Download (21.6 kB)

1 1ba13a5d edgar_igl
/*
2 1ba13a5d edgar_igl
 * QEMU ETRAX DMA Controller.
3 1ba13a5d edgar_igl
 *
4 1ba13a5d edgar_igl
 * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
5 1ba13a5d edgar_igl
 *
6 1ba13a5d edgar_igl
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 1ba13a5d edgar_igl
 * of this software and associated documentation files (the "Software"), to deal
8 1ba13a5d edgar_igl
 * in the Software without restriction, including without limitation the rights
9 1ba13a5d edgar_igl
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 1ba13a5d edgar_igl
 * copies of the Software, and to permit persons to whom the Software is
11 1ba13a5d edgar_igl
 * furnished to do so, subject to the following conditions:
12 1ba13a5d edgar_igl
 *
13 1ba13a5d edgar_igl
 * The above copyright notice and this permission notice shall be included in
14 1ba13a5d edgar_igl
 * all copies or substantial portions of the Software.
15 1ba13a5d edgar_igl
 *
16 1ba13a5d edgar_igl
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 1ba13a5d edgar_igl
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 1ba13a5d edgar_igl
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 1ba13a5d edgar_igl
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 1ba13a5d edgar_igl
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 1ba13a5d edgar_igl
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 1ba13a5d edgar_igl
 * THE SOFTWARE.
23 1ba13a5d edgar_igl
 */
24 1ba13a5d edgar_igl
#include <stdio.h>
25 1ba13a5d edgar_igl
#include <sys/time.h>
26 1ba13a5d edgar_igl
#include "hw.h"
27 492c30af aliguori
#include "qemu-common.h"
28 492c30af aliguori
#include "sysemu.h"
29 1ba13a5d edgar_igl
30 1ba13a5d edgar_igl
#include "etraxfs_dma.h"
31 1ba13a5d edgar_igl
32 1ba13a5d edgar_igl
#define D(x)
33 1ba13a5d edgar_igl
34 1ba13a5d edgar_igl
#define RW_DATA           0x0
35 1ba13a5d edgar_igl
#define RW_SAVED_DATA     0x58
36 1ba13a5d edgar_igl
#define RW_SAVED_DATA_BUF 0x5c
37 1ba13a5d edgar_igl
#define RW_GROUP          0x60
38 1ba13a5d edgar_igl
#define RW_GROUP_DOWN     0x7c
39 1ba13a5d edgar_igl
#define RW_CMD            0x80
40 1ba13a5d edgar_igl
#define RW_CFG            0x84
41 1ba13a5d edgar_igl
#define RW_STAT           0x88
42 1ba13a5d edgar_igl
#define RW_INTR_MASK      0x8c
43 1ba13a5d edgar_igl
#define RW_ACK_INTR       0x90
44 1ba13a5d edgar_igl
#define R_INTR            0x94
45 1ba13a5d edgar_igl
#define R_MASKED_INTR     0x98
46 1ba13a5d edgar_igl
#define RW_STREAM_CMD     0x9c
47 1ba13a5d edgar_igl
48 1ba13a5d edgar_igl
#define DMA_REG_MAX   0x100
49 1ba13a5d edgar_igl
50 1ba13a5d edgar_igl
/* descriptors */
51 1ba13a5d edgar_igl
52 1ba13a5d edgar_igl
// ------------------------------------------------------------ dma_descr_group
53 1ba13a5d edgar_igl
typedef struct dma_descr_group {
54 1ba13a5d edgar_igl
  struct dma_descr_group       *next;
55 1ba13a5d edgar_igl
  unsigned                      eol        : 1;
56 1ba13a5d edgar_igl
  unsigned                      tol        : 1;
57 1ba13a5d edgar_igl
  unsigned                      bol        : 1;
58 1ba13a5d edgar_igl
  unsigned                                 : 1;
59 1ba13a5d edgar_igl
  unsigned                      intr       : 1;
60 1ba13a5d edgar_igl
  unsigned                                 : 2;
61 1ba13a5d edgar_igl
  unsigned                      en         : 1;
62 1ba13a5d edgar_igl
  unsigned                                 : 7;
63 1ba13a5d edgar_igl
  unsigned                      dis        : 1;
64 1ba13a5d edgar_igl
  unsigned                      md         : 16;
65 1ba13a5d edgar_igl
  struct dma_descr_group       *up;
66 1ba13a5d edgar_igl
  union {
67 1ba13a5d edgar_igl
    struct dma_descr_context   *context;
68 1ba13a5d edgar_igl
    struct dma_descr_group     *group;
69 1ba13a5d edgar_igl
  }                             down;
70 1ba13a5d edgar_igl
} dma_descr_group;
71 1ba13a5d edgar_igl
72 1ba13a5d edgar_igl
// ---------------------------------------------------------- dma_descr_context
73 1ba13a5d edgar_igl
typedef struct dma_descr_context {
74 1ba13a5d edgar_igl
  struct dma_descr_context     *next;
75 1ba13a5d edgar_igl
  unsigned                      eol        : 1;
76 1ba13a5d edgar_igl
  unsigned                                 : 3;
77 1ba13a5d edgar_igl
  unsigned                      intr       : 1;
78 1ba13a5d edgar_igl
  unsigned                                 : 1;
79 1ba13a5d edgar_igl
  unsigned                      store_mode : 1;
80 1ba13a5d edgar_igl
  unsigned                      en         : 1;
81 1ba13a5d edgar_igl
  unsigned                                 : 7;
82 1ba13a5d edgar_igl
  unsigned                      dis        : 1;
83 1ba13a5d edgar_igl
  unsigned                      md0        : 16;
84 1ba13a5d edgar_igl
  unsigned                      md1;
85 1ba13a5d edgar_igl
  unsigned                      md2;
86 1ba13a5d edgar_igl
  unsigned                      md3;
87 1ba13a5d edgar_igl
  unsigned                      md4;
88 1ba13a5d edgar_igl
  struct dma_descr_data        *saved_data;
89 1ba13a5d edgar_igl
  char                         *saved_data_buf;
90 1ba13a5d edgar_igl
} dma_descr_context;
91 1ba13a5d edgar_igl
92 1ba13a5d edgar_igl
// ------------------------------------------------------------- dma_descr_data
93 1ba13a5d edgar_igl
typedef struct dma_descr_data {
94 1ba13a5d edgar_igl
  struct dma_descr_data        *next;
95 1ba13a5d edgar_igl
  char                         *buf;
96 1ba13a5d edgar_igl
  unsigned                      eol        : 1;
97 1ba13a5d edgar_igl
  unsigned                                 : 2;
98 1ba13a5d edgar_igl
  unsigned                      out_eop    : 1;
99 1ba13a5d edgar_igl
  unsigned                      intr       : 1;
100 1ba13a5d edgar_igl
  unsigned                      wait       : 1;
101 1ba13a5d edgar_igl
  unsigned                                 : 2;
102 1ba13a5d edgar_igl
  unsigned                                 : 3;
103 1ba13a5d edgar_igl
  unsigned                      in_eop     : 1;
104 1ba13a5d edgar_igl
  unsigned                                 : 4;
105 1ba13a5d edgar_igl
  unsigned                      md         : 16;
106 1ba13a5d edgar_igl
  char                         *after;
107 1ba13a5d edgar_igl
} dma_descr_data;
108 1ba13a5d edgar_igl
109 1ba13a5d edgar_igl
/* Constants */
110 1ba13a5d edgar_igl
enum {
111 1ba13a5d edgar_igl
  regk_dma_ack_pkt                         = 0x00000100,
112 1ba13a5d edgar_igl
  regk_dma_anytime                         = 0x00000001,
113 1ba13a5d edgar_igl
  regk_dma_array                           = 0x00000008,
114 1ba13a5d edgar_igl
  regk_dma_burst                           = 0x00000020,
115 1ba13a5d edgar_igl
  regk_dma_client                          = 0x00000002,
116 1ba13a5d edgar_igl
  regk_dma_copy_next                       = 0x00000010,
117 1ba13a5d edgar_igl
  regk_dma_copy_up                         = 0x00000020,
118 1ba13a5d edgar_igl
  regk_dma_data_at_eol                     = 0x00000001,
119 1ba13a5d edgar_igl
  regk_dma_dis_c                           = 0x00000010,
120 1ba13a5d edgar_igl
  regk_dma_dis_g                           = 0x00000020,
121 1ba13a5d edgar_igl
  regk_dma_idle                            = 0x00000001,
122 1ba13a5d edgar_igl
  regk_dma_intern                          = 0x00000004,
123 1ba13a5d edgar_igl
  regk_dma_load_c                          = 0x00000200,
124 1ba13a5d edgar_igl
  regk_dma_load_c_n                        = 0x00000280,
125 1ba13a5d edgar_igl
  regk_dma_load_c_next                     = 0x00000240,
126 1ba13a5d edgar_igl
  regk_dma_load_d                          = 0x00000140,
127 1ba13a5d edgar_igl
  regk_dma_load_g                          = 0x00000300,
128 1ba13a5d edgar_igl
  regk_dma_load_g_down                     = 0x000003c0,
129 1ba13a5d edgar_igl
  regk_dma_load_g_next                     = 0x00000340,
130 1ba13a5d edgar_igl
  regk_dma_load_g_up                       = 0x00000380,
131 1ba13a5d edgar_igl
  regk_dma_next_en                         = 0x00000010,
132 1ba13a5d edgar_igl
  regk_dma_next_pkt                        = 0x00000010,
133 1ba13a5d edgar_igl
  regk_dma_no                              = 0x00000000,
134 1ba13a5d edgar_igl
  regk_dma_only_at_wait                    = 0x00000000,
135 1ba13a5d edgar_igl
  regk_dma_restore                         = 0x00000020,
136 1ba13a5d edgar_igl
  regk_dma_rst                             = 0x00000001,
137 1ba13a5d edgar_igl
  regk_dma_running                         = 0x00000004,
138 1ba13a5d edgar_igl
  regk_dma_rw_cfg_default                  = 0x00000000,
139 1ba13a5d edgar_igl
  regk_dma_rw_cmd_default                  = 0x00000000,
140 1ba13a5d edgar_igl
  regk_dma_rw_intr_mask_default            = 0x00000000,
141 1ba13a5d edgar_igl
  regk_dma_rw_stat_default                 = 0x00000101,
142 1ba13a5d edgar_igl
  regk_dma_rw_stream_cmd_default           = 0x00000000,
143 1ba13a5d edgar_igl
  regk_dma_save_down                       = 0x00000020,
144 1ba13a5d edgar_igl
  regk_dma_save_up                         = 0x00000020,
145 1ba13a5d edgar_igl
  regk_dma_set_reg                         = 0x00000050,
146 1ba13a5d edgar_igl
  regk_dma_set_w_size1                     = 0x00000190,
147 1ba13a5d edgar_igl
  regk_dma_set_w_size2                     = 0x000001a0,
148 1ba13a5d edgar_igl
  regk_dma_set_w_size4                     = 0x000001c0,
149 1ba13a5d edgar_igl
  regk_dma_stopped                         = 0x00000002,
150 1ba13a5d edgar_igl
  regk_dma_store_c                         = 0x00000002,
151 1ba13a5d edgar_igl
  regk_dma_store_descr                     = 0x00000000,
152 1ba13a5d edgar_igl
  regk_dma_store_g                         = 0x00000004,
153 1ba13a5d edgar_igl
  regk_dma_store_md                        = 0x00000001,
154 1ba13a5d edgar_igl
  regk_dma_sw                              = 0x00000008,
155 1ba13a5d edgar_igl
  regk_dma_update_down                     = 0x00000020,
156 1ba13a5d edgar_igl
  regk_dma_yes                             = 0x00000001
157 1ba13a5d edgar_igl
};
158 1ba13a5d edgar_igl
159 1ba13a5d edgar_igl
enum dma_ch_state
160 1ba13a5d edgar_igl
{
161 4487fd34 edgar_igl
        RST = 1,
162 1ba13a5d edgar_igl
        STOPPED = 2,
163 1ba13a5d edgar_igl
        RUNNING = 4
164 1ba13a5d edgar_igl
};
165 1ba13a5d edgar_igl
166 1ba13a5d edgar_igl
struct fs_dma_channel
167 1ba13a5d edgar_igl
{
168 1ba13a5d edgar_igl
        qemu_irq *irq;
169 1ba13a5d edgar_igl
        struct etraxfs_dma_client *client;
170 1ba13a5d edgar_igl
171 1ba13a5d edgar_igl
        /* Internal status.  */
172 1ba13a5d edgar_igl
        int stream_cmd_src;
173 1ba13a5d edgar_igl
        enum dma_ch_state state;
174 1ba13a5d edgar_igl
175 1ba13a5d edgar_igl
        unsigned int input : 1;
176 1ba13a5d edgar_igl
        unsigned int eol : 1;
177 1ba13a5d edgar_igl
178 1ba13a5d edgar_igl
        struct dma_descr_group current_g;
179 1ba13a5d edgar_igl
        struct dma_descr_context current_c;
180 1ba13a5d edgar_igl
        struct dma_descr_data current_d;
181 1ba13a5d edgar_igl
182 1ba13a5d edgar_igl
        /* Controll registers.  */
183 1ba13a5d edgar_igl
        uint32_t regs[DMA_REG_MAX];
184 1ba13a5d edgar_igl
};
185 1ba13a5d edgar_igl
186 1ba13a5d edgar_igl
struct fs_dma_ctrl
187 1ba13a5d edgar_igl
{
188 e6320485 edgar_igl
        int map;
189 1ba13a5d edgar_igl
        CPUState *env;
190 1ba13a5d edgar_igl
191 1ba13a5d edgar_igl
        int nr_channels;
192 1ba13a5d edgar_igl
        struct fs_dma_channel *channels;
193 492c30af aliguori
194 492c30af aliguori
        QEMUBH *bh;
195 1ba13a5d edgar_igl
};
196 1ba13a5d edgar_igl
197 1ba13a5d edgar_igl
static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg)
198 1ba13a5d edgar_igl
{
199 1ba13a5d edgar_igl
        return ctrl->channels[c].regs[reg];
200 1ba13a5d edgar_igl
}
201 1ba13a5d edgar_igl
202 1ba13a5d edgar_igl
static inline int channel_stopped(struct fs_dma_ctrl *ctrl, int c)
203 1ba13a5d edgar_igl
{
204 1ba13a5d edgar_igl
        return channel_reg(ctrl, c, RW_CFG) & 2;
205 1ba13a5d edgar_igl
}
206 1ba13a5d edgar_igl
207 1ba13a5d edgar_igl
static inline int channel_en(struct fs_dma_ctrl *ctrl, int c)
208 1ba13a5d edgar_igl
{
209 1ba13a5d edgar_igl
        return (channel_reg(ctrl, c, RW_CFG) & 1)
210 1ba13a5d edgar_igl
                && ctrl->channels[c].client;
211 1ba13a5d edgar_igl
}
212 1ba13a5d edgar_igl
213 8da3ff18 pbrook
static inline int fs_channel(target_phys_addr_t addr)
214 1ba13a5d edgar_igl
{
215 1ba13a5d edgar_igl
        /* Every channel has a 0x2000 ctrl register map.  */
216 8da3ff18 pbrook
        return addr >> 13;
217 1ba13a5d edgar_igl
}
218 1ba13a5d edgar_igl
219 d297f464 edgar_igl
#ifdef USE_THIS_DEAD_CODE
220 1ba13a5d edgar_igl
static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
221 1ba13a5d edgar_igl
{
222 1ba13a5d edgar_igl
        target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);
223 1ba13a5d edgar_igl
224 1ba13a5d edgar_igl
        /* Load and decode. FIXME: handle endianness.  */
225 1ba13a5d edgar_igl
        cpu_physical_memory_read (addr, 
226 1ba13a5d edgar_igl
                                  (void *) &ctrl->channels[c].current_g, 
227 1ba13a5d edgar_igl
                                  sizeof ctrl->channels[c].current_g);
228 1ba13a5d edgar_igl
}
229 1ba13a5d edgar_igl
230 1ba13a5d edgar_igl
static void dump_c(int ch, struct dma_descr_context *c)
231 1ba13a5d edgar_igl
{
232 1ba13a5d edgar_igl
        printf("%s ch=%d\n", __func__, ch);
233 d297f464 edgar_igl
        printf("next=%p\n", c->next);
234 d297f464 edgar_igl
        printf("saved_data=%p\n", c->saved_data);
235 d297f464 edgar_igl
        printf("saved_data_buf=%p\n", c->saved_data_buf);
236 1ba13a5d edgar_igl
        printf("eol=%x\n", (uint32_t) c->eol);
237 1ba13a5d edgar_igl
}
238 1ba13a5d edgar_igl
239 1ba13a5d edgar_igl
static void dump_d(int ch, struct dma_descr_data *d)
240 1ba13a5d edgar_igl
{
241 1ba13a5d edgar_igl
        printf("%s ch=%d\n", __func__, ch);
242 d297f464 edgar_igl
        printf("next=%p\n", d->next);
243 d297f464 edgar_igl
        printf("buf=%p\n", d->buf);
244 d297f464 edgar_igl
        printf("after=%p\n", d->after);
245 1ba13a5d edgar_igl
        printf("intr=%x\n", (uint32_t) d->intr);
246 1ba13a5d edgar_igl
        printf("out_eop=%x\n", (uint32_t) d->out_eop);
247 1ba13a5d edgar_igl
        printf("in_eop=%x\n", (uint32_t) d->in_eop);
248 1ba13a5d edgar_igl
        printf("eol=%x\n", (uint32_t) d->eol);
249 1ba13a5d edgar_igl
}
250 d297f464 edgar_igl
#endif
251 1ba13a5d edgar_igl
252 1ba13a5d edgar_igl
static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
253 1ba13a5d edgar_igl
{
254 1ba13a5d edgar_igl
        target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
255 1ba13a5d edgar_igl
256 1ba13a5d edgar_igl
        /* Load and decode. FIXME: handle endianness.  */
257 1ba13a5d edgar_igl
        cpu_physical_memory_read (addr, 
258 1ba13a5d edgar_igl
                                  (void *) &ctrl->channels[c].current_c, 
259 1ba13a5d edgar_igl
                                  sizeof ctrl->channels[c].current_c);
260 1ba13a5d edgar_igl
261 1ba13a5d edgar_igl
        D(dump_c(c, &ctrl->channels[c].current_c));
262 1ba13a5d edgar_igl
        /* I guess this should update the current pos.  */
263 d297f464 edgar_igl
        ctrl->channels[c].regs[RW_SAVED_DATA] =
264 d297f464 edgar_igl
                (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data;
265 1ba13a5d edgar_igl
        ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
266 d297f464 edgar_igl
                (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data_buf;
267 1ba13a5d edgar_igl
}
268 1ba13a5d edgar_igl
269 1ba13a5d edgar_igl
static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
270 1ba13a5d edgar_igl
{
271 1ba13a5d edgar_igl
        target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
272 1ba13a5d edgar_igl
273 1ba13a5d edgar_igl
        /* Load and decode. FIXME: handle endianness.  */
274 a8303d18 edgar_igl
        D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
275 1ba13a5d edgar_igl
        cpu_physical_memory_read (addr,
276 1ba13a5d edgar_igl
                                  (void *) &ctrl->channels[c].current_d, 
277 1ba13a5d edgar_igl
                                  sizeof ctrl->channels[c].current_d);
278 1ba13a5d edgar_igl
279 1ba13a5d edgar_igl
        D(dump_d(c, &ctrl->channels[c].current_d));
280 fa1bdde4 edgar_igl
        ctrl->channels[c].regs[RW_DATA] = addr;
281 a8303d18 edgar_igl
}
282 a8303d18 edgar_igl
283 a8303d18 edgar_igl
static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
284 a8303d18 edgar_igl
{
285 a8303d18 edgar_igl
        target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
286 a8303d18 edgar_igl
287 a8303d18 edgar_igl
        /* Encode and store. FIXME: handle endianness.  */
288 a8303d18 edgar_igl
        D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
289 a8303d18 edgar_igl
        D(dump_d(c, &ctrl->channels[c].current_d));
290 a8303d18 edgar_igl
        cpu_physical_memory_write (addr,
291 a8303d18 edgar_igl
                                  (void *) &ctrl->channels[c].current_c,
292 a8303d18 edgar_igl
                                  sizeof ctrl->channels[c].current_c);
293 1ba13a5d edgar_igl
}
294 1ba13a5d edgar_igl
295 1ba13a5d edgar_igl
static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
296 1ba13a5d edgar_igl
{
297 1ba13a5d edgar_igl
        target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
298 1ba13a5d edgar_igl
299 a8303d18 edgar_igl
        /* Encode and store. FIXME: handle endianness.  */
300 a8303d18 edgar_igl
        D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
301 1ba13a5d edgar_igl
        cpu_physical_memory_write (addr,
302 1ba13a5d edgar_igl
                                  (void *) &ctrl->channels[c].current_d, 
303 1ba13a5d edgar_igl
                                  sizeof ctrl->channels[c].current_d);
304 1ba13a5d edgar_igl
}
305 1ba13a5d edgar_igl
306 1ba13a5d edgar_igl
static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c)
307 1ba13a5d edgar_igl
{
308 1ba13a5d edgar_igl
        /* FIXME:  */
309 1ba13a5d edgar_igl
}
310 1ba13a5d edgar_igl
311 1ba13a5d edgar_igl
static inline void channel_start(struct fs_dma_ctrl *ctrl, int c)
312 1ba13a5d edgar_igl
{
313 1ba13a5d edgar_igl
        if (ctrl->channels[c].client)
314 1ba13a5d edgar_igl
        {
315 1ba13a5d edgar_igl
                ctrl->channels[c].eol = 0;
316 1ba13a5d edgar_igl
                ctrl->channels[c].state = RUNNING;
317 1ba13a5d edgar_igl
        } else
318 1ba13a5d edgar_igl
                printf("WARNING: starting DMA ch %d with no client\n", c);
319 1ab5f75c edgar_igl
320 1ab5f75c edgar_igl
        qemu_bh_schedule_idle(ctrl->bh);
321 1ba13a5d edgar_igl
}
322 1ba13a5d edgar_igl
323 1ba13a5d edgar_igl
static void channel_continue(struct fs_dma_ctrl *ctrl, int c)
324 1ba13a5d edgar_igl
{
325 1ba13a5d edgar_igl
        if (!channel_en(ctrl, c) 
326 1ba13a5d edgar_igl
            || channel_stopped(ctrl, c)
327 1ba13a5d edgar_igl
            || ctrl->channels[c].state != RUNNING
328 1ba13a5d edgar_igl
            /* Only reload the current data descriptor if it has eol set.  */
329 1ba13a5d edgar_igl
            || !ctrl->channels[c].current_d.eol) {
330 1ba13a5d edgar_igl
                D(printf("continue failed ch=%d state=%d stopped=%d en=%d eol=%d\n", 
331 1ba13a5d edgar_igl
                         c, ctrl->channels[c].state,
332 1ba13a5d edgar_igl
                         channel_stopped(ctrl, c),
333 1ba13a5d edgar_igl
                         channel_en(ctrl,c),
334 1ba13a5d edgar_igl
                         ctrl->channels[c].eol));
335 1ba13a5d edgar_igl
                D(dump_d(c, &ctrl->channels[c].current_d));
336 1ba13a5d edgar_igl
                return;
337 1ba13a5d edgar_igl
        }
338 1ba13a5d edgar_igl
339 1ba13a5d edgar_igl
        /* Reload the current descriptor.  */
340 1ba13a5d edgar_igl
        channel_load_d(ctrl, c);
341 1ba13a5d edgar_igl
342 1ba13a5d edgar_igl
        /* If the current descriptor cleared the eol flag and we had already
343 1ba13a5d edgar_igl
           reached eol state, do the continue.  */
344 1ba13a5d edgar_igl
        if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) {
345 a8303d18 edgar_igl
                D(printf("continue %d ok %p\n", c,
346 1ba13a5d edgar_igl
                         ctrl->channels[c].current_d.next));
347 1ba13a5d edgar_igl
                ctrl->channels[c].regs[RW_SAVED_DATA] =
348 d297f464 edgar_igl
                        (uint32_t)(unsigned long)ctrl->channels[c].current_d.next;
349 1ba13a5d edgar_igl
                channel_load_d(ctrl, c);
350 1ba13a5d edgar_igl
                channel_start(ctrl, c);
351 1ba13a5d edgar_igl
        }
352 a8303d18 edgar_igl
        ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
353 d297f464 edgar_igl
                (uint32_t)(unsigned long)ctrl->channels[c].current_d.buf;
354 1ba13a5d edgar_igl
}
355 1ba13a5d edgar_igl
356 1ba13a5d edgar_igl
static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v)
357 1ba13a5d edgar_igl
{
358 1ba13a5d edgar_igl
        unsigned int cmd = v & ((1 << 10) - 1);
359 1ba13a5d edgar_igl
360 d27b2e50 edgar_igl
        D(printf("%s ch=%d cmd=%x\n",
361 d27b2e50 edgar_igl
                 __func__, c, cmd));
362 1ba13a5d edgar_igl
        if (cmd & regk_dma_load_d) {
363 1ba13a5d edgar_igl
                channel_load_d(ctrl, c);
364 1ba13a5d edgar_igl
                if (cmd & regk_dma_burst)
365 1ba13a5d edgar_igl
                        channel_start(ctrl, c);
366 1ba13a5d edgar_igl
        }
367 1ba13a5d edgar_igl
368 1ba13a5d edgar_igl
        if (cmd & regk_dma_load_c) {
369 1ba13a5d edgar_igl
                channel_load_c(ctrl, c);
370 a8303d18 edgar_igl
                channel_start(ctrl, c);
371 1ba13a5d edgar_igl
        }
372 1ba13a5d edgar_igl
}
373 1ba13a5d edgar_igl
374 1ba13a5d edgar_igl
static void channel_update_irq(struct fs_dma_ctrl *ctrl, int c)
375 1ba13a5d edgar_igl
{
376 1ba13a5d edgar_igl
        D(printf("%s %d\n", __func__, c));
377 1ba13a5d edgar_igl
        ctrl->channels[c].regs[R_INTR] &=
378 1ba13a5d edgar_igl
                ~(ctrl->channels[c].regs[RW_ACK_INTR]);
379 1ba13a5d edgar_igl
380 1ba13a5d edgar_igl
        ctrl->channels[c].regs[R_MASKED_INTR] =
381 1ba13a5d edgar_igl
                ctrl->channels[c].regs[R_INTR]
382 1ba13a5d edgar_igl
                & ctrl->channels[c].regs[RW_INTR_MASK];
383 1ba13a5d edgar_igl
384 1ba13a5d edgar_igl
        D(printf("%s: chan=%d masked_intr=%x\n", __func__, 
385 1ba13a5d edgar_igl
                 c,
386 1ba13a5d edgar_igl
                 ctrl->channels[c].regs[R_MASKED_INTR]));
387 1ba13a5d edgar_igl
388 1ba13a5d edgar_igl
        if (ctrl->channels[c].regs[R_MASKED_INTR])
389 1ba13a5d edgar_igl
                qemu_irq_raise(ctrl->channels[c].irq[0]);
390 1ba13a5d edgar_igl
        else
391 1ba13a5d edgar_igl
                qemu_irq_lower(ctrl->channels[c].irq[0]);
392 1ba13a5d edgar_igl
}
393 1ba13a5d edgar_igl
394 1ab5f75c edgar_igl
static int channel_out_run(struct fs_dma_ctrl *ctrl, int c)
395 1ba13a5d edgar_igl
{
396 1ba13a5d edgar_igl
        uint32_t len;
397 1ba13a5d edgar_igl
        uint32_t saved_data_buf;
398 1ba13a5d edgar_igl
        unsigned char buf[2 * 1024];
399 1ba13a5d edgar_igl
400 1ab5f75c edgar_igl
        if (ctrl->channels[c].eol)
401 1ab5f75c edgar_igl
                return 0;
402 1ab5f75c edgar_igl
403 1ab5f75c edgar_igl
        do {
404 c968ef8d edgar_igl
                saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
405 c968ef8d edgar_igl
406 c968ef8d edgar_igl
                D(printf("ch=%d buf=%x after=%x saved_data_buf=%x\n",
407 c968ef8d edgar_igl
                         c,
408 c968ef8d edgar_igl
                         (uint32_t)ctrl->channels[c].current_d.buf,
409 c968ef8d edgar_igl
                         (uint32_t)ctrl->channels[c].current_d.after,
410 c968ef8d edgar_igl
                         saved_data_buf));
411 c968ef8d edgar_igl
412 ea0f49a7 edgar_igl
                len = (uint32_t)(unsigned long)
413 ea0f49a7 edgar_igl
                        ctrl->channels[c].current_d.after;
414 c968ef8d edgar_igl
                len -= saved_data_buf;
415 c968ef8d edgar_igl
416 c968ef8d edgar_igl
                if (len > sizeof buf)
417 c968ef8d edgar_igl
                        len = sizeof buf;
418 c968ef8d edgar_igl
                cpu_physical_memory_read (saved_data_buf, buf, len);
419 c968ef8d edgar_igl
420 c968ef8d edgar_igl
                D(printf("channel %d pushes %x %u bytes\n", c, 
421 c968ef8d edgar_igl
                         saved_data_buf, len));
422 c968ef8d edgar_igl
423 c968ef8d edgar_igl
                if (ctrl->channels[c].client->client.push)
424 c968ef8d edgar_igl
                        ctrl->channels[c].client->client.push(
425 c968ef8d edgar_igl
                                ctrl->channels[c].client->client.opaque,
426 c968ef8d edgar_igl
                                buf, len);
427 c968ef8d edgar_igl
                else
428 c968ef8d edgar_igl
                        printf("WARNING: DMA ch%d dataloss,"
429 c968ef8d edgar_igl
                               " no attached client.\n", c);
430 c968ef8d edgar_igl
431 c968ef8d edgar_igl
                saved_data_buf += len;
432 c968ef8d edgar_igl
433 ea0f49a7 edgar_igl
                if (saved_data_buf == (uint32_t)(unsigned long)
434 ea0f49a7 edgar_igl
                                ctrl->channels[c].current_d.after) {
435 c968ef8d edgar_igl
                        /* Done. Step to next.  */
436 c968ef8d edgar_igl
                        if (ctrl->channels[c].current_d.out_eop) {
437 c968ef8d edgar_igl
                                /* TODO: signal eop to the client.  */
438 c968ef8d edgar_igl
                                D(printf("signal eop\n"));
439 c968ef8d edgar_igl
                        }
440 c968ef8d edgar_igl
                        if (ctrl->channels[c].current_d.intr) {
441 c968ef8d edgar_igl
                                /* TODO: signal eop to the client.  */
442 c968ef8d edgar_igl
                                /* data intr.  */
443 c968ef8d edgar_igl
                                D(printf("signal intr\n"));
444 c968ef8d edgar_igl
                                ctrl->channels[c].regs[R_INTR] |= (1 << 2);
445 c968ef8d edgar_igl
                                channel_update_irq(ctrl, c);
446 c968ef8d edgar_igl
                        }
447 c968ef8d edgar_igl
                        if (ctrl->channels[c].current_d.eol) {
448 c968ef8d edgar_igl
                                D(printf("channel %d EOL\n", c));
449 c968ef8d edgar_igl
                                ctrl->channels[c].eol = 1;
450 c968ef8d edgar_igl
451 c968ef8d edgar_igl
                                /* Mark the context as disabled.  */
452 c968ef8d edgar_igl
                                ctrl->channels[c].current_c.dis = 1;
453 c968ef8d edgar_igl
                                channel_store_c(ctrl, c);
454 c968ef8d edgar_igl
455 c968ef8d edgar_igl
                                channel_stop(ctrl, c);
456 c968ef8d edgar_igl
                        } else {
457 c968ef8d edgar_igl
                                ctrl->channels[c].regs[RW_SAVED_DATA] =
458 ea0f49a7 edgar_igl
                                        (uint32_t)(unsigned long)ctrl->
459 ea0f49a7 edgar_igl
                                                channels[c].current_d.next;
460 c968ef8d edgar_igl
                                /* Load new descriptor.  */
461 c968ef8d edgar_igl
                                channel_load_d(ctrl, c);
462 c968ef8d edgar_igl
                                saved_data_buf = (uint32_t)(unsigned long)
463 c968ef8d edgar_igl
                                        ctrl->channels[c].current_d.buf;
464 c968ef8d edgar_igl
                        }
465 c968ef8d edgar_igl
466 c968ef8d edgar_igl
                        channel_store_d(ctrl, c);
467 c968ef8d edgar_igl
                        ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
468 c968ef8d edgar_igl
                                                        saved_data_buf;
469 c968ef8d edgar_igl
                        D(dump_d(c, &ctrl->channels[c].current_d));
470 1ba13a5d edgar_igl
                }
471 a8303d18 edgar_igl
                ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
472 1ab5f75c edgar_igl
        } while (!ctrl->channels[c].eol);
473 1ab5f75c edgar_igl
        return 1;
474 1ba13a5d edgar_igl
}
475 1ba13a5d edgar_igl
476 1ba13a5d edgar_igl
static int channel_in_process(struct fs_dma_ctrl *ctrl, int c, 
477 1ba13a5d edgar_igl
                              unsigned char *buf, int buflen, int eop)
478 1ba13a5d edgar_igl
{
479 1ba13a5d edgar_igl
        uint32_t len;
480 1ba13a5d edgar_igl
        uint32_t saved_data_buf;
481 1ba13a5d edgar_igl
482 1ba13a5d edgar_igl
        if (ctrl->channels[c].eol == 1)
483 1ba13a5d edgar_igl
                return 0;
484 1ba13a5d edgar_igl
485 1ba13a5d edgar_igl
        saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
486 ea0f49a7 edgar_igl
        len = (uint32_t)(unsigned long)ctrl->channels[c].current_d.after;
487 1ba13a5d edgar_igl
        len -= saved_data_buf;
488 1ba13a5d edgar_igl
        
489 1ba13a5d edgar_igl
        if (len > buflen)
490 1ba13a5d edgar_igl
                len = buflen;
491 1ba13a5d edgar_igl
492 1ba13a5d edgar_igl
        cpu_physical_memory_write (saved_data_buf, buf, len);
493 1ba13a5d edgar_igl
        saved_data_buf += len;
494 1ba13a5d edgar_igl
495 d297f464 edgar_igl
        if (saved_data_buf ==
496 ea0f49a7 edgar_igl
            (uint32_t)(unsigned long)ctrl->channels[c].current_d.after
497 1ba13a5d edgar_igl
            || eop) {
498 1ba13a5d edgar_igl
                uint32_t r_intr = ctrl->channels[c].regs[R_INTR];
499 1ba13a5d edgar_igl
500 1ba13a5d edgar_igl
                D(printf("in dscr end len=%d\n", 
501 1ba13a5d edgar_igl
                         ctrl->channels[c].current_d.after
502 1ba13a5d edgar_igl
                         - ctrl->channels[c].current_d.buf));
503 1ba13a5d edgar_igl
                ctrl->channels[c].current_d.after = 
504 d297f464 edgar_igl
                        (void *)(unsigned long) saved_data_buf;
505 1ba13a5d edgar_igl
506 1ba13a5d edgar_igl
                /* Done. Step to next.  */
507 1ba13a5d edgar_igl
                if (ctrl->channels[c].current_d.intr) {
508 1ba13a5d edgar_igl
                        /* TODO: signal eop to the client.  */
509 1ba13a5d edgar_igl
                        /* data intr.  */
510 1ba13a5d edgar_igl
                        ctrl->channels[c].regs[R_INTR] |= 3;
511 1ba13a5d edgar_igl
                }
512 1ba13a5d edgar_igl
                if (eop) {
513 1ba13a5d edgar_igl
                        ctrl->channels[c].current_d.in_eop = 1;
514 1ba13a5d edgar_igl
                        ctrl->channels[c].regs[R_INTR] |= 8;
515 1ba13a5d edgar_igl
                }
516 1ba13a5d edgar_igl
                if (r_intr != ctrl->channels[c].regs[R_INTR])
517 1ba13a5d edgar_igl
                        channel_update_irq(ctrl, c);
518 1ba13a5d edgar_igl
519 1ba13a5d edgar_igl
                channel_store_d(ctrl, c);
520 1ba13a5d edgar_igl
                D(dump_d(c, &ctrl->channels[c].current_d));
521 1ba13a5d edgar_igl
522 1ba13a5d edgar_igl
                if (ctrl->channels[c].current_d.eol) {
523 1ba13a5d edgar_igl
                        D(printf("channel %d EOL\n", c));
524 1ba13a5d edgar_igl
                        ctrl->channels[c].eol = 1;
525 a8303d18 edgar_igl
526 a8303d18 edgar_igl
                        /* Mark the context as disabled.  */
527 a8303d18 edgar_igl
                        ctrl->channels[c].current_c.dis = 1;
528 a8303d18 edgar_igl
                        channel_store_c(ctrl, c);
529 a8303d18 edgar_igl
530 1ba13a5d edgar_igl
                        channel_stop(ctrl, c);
531 1ba13a5d edgar_igl
                } else {
532 1ba13a5d edgar_igl
                        ctrl->channels[c].regs[RW_SAVED_DATA] =
533 ea0f49a7 edgar_igl
                                (uint32_t)(unsigned long)ctrl->
534 ea0f49a7 edgar_igl
                                        channels[c].current_d.next;
535 1ba13a5d edgar_igl
                        /* Load new descriptor.  */
536 1ba13a5d edgar_igl
                        channel_load_d(ctrl, c);
537 ea0f49a7 edgar_igl
                        saved_data_buf = (uint32_t)(unsigned long)
538 a8303d18 edgar_igl
                                ctrl->channels[c].current_d.buf;
539 1ba13a5d edgar_igl
                }
540 1ba13a5d edgar_igl
        }
541 1ba13a5d edgar_igl
542 1ba13a5d edgar_igl
        ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
543 1ba13a5d edgar_igl
        return len;
544 1ba13a5d edgar_igl
}
545 1ba13a5d edgar_igl
546 1ab5f75c edgar_igl
static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c)
547 1ba13a5d edgar_igl
{
548 1ab5f75c edgar_igl
        if (ctrl->channels[c].client->client.pull) {
549 1ba13a5d edgar_igl
                ctrl->channels[c].client->client.pull(
550 1ba13a5d edgar_igl
                        ctrl->channels[c].client->client.opaque);
551 1ab5f75c edgar_igl
                return 1;
552 1ab5f75c edgar_igl
        } else
553 1ab5f75c edgar_igl
                return 0;
554 1ba13a5d edgar_igl
}
555 1ba13a5d edgar_igl
556 1ba13a5d edgar_igl
static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
557 1ba13a5d edgar_igl
{
558 1ba13a5d edgar_igl
        struct fs_dma_ctrl *ctrl = opaque;
559 1ba13a5d edgar_igl
        CPUState *env = ctrl->env;
560 d27b2e50 edgar_igl
        cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
561 d27b2e50 edgar_igl
                  addr);
562 1ba13a5d edgar_igl
        return 0;
563 1ba13a5d edgar_igl
}
564 1ba13a5d edgar_igl
565 1ba13a5d edgar_igl
static uint32_t
566 1ba13a5d edgar_igl
dma_readl (void *opaque, target_phys_addr_t addr)
567 1ba13a5d edgar_igl
{
568 1ba13a5d edgar_igl
        struct fs_dma_ctrl *ctrl = opaque;
569 1ba13a5d edgar_igl
        int c;
570 1ba13a5d edgar_igl
        uint32_t r = 0;
571 1ba13a5d edgar_igl
572 e6320485 edgar_igl
        /* Make addr relative to this channel and bounded to nr regs.  */
573 8da3ff18 pbrook
        c = fs_channel(addr);
574 e6320485 edgar_igl
        addr &= 0xff;
575 1ba13a5d edgar_igl
        switch (addr)
576 a8303d18 edgar_igl
        {
577 1ba13a5d edgar_igl
                case RW_STAT:
578 1ba13a5d edgar_igl
                        r = ctrl->channels[c].state & 7;
579 1ba13a5d edgar_igl
                        r |= ctrl->channels[c].eol << 5;
580 1ba13a5d edgar_igl
                        r |= ctrl->channels[c].stream_cmd_src << 8;
581 1ba13a5d edgar_igl
                        break;
582 1ba13a5d edgar_igl
583 a8303d18 edgar_igl
                default:
584 1ba13a5d edgar_igl
                        r = ctrl->channels[c].regs[addr];
585 d27b2e50 edgar_igl
                        D(printf ("%s c=%d addr=%x\n",
586 d27b2e50 edgar_igl
                                  __func__, c, addr));
587 a8303d18 edgar_igl
                        break;
588 a8303d18 edgar_igl
        }
589 1ba13a5d edgar_igl
        return r;
590 1ba13a5d edgar_igl
}
591 1ba13a5d edgar_igl
592 1ba13a5d edgar_igl
static void
593 1ba13a5d edgar_igl
dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
594 1ba13a5d edgar_igl
{
595 1ba13a5d edgar_igl
        struct fs_dma_ctrl *ctrl = opaque;
596 1ba13a5d edgar_igl
        CPUState *env = ctrl->env;
597 d27b2e50 edgar_igl
        cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
598 d27b2e50 edgar_igl
                  addr);
599 1ba13a5d edgar_igl
}
600 1ba13a5d edgar_igl
601 1ba13a5d edgar_igl
static void
602 4487fd34 edgar_igl
dma_update_state(struct fs_dma_ctrl *ctrl, int c)
603 4487fd34 edgar_igl
{
604 4487fd34 edgar_igl
        if ((ctrl->channels[c].regs[RW_CFG] & 1) != 3) {
605 4487fd34 edgar_igl
                if (ctrl->channels[c].regs[RW_CFG] & 2)
606 4487fd34 edgar_igl
                        ctrl->channels[c].state = STOPPED;
607 4487fd34 edgar_igl
                if (!(ctrl->channels[c].regs[RW_CFG] & 1))
608 4487fd34 edgar_igl
                        ctrl->channels[c].state = RST;
609 4487fd34 edgar_igl
        }
610 4487fd34 edgar_igl
}
611 4487fd34 edgar_igl
612 4487fd34 edgar_igl
static void
613 1ba13a5d edgar_igl
dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
614 1ba13a5d edgar_igl
{
615 1ba13a5d edgar_igl
        struct fs_dma_ctrl *ctrl = opaque;
616 1ba13a5d edgar_igl
        int c;
617 1ba13a5d edgar_igl
618 e6320485 edgar_igl
        /* Make addr relative to this channel and bounded to nr regs.  */
619 8da3ff18 pbrook
        c = fs_channel(addr);
620 e6320485 edgar_igl
        addr &= 0xff;
621 1ba13a5d edgar_igl
        switch (addr)
622 a8303d18 edgar_igl
        {
623 1ba13a5d edgar_igl
                case RW_DATA:
624 fa1bdde4 edgar_igl
                        ctrl->channels[c].regs[addr] = value;
625 1ba13a5d edgar_igl
                        break;
626 1ba13a5d edgar_igl
627 1ba13a5d edgar_igl
                case RW_CFG:
628 1ba13a5d edgar_igl
                        ctrl->channels[c].regs[addr] = value;
629 4487fd34 edgar_igl
                        dma_update_state(ctrl, c);
630 1ba13a5d edgar_igl
                        break;
631 1ba13a5d edgar_igl
                case RW_CMD:
632 1ba13a5d edgar_igl
                        /* continue.  */
633 4487fd34 edgar_igl
                        if (value & ~1)
634 4487fd34 edgar_igl
                                printf("Invalid store to ch=%d RW_CMD %x\n",
635 4487fd34 edgar_igl
                                       c, value);
636 1ba13a5d edgar_igl
                        ctrl->channels[c].regs[addr] = value;
637 1ba13a5d edgar_igl
                        channel_continue(ctrl, c);
638 1ba13a5d edgar_igl
                        break;
639 1ba13a5d edgar_igl
640 1ba13a5d edgar_igl
                case RW_SAVED_DATA:
641 1ba13a5d edgar_igl
                case RW_SAVED_DATA_BUF:
642 1ba13a5d edgar_igl
                case RW_GROUP:
643 1ba13a5d edgar_igl
                case RW_GROUP_DOWN:
644 1ba13a5d edgar_igl
                        ctrl->channels[c].regs[addr] = value;
645 1ba13a5d edgar_igl
                        break;
646 1ba13a5d edgar_igl
647 1ba13a5d edgar_igl
                case RW_ACK_INTR:
648 1ba13a5d edgar_igl
                case RW_INTR_MASK:
649 1ba13a5d edgar_igl
                        ctrl->channels[c].regs[addr] = value;
650 1ba13a5d edgar_igl
                        channel_update_irq(ctrl, c);
651 1ba13a5d edgar_igl
                        if (addr == RW_ACK_INTR)
652 1ba13a5d edgar_igl
                                ctrl->channels[c].regs[RW_ACK_INTR] = 0;
653 1ba13a5d edgar_igl
                        break;
654 1ba13a5d edgar_igl
655 1ba13a5d edgar_igl
                case RW_STREAM_CMD:
656 4487fd34 edgar_igl
                        if (value & ~1023)
657 4487fd34 edgar_igl
                                printf("Invalid store to ch=%d "
658 4487fd34 edgar_igl
                                       "RW_STREAMCMD %x\n",
659 4487fd34 edgar_igl
                                       c, value);
660 1ba13a5d edgar_igl
                        ctrl->channels[c].regs[addr] = value;
661 d27b2e50 edgar_igl
                        D(printf("stream_cmd ch=%d\n", c));
662 1ba13a5d edgar_igl
                        channel_stream_cmd(ctrl, c, value);
663 1ba13a5d edgar_igl
                        break;
664 1ba13a5d edgar_igl
665 a8303d18 edgar_igl
                default:
666 d27b2e50 edgar_igl
                        D(printf ("%s c=%d %x %x\n", __func__, c, addr));
667 a8303d18 edgar_igl
                        break;
668 1ba13a5d edgar_igl
        }
669 1ba13a5d edgar_igl
}
670 1ba13a5d edgar_igl
671 1ba13a5d edgar_igl
static CPUReadMemoryFunc *dma_read[] = {
672 1ba13a5d edgar_igl
        &dma_rinvalid,
673 1ba13a5d edgar_igl
        &dma_rinvalid,
674 1ba13a5d edgar_igl
        &dma_readl,
675 1ba13a5d edgar_igl
};
676 1ba13a5d edgar_igl
677 1ba13a5d edgar_igl
static CPUWriteMemoryFunc *dma_write[] = {
678 1ba13a5d edgar_igl
        &dma_winvalid,
679 1ba13a5d edgar_igl
        &dma_winvalid,
680 1ba13a5d edgar_igl
        &dma_writel,
681 1ba13a5d edgar_igl
};
682 1ba13a5d edgar_igl
683 1ab5f75c edgar_igl
static int etraxfs_dmac_run(void *opaque)
684 1ba13a5d edgar_igl
{
685 1ba13a5d edgar_igl
        struct fs_dma_ctrl *ctrl = opaque;
686 1ba13a5d edgar_igl
        int i;
687 1ba13a5d edgar_igl
        int p = 0;
688 1ba13a5d edgar_igl
689 1ba13a5d edgar_igl
        for (i = 0; 
690 1ba13a5d edgar_igl
             i < ctrl->nr_channels;
691 1ba13a5d edgar_igl
             i++)
692 1ba13a5d edgar_igl
        {
693 1ba13a5d edgar_igl
                if (ctrl->channels[i].state == RUNNING)
694 1ba13a5d edgar_igl
                {
695 1ab5f75c edgar_igl
                        if (ctrl->channels[i].input) {
696 1ab5f75c edgar_igl
                                p += channel_in_run(ctrl, i);
697 1ab5f75c edgar_igl
                        } else {
698 1ab5f75c edgar_igl
                                p += channel_out_run(ctrl, i);
699 1ab5f75c edgar_igl
                        }
700 1ba13a5d edgar_igl
                }
701 1ba13a5d edgar_igl
        }
702 1ab5f75c edgar_igl
        return p;
703 1ba13a5d edgar_igl
}
704 1ba13a5d edgar_igl
705 1ba13a5d edgar_igl
int etraxfs_dmac_input(struct etraxfs_dma_client *client, 
706 1ba13a5d edgar_igl
                       void *buf, int len, int eop)
707 1ba13a5d edgar_igl
{
708 1ba13a5d edgar_igl
        return channel_in_process(client->ctrl, client->channel, 
709 1ba13a5d edgar_igl
                                  buf, len, eop);
710 1ba13a5d edgar_igl
}
711 1ba13a5d edgar_igl
712 1ba13a5d edgar_igl
/* Connect an IRQ line with a channel.  */
713 1ba13a5d edgar_igl
void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input)
714 1ba13a5d edgar_igl
{
715 1ba13a5d edgar_igl
        struct fs_dma_ctrl *ctrl = opaque;
716 1ba13a5d edgar_igl
        ctrl->channels[c].irq = line;
717 1ba13a5d edgar_igl
        ctrl->channels[c].input = input;
718 1ba13a5d edgar_igl
}
719 1ba13a5d edgar_igl
720 1ba13a5d edgar_igl
void etraxfs_dmac_connect_client(void *opaque, int c, 
721 1ba13a5d edgar_igl
                                 struct etraxfs_dma_client *cl)
722 1ba13a5d edgar_igl
{
723 1ba13a5d edgar_igl
        struct fs_dma_ctrl *ctrl = opaque;
724 1ba13a5d edgar_igl
        cl->ctrl = ctrl;
725 1ba13a5d edgar_igl
        cl->channel = c;
726 1ba13a5d edgar_igl
        ctrl->channels[c].client = cl;
727 1ba13a5d edgar_igl
}
728 1ba13a5d edgar_igl
729 1ba13a5d edgar_igl
730 492c30af aliguori
static void DMA_run(void *opaque)
731 fa1bdde4 edgar_igl
{
732 492c30af aliguori
    struct fs_dma_ctrl *etraxfs_dmac = opaque;
733 1ab5f75c edgar_igl
    int p = 1;
734 1ab5f75c edgar_igl
735 492c30af aliguori
    if (vm_running)
736 1ab5f75c edgar_igl
        p = etraxfs_dmac_run(etraxfs_dmac);
737 1ab5f75c edgar_igl
738 1ab5f75c edgar_igl
    if (p)
739 1ab5f75c edgar_igl
        qemu_bh_schedule_idle(etraxfs_dmac->bh);
740 fa1bdde4 edgar_igl
}
741 fa1bdde4 edgar_igl
742 1ba13a5d edgar_igl
void *etraxfs_dmac_init(CPUState *env, 
743 1ba13a5d edgar_igl
                        target_phys_addr_t base, int nr_channels)
744 1ba13a5d edgar_igl
{
745 1ba13a5d edgar_igl
        struct fs_dma_ctrl *ctrl = NULL;
746 1ba13a5d edgar_igl
747 1ba13a5d edgar_igl
        ctrl = qemu_mallocz(sizeof *ctrl);
748 1ba13a5d edgar_igl
        if (!ctrl)
749 1ba13a5d edgar_igl
                return NULL;
750 1ba13a5d edgar_igl
751 492c30af aliguori
        ctrl->bh = qemu_bh_new(DMA_run, ctrl);
752 492c30af aliguori
753 1ba13a5d edgar_igl
        ctrl->env = env;
754 1ba13a5d edgar_igl
        ctrl->nr_channels = nr_channels;
755 1ba13a5d edgar_igl
        ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);
756 1ba13a5d edgar_igl
        if (!ctrl->channels)
757 1ba13a5d edgar_igl
                goto err;
758 1ba13a5d edgar_igl
759 e6320485 edgar_igl
        ctrl->map = cpu_register_io_memory(0, dma_read, dma_write, ctrl);
760 e6320485 edgar_igl
        cpu_register_physical_memory(base, nr_channels * 0x2000, ctrl->map);
761 1ba13a5d edgar_igl
        return ctrl;
762 1ba13a5d edgar_igl
  err:
763 1ba13a5d edgar_igl
        qemu_free(ctrl->channels);
764 1ba13a5d edgar_igl
        qemu_free(ctrl);
765 1ba13a5d edgar_igl
        return NULL;
766 1ba13a5d edgar_igl
}