root / hw / omap_gpio.c @ c6df7102
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/*
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* TI OMAP processors GPIO emulation.
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*
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* Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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* Copyright (C) 2007-2009 Nokia Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h" |
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#include "omap.h" |
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/* General-Purpose I/O */
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struct omap_gpio_s {
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qemu_irq irq; |
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qemu_irq *in; |
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qemu_irq handler[16];
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|
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uint16_t inputs; |
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uint16_t outputs; |
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uint16_t dir; |
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uint16_t edge; |
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uint16_t mask; |
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uint16_t ints; |
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uint16_t pins; |
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}; |
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|
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static void omap_gpio_set(void *opaque, int line, int level) |
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{
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struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
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uint16_t prev = s->inputs; |
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if (level)
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s->inputs |= 1 << line;
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else
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s->inputs &= ~(1 << line);
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if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
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(1 << line) & s->dir & ~s->mask) {
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s->ints |= 1 << line;
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qemu_irq_raise(s->irq); |
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} |
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} |
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|
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static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr) |
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{
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struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
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int offset = addr & OMAP_MPUI_REG_MASK;
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switch (offset) {
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case 0x00: /* DATA_INPUT */ |
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return s->inputs & s->pins;
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|
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case 0x04: /* DATA_OUTPUT */ |
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return s->outputs;
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|
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case 0x08: /* DIRECTION_CONTROL */ |
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return s->dir;
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|
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case 0x0c: /* INTERRUPT_CONTROL */ |
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return s->edge;
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case 0x10: /* INTERRUPT_MASK */ |
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return s->mask;
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|
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case 0x14: /* INTERRUPT_STATUS */ |
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return s->ints;
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case 0x18: /* PIN_CONTROL (not in OMAP310) */ |
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OMAP_BAD_REG(addr); |
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return s->pins;
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} |
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OMAP_BAD_REG(addr); |
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return 0; |
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} |
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|
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static void omap_gpio_write(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{
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struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
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int offset = addr & OMAP_MPUI_REG_MASK;
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uint16_t diff; |
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int ln;
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switch (offset) {
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case 0x00: /* DATA_INPUT */ |
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OMAP_RO_REG(addr); |
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return;
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case 0x04: /* DATA_OUTPUT */ |
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diff = (s->outputs ^ value) & ~s->dir; |
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s->outputs = value; |
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while ((ln = ffs(diff))) {
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ln --; |
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if (s->handler[ln])
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qemu_set_irq(s->handler[ln], (value >> ln) & 1);
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diff &= ~(1 << ln);
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} |
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break;
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case 0x08: /* DIRECTION_CONTROL */ |
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diff = s->outputs & (s->dir ^ value); |
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s->dir = value; |
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value = s->outputs & ~s->dir; |
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while ((ln = ffs(diff))) {
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ln --; |
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if (s->handler[ln])
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qemu_set_irq(s->handler[ln], (value >> ln) & 1);
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diff &= ~(1 << ln);
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} |
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break;
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case 0x0c: /* INTERRUPT_CONTROL */ |
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s->edge = value; |
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break;
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case 0x10: /* INTERRUPT_MASK */ |
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s->mask = value; |
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break;
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case 0x14: /* INTERRUPT_STATUS */ |
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s->ints &= ~value; |
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if (!s->ints)
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qemu_irq_lower(s->irq); |
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break;
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case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */ |
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OMAP_BAD_REG(addr); |
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s->pins = value; |
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break;
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default:
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OMAP_BAD_REG(addr); |
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return;
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} |
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} |
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/* *Some* sources say the memory region is 32-bit. */
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static CPUReadMemoryFunc * const omap_gpio_readfn[] = { |
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omap_badwidth_read16, |
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omap_gpio_read, |
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omap_badwidth_read16, |
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}; |
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static CPUWriteMemoryFunc * const omap_gpio_writefn[] = { |
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omap_badwidth_write16, |
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omap_gpio_write, |
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omap_badwidth_write16, |
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}; |
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void omap_gpio_reset(struct omap_gpio_s *s) |
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{
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s->inputs = 0;
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s->outputs = ~0;
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s->dir = ~0;
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s->edge = ~0;
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s->mask = ~0;
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s->ints = 0;
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s->pins = ~0;
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} |
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struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
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qemu_irq irq, omap_clk clk) |
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{
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int iomemtype;
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struct omap_gpio_s *s = (struct omap_gpio_s *) |
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qemu_mallocz(sizeof(struct omap_gpio_s)); |
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s->irq = irq; |
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s->in = qemu_allocate_irqs(omap_gpio_set, s, 16);
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omap_gpio_reset(s); |
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iomemtype = cpu_register_io_memory(omap_gpio_readfn, |
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omap_gpio_writefn, s, DEVICE_NATIVE_ENDIAN); |
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cpu_register_physical_memory(base, 0x1000, iomemtype);
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return s;
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} |
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qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s)
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{
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return s->in;
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} |
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void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler) |
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{
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if (line >= 16 || line < 0) |
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hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
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s->handler[line] = handler; |
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} |
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/* General-Purpose Interface of OMAP2 */
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struct omap2_gpio_s {
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qemu_irq irq[2];
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qemu_irq wkup; |
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qemu_irq *in; |
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qemu_irq handler[32];
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uint8_t config[2];
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uint32_t inputs; |
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uint32_t outputs; |
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uint32_t dir; |
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uint32_t level[2];
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uint32_t edge[2];
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uint32_t mask[2];
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uint32_t wumask; |
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uint32_t ints[2];
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uint32_t debounce; |
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uint8_t delay; |
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}; |
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static inline void omap2_gpio_module_int_update(struct omap2_gpio_s *s, |
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int line)
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{
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qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]); |
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} |
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static void omap2_gpio_module_wake(struct omap2_gpio_s *s, int line) |
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{
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if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */ |
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return;
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if (!(s->config[0] & (3 << 3))) /* Force Idle */ |
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return;
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if (!(s->wumask & (1 << line))) |
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return;
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qemu_irq_raise(s->wkup); |
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} |
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|
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static inline void omap2_gpio_module_out_update(struct omap2_gpio_s *s, |
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uint32_t diff) |
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{
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int ln;
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s->outputs ^= diff; |
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diff &= ~s->dir; |
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while ((ln = ffs(diff))) {
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ln --; |
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qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1);
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diff &= ~(1 << ln);
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} |
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} |
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static void omap2_gpio_module_level_update(struct omap2_gpio_s *s, int line) |
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{
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s->ints[line] |= s->dir & |
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((s->inputs & s->level[1]) | (~s->inputs & s->level[0])); |
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omap2_gpio_module_int_update(s, line); |
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} |
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static inline void omap2_gpio_module_int(struct omap2_gpio_s *s, int line) |
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{
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s->ints[0] |= 1 << line; |
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omap2_gpio_module_int_update(s, 0);
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s->ints[1] |= 1 << line; |
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omap2_gpio_module_int_update(s, 1);
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omap2_gpio_module_wake(s, line); |
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} |
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static void omap2_gpio_module_set(void *opaque, int line, int level) |
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{
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struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; |
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if (level) {
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if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1])) |
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omap2_gpio_module_int(s, line); |
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s->inputs |= 1 << line;
|
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} else {
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if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0])) |
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omap2_gpio_module_int(s, line); |
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s->inputs &= ~(1 << line);
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} |
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} |
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static void omap2_gpio_module_reset(struct omap2_gpio_s *s) |
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{
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s->config[0] = 0; |
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s->config[1] = 2; |
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s->ints[0] = 0; |
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s->ints[1] = 0; |
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s->mask[0] = 0; |
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s->mask[1] = 0; |
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s->wumask = 0;
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s->dir = ~0;
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s->level[0] = 0; |
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s->level[1] = 0; |
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s->edge[0] = 0; |
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s->edge[1] = 0; |
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s->debounce = 0;
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s->delay = 0;
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} |
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|
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static uint32_t omap2_gpio_module_read(void *opaque, target_phys_addr_t addr) |
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{
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struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; |
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switch (addr) {
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case 0x00: /* GPIO_REVISION */ |
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return 0x18; |
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|
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case 0x10: /* GPIO_SYSCONFIG */ |
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return s->config[0]; |
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|
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case 0x14: /* GPIO_SYSSTATUS */ |
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return 0x01; |
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|
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case 0x18: /* GPIO_IRQSTATUS1 */ |
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return s->ints[0]; |
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|
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case 0x1c: /* GPIO_IRQENABLE1 */ |
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case 0x60: /* GPIO_CLEARIRQENABLE1 */ |
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case 0x64: /* GPIO_SETIRQENABLE1 */ |
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return s->mask[0]; |
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|
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case 0x20: /* GPIO_WAKEUPENABLE */ |
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case 0x80: /* GPIO_CLEARWKUENA */ |
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case 0x84: /* GPIO_SETWKUENA */ |
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return s->wumask;
|
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|
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case 0x28: /* GPIO_IRQSTATUS2 */ |
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return s->ints[1]; |
| 334 |
|
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case 0x2c: /* GPIO_IRQENABLE2 */ |
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case 0x70: /* GPIO_CLEARIRQENABLE2 */ |
| 337 |
case 0x74: /* GPIO_SETIREQNEABLE2 */ |
| 338 |
return s->mask[1]; |
| 339 |
|
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case 0x30: /* GPIO_CTRL */ |
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return s->config[1]; |
| 342 |
|
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case 0x34: /* GPIO_OE */ |
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return s->dir;
|
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|
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case 0x38: /* GPIO_DATAIN */ |
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return s->inputs;
|
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|
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case 0x3c: /* GPIO_DATAOUT */ |
| 350 |
case 0x90: /* GPIO_CLEARDATAOUT */ |
| 351 |
case 0x94: /* GPIO_SETDATAOUT */ |
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return s->outputs;
|
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|
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case 0x40: /* GPIO_LEVELDETECT0 */ |
| 355 |
return s->level[0]; |
| 356 |
|
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case 0x44: /* GPIO_LEVELDETECT1 */ |
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return s->level[1]; |
| 359 |
|
| 360 |
case 0x48: /* GPIO_RISINGDETECT */ |
| 361 |
return s->edge[0]; |
| 362 |
|
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case 0x4c: /* GPIO_FALLINGDETECT */ |
| 364 |
return s->edge[1]; |
| 365 |
|
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case 0x50: /* GPIO_DEBOUNCENABLE */ |
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return s->debounce;
|
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|
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case 0x54: /* GPIO_DEBOUNCINGTIME */ |
| 370 |
return s->delay;
|
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} |
| 372 |
|
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OMAP_BAD_REG(addr); |
| 374 |
return 0; |
| 375 |
} |
| 376 |
|
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static void omap2_gpio_module_write(void *opaque, target_phys_addr_t addr, |
| 378 |
uint32_t value) |
| 379 |
{
|
| 380 |
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; |
| 381 |
uint32_t diff; |
| 382 |
int ln;
|
| 383 |
|
| 384 |
switch (addr) {
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case 0x00: /* GPIO_REVISION */ |
| 386 |
case 0x14: /* GPIO_SYSSTATUS */ |
| 387 |
case 0x38: /* GPIO_DATAIN */ |
| 388 |
OMAP_RO_REG(addr); |
| 389 |
break;
|
| 390 |
|
| 391 |
case 0x10: /* GPIO_SYSCONFIG */ |
| 392 |
if (((value >> 3) & 3) == 3) |
| 393 |
fprintf(stderr, "%s: bad IDLEMODE value\n", __FUNCTION__);
|
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if (value & 2) |
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omap2_gpio_module_reset(s); |
| 396 |
s->config[0] = value & 0x1d; |
| 397 |
break;
|
| 398 |
|
| 399 |
case 0x18: /* GPIO_IRQSTATUS1 */ |
| 400 |
if (s->ints[0] & value) { |
| 401 |
s->ints[0] &= ~value;
|
| 402 |
omap2_gpio_module_level_update(s, 0);
|
| 403 |
} |
| 404 |
break;
|
| 405 |
|
| 406 |
case 0x1c: /* GPIO_IRQENABLE1 */ |
| 407 |
s->mask[0] = value;
|
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omap2_gpio_module_int_update(s, 0);
|
| 409 |
break;
|
| 410 |
|
| 411 |
case 0x20: /* GPIO_WAKEUPENABLE */ |
| 412 |
s->wumask = value; |
| 413 |
break;
|
| 414 |
|
| 415 |
case 0x28: /* GPIO_IRQSTATUS2 */ |
| 416 |
if (s->ints[1] & value) { |
| 417 |
s->ints[1] &= ~value;
|
| 418 |
omap2_gpio_module_level_update(s, 1);
|
| 419 |
} |
| 420 |
break;
|
| 421 |
|
| 422 |
case 0x2c: /* GPIO_IRQENABLE2 */ |
| 423 |
s->mask[1] = value;
|
| 424 |
omap2_gpio_module_int_update(s, 1);
|
| 425 |
break;
|
| 426 |
|
| 427 |
case 0x30: /* GPIO_CTRL */ |
| 428 |
s->config[1] = value & 7; |
| 429 |
break;
|
| 430 |
|
| 431 |
case 0x34: /* GPIO_OE */ |
| 432 |
diff = s->outputs & (s->dir ^ value); |
| 433 |
s->dir = value; |
| 434 |
|
| 435 |
value = s->outputs & ~s->dir; |
| 436 |
while ((ln = ffs(diff))) {
|
| 437 |
diff &= ~(1 <<-- ln);
|
| 438 |
qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
| 439 |
} |
| 440 |
|
| 441 |
omap2_gpio_module_level_update(s, 0);
|
| 442 |
omap2_gpio_module_level_update(s, 1);
|
| 443 |
break;
|
| 444 |
|
| 445 |
case 0x3c: /* GPIO_DATAOUT */ |
| 446 |
omap2_gpio_module_out_update(s, s->outputs ^ value); |
| 447 |
break;
|
| 448 |
|
| 449 |
case 0x40: /* GPIO_LEVELDETECT0 */ |
| 450 |
s->level[0] = value;
|
| 451 |
omap2_gpio_module_level_update(s, 0);
|
| 452 |
omap2_gpio_module_level_update(s, 1);
|
| 453 |
break;
|
| 454 |
|
| 455 |
case 0x44: /* GPIO_LEVELDETECT1 */ |
| 456 |
s->level[1] = value;
|
| 457 |
omap2_gpio_module_level_update(s, 0);
|
| 458 |
omap2_gpio_module_level_update(s, 1);
|
| 459 |
break;
|
| 460 |
|
| 461 |
case 0x48: /* GPIO_RISINGDETECT */ |
| 462 |
s->edge[0] = value;
|
| 463 |
break;
|
| 464 |
|
| 465 |
case 0x4c: /* GPIO_FALLINGDETECT */ |
| 466 |
s->edge[1] = value;
|
| 467 |
break;
|
| 468 |
|
| 469 |
case 0x50: /* GPIO_DEBOUNCENABLE */ |
| 470 |
s->debounce = value; |
| 471 |
break;
|
| 472 |
|
| 473 |
case 0x54: /* GPIO_DEBOUNCINGTIME */ |
| 474 |
s->delay = value; |
| 475 |
break;
|
| 476 |
|
| 477 |
case 0x60: /* GPIO_CLEARIRQENABLE1 */ |
| 478 |
s->mask[0] &= ~value;
|
| 479 |
omap2_gpio_module_int_update(s, 0);
|
| 480 |
break;
|
| 481 |
|
| 482 |
case 0x64: /* GPIO_SETIRQENABLE1 */ |
| 483 |
s->mask[0] |= value;
|
| 484 |
omap2_gpio_module_int_update(s, 0);
|
| 485 |
break;
|
| 486 |
|
| 487 |
case 0x70: /* GPIO_CLEARIRQENABLE2 */ |
| 488 |
s->mask[1] &= ~value;
|
| 489 |
omap2_gpio_module_int_update(s, 1);
|
| 490 |
break;
|
| 491 |
|
| 492 |
case 0x74: /* GPIO_SETIREQNEABLE2 */ |
| 493 |
s->mask[1] |= value;
|
| 494 |
omap2_gpio_module_int_update(s, 1);
|
| 495 |
break;
|
| 496 |
|
| 497 |
case 0x80: /* GPIO_CLEARWKUENA */ |
| 498 |
s->wumask &= ~value; |
| 499 |
break;
|
| 500 |
|
| 501 |
case 0x84: /* GPIO_SETWKUENA */ |
| 502 |
s->wumask |= value; |
| 503 |
break;
|
| 504 |
|
| 505 |
case 0x90: /* GPIO_CLEARDATAOUT */ |
| 506 |
omap2_gpio_module_out_update(s, s->outputs & value); |
| 507 |
break;
|
| 508 |
|
| 509 |
case 0x94: /* GPIO_SETDATAOUT */ |
| 510 |
omap2_gpio_module_out_update(s, ~s->outputs & value); |
| 511 |
break;
|
| 512 |
|
| 513 |
default:
|
| 514 |
OMAP_BAD_REG(addr); |
| 515 |
return;
|
| 516 |
} |
| 517 |
} |
| 518 |
|
| 519 |
static uint32_t omap2_gpio_module_readp(void *opaque, target_phys_addr_t addr) |
| 520 |
{
|
| 521 |
return omap2_gpio_module_readp(opaque, addr) >> ((addr & 3) << 3); |
| 522 |
} |
| 523 |
|
| 524 |
static void omap2_gpio_module_writep(void *opaque, target_phys_addr_t addr, |
| 525 |
uint32_t value) |
| 526 |
{
|
| 527 |
uint32_t cur = 0;
|
| 528 |
uint32_t mask = 0xffff;
|
| 529 |
|
| 530 |
switch (addr & ~3) { |
| 531 |
case 0x00: /* GPIO_REVISION */ |
| 532 |
case 0x14: /* GPIO_SYSSTATUS */ |
| 533 |
case 0x38: /* GPIO_DATAIN */ |
| 534 |
OMAP_RO_REG(addr); |
| 535 |
break;
|
| 536 |
|
| 537 |
case 0x10: /* GPIO_SYSCONFIG */ |
| 538 |
case 0x1c: /* GPIO_IRQENABLE1 */ |
| 539 |
case 0x20: /* GPIO_WAKEUPENABLE */ |
| 540 |
case 0x2c: /* GPIO_IRQENABLE2 */ |
| 541 |
case 0x30: /* GPIO_CTRL */ |
| 542 |
case 0x34: /* GPIO_OE */ |
| 543 |
case 0x3c: /* GPIO_DATAOUT */ |
| 544 |
case 0x40: /* GPIO_LEVELDETECT0 */ |
| 545 |
case 0x44: /* GPIO_LEVELDETECT1 */ |
| 546 |
case 0x48: /* GPIO_RISINGDETECT */ |
| 547 |
case 0x4c: /* GPIO_FALLINGDETECT */ |
| 548 |
case 0x50: /* GPIO_DEBOUNCENABLE */ |
| 549 |
case 0x54: /* GPIO_DEBOUNCINGTIME */ |
| 550 |
cur = omap2_gpio_module_read(opaque, addr & ~3) &
|
| 551 |
~(mask << ((addr & 3) << 3)); |
| 552 |
|
| 553 |
/* Fall through. */
|
| 554 |
case 0x18: /* GPIO_IRQSTATUS1 */ |
| 555 |
case 0x28: /* GPIO_IRQSTATUS2 */ |
| 556 |
case 0x60: /* GPIO_CLEARIRQENABLE1 */ |
| 557 |
case 0x64: /* GPIO_SETIRQENABLE1 */ |
| 558 |
case 0x70: /* GPIO_CLEARIRQENABLE2 */ |
| 559 |
case 0x74: /* GPIO_SETIREQNEABLE2 */ |
| 560 |
case 0x80: /* GPIO_CLEARWKUENA */ |
| 561 |
case 0x84: /* GPIO_SETWKUENA */ |
| 562 |
case 0x90: /* GPIO_CLEARDATAOUT */ |
| 563 |
case 0x94: /* GPIO_SETDATAOUT */ |
| 564 |
value <<= (addr & 3) << 3; |
| 565 |
omap2_gpio_module_write(opaque, addr, cur | value); |
| 566 |
break;
|
| 567 |
|
| 568 |
default:
|
| 569 |
OMAP_BAD_REG(addr); |
| 570 |
return;
|
| 571 |
} |
| 572 |
} |
| 573 |
|
| 574 |
static CPUReadMemoryFunc * const omap2_gpio_module_readfn[] = { |
| 575 |
omap2_gpio_module_readp, |
| 576 |
omap2_gpio_module_readp, |
| 577 |
omap2_gpio_module_read, |
| 578 |
}; |
| 579 |
|
| 580 |
static CPUWriteMemoryFunc * const omap2_gpio_module_writefn[] = { |
| 581 |
omap2_gpio_module_writep, |
| 582 |
omap2_gpio_module_writep, |
| 583 |
omap2_gpio_module_write, |
| 584 |
}; |
| 585 |
|
| 586 |
static void omap2_gpio_module_init(struct omap2_gpio_s *s, |
| 587 |
struct omap_target_agent_s *ta, int region, |
| 588 |
qemu_irq mpu, qemu_irq dsp, qemu_irq wkup, |
| 589 |
omap_clk fclk, omap_clk iclk) |
| 590 |
{
|
| 591 |
int iomemtype;
|
| 592 |
|
| 593 |
s->irq[0] = mpu;
|
| 594 |
s->irq[1] = dsp;
|
| 595 |
s->wkup = wkup; |
| 596 |
s->in = qemu_allocate_irqs(omap2_gpio_module_set, s, 32);
|
| 597 |
|
| 598 |
iomemtype = l4_register_io_memory(omap2_gpio_module_readfn, |
| 599 |
omap2_gpio_module_writefn, s); |
| 600 |
omap_l4_attach(ta, region, iomemtype); |
| 601 |
} |
| 602 |
|
| 603 |
struct omap_gpif_s {
|
| 604 |
struct omap2_gpio_s module[5]; |
| 605 |
int modules;
|
| 606 |
|
| 607 |
int autoidle;
|
| 608 |
int gpo;
|
| 609 |
}; |
| 610 |
|
| 611 |
void omap_gpif_reset(struct omap_gpif_s *s) |
| 612 |
{
|
| 613 |
int i;
|
| 614 |
|
| 615 |
for (i = 0; i < s->modules; i ++) |
| 616 |
omap2_gpio_module_reset(s->module + i); |
| 617 |
|
| 618 |
s->autoidle = 0;
|
| 619 |
s->gpo = 0;
|
| 620 |
} |
| 621 |
|
| 622 |
static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr) |
| 623 |
{
|
| 624 |
struct omap_gpif_s *s = (struct omap_gpif_s *) opaque; |
| 625 |
|
| 626 |
switch (addr) {
|
| 627 |
case 0x00: /* IPGENERICOCPSPL_REVISION */ |
| 628 |
return 0x18; |
| 629 |
|
| 630 |
case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ |
| 631 |
return s->autoidle;
|
| 632 |
|
| 633 |
case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ |
| 634 |
return 0x01; |
| 635 |
|
| 636 |
case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ |
| 637 |
return 0x00; |
| 638 |
|
| 639 |
case 0x40: /* IPGENERICOCPSPL_GPO */ |
| 640 |
return s->gpo;
|
| 641 |
|
| 642 |
case 0x50: /* IPGENERICOCPSPL_GPI */ |
| 643 |
return 0x00; |
| 644 |
} |
| 645 |
|
| 646 |
OMAP_BAD_REG(addr); |
| 647 |
return 0; |
| 648 |
} |
| 649 |
|
| 650 |
static void omap_gpif_top_write(void *opaque, target_phys_addr_t addr, |
| 651 |
uint32_t value) |
| 652 |
{
|
| 653 |
struct omap_gpif_s *s = (struct omap_gpif_s *) opaque; |
| 654 |
|
| 655 |
switch (addr) {
|
| 656 |
case 0x00: /* IPGENERICOCPSPL_REVISION */ |
| 657 |
case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ |
| 658 |
case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ |
| 659 |
case 0x50: /* IPGENERICOCPSPL_GPI */ |
| 660 |
OMAP_RO_REG(addr); |
| 661 |
break;
|
| 662 |
|
| 663 |
case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ |
| 664 |
if (value & (1 << 1)) /* SOFTRESET */ |
| 665 |
omap_gpif_reset(s); |
| 666 |
s->autoidle = value & 1;
|
| 667 |
break;
|
| 668 |
|
| 669 |
case 0x40: /* IPGENERICOCPSPL_GPO */ |
| 670 |
s->gpo = value & 1;
|
| 671 |
break;
|
| 672 |
|
| 673 |
default:
|
| 674 |
OMAP_BAD_REG(addr); |
| 675 |
return;
|
| 676 |
} |
| 677 |
} |
| 678 |
|
| 679 |
static CPUReadMemoryFunc * const omap_gpif_top_readfn[] = { |
| 680 |
omap_gpif_top_read, |
| 681 |
omap_gpif_top_read, |
| 682 |
omap_gpif_top_read, |
| 683 |
}; |
| 684 |
|
| 685 |
static CPUWriteMemoryFunc * const omap_gpif_top_writefn[] = { |
| 686 |
omap_gpif_top_write, |
| 687 |
omap_gpif_top_write, |
| 688 |
omap_gpif_top_write, |
| 689 |
}; |
| 690 |
|
| 691 |
struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta, |
| 692 |
qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules)
|
| 693 |
{
|
| 694 |
int iomemtype, i;
|
| 695 |
struct omap_gpif_s *s = (struct omap_gpif_s *) |
| 696 |
qemu_mallocz(sizeof(struct omap_gpif_s)); |
| 697 |
int region[4] = { 0, 2, 4, 5 }; |
| 698 |
|
| 699 |
s->modules = modules; |
| 700 |
for (i = 0; i < modules; i ++) |
| 701 |
omap2_gpio_module_init(s->module + i, ta, region[i], |
| 702 |
irq[i], NULL, NULL, fclk[i], iclk); |
| 703 |
|
| 704 |
omap_gpif_reset(s); |
| 705 |
|
| 706 |
iomemtype = l4_register_io_memory(omap_gpif_top_readfn, |
| 707 |
omap_gpif_top_writefn, s); |
| 708 |
omap_l4_attach(ta, 1, iomemtype);
|
| 709 |
|
| 710 |
return s;
|
| 711 |
} |
| 712 |
|
| 713 |
qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start) |
| 714 |
{
|
| 715 |
if (start >= s->modules * 32 || start < 0) |
| 716 |
hw_error("%s: No GPIO line %i\n", __FUNCTION__, start);
|
| 717 |
return s->module[start >> 5].in + (start & 31); |
| 718 |
} |
| 719 |
|
| 720 |
void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler) |
| 721 |
{
|
| 722 |
if (line >= s->modules * 32 || line < 0) |
| 723 |
hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
|
| 724 |
s->module[line >> 5].handler[line & 31] = handler; |
| 725 |
} |