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1 | 7e7c5e4c | balrog | /*
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2 | 7e7c5e4c | balrog | * OneNAND flash memories emulation.
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3 | 7e7c5e4c | balrog | *
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4 | 7e7c5e4c | balrog | * Copyright (C) 2008 Nokia Corporation
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5 | 7e7c5e4c | balrog | * Written by Andrzej Zaborowski <andrew@openedhand.com>
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6 | 7e7c5e4c | balrog | *
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7 | 7e7c5e4c | balrog | * This program is free software; you can redistribute it and/or
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8 | 7e7c5e4c | balrog | * modify it under the terms of the GNU General Public License as
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9 | 7e7c5e4c | balrog | * published by the Free Software Foundation; either version 2 or
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10 | 7e7c5e4c | balrog | * (at your option) version 3 of the License.
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11 | 7e7c5e4c | balrog | *
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12 | 7e7c5e4c | balrog | * This program is distributed in the hope that it will be useful,
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13 | 7e7c5e4c | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 7e7c5e4c | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | 7e7c5e4c | balrog | * GNU General Public License for more details.
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16 | 7e7c5e4c | balrog | *
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17 | 7e7c5e4c | balrog | * You should have received a copy of the GNU General Public License
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18 | 7e7c5e4c | balrog | * along with this program; if not, write to the Free Software
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19 | 7e7c5e4c | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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20 | 7e7c5e4c | balrog | * MA 02111-1307 USA
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21 | 7e7c5e4c | balrog | */
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22 | 7e7c5e4c | balrog | |
23 | 7e7c5e4c | balrog | #include "qemu-common.h" |
24 | 7e7c5e4c | balrog | #include "flash.h" |
25 | 7e7c5e4c | balrog | #include "irq.h" |
26 | 7e7c5e4c | balrog | #include "sysemu.h" |
27 | 7e7c5e4c | balrog | #include "block.h" |
28 | 7e7c5e4c | balrog | |
29 | 7e7c5e4c | balrog | /* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
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30 | 7e7c5e4c | balrog | #define PAGE_SHIFT 11 |
31 | 7e7c5e4c | balrog | |
32 | 7e7c5e4c | balrog | /* Fixed */
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33 | 7e7c5e4c | balrog | #define BLOCK_SHIFT (PAGE_SHIFT + 6) |
34 | 7e7c5e4c | balrog | |
35 | 7e7c5e4c | balrog | struct onenand_s {
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36 | 7e7c5e4c | balrog | uint32_t id; |
37 | 7e7c5e4c | balrog | int shift;
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38 | 7e7c5e4c | balrog | target_phys_addr_t base; |
39 | 7e7c5e4c | balrog | qemu_irq intr; |
40 | 7e7c5e4c | balrog | qemu_irq rdy; |
41 | 7e7c5e4c | balrog | BlockDriverState *bdrv; |
42 | 7e7c5e4c | balrog | BlockDriverState *bdrv_cur; |
43 | 7e7c5e4c | balrog | uint8_t *image; |
44 | 7e7c5e4c | balrog | uint8_t *otp; |
45 | 7e7c5e4c | balrog | uint8_t *current; |
46 | 7e7c5e4c | balrog | ram_addr_t ram; |
47 | 7e7c5e4c | balrog | uint8_t *boot[2];
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48 | 7e7c5e4c | balrog | uint8_t *data[2][2]; |
49 | 7e7c5e4c | balrog | int iomemtype;
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50 | 7e7c5e4c | balrog | int cycle;
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51 | 7e7c5e4c | balrog | int otpmode;
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52 | 7e7c5e4c | balrog | |
53 | 7e7c5e4c | balrog | uint16_t addr[8];
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54 | 7e7c5e4c | balrog | uint16_t unladdr[8];
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55 | 7e7c5e4c | balrog | int bufaddr;
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56 | 7e7c5e4c | balrog | int count;
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57 | 7e7c5e4c | balrog | uint16_t command; |
58 | 7e7c5e4c | balrog | uint16_t config[2];
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59 | 7e7c5e4c | balrog | uint16_t status; |
60 | 7e7c5e4c | balrog | uint16_t intstatus; |
61 | 7e7c5e4c | balrog | uint16_t wpstatus; |
62 | 7e7c5e4c | balrog | |
63 | 7e7c5e4c | balrog | struct ecc_state_s ecc;
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64 | 7e7c5e4c | balrog | |
65 | 7e7c5e4c | balrog | int density_mask;
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66 | 7e7c5e4c | balrog | int secs;
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67 | 7e7c5e4c | balrog | int secs_cur;
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68 | 7e7c5e4c | balrog | int blocks;
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69 | 7e7c5e4c | balrog | uint8_t *blockwp; |
70 | 7e7c5e4c | balrog | }; |
71 | 7e7c5e4c | balrog | |
72 | 7e7c5e4c | balrog | enum {
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73 | 7e7c5e4c | balrog | ONEN_BUF_BLOCK = 0,
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74 | 7e7c5e4c | balrog | ONEN_BUF_BLOCK2 = 1,
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75 | 7e7c5e4c | balrog | ONEN_BUF_DEST_BLOCK = 2,
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76 | 7e7c5e4c | balrog | ONEN_BUF_DEST_PAGE = 3,
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77 | 7e7c5e4c | balrog | ONEN_BUF_PAGE = 7,
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78 | 7e7c5e4c | balrog | }; |
79 | 7e7c5e4c | balrog | |
80 | 7e7c5e4c | balrog | enum {
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81 | 7e7c5e4c | balrog | ONEN_ERR_CMD = 1 << 10, |
82 | 7e7c5e4c | balrog | ONEN_ERR_ERASE = 1 << 11, |
83 | 7e7c5e4c | balrog | ONEN_ERR_PROG = 1 << 12, |
84 | 7e7c5e4c | balrog | ONEN_ERR_LOAD = 1 << 13, |
85 | 7e7c5e4c | balrog | }; |
86 | 7e7c5e4c | balrog | |
87 | 7e7c5e4c | balrog | enum {
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88 | 7e7c5e4c | balrog | ONEN_INT_RESET = 1 << 4, |
89 | 7e7c5e4c | balrog | ONEN_INT_ERASE = 1 << 5, |
90 | 7e7c5e4c | balrog | ONEN_INT_PROG = 1 << 6, |
91 | 7e7c5e4c | balrog | ONEN_INT_LOAD = 1 << 7, |
92 | 7e7c5e4c | balrog | ONEN_INT = 1 << 15, |
93 | 7e7c5e4c | balrog | }; |
94 | 7e7c5e4c | balrog | |
95 | 7e7c5e4c | balrog | enum {
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96 | 7e7c5e4c | balrog | ONEN_LOCK_LOCKTIGHTEN = 1 << 0, |
97 | 7e7c5e4c | balrog | ONEN_LOCK_LOCKED = 1 << 1, |
98 | 7e7c5e4c | balrog | ONEN_LOCK_UNLOCKED = 1 << 2, |
99 | 7e7c5e4c | balrog | }; |
100 | 7e7c5e4c | balrog | |
101 | 7e7c5e4c | balrog | void onenand_base_update(void *opaque, target_phys_addr_t new) |
102 | 7e7c5e4c | balrog | { |
103 | 7e7c5e4c | balrog | struct onenand_s *s = (struct onenand_s *) opaque; |
104 | 7e7c5e4c | balrog | |
105 | 7e7c5e4c | balrog | s->base = new; |
106 | 7e7c5e4c | balrog | |
107 | 7e7c5e4c | balrog | /* XXX: We should use IO_MEM_ROMD but we broke it earlier...
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108 | 7e7c5e4c | balrog | * Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
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109 | 7e7c5e4c | balrog | * write boot commands. Also take note of the BWPS bit. */
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110 | 7e7c5e4c | balrog | cpu_register_physical_memory(s->base + (0x0000 << s->shift),
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111 | 7e7c5e4c | balrog | 0x0200 << s->shift, s->iomemtype);
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112 | 7e7c5e4c | balrog | cpu_register_physical_memory(s->base + (0x0200 << s->shift),
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113 | 7e7c5e4c | balrog | 0xbe00 << s->shift,
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114 | 7e7c5e4c | balrog | (s->ram +(0x0200 << s->shift)) | IO_MEM_RAM);
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115 | 7e7c5e4c | balrog | if (s->iomemtype)
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116 | 7e7c5e4c | balrog | cpu_register_physical_memory(s->base + (0xc000 << s->shift),
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117 | 7e7c5e4c | balrog | 0x4000 << s->shift, s->iomemtype);
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118 | 7e7c5e4c | balrog | } |
119 | 7e7c5e4c | balrog | |
120 | 7e7c5e4c | balrog | void onenand_base_unmap(void *opaque) |
121 | 7e7c5e4c | balrog | { |
122 | 7e7c5e4c | balrog | struct onenand_s *s = (struct onenand_s *) opaque; |
123 | 7e7c5e4c | balrog | |
124 | 7e7c5e4c | balrog | cpu_register_physical_memory(s->base, |
125 | 7e7c5e4c | balrog | 0x10000 << s->shift, IO_MEM_UNASSIGNED);
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126 | 7e7c5e4c | balrog | } |
127 | 7e7c5e4c | balrog | |
128 | 7e7c5e4c | balrog | static void onenand_intr_update(struct onenand_s *s) |
129 | 7e7c5e4c | balrog | { |
130 | 7e7c5e4c | balrog | qemu_set_irq(s->intr, ((s->intstatus >> 15) ^ (~s->config[0] >> 6)) & 1); |
131 | 7e7c5e4c | balrog | } |
132 | 7e7c5e4c | balrog | |
133 | 7e7c5e4c | balrog | /* Hot reset (Reset OneNAND command) or warm reset (RP pin low) */
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134 | 7e7c5e4c | balrog | static void onenand_reset(struct onenand_s *s, int cold) |
135 | 7e7c5e4c | balrog | { |
136 | 7e7c5e4c | balrog | memset(&s->addr, 0, sizeof(s->addr)); |
137 | 7e7c5e4c | balrog | s->command = 0;
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138 | 7e7c5e4c | balrog | s->count = 1;
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139 | 7e7c5e4c | balrog | s->bufaddr = 0;
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140 | 7e7c5e4c | balrog | s->config[0] = 0x40c0; |
141 | 7e7c5e4c | balrog | s->config[1] = 0x0000; |
142 | 7e7c5e4c | balrog | onenand_intr_update(s); |
143 | 7e7c5e4c | balrog | qemu_irq_raise(s->rdy); |
144 | 7e7c5e4c | balrog | s->status = 0x0000;
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145 | 7e7c5e4c | balrog | s->intstatus = cold ? 0x8080 : 0x8010; |
146 | 7e7c5e4c | balrog | s->unladdr[0] = 0; |
147 | 7e7c5e4c | balrog | s->unladdr[1] = 0; |
148 | 7e7c5e4c | balrog | s->wpstatus = 0x0002;
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149 | 7e7c5e4c | balrog | s->cycle = 0;
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150 | 7e7c5e4c | balrog | s->otpmode = 0;
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151 | 7e7c5e4c | balrog | s->bdrv_cur = s->bdrv; |
152 | 7e7c5e4c | balrog | s->current = s->image; |
153 | 7e7c5e4c | balrog | s->secs_cur = s->secs; |
154 | 7e7c5e4c | balrog | |
155 | 7e7c5e4c | balrog | if (cold) {
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156 | 7e7c5e4c | balrog | /* Lock the whole flash */
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157 | 7e7c5e4c | balrog | memset(s->blockwp, ONEN_LOCK_LOCKED, s->blocks); |
158 | 7e7c5e4c | balrog | |
159 | 7e7c5e4c | balrog | if (s->bdrv && bdrv_read(s->bdrv, 0, s->boot[0], 8) < 0) |
160 | 7e7c5e4c | balrog | cpu_abort(cpu_single_env, "%s: Loading the BootRAM failed.\n",
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161 | 7e7c5e4c | balrog | __FUNCTION__); |
162 | 7e7c5e4c | balrog | } |
163 | 7e7c5e4c | balrog | } |
164 | 7e7c5e4c | balrog | |
165 | 7e7c5e4c | balrog | static inline int onenand_load_main(struct onenand_s *s, int sec, int secn, |
166 | 7e7c5e4c | balrog | void *dest)
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167 | 7e7c5e4c | balrog | { |
168 | 7e7c5e4c | balrog | if (s->bdrv_cur)
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169 | 7e7c5e4c | balrog | return bdrv_read(s->bdrv_cur, sec, dest, secn) < 0; |
170 | 7e7c5e4c | balrog | else if (sec + secn > s->secs_cur) |
171 | 7e7c5e4c | balrog | return 1; |
172 | 7e7c5e4c | balrog | |
173 | 7e7c5e4c | balrog | memcpy(dest, s->current + (sec << 9), secn << 9); |
174 | 7e7c5e4c | balrog | |
175 | 7e7c5e4c | balrog | return 0; |
176 | 7e7c5e4c | balrog | } |
177 | 7e7c5e4c | balrog | |
178 | 7e7c5e4c | balrog | static inline int onenand_prog_main(struct onenand_s *s, int sec, int secn, |
179 | 7e7c5e4c | balrog | void *src)
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180 | 7e7c5e4c | balrog | { |
181 | 7e7c5e4c | balrog | if (s->bdrv_cur)
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182 | 7e7c5e4c | balrog | return bdrv_write(s->bdrv_cur, sec, src, secn) < 0; |
183 | 7e7c5e4c | balrog | else if (sec + secn > s->secs_cur) |
184 | 7e7c5e4c | balrog | return 1; |
185 | 7e7c5e4c | balrog | |
186 | 7e7c5e4c | balrog | memcpy(s->current + (sec << 9), src, secn << 9); |
187 | 7e7c5e4c | balrog | |
188 | 7e7c5e4c | balrog | return 0; |
189 | 7e7c5e4c | balrog | } |
190 | 7e7c5e4c | balrog | |
191 | 7e7c5e4c | balrog | static inline int onenand_load_spare(struct onenand_s *s, int sec, int secn, |
192 | 7e7c5e4c | balrog | void *dest)
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193 | 7e7c5e4c | balrog | { |
194 | 7e7c5e4c | balrog | uint8_t buf[512];
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195 | 7e7c5e4c | balrog | |
196 | 7e7c5e4c | balrog | if (s->bdrv_cur) {
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197 | 7e7c5e4c | balrog | if (bdrv_read(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0) |
198 | 7e7c5e4c | balrog | return 1; |
199 | 7e7c5e4c | balrog | memcpy(dest, buf + ((sec & 31) << 4), secn << 4); |
200 | 7e7c5e4c | balrog | } else if (sec + secn > s->secs_cur) |
201 | 7e7c5e4c | balrog | return 1; |
202 | 7e7c5e4c | balrog | else
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203 | 7e7c5e4c | balrog | memcpy(dest, s->current + (s->secs_cur << 9) + (sec << 4), secn << 4); |
204 | 7e7c5e4c | balrog | |
205 | 7e7c5e4c | balrog | return 0; |
206 | 7e7c5e4c | balrog | } |
207 | 7e7c5e4c | balrog | |
208 | 7e7c5e4c | balrog | static inline int onenand_prog_spare(struct onenand_s *s, int sec, int secn, |
209 | 7e7c5e4c | balrog | void *src)
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210 | 7e7c5e4c | balrog | { |
211 | 7e7c5e4c | balrog | uint8_t buf[512];
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212 | 7e7c5e4c | balrog | |
213 | 7e7c5e4c | balrog | if (s->bdrv_cur) {
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214 | 7e7c5e4c | balrog | if (bdrv_read(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0) |
215 | 7e7c5e4c | balrog | return 1; |
216 | 7e7c5e4c | balrog | memcpy(buf + ((sec & 31) << 4), src, secn << 4); |
217 | 7e7c5e4c | balrog | return bdrv_write(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0; |
218 | 7e7c5e4c | balrog | } else if (sec + secn > s->secs_cur) |
219 | 7e7c5e4c | balrog | return 1; |
220 | 7e7c5e4c | balrog | |
221 | 7e7c5e4c | balrog | memcpy(s->current + (s->secs_cur << 9) + (sec << 4), src, secn << 4); |
222 | 7e7c5e4c | balrog | |
223 | 7e7c5e4c | balrog | return 0; |
224 | 7e7c5e4c | balrog | } |
225 | 7e7c5e4c | balrog | |
226 | 7e7c5e4c | balrog | static inline int onenand_erase(struct onenand_s *s, int sec, int num) |
227 | 7e7c5e4c | balrog | { |
228 | 7e7c5e4c | balrog | /* TODO: optimise */
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229 | 7e7c5e4c | balrog | uint8_t buf[512];
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230 | 7e7c5e4c | balrog | |
231 | 7e7c5e4c | balrog | memset(buf, 0xff, sizeof(buf)); |
232 | 7e7c5e4c | balrog | for (; num > 0; num --, sec ++) { |
233 | 7e7c5e4c | balrog | if (onenand_prog_main(s, sec, 1, buf)) |
234 | 7e7c5e4c | balrog | return 1; |
235 | 7e7c5e4c | balrog | if (onenand_prog_spare(s, sec, 1, buf)) |
236 | 7e7c5e4c | balrog | return 1; |
237 | 7e7c5e4c | balrog | } |
238 | 7e7c5e4c | balrog | |
239 | 7e7c5e4c | balrog | return 0; |
240 | 7e7c5e4c | balrog | } |
241 | 7e7c5e4c | balrog | |
242 | 7e7c5e4c | balrog | static void onenand_command(struct onenand_s *s, int cmd) |
243 | 7e7c5e4c | balrog | { |
244 | 7e7c5e4c | balrog | int b;
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245 | 7e7c5e4c | balrog | int sec;
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246 | 7e7c5e4c | balrog | void *buf;
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247 | 7e7c5e4c | balrog | #define SETADDR(block, page) \
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248 | 7e7c5e4c | balrog | sec = (s->addr[page] & 3) + \
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249 | 7e7c5e4c | balrog | ((((s->addr[page] >> 2) & 0x3f) + \ |
250 | 7e7c5e4c | balrog | (((s->addr[block] & 0xfff) | \
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251 | 7e7c5e4c | balrog | (s->addr[block] >> 15 ? \
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252 | 7e7c5e4c | balrog | s->density_mask : 0)) << 6)) << (PAGE_SHIFT - 9)); |
253 | 7e7c5e4c | balrog | #define SETBUF_M() \
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254 | 7e7c5e4c | balrog | buf = (s->bufaddr & 8) ? \
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255 | 7e7c5e4c | balrog | s->data[(s->bufaddr >> 2) & 1][0] : s->boot[0]; \ |
256 | 7e7c5e4c | balrog | buf += (s->bufaddr & 3) << 9; |
257 | 7e7c5e4c | balrog | #define SETBUF_S() \
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258 | 7e7c5e4c | balrog | buf = (s->bufaddr & 8) ? \
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259 | 7e7c5e4c | balrog | s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \ |
260 | 7e7c5e4c | balrog | buf += (s->bufaddr & 3) << 4; |
261 | 7e7c5e4c | balrog | |
262 | 7e7c5e4c | balrog | switch (cmd) {
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263 | 7e7c5e4c | balrog | case 0x00: /* Load single/multiple sector data unit into buffer */ |
264 | 7e7c5e4c | balrog | SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
265 | 7e7c5e4c | balrog | |
266 | 7e7c5e4c | balrog | SETBUF_M() |
267 | 7e7c5e4c | balrog | if (onenand_load_main(s, sec, s->count, buf))
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268 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD; |
269 | 7e7c5e4c | balrog | |
270 | 7e7c5e4c | balrog | #if 0
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271 | 7e7c5e4c | balrog | SETBUF_S()
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272 | 7e7c5e4c | balrog | if (onenand_load_spare(s, sec, s->count, buf))
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273 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD;
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274 | 7e7c5e4c | balrog | #endif
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275 | 7e7c5e4c | balrog | |
276 | 7e7c5e4c | balrog | /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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277 | 7e7c5e4c | balrog | * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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278 | 7e7c5e4c | balrog | * then we need two split the read/write into two chunks.
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279 | 7e7c5e4c | balrog | */
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280 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT | ONEN_INT_LOAD; |
281 | 7e7c5e4c | balrog | break;
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282 | 7e7c5e4c | balrog | case 0x13: /* Load single/multiple spare sector into buffer */ |
283 | 7e7c5e4c | balrog | SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
284 | 7e7c5e4c | balrog | |
285 | 7e7c5e4c | balrog | SETBUF_S() |
286 | 7e7c5e4c | balrog | if (onenand_load_spare(s, sec, s->count, buf))
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287 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD; |
288 | 7e7c5e4c | balrog | |
289 | 7e7c5e4c | balrog | /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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290 | 7e7c5e4c | balrog | * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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291 | 7e7c5e4c | balrog | * then we need two split the read/write into two chunks.
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292 | 7e7c5e4c | balrog | */
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293 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT | ONEN_INT_LOAD; |
294 | 7e7c5e4c | balrog | break;
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295 | 7e7c5e4c | balrog | case 0x80: /* Program single/multiple sector data unit from buffer */ |
296 | 7e7c5e4c | balrog | SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
297 | 7e7c5e4c | balrog | |
298 | 7e7c5e4c | balrog | SETBUF_M() |
299 | 7e7c5e4c | balrog | if (onenand_prog_main(s, sec, s->count, buf))
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300 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
301 | 7e7c5e4c | balrog | |
302 | 7e7c5e4c | balrog | #if 0
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303 | 7e7c5e4c | balrog | SETBUF_S()
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304 | 7e7c5e4c | balrog | if (onenand_prog_spare(s, sec, s->count, buf))
|
305 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
|
306 | 7e7c5e4c | balrog | #endif
|
307 | 7e7c5e4c | balrog | |
308 | 7e7c5e4c | balrog | /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
|
309 | 7e7c5e4c | balrog | * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
|
310 | 7e7c5e4c | balrog | * then we need two split the read/write into two chunks.
|
311 | 7e7c5e4c | balrog | */
|
312 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
313 | 7e7c5e4c | balrog | break;
|
314 | 7e7c5e4c | balrog | case 0x1a: /* Program single/multiple spare area sector from buffer */ |
315 | 7e7c5e4c | balrog | SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
316 | 7e7c5e4c | balrog | |
317 | 7e7c5e4c | balrog | SETBUF_S() |
318 | 7e7c5e4c | balrog | if (onenand_prog_spare(s, sec, s->count, buf))
|
319 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
320 | 7e7c5e4c | balrog | |
321 | 7e7c5e4c | balrog | /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
|
322 | 7e7c5e4c | balrog | * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
|
323 | 7e7c5e4c | balrog | * then we need two split the read/write into two chunks.
|
324 | 7e7c5e4c | balrog | */
|
325 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
326 | 7e7c5e4c | balrog | break;
|
327 | 7e7c5e4c | balrog | case 0x1b: /* Copy-back program */ |
328 | 7e7c5e4c | balrog | SETBUF_S() |
329 | 7e7c5e4c | balrog | |
330 | 7e7c5e4c | balrog | SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
331 | 7e7c5e4c | balrog | if (onenand_load_main(s, sec, s->count, buf))
|
332 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
333 | 7e7c5e4c | balrog | |
334 | 7e7c5e4c | balrog | SETADDR(ONEN_BUF_DEST_BLOCK, ONEN_BUF_DEST_PAGE) |
335 | 7e7c5e4c | balrog | if (onenand_prog_main(s, sec, s->count, buf))
|
336 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
337 | 7e7c5e4c | balrog | |
338 | 7e7c5e4c | balrog | /* TODO: spare areas */
|
339 | 7e7c5e4c | balrog | |
340 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
341 | 7e7c5e4c | balrog | break;
|
342 | 7e7c5e4c | balrog | |
343 | 7e7c5e4c | balrog | case 0x23: /* Unlock NAND array block(s) */ |
344 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT; |
345 | 7e7c5e4c | balrog | |
346 | 7e7c5e4c | balrog | /* XXX the previous (?) area should be locked automatically */
|
347 | 7e7c5e4c | balrog | for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
348 | 7e7c5e4c | balrog | if (b >= s->blocks) {
|
349 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD; |
350 | 7e7c5e4c | balrog | break;
|
351 | 7e7c5e4c | balrog | } |
352 | 7e7c5e4c | balrog | if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
|
353 | 7e7c5e4c | balrog | break;
|
354 | 7e7c5e4c | balrog | |
355 | 7e7c5e4c | balrog | s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED; |
356 | 7e7c5e4c | balrog | } |
357 | 7e7c5e4c | balrog | break;
|
358 | 7e7c5e4c | balrog | case 0x2a: /* Lock NAND array block(s) */ |
359 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT; |
360 | 7e7c5e4c | balrog | |
361 | 7e7c5e4c | balrog | for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
362 | 7e7c5e4c | balrog | if (b >= s->blocks) {
|
363 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD; |
364 | 7e7c5e4c | balrog | break;
|
365 | 7e7c5e4c | balrog | } |
366 | 7e7c5e4c | balrog | if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
|
367 | 7e7c5e4c | balrog | break;
|
368 | 7e7c5e4c | balrog | |
369 | 7e7c5e4c | balrog | s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKED; |
370 | 7e7c5e4c | balrog | } |
371 | 7e7c5e4c | balrog | break;
|
372 | 7e7c5e4c | balrog | case 0x2c: /* Lock-tight NAND array block(s) */ |
373 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT; |
374 | 7e7c5e4c | balrog | |
375 | 7e7c5e4c | balrog | for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
376 | 7e7c5e4c | balrog | if (b >= s->blocks) {
|
377 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD; |
378 | 7e7c5e4c | balrog | break;
|
379 | 7e7c5e4c | balrog | } |
380 | 7e7c5e4c | balrog | if (s->blockwp[b] == ONEN_LOCK_UNLOCKED)
|
381 | 7e7c5e4c | balrog | continue;
|
382 | 7e7c5e4c | balrog | |
383 | 7e7c5e4c | balrog | s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKTIGHTEN; |
384 | 7e7c5e4c | balrog | } |
385 | 7e7c5e4c | balrog | break;
|
386 | 7e7c5e4c | balrog | |
387 | 7e7c5e4c | balrog | case 0x71: /* Erase-Verify-Read */ |
388 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT; |
389 | 7e7c5e4c | balrog | break;
|
390 | 7e7c5e4c | balrog | case 0x95: /* Multi-block erase */ |
391 | 7e7c5e4c | balrog | qemu_irq_pulse(s->intr); |
392 | 7e7c5e4c | balrog | /* Fall through. */
|
393 | 7e7c5e4c | balrog | case 0x94: /* Block erase */ |
394 | 7e7c5e4c | balrog | sec = ((s->addr[ONEN_BUF_BLOCK] & 0xfff) |
|
395 | 7e7c5e4c | balrog | (s->addr[ONEN_BUF_BLOCK] >> 15 ? s->density_mask : 0)) |
396 | 7e7c5e4c | balrog | << (BLOCK_SHIFT - 9);
|
397 | 7e7c5e4c | balrog | if (onenand_erase(s, sec, 1 << (BLOCK_SHIFT - 9))) |
398 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD | ONEN_ERR_ERASE; |
399 | 7e7c5e4c | balrog | |
400 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT | ONEN_INT_ERASE; |
401 | 7e7c5e4c | balrog | break;
|
402 | 7e7c5e4c | balrog | case 0xb0: /* Erase suspend */ |
403 | 7e7c5e4c | balrog | break;
|
404 | 7e7c5e4c | balrog | case 0x30: /* Erase resume */ |
405 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT | ONEN_INT_ERASE; |
406 | 7e7c5e4c | balrog | break;
|
407 | 7e7c5e4c | balrog | |
408 | 7e7c5e4c | balrog | case 0xf0: /* Reset NAND Flash core */ |
409 | 7e7c5e4c | balrog | onenand_reset(s, 0);
|
410 | 7e7c5e4c | balrog | break;
|
411 | 7e7c5e4c | balrog | case 0xf3: /* Reset OneNAND */ |
412 | 7e7c5e4c | balrog | onenand_reset(s, 0);
|
413 | 7e7c5e4c | balrog | break;
|
414 | 7e7c5e4c | balrog | |
415 | 7e7c5e4c | balrog | case 0x65: /* OTP Access */ |
416 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT; |
417 | 7e7c5e4c | balrog | s->bdrv_cur = 0;
|
418 | 7e7c5e4c | balrog | s->current = s->otp; |
419 | 7e7c5e4c | balrog | s->secs_cur = 1 << (BLOCK_SHIFT - 9); |
420 | 7e7c5e4c | balrog | s->addr[ONEN_BUF_BLOCK] = 0;
|
421 | 7e7c5e4c | balrog | s->otpmode = 1;
|
422 | 7e7c5e4c | balrog | break;
|
423 | 7e7c5e4c | balrog | |
424 | 7e7c5e4c | balrog | default:
|
425 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD; |
426 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT; |
427 | 7e7c5e4c | balrog | fprintf(stderr, "%s: unknown OneNAND command %x\n",
|
428 | 7e7c5e4c | balrog | __FUNCTION__, cmd); |
429 | 7e7c5e4c | balrog | } |
430 | 7e7c5e4c | balrog | |
431 | 7e7c5e4c | balrog | onenand_intr_update(s); |
432 | 7e7c5e4c | balrog | } |
433 | 7e7c5e4c | balrog | |
434 | 7e7c5e4c | balrog | static uint32_t onenand_read(void *opaque, target_phys_addr_t addr) |
435 | 7e7c5e4c | balrog | { |
436 | 7e7c5e4c | balrog | struct onenand_s *s = (struct onenand_s *) opaque; |
437 | 7e7c5e4c | balrog | int offset = (addr - s->base) >> s->shift;
|
438 | 7e7c5e4c | balrog | |
439 | 7e7c5e4c | balrog | switch (offset) {
|
440 | 7e7c5e4c | balrog | case 0x0000 ... 0xc000: |
441 | 7e7c5e4c | balrog | return lduw_le_p(s->boot[0] + (addr - s->base)); |
442 | 7e7c5e4c | balrog | |
443 | 7e7c5e4c | balrog | case 0xf000: /* Manufacturer ID */ |
444 | 7e7c5e4c | balrog | return (s->id >> 16) & 0xff; |
445 | 7e7c5e4c | balrog | case 0xf001: /* Device ID */ |
446 | 7e7c5e4c | balrog | return (s->id >> 8) & 0xff; |
447 | 7e7c5e4c | balrog | /* TODO: get the following values from a real chip! */
|
448 | 7e7c5e4c | balrog | case 0xf002: /* Version ID */ |
449 | 7e7c5e4c | balrog | return (s->id >> 0) & 0xff; |
450 | 7e7c5e4c | balrog | case 0xf003: /* Data Buffer size */ |
451 | 7e7c5e4c | balrog | return 1 << PAGE_SHIFT; |
452 | 7e7c5e4c | balrog | case 0xf004: /* Boot Buffer size */ |
453 | 7e7c5e4c | balrog | return 0x200; |
454 | 7e7c5e4c | balrog | case 0xf005: /* Amount of buffers */ |
455 | 7e7c5e4c | balrog | return 1 | (2 << 8); |
456 | 7e7c5e4c | balrog | case 0xf006: /* Technology */ |
457 | 7e7c5e4c | balrog | return 0; |
458 | 7e7c5e4c | balrog | |
459 | 7e7c5e4c | balrog | case 0xf100 ... 0xf107: /* Start addresses */ |
460 | 7e7c5e4c | balrog | return s->addr[offset - 0xf100]; |
461 | 7e7c5e4c | balrog | |
462 | 7e7c5e4c | balrog | case 0xf200: /* Start buffer */ |
463 | 7e7c5e4c | balrog | return (s->bufaddr << 8) | ((s->count - 1) & (1 << (PAGE_SHIFT - 10))); |
464 | 7e7c5e4c | balrog | |
465 | 7e7c5e4c | balrog | case 0xf220: /* Command */ |
466 | 7e7c5e4c | balrog | return s->command;
|
467 | 7e7c5e4c | balrog | case 0xf221: /* System Configuration 1 */ |
468 | 7e7c5e4c | balrog | return s->config[0] & 0xffe0; |
469 | 7e7c5e4c | balrog | case 0xf222: /* System Configuration 2 */ |
470 | 7e7c5e4c | balrog | return s->config[1]; |
471 | 7e7c5e4c | balrog | |
472 | 7e7c5e4c | balrog | case 0xf240: /* Controller Status */ |
473 | 7e7c5e4c | balrog | return s->status;
|
474 | 7e7c5e4c | balrog | case 0xf241: /* Interrupt */ |
475 | 7e7c5e4c | balrog | return s->intstatus;
|
476 | 7e7c5e4c | balrog | case 0xf24c: /* Unlock Start Block Address */ |
477 | 7e7c5e4c | balrog | return s->unladdr[0]; |
478 | 7e7c5e4c | balrog | case 0xf24d: /* Unlock End Block Address */ |
479 | 7e7c5e4c | balrog | return s->unladdr[1]; |
480 | 7e7c5e4c | balrog | case 0xf24e: /* Write Protection Status */ |
481 | 7e7c5e4c | balrog | return s->wpstatus;
|
482 | 7e7c5e4c | balrog | |
483 | 7e7c5e4c | balrog | case 0xff00: /* ECC Status */ |
484 | 7e7c5e4c | balrog | return 0x00; |
485 | 7e7c5e4c | balrog | case 0xff01: /* ECC Result of main area data */ |
486 | 7e7c5e4c | balrog | case 0xff02: /* ECC Result of spare area data */ |
487 | 7e7c5e4c | balrog | case 0xff03: /* ECC Result of main area data */ |
488 | 7e7c5e4c | balrog | case 0xff04: /* ECC Result of spare area data */ |
489 | 7e7c5e4c | balrog | cpu_abort(cpu_single_env, "%s: imeplement ECC\n", __FUNCTION__);
|
490 | 7e7c5e4c | balrog | return 0x0000; |
491 | 7e7c5e4c | balrog | } |
492 | 7e7c5e4c | balrog | |
493 | 7e7c5e4c | balrog | fprintf(stderr, "%s: unknown OneNAND register %x\n",
|
494 | 7e7c5e4c | balrog | __FUNCTION__, offset); |
495 | 7e7c5e4c | balrog | return 0; |
496 | 7e7c5e4c | balrog | } |
497 | 7e7c5e4c | balrog | |
498 | 7e7c5e4c | balrog | static void onenand_write(void *opaque, target_phys_addr_t addr, |
499 | 7e7c5e4c | balrog | uint32_t value) |
500 | 7e7c5e4c | balrog | { |
501 | 7e7c5e4c | balrog | struct onenand_s *s = (struct onenand_s *) opaque; |
502 | 7e7c5e4c | balrog | int offset = (addr - s->base) >> s->shift;
|
503 | 7e7c5e4c | balrog | int sec;
|
504 | 7e7c5e4c | balrog | |
505 | 7e7c5e4c | balrog | switch (offset) {
|
506 | 7e7c5e4c | balrog | case 0x0000 ... 0x01ff: |
507 | 7e7c5e4c | balrog | case 0x8000 ... 0x800f: |
508 | 7e7c5e4c | balrog | if (s->cycle) {
|
509 | 7e7c5e4c | balrog | s->cycle = 0;
|
510 | 7e7c5e4c | balrog | |
511 | 7e7c5e4c | balrog | if (value == 0x0000) { |
512 | 7e7c5e4c | balrog | SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
513 | 7e7c5e4c | balrog | onenand_load_main(s, sec, |
514 | 7e7c5e4c | balrog | 1 << (PAGE_SHIFT - 9), s->data[0][0]); |
515 | 7e7c5e4c | balrog | s->addr[ONEN_BUF_PAGE] += 4;
|
516 | 7e7c5e4c | balrog | s->addr[ONEN_BUF_PAGE] &= 0xff;
|
517 | 7e7c5e4c | balrog | } |
518 | 7e7c5e4c | balrog | break;
|
519 | 7e7c5e4c | balrog | } |
520 | 7e7c5e4c | balrog | |
521 | 7e7c5e4c | balrog | switch (value) {
|
522 | 7e7c5e4c | balrog | case 0x00f0: /* Reset OneNAND */ |
523 | 7e7c5e4c | balrog | onenand_reset(s, 0);
|
524 | 7e7c5e4c | balrog | break;
|
525 | 7e7c5e4c | balrog | |
526 | 7e7c5e4c | balrog | case 0x00e0: /* Load Data into Buffer */ |
527 | 7e7c5e4c | balrog | s->cycle = 1;
|
528 | 7e7c5e4c | balrog | break;
|
529 | 7e7c5e4c | balrog | |
530 | 7e7c5e4c | balrog | case 0x0090: /* Read Identification Data */ |
531 | 7e7c5e4c | balrog | memset(s->boot[0], 0, 3 << s->shift); |
532 | 7e7c5e4c | balrog | s->boot[0][0 << s->shift] = (s->id >> 16) & 0xff; |
533 | 7e7c5e4c | balrog | s->boot[0][1 << s->shift] = (s->id >> 8) & 0xff; |
534 | 7e7c5e4c | balrog | s->boot[0][2 << s->shift] = s->wpstatus & 0xff; |
535 | 7e7c5e4c | balrog | break;
|
536 | 7e7c5e4c | balrog | |
537 | 7e7c5e4c | balrog | default:
|
538 | 7e7c5e4c | balrog | fprintf(stderr, "%s: unknown OneNAND boot command %x\n",
|
539 | 7e7c5e4c | balrog | __FUNCTION__, value); |
540 | 7e7c5e4c | balrog | } |
541 | 7e7c5e4c | balrog | break;
|
542 | 7e7c5e4c | balrog | |
543 | 7e7c5e4c | balrog | case 0xf100 ... 0xf107: /* Start addresses */ |
544 | 7e7c5e4c | balrog | s->addr[offset - 0xf100] = value;
|
545 | 7e7c5e4c | balrog | break;
|
546 | 7e7c5e4c | balrog | |
547 | 7e7c5e4c | balrog | case 0xf200: /* Start buffer */ |
548 | 7e7c5e4c | balrog | s->bufaddr = (value >> 8) & 0xf; |
549 | 7e7c5e4c | balrog | if (PAGE_SHIFT == 11) |
550 | 7e7c5e4c | balrog | s->count = (value & 3) ?: 4; |
551 | 7e7c5e4c | balrog | else if (PAGE_SHIFT == 10) |
552 | 7e7c5e4c | balrog | s->count = (value & 1) ?: 2; |
553 | 7e7c5e4c | balrog | break;
|
554 | 7e7c5e4c | balrog | |
555 | 7e7c5e4c | balrog | case 0xf220: /* Command */ |
556 | 7e7c5e4c | balrog | if (s->intstatus & (1 << 15)) |
557 | 7e7c5e4c | balrog | break;
|
558 | 7e7c5e4c | balrog | s->command = value; |
559 | 7e7c5e4c | balrog | onenand_command(s, s->command); |
560 | 7e7c5e4c | balrog | break;
|
561 | 7e7c5e4c | balrog | case 0xf221: /* System Configuration 1 */ |
562 | 7e7c5e4c | balrog | s->config[0] = value;
|
563 | 7e7c5e4c | balrog | onenand_intr_update(s); |
564 | 7e7c5e4c | balrog | qemu_set_irq(s->rdy, (s->config[0] >> 7) & 1); |
565 | 7e7c5e4c | balrog | break;
|
566 | 7e7c5e4c | balrog | case 0xf222: /* System Configuration 2 */ |
567 | 7e7c5e4c | balrog | s->config[1] = value;
|
568 | 7e7c5e4c | balrog | break;
|
569 | 7e7c5e4c | balrog | |
570 | 7e7c5e4c | balrog | case 0xf241: /* Interrupt */ |
571 | 7e7c5e4c | balrog | s->intstatus &= value; |
572 | 7e7c5e4c | balrog | if ((1 << 15) & ~s->intstatus) |
573 | 7e7c5e4c | balrog | s->status &= ~(ONEN_ERR_CMD | ONEN_ERR_ERASE | |
574 | 7e7c5e4c | balrog | ONEN_ERR_PROG | ONEN_ERR_LOAD); |
575 | 7e7c5e4c | balrog | onenand_intr_update(s); |
576 | 7e7c5e4c | balrog | break;
|
577 | 7e7c5e4c | balrog | case 0xf24c: /* Unlock Start Block Address */ |
578 | 7e7c5e4c | balrog | s->unladdr[0] = value & (s->blocks - 1); |
579 | 7e7c5e4c | balrog | /* For some reason we have to set the end address to by default
|
580 | 7e7c5e4c | balrog | * be same as start because the software forgets to write anything
|
581 | 7e7c5e4c | balrog | * in there. */
|
582 | 7e7c5e4c | balrog | s->unladdr[1] = value & (s->blocks - 1); |
583 | 7e7c5e4c | balrog | break;
|
584 | 7e7c5e4c | balrog | case 0xf24d: /* Unlock End Block Address */ |
585 | 7e7c5e4c | balrog | s->unladdr[1] = value & (s->blocks - 1); |
586 | 7e7c5e4c | balrog | break;
|
587 | 7e7c5e4c | balrog | |
588 | 7e7c5e4c | balrog | default:
|
589 | 7e7c5e4c | balrog | fprintf(stderr, "%s: unknown OneNAND register %x\n",
|
590 | 7e7c5e4c | balrog | __FUNCTION__, offset); |
591 | 7e7c5e4c | balrog | } |
592 | 7e7c5e4c | balrog | } |
593 | 7e7c5e4c | balrog | |
594 | 7e7c5e4c | balrog | static CPUReadMemoryFunc *onenand_readfn[] = {
|
595 | 7e7c5e4c | balrog | onenand_read, /* TODO */
|
596 | 7e7c5e4c | balrog | onenand_read, |
597 | 7e7c5e4c | balrog | onenand_read, |
598 | 7e7c5e4c | balrog | }; |
599 | 7e7c5e4c | balrog | |
600 | 7e7c5e4c | balrog | static CPUWriteMemoryFunc *onenand_writefn[] = {
|
601 | 7e7c5e4c | balrog | onenand_write, /* TODO */
|
602 | 7e7c5e4c | balrog | onenand_write, |
603 | 7e7c5e4c | balrog | onenand_write, |
604 | 7e7c5e4c | balrog | }; |
605 | 7e7c5e4c | balrog | |
606 | 7e7c5e4c | balrog | void *onenand_init(uint32_t id, int regshift, qemu_irq irq) |
607 | 7e7c5e4c | balrog | { |
608 | 7e7c5e4c | balrog | struct onenand_s *s = (struct onenand_s *) qemu_mallocz(sizeof(*s)); |
609 | 7e7c5e4c | balrog | int bdrv_index = drive_get_index(IF_MTD, 0, 0); |
610 | 7e7c5e4c | balrog | uint32_t size = 1 << (24 + ((id >> 12) & 7)); |
611 | 7e7c5e4c | balrog | void *ram;
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612 | 7e7c5e4c | balrog | |
613 | 7e7c5e4c | balrog | s->shift = regshift; |
614 | 7e7c5e4c | balrog | s->intr = irq; |
615 | 7e7c5e4c | balrog | s->rdy = 0;
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616 | 7e7c5e4c | balrog | s->id = id; |
617 | 7e7c5e4c | balrog | s->blocks = size >> BLOCK_SHIFT; |
618 | 7e7c5e4c | balrog | s->secs = size >> 9;
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619 | 7e7c5e4c | balrog | s->blockwp = qemu_malloc(s->blocks); |
620 | 7e7c5e4c | balrog | s->density_mask = (id & (1 << 11)) ? (1 << (6 + ((id >> 12) & 7))) : 0; |
621 | 7e7c5e4c | balrog | s->iomemtype = cpu_register_io_memory(0, onenand_readfn,
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622 | 7e7c5e4c | balrog | onenand_writefn, s); |
623 | 7e7c5e4c | balrog | if (bdrv_index == -1) |
624 | 7e7c5e4c | balrog | s->image = memset(qemu_malloc(size + (size >> 5)),
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625 | 7e7c5e4c | balrog | 0xff, size + (size >> 5)); |
626 | 7e7c5e4c | balrog | else
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627 | 7e7c5e4c | balrog | s->bdrv = drives_table[bdrv_index].bdrv; |
628 | 7e7c5e4c | balrog | s->otp = memset(qemu_malloc((64 + 2) << PAGE_SHIFT), |
629 | 7e7c5e4c | balrog | 0xff, (64 + 2) << PAGE_SHIFT); |
630 | 7e7c5e4c | balrog | s->ram = qemu_ram_alloc(0xc000 << s->shift);
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631 | 7e7c5e4c | balrog | ram = phys_ram_base + s->ram; |
632 | 7e7c5e4c | balrog | s->boot[0] = ram + (0x0000 << s->shift); |
633 | 7e7c5e4c | balrog | s->boot[1] = ram + (0x8000 << s->shift); |
634 | 7e7c5e4c | balrog | s->data[0][0] = ram + ((0x0200 + (0 << (PAGE_SHIFT - 1))) << s->shift); |
635 | 7e7c5e4c | balrog | s->data[0][1] = ram + ((0x8010 + (0 << (PAGE_SHIFT - 6))) << s->shift); |
636 | 7e7c5e4c | balrog | s->data[1][0] = ram + ((0x0200 + (1 << (PAGE_SHIFT - 1))) << s->shift); |
637 | 7e7c5e4c | balrog | s->data[1][1] = ram + ((0x8010 + (1 << (PAGE_SHIFT - 6))) << s->shift); |
638 | 7e7c5e4c | balrog | |
639 | 7e7c5e4c | balrog | onenand_reset(s, 1);
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640 | 7e7c5e4c | balrog | |
641 | 7e7c5e4c | balrog | return s;
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642 | 7e7c5e4c | balrog | } |