root / hw / pxa2xx_lcd.c @ c701b35b
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1 | a171fe39 | balrog | /*
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2 | a171fe39 | balrog | * Intel XScale PXA255/270 LCDC emulation.
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3 | a171fe39 | balrog | *
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4 | a171fe39 | balrog | * Copyright (c) 2006 Openedhand Ltd.
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5 | a171fe39 | balrog | * Written by Andrzej Zaborowski <balrog@zabor.org>
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6 | a171fe39 | balrog | *
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7 | a171fe39 | balrog | * This code is licensed under the GPLv2.
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8 | a171fe39 | balrog | */
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9 | a171fe39 | balrog | |
10 | 87ecb68b | pbrook | #include "hw.h" |
11 | 87ecb68b | pbrook | #include "console.h" |
12 | 87ecb68b | pbrook | #include "pxa.h" |
13 | e27f01ef | balrog | #include "pixel_ops.h" |
14 | 87ecb68b | pbrook | /* FIXME: For graphic_rotate. Should probably be done in common code. */
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15 | 87ecb68b | pbrook | #include "sysemu.h" |
16 | a171fe39 | balrog | |
17 | a171fe39 | balrog | typedef void (*drawfn)(uint32_t *, uint8_t *, const uint8_t *, int, int); |
18 | a171fe39 | balrog | |
19 | a171fe39 | balrog | struct pxa2xx_lcdc_s {
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20 | a171fe39 | balrog | target_phys_addr_t base; |
21 | a171fe39 | balrog | qemu_irq irq; |
22 | a171fe39 | balrog | int irqlevel;
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23 | a171fe39 | balrog | |
24 | a171fe39 | balrog | int invalidated;
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25 | a171fe39 | balrog | DisplayState *ds; |
26 | c60e08d9 | pbrook | QEMUConsole *console; |
27 | a171fe39 | balrog | drawfn *line_fn[2];
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28 | a171fe39 | balrog | int dest_width;
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29 | a171fe39 | balrog | int xres, yres;
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30 | a171fe39 | balrog | int pal_for;
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31 | a171fe39 | balrog | int transp;
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32 | a171fe39 | balrog | enum {
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33 | a171fe39 | balrog | pxa_lcdc_2bpp = 1,
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34 | a171fe39 | balrog | pxa_lcdc_4bpp = 2,
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35 | a171fe39 | balrog | pxa_lcdc_8bpp = 3,
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36 | a171fe39 | balrog | pxa_lcdc_16bpp = 4,
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37 | a171fe39 | balrog | pxa_lcdc_18bpp = 5,
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38 | a171fe39 | balrog | pxa_lcdc_18pbpp = 6,
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39 | a171fe39 | balrog | pxa_lcdc_19bpp = 7,
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40 | a171fe39 | balrog | pxa_lcdc_19pbpp = 8,
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41 | a171fe39 | balrog | pxa_lcdc_24bpp = 9,
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42 | a171fe39 | balrog | pxa_lcdc_25bpp = 10,
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43 | a171fe39 | balrog | } bpp; |
44 | a171fe39 | balrog | |
45 | a171fe39 | balrog | uint32_t control[6];
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46 | a171fe39 | balrog | uint32_t status[2];
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47 | a171fe39 | balrog | uint32_t ovl1c[2];
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48 | a171fe39 | balrog | uint32_t ovl2c[2];
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49 | a171fe39 | balrog | uint32_t ccr; |
50 | a171fe39 | balrog | uint32_t cmdcr; |
51 | a171fe39 | balrog | uint32_t trgbr; |
52 | a171fe39 | balrog | uint32_t tcr; |
53 | a171fe39 | balrog | uint32_t liidr; |
54 | a171fe39 | balrog | uint8_t bscntr; |
55 | a171fe39 | balrog | |
56 | a171fe39 | balrog | struct {
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57 | a171fe39 | balrog | target_phys_addr_t branch; |
58 | a171fe39 | balrog | int up;
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59 | a171fe39 | balrog | uint8_t palette[1024];
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60 | a171fe39 | balrog | uint8_t pbuffer[1024];
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61 | a171fe39 | balrog | void (*redraw)(struct pxa2xx_lcdc_s *s, uint8_t *fb, |
62 | a171fe39 | balrog | int *miny, int *maxy); |
63 | a171fe39 | balrog | |
64 | a171fe39 | balrog | target_phys_addr_t descriptor; |
65 | a171fe39 | balrog | target_phys_addr_t source; |
66 | a171fe39 | balrog | uint32_t id; |
67 | a171fe39 | balrog | uint32_t command; |
68 | a171fe39 | balrog | } dma_ch[7];
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69 | a171fe39 | balrog | |
70 | 38641a52 | balrog | qemu_irq vsync_cb; |
71 | a171fe39 | balrog | int orientation;
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72 | a171fe39 | balrog | }; |
73 | a171fe39 | balrog | |
74 | a171fe39 | balrog | struct __attribute__ ((__packed__)) pxa_frame_descriptor_s {
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75 | a171fe39 | balrog | uint32_t fdaddr; |
76 | a171fe39 | balrog | uint32_t fsaddr; |
77 | a171fe39 | balrog | uint32_t fidr; |
78 | a171fe39 | balrog | uint32_t ldcmd; |
79 | a171fe39 | balrog | }; |
80 | a171fe39 | balrog | |
81 | a171fe39 | balrog | #define LCCR0 0x000 /* LCD Controller Control register 0 */ |
82 | a171fe39 | balrog | #define LCCR1 0x004 /* LCD Controller Control register 1 */ |
83 | a171fe39 | balrog | #define LCCR2 0x008 /* LCD Controller Control register 2 */ |
84 | a171fe39 | balrog | #define LCCR3 0x00c /* LCD Controller Control register 3 */ |
85 | a171fe39 | balrog | #define LCCR4 0x010 /* LCD Controller Control register 4 */ |
86 | a171fe39 | balrog | #define LCCR5 0x014 /* LCD Controller Control register 5 */ |
87 | a171fe39 | balrog | |
88 | a171fe39 | balrog | #define FBR0 0x020 /* DMA Channel 0 Frame Branch register */ |
89 | a171fe39 | balrog | #define FBR1 0x024 /* DMA Channel 1 Frame Branch register */ |
90 | a171fe39 | balrog | #define FBR2 0x028 /* DMA Channel 2 Frame Branch register */ |
91 | a171fe39 | balrog | #define FBR3 0x02c /* DMA Channel 3 Frame Branch register */ |
92 | a171fe39 | balrog | #define FBR4 0x030 /* DMA Channel 4 Frame Branch register */ |
93 | a171fe39 | balrog | #define FBR5 0x110 /* DMA Channel 5 Frame Branch register */ |
94 | a171fe39 | balrog | #define FBR6 0x114 /* DMA Channel 6 Frame Branch register */ |
95 | a171fe39 | balrog | |
96 | a171fe39 | balrog | #define LCSR1 0x034 /* LCD Controller Status register 1 */ |
97 | a171fe39 | balrog | #define LCSR0 0x038 /* LCD Controller Status register 0 */ |
98 | a171fe39 | balrog | #define LIIDR 0x03c /* LCD Controller Interrupt ID register */ |
99 | a171fe39 | balrog | |
100 | a171fe39 | balrog | #define TRGBR 0x040 /* TMED RGB Seed register */ |
101 | a171fe39 | balrog | #define TCR 0x044 /* TMED Control register */ |
102 | a171fe39 | balrog | |
103 | a171fe39 | balrog | #define OVL1C1 0x050 /* Overlay 1 Control register 1 */ |
104 | a171fe39 | balrog | #define OVL1C2 0x060 /* Overlay 1 Control register 2 */ |
105 | a171fe39 | balrog | #define OVL2C1 0x070 /* Overlay 2 Control register 1 */ |
106 | a171fe39 | balrog | #define OVL2C2 0x080 /* Overlay 2 Control register 2 */ |
107 | a171fe39 | balrog | #define CCR 0x090 /* Cursor Control register */ |
108 | a171fe39 | balrog | |
109 | a171fe39 | balrog | #define CMDCR 0x100 /* Command Control register */ |
110 | a171fe39 | balrog | #define PRSR 0x104 /* Panel Read Status register */ |
111 | a171fe39 | balrog | |
112 | a171fe39 | balrog | #define PXA_LCDDMA_CHANS 7 |
113 | a171fe39 | balrog | #define DMA_FDADR 0x00 /* Frame Descriptor Address register */ |
114 | a171fe39 | balrog | #define DMA_FSADR 0x04 /* Frame Source Address register */ |
115 | a171fe39 | balrog | #define DMA_FIDR 0x08 /* Frame ID register */ |
116 | a171fe39 | balrog | #define DMA_LDCMD 0x0c /* Command register */ |
117 | a171fe39 | balrog | |
118 | a171fe39 | balrog | /* LCD Buffer Strength Control register */
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119 | a171fe39 | balrog | #define BSCNTR 0x04000054 |
120 | a171fe39 | balrog | |
121 | a171fe39 | balrog | /* Bitfield masks */
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122 | a171fe39 | balrog | #define LCCR0_ENB (1 << 0) |
123 | a171fe39 | balrog | #define LCCR0_CMS (1 << 1) |
124 | a171fe39 | balrog | #define LCCR0_SDS (1 << 2) |
125 | a171fe39 | balrog | #define LCCR0_LDM (1 << 3) |
126 | a171fe39 | balrog | #define LCCR0_SOFM0 (1 << 4) |
127 | a171fe39 | balrog | #define LCCR0_IUM (1 << 5) |
128 | a171fe39 | balrog | #define LCCR0_EOFM0 (1 << 6) |
129 | a171fe39 | balrog | #define LCCR0_PAS (1 << 7) |
130 | a171fe39 | balrog | #define LCCR0_DPD (1 << 9) |
131 | a171fe39 | balrog | #define LCCR0_DIS (1 << 10) |
132 | a171fe39 | balrog | #define LCCR0_QDM (1 << 11) |
133 | a171fe39 | balrog | #define LCCR0_PDD (0xff << 12) |
134 | a171fe39 | balrog | #define LCCR0_BSM0 (1 << 20) |
135 | a171fe39 | balrog | #define LCCR0_OUM (1 << 21) |
136 | a171fe39 | balrog | #define LCCR0_LCDT (1 << 22) |
137 | a171fe39 | balrog | #define LCCR0_RDSTM (1 << 23) |
138 | a171fe39 | balrog | #define LCCR0_CMDIM (1 << 24) |
139 | a171fe39 | balrog | #define LCCR0_OUC (1 << 25) |
140 | a171fe39 | balrog | #define LCCR0_LDDALT (1 << 26) |
141 | a171fe39 | balrog | #define LCCR1_PPL(x) ((x) & 0x3ff) |
142 | a171fe39 | balrog | #define LCCR2_LPP(x) ((x) & 0x3ff) |
143 | a171fe39 | balrog | #define LCCR3_API (15 << 16) |
144 | a171fe39 | balrog | #define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8)) |
145 | a171fe39 | balrog | #define LCCR3_PDFOR(x) (((x) >> 30) & 3) |
146 | a171fe39 | balrog | #define LCCR4_K1(x) (((x) >> 0) & 7) |
147 | a171fe39 | balrog | #define LCCR4_K2(x) (((x) >> 3) & 7) |
148 | a171fe39 | balrog | #define LCCR4_K3(x) (((x) >> 6) & 7) |
149 | a171fe39 | balrog | #define LCCR4_PALFOR(x) (((x) >> 15) & 3) |
150 | a171fe39 | balrog | #define LCCR5_SOFM(ch) (1 << (ch - 1)) |
151 | a171fe39 | balrog | #define LCCR5_EOFM(ch) (1 << (ch + 7)) |
152 | a171fe39 | balrog | #define LCCR5_BSM(ch) (1 << (ch + 15)) |
153 | a171fe39 | balrog | #define LCCR5_IUM(ch) (1 << (ch + 23)) |
154 | a171fe39 | balrog | #define OVLC1_EN (1 << 31) |
155 | a171fe39 | balrog | #define CCR_CEN (1 << 31) |
156 | a171fe39 | balrog | #define FBR_BRA (1 << 0) |
157 | a171fe39 | balrog | #define FBR_BINT (1 << 1) |
158 | a171fe39 | balrog | #define FBR_SRCADDR (0xfffffff << 4) |
159 | a171fe39 | balrog | #define LCSR0_LDD (1 << 0) |
160 | a171fe39 | balrog | #define LCSR0_SOF0 (1 << 1) |
161 | a171fe39 | balrog | #define LCSR0_BER (1 << 2) |
162 | a171fe39 | balrog | #define LCSR0_ABC (1 << 3) |
163 | a171fe39 | balrog | #define LCSR0_IU0 (1 << 4) |
164 | a171fe39 | balrog | #define LCSR0_IU1 (1 << 5) |
165 | a171fe39 | balrog | #define LCSR0_OU (1 << 6) |
166 | a171fe39 | balrog | #define LCSR0_QD (1 << 7) |
167 | a171fe39 | balrog | #define LCSR0_EOF0 (1 << 8) |
168 | a171fe39 | balrog | #define LCSR0_BS0 (1 << 9) |
169 | a171fe39 | balrog | #define LCSR0_SINT (1 << 10) |
170 | a171fe39 | balrog | #define LCSR0_RDST (1 << 11) |
171 | a171fe39 | balrog | #define LCSR0_CMDINT (1 << 12) |
172 | a171fe39 | balrog | #define LCSR0_BERCH(x) (((x) & 7) << 28) |
173 | a171fe39 | balrog | #define LCSR1_SOF(ch) (1 << (ch - 1)) |
174 | a171fe39 | balrog | #define LCSR1_EOF(ch) (1 << (ch + 7)) |
175 | a171fe39 | balrog | #define LCSR1_BS(ch) (1 << (ch + 15)) |
176 | a171fe39 | balrog | #define LCSR1_IU(ch) (1 << (ch + 23)) |
177 | a171fe39 | balrog | #define LDCMD_LENGTH(x) ((x) & 0x001ffffc) |
178 | a171fe39 | balrog | #define LDCMD_EOFINT (1 << 21) |
179 | a171fe39 | balrog | #define LDCMD_SOFINT (1 << 22) |
180 | a171fe39 | balrog | #define LDCMD_PAL (1 << 26) |
181 | a171fe39 | balrog | |
182 | a171fe39 | balrog | /* Route internal interrupt lines to the global IC */
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183 | a171fe39 | balrog | static void pxa2xx_lcdc_int_update(struct pxa2xx_lcdc_s *s) |
184 | a171fe39 | balrog | { |
185 | a171fe39 | balrog | int level = 0; |
186 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM); |
187 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SOFM0); |
188 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IUM); |
189 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IUM(1)); |
190 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OUM); |
191 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QDM); |
192 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EOFM0); |
193 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BSM0); |
194 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RDSTM); |
195 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM); |
196 | a171fe39 | balrog | level |= (s->status[1] & ~s->control[5]); |
197 | a171fe39 | balrog | |
198 | a171fe39 | balrog | qemu_set_irq(s->irq, !!level); |
199 | a171fe39 | balrog | s->irqlevel = level; |
200 | a171fe39 | balrog | } |
201 | a171fe39 | balrog | |
202 | a171fe39 | balrog | /* Set Branch Status interrupt high and poke associated registers */
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203 | a171fe39 | balrog | static inline void pxa2xx_dma_bs_set(struct pxa2xx_lcdc_s *s, int ch) |
204 | a171fe39 | balrog | { |
205 | a171fe39 | balrog | int unmasked;
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206 | a171fe39 | balrog | if (ch == 0) { |
207 | a171fe39 | balrog | s->status[0] |= LCSR0_BS0;
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208 | a171fe39 | balrog | unmasked = !(s->control[0] & LCCR0_BSM0);
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209 | a171fe39 | balrog | } else {
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210 | a171fe39 | balrog | s->status[1] |= LCSR1_BS(ch);
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211 | a171fe39 | balrog | unmasked = !(s->control[5] & LCCR5_BSM(ch));
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212 | a171fe39 | balrog | } |
213 | a171fe39 | balrog | |
214 | a171fe39 | balrog | if (unmasked) {
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215 | a171fe39 | balrog | if (s->irqlevel)
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216 | a171fe39 | balrog | s->status[0] |= LCSR0_SINT;
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217 | a171fe39 | balrog | else
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218 | a171fe39 | balrog | s->liidr = s->dma_ch[ch].id; |
219 | a171fe39 | balrog | } |
220 | a171fe39 | balrog | } |
221 | a171fe39 | balrog | |
222 | a171fe39 | balrog | /* Set Start Of Frame Status interrupt high and poke associated registers */
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223 | a171fe39 | balrog | static inline void pxa2xx_dma_sof_set(struct pxa2xx_lcdc_s *s, int ch) |
224 | a171fe39 | balrog | { |
225 | a171fe39 | balrog | int unmasked;
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226 | a171fe39 | balrog | if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
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227 | a171fe39 | balrog | return;
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228 | a171fe39 | balrog | |
229 | a171fe39 | balrog | if (ch == 0) { |
230 | a171fe39 | balrog | s->status[0] |= LCSR0_SOF0;
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231 | a171fe39 | balrog | unmasked = !(s->control[0] & LCCR0_SOFM0);
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232 | a171fe39 | balrog | } else {
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233 | a171fe39 | balrog | s->status[1] |= LCSR1_SOF(ch);
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234 | a171fe39 | balrog | unmasked = !(s->control[5] & LCCR5_SOFM(ch));
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235 | a171fe39 | balrog | } |
236 | a171fe39 | balrog | |
237 | a171fe39 | balrog | if (unmasked) {
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238 | a171fe39 | balrog | if (s->irqlevel)
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239 | a171fe39 | balrog | s->status[0] |= LCSR0_SINT;
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240 | a171fe39 | balrog | else
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241 | a171fe39 | balrog | s->liidr = s->dma_ch[ch].id; |
242 | a171fe39 | balrog | } |
243 | a171fe39 | balrog | } |
244 | a171fe39 | balrog | |
245 | a171fe39 | balrog | /* Set End Of Frame Status interrupt high and poke associated registers */
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246 | a171fe39 | balrog | static inline void pxa2xx_dma_eof_set(struct pxa2xx_lcdc_s *s, int ch) |
247 | a171fe39 | balrog | { |
248 | a171fe39 | balrog | int unmasked;
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249 | a171fe39 | balrog | if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
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250 | a171fe39 | balrog | return;
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251 | a171fe39 | balrog | |
252 | a171fe39 | balrog | if (ch == 0) { |
253 | a171fe39 | balrog | s->status[0] |= LCSR0_EOF0;
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254 | a171fe39 | balrog | unmasked = !(s->control[0] & LCCR0_EOFM0);
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255 | a171fe39 | balrog | } else {
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256 | a171fe39 | balrog | s->status[1] |= LCSR1_EOF(ch);
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257 | a171fe39 | balrog | unmasked = !(s->control[5] & LCCR5_EOFM(ch));
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258 | a171fe39 | balrog | } |
259 | a171fe39 | balrog | |
260 | a171fe39 | balrog | if (unmasked) {
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261 | a171fe39 | balrog | if (s->irqlevel)
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262 | a171fe39 | balrog | s->status[0] |= LCSR0_SINT;
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263 | a171fe39 | balrog | else
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264 | a171fe39 | balrog | s->liidr = s->dma_ch[ch].id; |
265 | a171fe39 | balrog | } |
266 | a171fe39 | balrog | } |
267 | a171fe39 | balrog | |
268 | a171fe39 | balrog | /* Set Bus Error Status interrupt high and poke associated registers */
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269 | a171fe39 | balrog | static inline void pxa2xx_dma_ber_set(struct pxa2xx_lcdc_s *s, int ch) |
270 | a171fe39 | balrog | { |
271 | a171fe39 | balrog | s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
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272 | a171fe39 | balrog | if (s->irqlevel)
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273 | a171fe39 | balrog | s->status[0] |= LCSR0_SINT;
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274 | a171fe39 | balrog | else
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275 | a171fe39 | balrog | s->liidr = s->dma_ch[ch].id; |
276 | a171fe39 | balrog | } |
277 | a171fe39 | balrog | |
278 | a171fe39 | balrog | /* Set Read Status interrupt high and poke associated registers */
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279 | a171fe39 | balrog | static inline void pxa2xx_dma_rdst_set(struct pxa2xx_lcdc_s *s) |
280 | a171fe39 | balrog | { |
281 | a171fe39 | balrog | s->status[0] |= LCSR0_RDST;
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282 | a171fe39 | balrog | if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM)) |
283 | a171fe39 | balrog | s->status[0] |= LCSR0_SINT;
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284 | a171fe39 | balrog | } |
285 | a171fe39 | balrog | |
286 | a171fe39 | balrog | /* Load new Frame Descriptors from DMA */
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287 | a171fe39 | balrog | static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s) |
288 | a171fe39 | balrog | { |
289 | a171fe39 | balrog | struct pxa_frame_descriptor_s *desc[PXA_LCDDMA_CHANS];
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290 | a171fe39 | balrog | target_phys_addr_t descptr; |
291 | a171fe39 | balrog | int i;
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292 | a171fe39 | balrog | |
293 | a171fe39 | balrog | for (i = 0; i < PXA_LCDDMA_CHANS; i ++) { |
294 | a171fe39 | balrog | desc[i] = 0;
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295 | a171fe39 | balrog | s->dma_ch[i].source = 0;
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296 | a171fe39 | balrog | |
297 | a171fe39 | balrog | if (!s->dma_ch[i].up)
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298 | a171fe39 | balrog | continue;
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299 | a171fe39 | balrog | |
300 | a171fe39 | balrog | if (s->dma_ch[i].branch & FBR_BRA) {
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301 | a171fe39 | balrog | descptr = s->dma_ch[i].branch & FBR_SRCADDR; |
302 | a171fe39 | balrog | if (s->dma_ch[i].branch & FBR_BINT)
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303 | a171fe39 | balrog | pxa2xx_dma_bs_set(s, i); |
304 | a171fe39 | balrog | s->dma_ch[i].branch &= ~FBR_BRA; |
305 | a171fe39 | balrog | } else
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306 | a171fe39 | balrog | descptr = s->dma_ch[i].descriptor; |
307 | a171fe39 | balrog | |
308 | d95b2f8d | balrog | if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
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309 | d95b2f8d | balrog | sizeof(*desc[i]) <= PXA2XX_SDRAM_BASE + phys_ram_size))
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310 | a171fe39 | balrog | continue;
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311 | a171fe39 | balrog | |
312 | d95b2f8d | balrog | descptr -= PXA2XX_SDRAM_BASE; |
313 | a171fe39 | balrog | desc[i] = (struct pxa_frame_descriptor_s *) (phys_ram_base + descptr);
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314 | a171fe39 | balrog | s->dma_ch[i].descriptor = desc[i]->fdaddr; |
315 | a171fe39 | balrog | s->dma_ch[i].source = desc[i]->fsaddr; |
316 | a171fe39 | balrog | s->dma_ch[i].id = desc[i]->fidr; |
317 | a171fe39 | balrog | s->dma_ch[i].command = desc[i]->ldcmd; |
318 | a171fe39 | balrog | } |
319 | a171fe39 | balrog | } |
320 | a171fe39 | balrog | |
321 | a171fe39 | balrog | static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset) |
322 | a171fe39 | balrog | { |
323 | a171fe39 | balrog | struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
324 | a171fe39 | balrog | int ch;
|
325 | a171fe39 | balrog | offset -= s->base; |
326 | a171fe39 | balrog | |
327 | a171fe39 | balrog | switch (offset) {
|
328 | a171fe39 | balrog | case LCCR0:
|
329 | a171fe39 | balrog | return s->control[0]; |
330 | a171fe39 | balrog | case LCCR1:
|
331 | a171fe39 | balrog | return s->control[1]; |
332 | a171fe39 | balrog | case LCCR2:
|
333 | a171fe39 | balrog | return s->control[2]; |
334 | a171fe39 | balrog | case LCCR3:
|
335 | a171fe39 | balrog | return s->control[3]; |
336 | a171fe39 | balrog | case LCCR4:
|
337 | a171fe39 | balrog | return s->control[4]; |
338 | a171fe39 | balrog | case LCCR5:
|
339 | a171fe39 | balrog | return s->control[5]; |
340 | a171fe39 | balrog | |
341 | a171fe39 | balrog | case OVL1C1:
|
342 | a171fe39 | balrog | return s->ovl1c[0]; |
343 | a171fe39 | balrog | case OVL1C2:
|
344 | a171fe39 | balrog | return s->ovl1c[1]; |
345 | a171fe39 | balrog | case OVL2C1:
|
346 | a171fe39 | balrog | return s->ovl2c[0]; |
347 | a171fe39 | balrog | case OVL2C2:
|
348 | a171fe39 | balrog | return s->ovl2c[1]; |
349 | a171fe39 | balrog | |
350 | a171fe39 | balrog | case CCR:
|
351 | a171fe39 | balrog | return s->ccr;
|
352 | a171fe39 | balrog | |
353 | a171fe39 | balrog | case CMDCR:
|
354 | a171fe39 | balrog | return s->cmdcr;
|
355 | a171fe39 | balrog | |
356 | a171fe39 | balrog | case TRGBR:
|
357 | a171fe39 | balrog | return s->trgbr;
|
358 | a171fe39 | balrog | case TCR:
|
359 | a171fe39 | balrog | return s->tcr;
|
360 | a171fe39 | balrog | |
361 | a171fe39 | balrog | case 0x200 ... 0x1000: /* DMA per-channel registers */ |
362 | a171fe39 | balrog | ch = (offset - 0x200) >> 4; |
363 | a171fe39 | balrog | if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS)) |
364 | a171fe39 | balrog | goto fail;
|
365 | a171fe39 | balrog | |
366 | a171fe39 | balrog | switch (offset & 0xf) { |
367 | a171fe39 | balrog | case DMA_FDADR:
|
368 | a171fe39 | balrog | return s->dma_ch[ch].descriptor;
|
369 | a171fe39 | balrog | case DMA_FSADR:
|
370 | a171fe39 | balrog | return s->dma_ch[ch].source;
|
371 | a171fe39 | balrog | case DMA_FIDR:
|
372 | a171fe39 | balrog | return s->dma_ch[ch].id;
|
373 | a171fe39 | balrog | case DMA_LDCMD:
|
374 | a171fe39 | balrog | return s->dma_ch[ch].command;
|
375 | a171fe39 | balrog | default:
|
376 | a171fe39 | balrog | goto fail;
|
377 | a171fe39 | balrog | } |
378 | a171fe39 | balrog | |
379 | a171fe39 | balrog | case FBR0:
|
380 | a171fe39 | balrog | return s->dma_ch[0].branch; |
381 | a171fe39 | balrog | case FBR1:
|
382 | a171fe39 | balrog | return s->dma_ch[1].branch; |
383 | a171fe39 | balrog | case FBR2:
|
384 | a171fe39 | balrog | return s->dma_ch[2].branch; |
385 | a171fe39 | balrog | case FBR3:
|
386 | a171fe39 | balrog | return s->dma_ch[3].branch; |
387 | a171fe39 | balrog | case FBR4:
|
388 | a171fe39 | balrog | return s->dma_ch[4].branch; |
389 | a171fe39 | balrog | case FBR5:
|
390 | a171fe39 | balrog | return s->dma_ch[5].branch; |
391 | a171fe39 | balrog | case FBR6:
|
392 | a171fe39 | balrog | return s->dma_ch[6].branch; |
393 | a171fe39 | balrog | |
394 | a171fe39 | balrog | case BSCNTR:
|
395 | a171fe39 | balrog | return s->bscntr;
|
396 | a171fe39 | balrog | |
397 | a171fe39 | balrog | case PRSR:
|
398 | a171fe39 | balrog | return 0; |
399 | a171fe39 | balrog | |
400 | a171fe39 | balrog | case LCSR0:
|
401 | a171fe39 | balrog | return s->status[0]; |
402 | a171fe39 | balrog | case LCSR1:
|
403 | a171fe39 | balrog | return s->status[1]; |
404 | a171fe39 | balrog | case LIIDR:
|
405 | a171fe39 | balrog | return s->liidr;
|
406 | a171fe39 | balrog | |
407 | a171fe39 | balrog | default:
|
408 | a171fe39 | balrog | fail:
|
409 | a171fe39 | balrog | cpu_abort(cpu_single_env, |
410 | a171fe39 | balrog | "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); |
411 | a171fe39 | balrog | } |
412 | a171fe39 | balrog | |
413 | a171fe39 | balrog | return 0; |
414 | a171fe39 | balrog | } |
415 | a171fe39 | balrog | |
416 | a171fe39 | balrog | static void pxa2xx_lcdc_write(void *opaque, |
417 | a171fe39 | balrog | target_phys_addr_t offset, uint32_t value) |
418 | a171fe39 | balrog | { |
419 | a171fe39 | balrog | struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
420 | a171fe39 | balrog | int ch;
|
421 | a171fe39 | balrog | offset -= s->base; |
422 | a171fe39 | balrog | |
423 | a171fe39 | balrog | switch (offset) {
|
424 | a171fe39 | balrog | case LCCR0:
|
425 | a171fe39 | balrog | /* ACK Quick Disable done */
|
426 | a171fe39 | balrog | if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB)) |
427 | a171fe39 | balrog | s->status[0] |= LCSR0_QD;
|
428 | a171fe39 | balrog | |
429 | a171fe39 | balrog | if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT)) |
430 | a171fe39 | balrog | printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
|
431 | a171fe39 | balrog | |
432 | a171fe39 | balrog | if ((s->control[3] & LCCR3_API) && |
433 | a171fe39 | balrog | (value & LCCR0_ENB) && !(value & LCCR0_LCDT)) |
434 | a171fe39 | balrog | s->status[0] |= LCSR0_ABC;
|
435 | a171fe39 | balrog | |
436 | a171fe39 | balrog | s->control[0] = value & 0x07ffffff; |
437 | a171fe39 | balrog | pxa2xx_lcdc_int_update(s); |
438 | a171fe39 | balrog | |
439 | a171fe39 | balrog | s->dma_ch[0].up = !!(value & LCCR0_ENB);
|
440 | a171fe39 | balrog | s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS); |
441 | a171fe39 | balrog | break;
|
442 | a171fe39 | balrog | |
443 | a171fe39 | balrog | case LCCR1:
|
444 | a171fe39 | balrog | s->control[1] = value;
|
445 | a171fe39 | balrog | break;
|
446 | a171fe39 | balrog | |
447 | a171fe39 | balrog | case LCCR2:
|
448 | a171fe39 | balrog | s->control[2] = value;
|
449 | a171fe39 | balrog | break;
|
450 | a171fe39 | balrog | |
451 | a171fe39 | balrog | case LCCR3:
|
452 | a171fe39 | balrog | s->control[3] = value & 0xefffffff; |
453 | a171fe39 | balrog | s->bpp = LCCR3_BPP(value); |
454 | a171fe39 | balrog | break;
|
455 | a171fe39 | balrog | |
456 | a171fe39 | balrog | case LCCR4:
|
457 | a171fe39 | balrog | s->control[4] = value & 0x83ff81ff; |
458 | a171fe39 | balrog | break;
|
459 | a171fe39 | balrog | |
460 | a171fe39 | balrog | case LCCR5:
|
461 | a171fe39 | balrog | s->control[5] = value & 0x3f3f3f3f; |
462 | a171fe39 | balrog | break;
|
463 | a171fe39 | balrog | |
464 | a171fe39 | balrog | case OVL1C1:
|
465 | a171fe39 | balrog | if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN)) |
466 | a171fe39 | balrog | printf("%s: Overlay 1 not supported\n", __FUNCTION__);
|
467 | a171fe39 | balrog | |
468 | a171fe39 | balrog | s->ovl1c[0] = value & 0x80ffffff; |
469 | a171fe39 | balrog | s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS); |
470 | a171fe39 | balrog | break;
|
471 | a171fe39 | balrog | |
472 | a171fe39 | balrog | case OVL1C2:
|
473 | a171fe39 | balrog | s->ovl1c[1] = value & 0x000fffff; |
474 | a171fe39 | balrog | break;
|
475 | a171fe39 | balrog | |
476 | a171fe39 | balrog | case OVL2C1:
|
477 | a171fe39 | balrog | if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN)) |
478 | a171fe39 | balrog | printf("%s: Overlay 2 not supported\n", __FUNCTION__);
|
479 | a171fe39 | balrog | |
480 | a171fe39 | balrog | s->ovl2c[0] = value & 0x80ffffff; |
481 | a171fe39 | balrog | s->dma_ch[2].up = !!(value & OVLC1_EN);
|
482 | a171fe39 | balrog | s->dma_ch[3].up = !!(value & OVLC1_EN);
|
483 | a171fe39 | balrog | s->dma_ch[4].up = !!(value & OVLC1_EN);
|
484 | a171fe39 | balrog | break;
|
485 | a171fe39 | balrog | |
486 | a171fe39 | balrog | case OVL2C2:
|
487 | a171fe39 | balrog | s->ovl2c[1] = value & 0x007fffff; |
488 | a171fe39 | balrog | break;
|
489 | a171fe39 | balrog | |
490 | a171fe39 | balrog | case CCR:
|
491 | a171fe39 | balrog | if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
|
492 | a171fe39 | balrog | printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
|
493 | a171fe39 | balrog | |
494 | a171fe39 | balrog | s->ccr = value & 0x81ffffe7;
|
495 | a171fe39 | balrog | s->dma_ch[5].up = !!(value & CCR_CEN);
|
496 | a171fe39 | balrog | break;
|
497 | a171fe39 | balrog | |
498 | a171fe39 | balrog | case CMDCR:
|
499 | a171fe39 | balrog | s->cmdcr = value & 0xff;
|
500 | a171fe39 | balrog | break;
|
501 | a171fe39 | balrog | |
502 | a171fe39 | balrog | case TRGBR:
|
503 | a171fe39 | balrog | s->trgbr = value & 0x00ffffff;
|
504 | a171fe39 | balrog | break;
|
505 | a171fe39 | balrog | |
506 | a171fe39 | balrog | case TCR:
|
507 | a171fe39 | balrog | s->tcr = value & 0x7fff;
|
508 | a171fe39 | balrog | break;
|
509 | a171fe39 | balrog | |
510 | a171fe39 | balrog | case 0x200 ... 0x1000: /* DMA per-channel registers */ |
511 | a171fe39 | balrog | ch = (offset - 0x200) >> 4; |
512 | a171fe39 | balrog | if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS)) |
513 | a171fe39 | balrog | goto fail;
|
514 | a171fe39 | balrog | |
515 | a171fe39 | balrog | switch (offset & 0xf) { |
516 | a171fe39 | balrog | case DMA_FDADR:
|
517 | a171fe39 | balrog | s->dma_ch[ch].descriptor = value & 0xfffffff0;
|
518 | a171fe39 | balrog | break;
|
519 | a171fe39 | balrog | |
520 | a171fe39 | balrog | default:
|
521 | a171fe39 | balrog | goto fail;
|
522 | a171fe39 | balrog | } |
523 | a171fe39 | balrog | break;
|
524 | a171fe39 | balrog | |
525 | a171fe39 | balrog | case FBR0:
|
526 | a171fe39 | balrog | s->dma_ch[0].branch = value & 0xfffffff3; |
527 | a171fe39 | balrog | break;
|
528 | a171fe39 | balrog | case FBR1:
|
529 | a171fe39 | balrog | s->dma_ch[1].branch = value & 0xfffffff3; |
530 | a171fe39 | balrog | break;
|
531 | a171fe39 | balrog | case FBR2:
|
532 | a171fe39 | balrog | s->dma_ch[2].branch = value & 0xfffffff3; |
533 | a171fe39 | balrog | break;
|
534 | a171fe39 | balrog | case FBR3:
|
535 | a171fe39 | balrog | s->dma_ch[3].branch = value & 0xfffffff3; |
536 | a171fe39 | balrog | break;
|
537 | a171fe39 | balrog | case FBR4:
|
538 | a171fe39 | balrog | s->dma_ch[4].branch = value & 0xfffffff3; |
539 | a171fe39 | balrog | break;
|
540 | a171fe39 | balrog | case FBR5:
|
541 | a171fe39 | balrog | s->dma_ch[5].branch = value & 0xfffffff3; |
542 | a171fe39 | balrog | break;
|
543 | a171fe39 | balrog | case FBR6:
|
544 | a171fe39 | balrog | s->dma_ch[6].branch = value & 0xfffffff3; |
545 | a171fe39 | balrog | break;
|
546 | a171fe39 | balrog | |
547 | a171fe39 | balrog | case BSCNTR:
|
548 | a171fe39 | balrog | s->bscntr = value & 0xf;
|
549 | a171fe39 | balrog | break;
|
550 | a171fe39 | balrog | |
551 | a171fe39 | balrog | case PRSR:
|
552 | a171fe39 | balrog | break;
|
553 | a171fe39 | balrog | |
554 | a171fe39 | balrog | case LCSR0:
|
555 | a171fe39 | balrog | s->status[0] &= ~(value & 0xfff); |
556 | a171fe39 | balrog | if (value & LCSR0_BER)
|
557 | a171fe39 | balrog | s->status[0] &= ~LCSR0_BERCH(7); |
558 | a171fe39 | balrog | break;
|
559 | a171fe39 | balrog | |
560 | a171fe39 | balrog | case LCSR1:
|
561 | a171fe39 | balrog | s->status[1] &= ~(value & 0x3e3f3f); |
562 | a171fe39 | balrog | break;
|
563 | a171fe39 | balrog | |
564 | a171fe39 | balrog | default:
|
565 | a171fe39 | balrog | fail:
|
566 | a171fe39 | balrog | cpu_abort(cpu_single_env, |
567 | a171fe39 | balrog | "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); |
568 | a171fe39 | balrog | } |
569 | a171fe39 | balrog | } |
570 | a171fe39 | balrog | |
571 | a171fe39 | balrog | static CPUReadMemoryFunc *pxa2xx_lcdc_readfn[] = {
|
572 | a171fe39 | balrog | pxa2xx_lcdc_read, |
573 | a171fe39 | balrog | pxa2xx_lcdc_read, |
574 | a171fe39 | balrog | pxa2xx_lcdc_read |
575 | a171fe39 | balrog | }; |
576 | a171fe39 | balrog | |
577 | a171fe39 | balrog | static CPUWriteMemoryFunc *pxa2xx_lcdc_writefn[] = {
|
578 | a171fe39 | balrog | pxa2xx_lcdc_write, |
579 | a171fe39 | balrog | pxa2xx_lcdc_write, |
580 | a171fe39 | balrog | pxa2xx_lcdc_write |
581 | a171fe39 | balrog | }; |
582 | a171fe39 | balrog | |
583 | a171fe39 | balrog | /* Load new palette for a given DMA channel, convert to internal format */
|
584 | a171fe39 | balrog | static void pxa2xx_palette_parse(struct pxa2xx_lcdc_s *s, int ch, int bpp) |
585 | a171fe39 | balrog | { |
586 | a171fe39 | balrog | int i, n, format, r, g, b, alpha;
|
587 | a171fe39 | balrog | uint32_t *dest, *src; |
588 | a171fe39 | balrog | s->pal_for = LCCR4_PALFOR(s->control[4]);
|
589 | a171fe39 | balrog | format = s->pal_for; |
590 | a171fe39 | balrog | |
591 | a171fe39 | balrog | switch (bpp) {
|
592 | a171fe39 | balrog | case pxa_lcdc_2bpp:
|
593 | a171fe39 | balrog | n = 4;
|
594 | a171fe39 | balrog | break;
|
595 | a171fe39 | balrog | case pxa_lcdc_4bpp:
|
596 | a171fe39 | balrog | n = 16;
|
597 | a171fe39 | balrog | break;
|
598 | a171fe39 | balrog | case pxa_lcdc_8bpp:
|
599 | a171fe39 | balrog | n = 256;
|
600 | a171fe39 | balrog | break;
|
601 | a171fe39 | balrog | default:
|
602 | a171fe39 | balrog | format = 0;
|
603 | a171fe39 | balrog | return;
|
604 | a171fe39 | balrog | } |
605 | a171fe39 | balrog | |
606 | a171fe39 | balrog | src = (uint32_t *) s->dma_ch[ch].pbuffer; |
607 | a171fe39 | balrog | dest = (uint32_t *) s->dma_ch[ch].palette; |
608 | a171fe39 | balrog | alpha = r = g = b = 0;
|
609 | a171fe39 | balrog | |
610 | a171fe39 | balrog | for (i = 0; i < n; i ++) { |
611 | a171fe39 | balrog | switch (format) {
|
612 | a171fe39 | balrog | case 0: /* 16 bpp, no transparency */ |
613 | a171fe39 | balrog | alpha = 0;
|
614 | a171fe39 | balrog | if (s->control[0] & LCCR0_CMS) |
615 | a171fe39 | balrog | r = g = b = *src & 0xff;
|
616 | a171fe39 | balrog | else {
|
617 | a171fe39 | balrog | r = (*src & 0xf800) >> 8; |
618 | a171fe39 | balrog | g = (*src & 0x07e0) >> 3; |
619 | a171fe39 | balrog | b = (*src & 0x001f) << 3; |
620 | a171fe39 | balrog | } |
621 | a171fe39 | balrog | break;
|
622 | a171fe39 | balrog | case 1: /* 16 bpp plus transparency */ |
623 | a171fe39 | balrog | alpha = *src & (1 << 24); |
624 | a171fe39 | balrog | if (s->control[0] & LCCR0_CMS) |
625 | a171fe39 | balrog | r = g = b = *src & 0xff;
|
626 | a171fe39 | balrog | else {
|
627 | a171fe39 | balrog | r = (*src & 0xf800) >> 8; |
628 | a171fe39 | balrog | g = (*src & 0x07e0) >> 3; |
629 | a171fe39 | balrog | b = (*src & 0x001f) << 3; |
630 | a171fe39 | balrog | } |
631 | a171fe39 | balrog | break;
|
632 | a171fe39 | balrog | case 2: /* 18 bpp plus transparency */ |
633 | a171fe39 | balrog | alpha = *src & (1 << 24); |
634 | a171fe39 | balrog | if (s->control[0] & LCCR0_CMS) |
635 | a171fe39 | balrog | r = g = b = *src & 0xff;
|
636 | a171fe39 | balrog | else {
|
637 | a171fe39 | balrog | r = (*src & 0xf80000) >> 16; |
638 | a171fe39 | balrog | g = (*src & 0x00fc00) >> 8; |
639 | a171fe39 | balrog | b = (*src & 0x0000f8);
|
640 | a171fe39 | balrog | } |
641 | a171fe39 | balrog | break;
|
642 | a171fe39 | balrog | case 3: /* 24 bpp plus transparency */ |
643 | a171fe39 | balrog | alpha = *src & (1 << 24); |
644 | a171fe39 | balrog | if (s->control[0] & LCCR0_CMS) |
645 | a171fe39 | balrog | r = g = b = *src & 0xff;
|
646 | a171fe39 | balrog | else {
|
647 | a171fe39 | balrog | r = (*src & 0xff0000) >> 16; |
648 | a171fe39 | balrog | g = (*src & 0x00ff00) >> 8; |
649 | a171fe39 | balrog | b = (*src & 0x0000ff);
|
650 | a171fe39 | balrog | } |
651 | a171fe39 | balrog | break;
|
652 | a171fe39 | balrog | } |
653 | a171fe39 | balrog | switch (s->ds->depth) {
|
654 | a171fe39 | balrog | case 8: |
655 | a171fe39 | balrog | *dest = rgb_to_pixel8(r, g, b) | alpha; |
656 | a171fe39 | balrog | break;
|
657 | a171fe39 | balrog | case 15: |
658 | a171fe39 | balrog | *dest = rgb_to_pixel15(r, g, b) | alpha; |
659 | a171fe39 | balrog | break;
|
660 | a171fe39 | balrog | case 16: |
661 | a171fe39 | balrog | *dest = rgb_to_pixel16(r, g, b) | alpha; |
662 | a171fe39 | balrog | break;
|
663 | a171fe39 | balrog | case 24: |
664 | a171fe39 | balrog | *dest = rgb_to_pixel24(r, g, b) | alpha; |
665 | a171fe39 | balrog | break;
|
666 | a171fe39 | balrog | case 32: |
667 | a171fe39 | balrog | *dest = rgb_to_pixel32(r, g, b) | alpha; |
668 | a171fe39 | balrog | break;
|
669 | a171fe39 | balrog | } |
670 | a171fe39 | balrog | src ++; |
671 | a171fe39 | balrog | dest ++; |
672 | a171fe39 | balrog | } |
673 | a171fe39 | balrog | } |
674 | a171fe39 | balrog | |
675 | a171fe39 | balrog | static void pxa2xx_lcdc_dma0_redraw_horiz(struct pxa2xx_lcdc_s *s, |
676 | a171fe39 | balrog | uint8_t *fb, int *miny, int *maxy) |
677 | a171fe39 | balrog | { |
678 | a171fe39 | balrog | int y, src_width, dest_width, dirty[2]; |
679 | a171fe39 | balrog | uint8_t *src, *dest; |
680 | a171fe39 | balrog | ram_addr_t x, addr, new_addr, start, end; |
681 | a171fe39 | balrog | drawfn fn = 0;
|
682 | a171fe39 | balrog | if (s->dest_width)
|
683 | a171fe39 | balrog | fn = s->line_fn[s->transp][s->bpp]; |
684 | a171fe39 | balrog | if (!fn)
|
685 | a171fe39 | balrog | return;
|
686 | a171fe39 | balrog | |
687 | a171fe39 | balrog | src = fb; |
688 | a171fe39 | balrog | src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */ |
689 | a171fe39 | balrog | if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
|
690 | a171fe39 | balrog | src_width *= 3;
|
691 | a171fe39 | balrog | else if (s->bpp > pxa_lcdc_16bpp) |
692 | a171fe39 | balrog | src_width *= 4;
|
693 | a171fe39 | balrog | else if (s->bpp > pxa_lcdc_8bpp) |
694 | a171fe39 | balrog | src_width *= 2;
|
695 | a171fe39 | balrog | |
696 | a171fe39 | balrog | dest = s->ds->data; |
697 | a171fe39 | balrog | dest_width = s->xres * s->dest_width; |
698 | a171fe39 | balrog | |
699 | a171fe39 | balrog | addr = (ram_addr_t) (fb - phys_ram_base); |
700 | a171fe39 | balrog | start = addr + s->yres * src_width; |
701 | a171fe39 | balrog | end = addr; |
702 | a171fe39 | balrog | dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(start, VGA_DIRTY_FLAG); |
703 | a171fe39 | balrog | for (y = 0; y < s->yres; y ++) { |
704 | a171fe39 | balrog | new_addr = addr + src_width; |
705 | a171fe39 | balrog | for (x = addr + TARGET_PAGE_SIZE; x < new_addr;
|
706 | a171fe39 | balrog | x += TARGET_PAGE_SIZE) { |
707 | a171fe39 | balrog | dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
|
708 | a171fe39 | balrog | dirty[0] |= dirty[1]; |
709 | a171fe39 | balrog | } |
710 | a171fe39 | balrog | if (dirty[0] || s->invalidated) { |
711 | a171fe39 | balrog | fn((uint32_t *) s->dma_ch[0].palette,
|
712 | a171fe39 | balrog | dest, src, s->xres, s->dest_width); |
713 | a171fe39 | balrog | if (addr < start)
|
714 | a171fe39 | balrog | start = addr; |
715 | a07dec22 | balrog | end = new_addr; |
716 | a171fe39 | balrog | if (y < *miny)
|
717 | a171fe39 | balrog | *miny = y; |
718 | a171fe39 | balrog | if (y >= *maxy)
|
719 | a171fe39 | balrog | *maxy = y + 1;
|
720 | a171fe39 | balrog | } |
721 | a171fe39 | balrog | addr = new_addr; |
722 | a171fe39 | balrog | dirty[0] = dirty[1]; |
723 | a171fe39 | balrog | src += src_width; |
724 | a171fe39 | balrog | dest += dest_width; |
725 | a171fe39 | balrog | } |
726 | a171fe39 | balrog | |
727 | a171fe39 | balrog | if (end > start)
|
728 | a171fe39 | balrog | cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG); |
729 | a171fe39 | balrog | } |
730 | a171fe39 | balrog | |
731 | a171fe39 | balrog | static void pxa2xx_lcdc_dma0_redraw_vert(struct pxa2xx_lcdc_s *s, |
732 | a171fe39 | balrog | uint8_t *fb, int *miny, int *maxy) |
733 | a171fe39 | balrog | { |
734 | a171fe39 | balrog | int y, src_width, dest_width, dirty[2]; |
735 | a171fe39 | balrog | uint8_t *src, *dest; |
736 | a171fe39 | balrog | ram_addr_t x, addr, new_addr, start, end; |
737 | a171fe39 | balrog | drawfn fn = 0;
|
738 | a171fe39 | balrog | if (s->dest_width)
|
739 | a171fe39 | balrog | fn = s->line_fn[s->transp][s->bpp]; |
740 | a171fe39 | balrog | if (!fn)
|
741 | a171fe39 | balrog | return;
|
742 | a171fe39 | balrog | |
743 | a171fe39 | balrog | src = fb; |
744 | a171fe39 | balrog | src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */ |
745 | a171fe39 | balrog | if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
|
746 | a171fe39 | balrog | src_width *= 3;
|
747 | a171fe39 | balrog | else if (s->bpp > pxa_lcdc_16bpp) |
748 | a171fe39 | balrog | src_width *= 4;
|
749 | a171fe39 | balrog | else if (s->bpp > pxa_lcdc_8bpp) |
750 | a171fe39 | balrog | src_width *= 2;
|
751 | a171fe39 | balrog | |
752 | a171fe39 | balrog | dest_width = s->yres * s->dest_width; |
753 | a171fe39 | balrog | dest = s->ds->data + dest_width * (s->xres - 1);
|
754 | a171fe39 | balrog | |
755 | a171fe39 | balrog | addr = (ram_addr_t) (fb - phys_ram_base); |
756 | a171fe39 | balrog | start = addr + s->yres * src_width; |
757 | a171fe39 | balrog | end = addr; |
758 | a171fe39 | balrog | dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(start, VGA_DIRTY_FLAG); |
759 | a171fe39 | balrog | for (y = 0; y < s->yres; y ++) { |
760 | a171fe39 | balrog | new_addr = addr + src_width; |
761 | a171fe39 | balrog | for (x = addr + TARGET_PAGE_SIZE; x < new_addr;
|
762 | a171fe39 | balrog | x += TARGET_PAGE_SIZE) { |
763 | a171fe39 | balrog | dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
|
764 | a171fe39 | balrog | dirty[0] |= dirty[1]; |
765 | a171fe39 | balrog | } |
766 | a171fe39 | balrog | if (dirty[0] || s->invalidated) { |
767 | a171fe39 | balrog | fn((uint32_t *) s->dma_ch[0].palette,
|
768 | a171fe39 | balrog | dest, src, s->xres, -dest_width); |
769 | a171fe39 | balrog | if (addr < start)
|
770 | a171fe39 | balrog | start = addr; |
771 | 3f582262 | balrog | end = new_addr; |
772 | a171fe39 | balrog | if (y < *miny)
|
773 | a171fe39 | balrog | *miny = y; |
774 | a171fe39 | balrog | if (y >= *maxy)
|
775 | a171fe39 | balrog | *maxy = y + 1;
|
776 | a171fe39 | balrog | } |
777 | a171fe39 | balrog | addr = new_addr; |
778 | a171fe39 | balrog | dirty[0] = dirty[1]; |
779 | a171fe39 | balrog | src += src_width; |
780 | a171fe39 | balrog | dest += s->dest_width; |
781 | a171fe39 | balrog | } |
782 | a171fe39 | balrog | |
783 | a171fe39 | balrog | if (end > start)
|
784 | a171fe39 | balrog | cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG); |
785 | a171fe39 | balrog | } |
786 | a171fe39 | balrog | |
787 | a171fe39 | balrog | static void pxa2xx_lcdc_resize(struct pxa2xx_lcdc_s *s) |
788 | a171fe39 | balrog | { |
789 | a171fe39 | balrog | int width, height;
|
790 | a171fe39 | balrog | if (!(s->control[0] & LCCR0_ENB)) |
791 | a171fe39 | balrog | return;
|
792 | a171fe39 | balrog | |
793 | a171fe39 | balrog | width = LCCR1_PPL(s->control[1]) + 1; |
794 | a171fe39 | balrog | height = LCCR2_LPP(s->control[2]) + 1; |
795 | a171fe39 | balrog | |
796 | a171fe39 | balrog | if (width != s->xres || height != s->yres) {
|
797 | a171fe39 | balrog | if (s->orientation)
|
798 | c60e08d9 | pbrook | qemu_console_resize(s->console, height, width); |
799 | a171fe39 | balrog | else
|
800 | c60e08d9 | pbrook | qemu_console_resize(s->console, width, height); |
801 | a171fe39 | balrog | s->invalidated = 1;
|
802 | a171fe39 | balrog | s->xres = width; |
803 | a171fe39 | balrog | s->yres = height; |
804 | a171fe39 | balrog | } |
805 | a171fe39 | balrog | } |
806 | a171fe39 | balrog | |
807 | a171fe39 | balrog | static void pxa2xx_update_display(void *opaque) |
808 | a171fe39 | balrog | { |
809 | a171fe39 | balrog | struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
810 | a171fe39 | balrog | uint8_t *fb; |
811 | a171fe39 | balrog | target_phys_addr_t fbptr; |
812 | a171fe39 | balrog | int miny, maxy;
|
813 | a171fe39 | balrog | int ch;
|
814 | a171fe39 | balrog | if (!(s->control[0] & LCCR0_ENB)) |
815 | a171fe39 | balrog | return;
|
816 | a171fe39 | balrog | |
817 | a171fe39 | balrog | pxa2xx_descriptor_load(s); |
818 | a171fe39 | balrog | |
819 | a171fe39 | balrog | pxa2xx_lcdc_resize(s); |
820 | a171fe39 | balrog | miny = s->yres; |
821 | a171fe39 | balrog | maxy = 0;
|
822 | a171fe39 | balrog | s->transp = s->dma_ch[2].up || s->dma_ch[3].up; |
823 | a171fe39 | balrog | /* Note: With overlay planes the order depends on LCCR0 bit 25. */
|
824 | a171fe39 | balrog | for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++) |
825 | a171fe39 | balrog | if (s->dma_ch[ch].up) {
|
826 | a171fe39 | balrog | if (!s->dma_ch[ch].source) {
|
827 | a171fe39 | balrog | pxa2xx_dma_ber_set(s, ch); |
828 | a171fe39 | balrog | continue;
|
829 | a171fe39 | balrog | } |
830 | a171fe39 | balrog | fbptr = s->dma_ch[ch].source; |
831 | d95b2f8d | balrog | if (!(fbptr >= PXA2XX_SDRAM_BASE &&
|
832 | d95b2f8d | balrog | fbptr <= PXA2XX_SDRAM_BASE + phys_ram_size)) { |
833 | a171fe39 | balrog | pxa2xx_dma_ber_set(s, ch); |
834 | a171fe39 | balrog | continue;
|
835 | a171fe39 | balrog | } |
836 | d95b2f8d | balrog | fbptr -= PXA2XX_SDRAM_BASE; |
837 | a171fe39 | balrog | fb = phys_ram_base + fbptr; |
838 | a171fe39 | balrog | |
839 | a171fe39 | balrog | if (s->dma_ch[ch].command & LDCMD_PAL) {
|
840 | a171fe39 | balrog | memcpy(s->dma_ch[ch].pbuffer, fb, |
841 | a171fe39 | balrog | MAX(LDCMD_LENGTH(s->dma_ch[ch].command), |
842 | a171fe39 | balrog | sizeof(s->dma_ch[ch].pbuffer)));
|
843 | a171fe39 | balrog | pxa2xx_palette_parse(s, ch, s->bpp); |
844 | a171fe39 | balrog | } else {
|
845 | a171fe39 | balrog | /* Do we need to reparse palette */
|
846 | a171fe39 | balrog | if (LCCR4_PALFOR(s->control[4]) != s->pal_for) |
847 | a171fe39 | balrog | pxa2xx_palette_parse(s, ch, s->bpp); |
848 | a171fe39 | balrog | |
849 | a171fe39 | balrog | /* ACK frame start */
|
850 | a171fe39 | balrog | pxa2xx_dma_sof_set(s, ch); |
851 | a171fe39 | balrog | |
852 | a171fe39 | balrog | s->dma_ch[ch].redraw(s, fb, &miny, &maxy); |
853 | a171fe39 | balrog | s->invalidated = 0;
|
854 | a171fe39 | balrog | |
855 | a171fe39 | balrog | /* ACK frame completed */
|
856 | a171fe39 | balrog | pxa2xx_dma_eof_set(s, ch); |
857 | a171fe39 | balrog | } |
858 | a171fe39 | balrog | } |
859 | a171fe39 | balrog | |
860 | a171fe39 | balrog | if (s->control[0] & LCCR0_DIS) { |
861 | a171fe39 | balrog | /* ACK last frame completed */
|
862 | a171fe39 | balrog | s->control[0] &= ~LCCR0_ENB;
|
863 | a171fe39 | balrog | s->status[0] |= LCSR0_LDD;
|
864 | a171fe39 | balrog | } |
865 | a171fe39 | balrog | |
866 | a171fe39 | balrog | if (s->orientation)
|
867 | a171fe39 | balrog | dpy_update(s->ds, miny, 0, maxy, s->xres);
|
868 | a171fe39 | balrog | else
|
869 | a171fe39 | balrog | dpy_update(s->ds, 0, miny, s->xres, maxy);
|
870 | a171fe39 | balrog | pxa2xx_lcdc_int_update(s); |
871 | a171fe39 | balrog | |
872 | 38641a52 | balrog | qemu_irq_raise(s->vsync_cb); |
873 | a171fe39 | balrog | } |
874 | a171fe39 | balrog | |
875 | a171fe39 | balrog | static void pxa2xx_invalidate_display(void *opaque) |
876 | a171fe39 | balrog | { |
877 | a171fe39 | balrog | struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
878 | a171fe39 | balrog | s->invalidated = 1;
|
879 | a171fe39 | balrog | } |
880 | a171fe39 | balrog | |
881 | a171fe39 | balrog | static void pxa2xx_screen_dump(void *opaque, const char *filename) |
882 | a171fe39 | balrog | { |
883 | a171fe39 | balrog | /* TODO */
|
884 | a171fe39 | balrog | } |
885 | a171fe39 | balrog | |
886 | 9596ebb7 | pbrook | static void pxa2xx_lcdc_orientation(void *opaque, int angle) |
887 | a171fe39 | balrog | { |
888 | a171fe39 | balrog | struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
889 | a171fe39 | balrog | |
890 | a171fe39 | balrog | if (angle) {
|
891 | a171fe39 | balrog | s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_vert;
|
892 | a171fe39 | balrog | } else {
|
893 | a171fe39 | balrog | s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_horiz;
|
894 | a171fe39 | balrog | } |
895 | a171fe39 | balrog | |
896 | a171fe39 | balrog | s->orientation = angle; |
897 | a171fe39 | balrog | s->xres = s->yres = -1;
|
898 | a171fe39 | balrog | pxa2xx_lcdc_resize(s); |
899 | a171fe39 | balrog | } |
900 | a171fe39 | balrog | |
901 | aa941b94 | balrog | static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque) |
902 | aa941b94 | balrog | { |
903 | aa941b94 | balrog | struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
904 | aa941b94 | balrog | int i;
|
905 | aa941b94 | balrog | |
906 | aa941b94 | balrog | qemu_put_be32(f, s->irqlevel); |
907 | aa941b94 | balrog | qemu_put_be32(f, s->transp); |
908 | aa941b94 | balrog | |
909 | aa941b94 | balrog | for (i = 0; i < 6; i ++) |
910 | aa941b94 | balrog | qemu_put_be32s(f, &s->control[i]); |
911 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
912 | aa941b94 | balrog | qemu_put_be32s(f, &s->status[i]); |
913 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
914 | aa941b94 | balrog | qemu_put_be32s(f, &s->ovl1c[i]); |
915 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
916 | aa941b94 | balrog | qemu_put_be32s(f, &s->ovl2c[i]); |
917 | aa941b94 | balrog | qemu_put_be32s(f, &s->ccr); |
918 | aa941b94 | balrog | qemu_put_be32s(f, &s->cmdcr); |
919 | aa941b94 | balrog | qemu_put_be32s(f, &s->trgbr); |
920 | aa941b94 | balrog | qemu_put_be32s(f, &s->tcr); |
921 | aa941b94 | balrog | qemu_put_be32s(f, &s->liidr); |
922 | aa941b94 | balrog | qemu_put_8s(f, &s->bscntr); |
923 | aa941b94 | balrog | |
924 | aa941b94 | balrog | for (i = 0; i < 7; i ++) { |
925 | aa941b94 | balrog | qemu_put_betl(f, s->dma_ch[i].branch); |
926 | aa941b94 | balrog | qemu_put_byte(f, s->dma_ch[i].up); |
927 | aa941b94 | balrog | qemu_put_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
|
928 | aa941b94 | balrog | |
929 | aa941b94 | balrog | qemu_put_betl(f, s->dma_ch[i].descriptor); |
930 | aa941b94 | balrog | qemu_put_betl(f, s->dma_ch[i].source); |
931 | aa941b94 | balrog | qemu_put_be32s(f, &s->dma_ch[i].id); |
932 | aa941b94 | balrog | qemu_put_be32s(f, &s->dma_ch[i].command); |
933 | aa941b94 | balrog | } |
934 | aa941b94 | balrog | } |
935 | aa941b94 | balrog | |
936 | aa941b94 | balrog | static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id) |
937 | aa941b94 | balrog | { |
938 | aa941b94 | balrog | struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
939 | aa941b94 | balrog | int i;
|
940 | aa941b94 | balrog | |
941 | aa941b94 | balrog | s->irqlevel = qemu_get_be32(f); |
942 | aa941b94 | balrog | s->transp = qemu_get_be32(f); |
943 | aa941b94 | balrog | |
944 | aa941b94 | balrog | for (i = 0; i < 6; i ++) |
945 | aa941b94 | balrog | qemu_get_be32s(f, &s->control[i]); |
946 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
947 | aa941b94 | balrog | qemu_get_be32s(f, &s->status[i]); |
948 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
949 | aa941b94 | balrog | qemu_get_be32s(f, &s->ovl1c[i]); |
950 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
951 | aa941b94 | balrog | qemu_get_be32s(f, &s->ovl2c[i]); |
952 | aa941b94 | balrog | qemu_get_be32s(f, &s->ccr); |
953 | aa941b94 | balrog | qemu_get_be32s(f, &s->cmdcr); |
954 | aa941b94 | balrog | qemu_get_be32s(f, &s->trgbr); |
955 | aa941b94 | balrog | qemu_get_be32s(f, &s->tcr); |
956 | aa941b94 | balrog | qemu_get_be32s(f, &s->liidr); |
957 | aa941b94 | balrog | qemu_get_8s(f, &s->bscntr); |
958 | aa941b94 | balrog | |
959 | aa941b94 | balrog | for (i = 0; i < 7; i ++) { |
960 | aa941b94 | balrog | s->dma_ch[i].branch = qemu_get_betl(f); |
961 | aa941b94 | balrog | s->dma_ch[i].up = qemu_get_byte(f); |
962 | aa941b94 | balrog | qemu_get_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
|
963 | aa941b94 | balrog | |
964 | aa941b94 | balrog | s->dma_ch[i].descriptor = qemu_get_betl(f); |
965 | aa941b94 | balrog | s->dma_ch[i].source = qemu_get_betl(f); |
966 | aa941b94 | balrog | qemu_get_be32s(f, &s->dma_ch[i].id); |
967 | aa941b94 | balrog | qemu_get_be32s(f, &s->dma_ch[i].command); |
968 | aa941b94 | balrog | } |
969 | aa941b94 | balrog | |
970 | aa941b94 | balrog | s->bpp = LCCR3_BPP(s->control[3]);
|
971 | aa941b94 | balrog | s->xres = s->yres = s->pal_for = -1;
|
972 | aa941b94 | balrog | |
973 | aa941b94 | balrog | return 0; |
974 | aa941b94 | balrog | } |
975 | aa941b94 | balrog | |
976 | a171fe39 | balrog | #define BITS 8 |
977 | a171fe39 | balrog | #include "pxa2xx_template.h" |
978 | a171fe39 | balrog | #define BITS 15 |
979 | a171fe39 | balrog | #include "pxa2xx_template.h" |
980 | a171fe39 | balrog | #define BITS 16 |
981 | a171fe39 | balrog | #include "pxa2xx_template.h" |
982 | a171fe39 | balrog | #define BITS 24 |
983 | a171fe39 | balrog | #include "pxa2xx_template.h" |
984 | a171fe39 | balrog | #define BITS 32 |
985 | a171fe39 | balrog | #include "pxa2xx_template.h" |
986 | a171fe39 | balrog | |
987 | a171fe39 | balrog | struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq,
|
988 | a171fe39 | balrog | DisplayState *ds) |
989 | a171fe39 | balrog | { |
990 | a171fe39 | balrog | int iomemtype;
|
991 | a171fe39 | balrog | struct pxa2xx_lcdc_s *s;
|
992 | a171fe39 | balrog | |
993 | a171fe39 | balrog | s = (struct pxa2xx_lcdc_s *) qemu_mallocz(sizeof(struct pxa2xx_lcdc_s)); |
994 | a171fe39 | balrog | s->base = base; |
995 | a171fe39 | balrog | s->invalidated = 1;
|
996 | a171fe39 | balrog | s->irq = irq; |
997 | a171fe39 | balrog | s->ds = ds; |
998 | a171fe39 | balrog | |
999 | a171fe39 | balrog | pxa2xx_lcdc_orientation(s, graphic_rotate); |
1000 | a171fe39 | balrog | |
1001 | a171fe39 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_lcdc_readfn,
|
1002 | a171fe39 | balrog | pxa2xx_lcdc_writefn, s); |
1003 | 187337f8 | pbrook | cpu_register_physical_memory(base, 0x00100000, iomemtype);
|
1004 | a171fe39 | balrog | |
1005 | c60e08d9 | pbrook | s->console = graphic_console_init(ds, pxa2xx_update_display, |
1006 | c60e08d9 | pbrook | pxa2xx_invalidate_display, |
1007 | c60e08d9 | pbrook | pxa2xx_screen_dump, NULL, s);
|
1008 | a171fe39 | balrog | |
1009 | a171fe39 | balrog | switch (s->ds->depth) {
|
1010 | a171fe39 | balrog | case 0: |
1011 | a171fe39 | balrog | s->dest_width = 0;
|
1012 | a171fe39 | balrog | break;
|
1013 | a171fe39 | balrog | case 8: |
1014 | a171fe39 | balrog | s->line_fn[0] = pxa2xx_draw_fn_8;
|
1015 | a171fe39 | balrog | s->line_fn[1] = pxa2xx_draw_fn_8t;
|
1016 | a171fe39 | balrog | s->dest_width = 1;
|
1017 | a171fe39 | balrog | break;
|
1018 | a171fe39 | balrog | case 15: |
1019 | a171fe39 | balrog | s->line_fn[0] = pxa2xx_draw_fn_15;
|
1020 | a171fe39 | balrog | s->line_fn[1] = pxa2xx_draw_fn_15t;
|
1021 | a171fe39 | balrog | s->dest_width = 2;
|
1022 | a171fe39 | balrog | break;
|
1023 | a171fe39 | balrog | case 16: |
1024 | a171fe39 | balrog | s->line_fn[0] = pxa2xx_draw_fn_16;
|
1025 | a171fe39 | balrog | s->line_fn[1] = pxa2xx_draw_fn_16t;
|
1026 | a171fe39 | balrog | s->dest_width = 2;
|
1027 | a171fe39 | balrog | break;
|
1028 | a171fe39 | balrog | case 24: |
1029 | a171fe39 | balrog | s->line_fn[0] = pxa2xx_draw_fn_24;
|
1030 | a171fe39 | balrog | s->line_fn[1] = pxa2xx_draw_fn_24t;
|
1031 | a171fe39 | balrog | s->dest_width = 3;
|
1032 | a171fe39 | balrog | break;
|
1033 | a171fe39 | balrog | case 32: |
1034 | a171fe39 | balrog | s->line_fn[0] = pxa2xx_draw_fn_32;
|
1035 | a171fe39 | balrog | s->line_fn[1] = pxa2xx_draw_fn_32t;
|
1036 | a171fe39 | balrog | s->dest_width = 4;
|
1037 | a171fe39 | balrog | break;
|
1038 | a171fe39 | balrog | default:
|
1039 | a171fe39 | balrog | fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
|
1040 | a171fe39 | balrog | exit(1);
|
1041 | a171fe39 | balrog | } |
1042 | aa941b94 | balrog | |
1043 | aa941b94 | balrog | register_savevm("pxa2xx_lcdc", 0, 0, |
1044 | aa941b94 | balrog | pxa2xx_lcdc_save, pxa2xx_lcdc_load, s); |
1045 | aa941b94 | balrog | |
1046 | a171fe39 | balrog | return s;
|
1047 | a171fe39 | balrog | } |
1048 | a171fe39 | balrog | |
1049 | 38641a52 | balrog | void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler) |
1050 | 38641a52 | balrog | { |
1051 | 38641a52 | balrog | s->vsync_cb = handler; |
1052 | a171fe39 | balrog | } |