root / hw / realview_gic.c @ c701b35b
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1 | 9ee6e8bb | pbrook | /*
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2 | 9ee6e8bb | pbrook | * ARM RealView Emulation Baseboard Interrupt Controller
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3 | 9ee6e8bb | pbrook | *
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4 | 9ee6e8bb | pbrook | * Copyright (c) 2006-2007 CodeSourcery.
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5 | 9ee6e8bb | pbrook | * Written by Paul Brook
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6 | 9ee6e8bb | pbrook | *
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7 | 9ee6e8bb | pbrook | * This code is licenced under the GPL.
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8 | 9ee6e8bb | pbrook | */
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9 | 9ee6e8bb | pbrook | |
10 | 87ecb68b | pbrook | #include "hw.h" |
11 | 9596ebb7 | pbrook | #include "primecell.h" |
12 | 9ee6e8bb | pbrook | |
13 | 9ee6e8bb | pbrook | #define GIC_NIRQ 96 |
14 | 9ee6e8bb | pbrook | #define NCPU 1 |
15 | 9ee6e8bb | pbrook | |
16 | 9ee6e8bb | pbrook | /* Only a single "CPU" interface is present. */
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17 | 9ee6e8bb | pbrook | static inline int |
18 | 9ee6e8bb | pbrook | gic_get_current_cpu(void)
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19 | 9ee6e8bb | pbrook | { |
20 | 9ee6e8bb | pbrook | return 0; |
21 | 9ee6e8bb | pbrook | } |
22 | 9ee6e8bb | pbrook | |
23 | 9ee6e8bb | pbrook | #include "arm_gic.c" |
24 | 9ee6e8bb | pbrook | |
25 | 9ee6e8bb | pbrook | static uint32_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset) |
26 | 9ee6e8bb | pbrook | { |
27 | 9ee6e8bb | pbrook | gic_state *s = (gic_state *)opaque; |
28 | 9ee6e8bb | pbrook | offset -= s->base; |
29 | 9ee6e8bb | pbrook | return gic_cpu_read(s, gic_get_current_cpu(), offset);
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30 | 9ee6e8bb | pbrook | } |
31 | 9ee6e8bb | pbrook | |
32 | 9ee6e8bb | pbrook | static void realview_gic_cpu_write(void *opaque, target_phys_addr_t offset, |
33 | 9ee6e8bb | pbrook | uint32_t value) |
34 | 9ee6e8bb | pbrook | { |
35 | 9ee6e8bb | pbrook | gic_state *s = (gic_state *)opaque; |
36 | 9ee6e8bb | pbrook | offset -= s->base; |
37 | 9ee6e8bb | pbrook | gic_cpu_write(s, gic_get_current_cpu(), offset, value); |
38 | 9ee6e8bb | pbrook | } |
39 | 9ee6e8bb | pbrook | |
40 | 9ee6e8bb | pbrook | static CPUReadMemoryFunc *realview_gic_cpu_readfn[] = {
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41 | 9ee6e8bb | pbrook | realview_gic_cpu_read, |
42 | 9ee6e8bb | pbrook | realview_gic_cpu_read, |
43 | 9ee6e8bb | pbrook | realview_gic_cpu_read |
44 | 9ee6e8bb | pbrook | }; |
45 | 9ee6e8bb | pbrook | |
46 | 9ee6e8bb | pbrook | static CPUWriteMemoryFunc *realview_gic_cpu_writefn[] = {
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47 | 9ee6e8bb | pbrook | realview_gic_cpu_write, |
48 | 9ee6e8bb | pbrook | realview_gic_cpu_write, |
49 | 9ee6e8bb | pbrook | realview_gic_cpu_write |
50 | 9ee6e8bb | pbrook | }; |
51 | 9ee6e8bb | pbrook | |
52 | 9ee6e8bb | pbrook | qemu_irq *realview_gic_init(uint32_t base, qemu_irq parent_irq) |
53 | 9ee6e8bb | pbrook | { |
54 | 9ee6e8bb | pbrook | gic_state *s; |
55 | 9ee6e8bb | pbrook | int iomemtype;
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56 | 9ee6e8bb | pbrook | |
57 | 9ee6e8bb | pbrook | s = gic_init(base, &parent_irq); |
58 | 9ee6e8bb | pbrook | if (!s)
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59 | 9ee6e8bb | pbrook | return NULL; |
60 | 9ee6e8bb | pbrook | iomemtype = cpu_register_io_memory(0, realview_gic_cpu_readfn,
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61 | 9ee6e8bb | pbrook | realview_gic_cpu_writefn, s); |
62 | 9ee6e8bb | pbrook | cpu_register_physical_memory(base, 0x00001000, iomemtype);
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63 | 9ee6e8bb | pbrook | return s->in;
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64 | 9ee6e8bb | pbrook | } |