root / hw / ds1225y.c @ c75a823c
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1 | 30aa5c0d | aurel32 | /*
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2 | 30aa5c0d | aurel32 | * QEMU NVRAM emulation for DS1225Y chip
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3 | 02cb1585 | aurel32 | *
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4 | 02cb1585 | aurel32 | * Copyright (c) 2007-2008 Herv? Poussineau
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5 | 02cb1585 | aurel32 | *
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6 | 30aa5c0d | aurel32 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 30aa5c0d | aurel32 | * of this software and associated documentation files (the "Software"), to deal
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8 | 30aa5c0d | aurel32 | * in the Software without restriction, including without limitation the rights
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9 | 30aa5c0d | aurel32 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 30aa5c0d | aurel32 | * copies of the Software, and to permit persons to whom the Software is
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11 | 30aa5c0d | aurel32 | * furnished to do so, subject to the following conditions:
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12 | 30aa5c0d | aurel32 | *
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13 | 30aa5c0d | aurel32 | * The above copyright notice and this permission notice shall be included in
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14 | 30aa5c0d | aurel32 | * all copies or substantial portions of the Software.
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15 | 30aa5c0d | aurel32 | *
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16 | 30aa5c0d | aurel32 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 30aa5c0d | aurel32 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 30aa5c0d | aurel32 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 30aa5c0d | aurel32 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 30aa5c0d | aurel32 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 30aa5c0d | aurel32 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 30aa5c0d | aurel32 | * THE SOFTWARE.
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23 | 30aa5c0d | aurel32 | */
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24 | 30aa5c0d | aurel32 | |
25 | 30aa5c0d | aurel32 | #include "hw.h" |
26 | 30aa5c0d | aurel32 | #include "mips.h" |
27 | 30aa5c0d | aurel32 | #include "nvram.h" |
28 | 30aa5c0d | aurel32 | |
29 | 02cb1585 | aurel32 | //#define DEBUG_NVRAM
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30 | 30aa5c0d | aurel32 | |
31 | 02cb1585 | aurel32 | typedef struct ds1225y_t |
32 | 30aa5c0d | aurel32 | { |
33 | 30aa5c0d | aurel32 | target_phys_addr_t mem_base; |
34 | 02cb1585 | aurel32 | uint32_t chip_size; |
35 | 30aa5c0d | aurel32 | QEMUFile *file; |
36 | 02cb1585 | aurel32 | uint8_t *contents; |
37 | 02cb1585 | aurel32 | uint8_t protection; |
38 | 02cb1585 | aurel32 | } ds1225y_t; |
39 | 30aa5c0d | aurel32 | |
40 | 30aa5c0d | aurel32 | |
41 | 30aa5c0d | aurel32 | static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) |
42 | 30aa5c0d | aurel32 | { |
43 | 02cb1585 | aurel32 | ds1225y_t *s = opaque; |
44 | 30aa5c0d | aurel32 | int64_t pos; |
45 | 02cb1585 | aurel32 | uint32_t val; |
46 | 02cb1585 | aurel32 | |
47 | 02cb1585 | aurel32 | pos = addr - s->mem_base; |
48 | 02cb1585 | aurel32 | if (pos >= s->chip_size)
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49 | 02cb1585 | aurel32 | pos -= s->chip_size; |
50 | 02cb1585 | aurel32 | |
51 | 02cb1585 | aurel32 | val = s->contents[pos]; |
52 | 02cb1585 | aurel32 | |
53 | 02cb1585 | aurel32 | #ifdef DEBUG_NVRAM
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54 | 02cb1585 | aurel32 | printf("nvram: read 0x%x at " TARGET_FMT_lx "\n", val, addr); |
55 | 02cb1585 | aurel32 | #endif
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56 | 02cb1585 | aurel32 | return val;
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57 | 02cb1585 | aurel32 | } |
58 | 30aa5c0d | aurel32 | |
59 | 02cb1585 | aurel32 | static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) |
60 | 02cb1585 | aurel32 | { |
61 | 02cb1585 | aurel32 | uint32_t v; |
62 | 02cb1585 | aurel32 | v = nvram_readb(opaque, addr); |
63 | 02cb1585 | aurel32 | v |= nvram_readb(opaque, addr + 1) << 8; |
64 | 02cb1585 | aurel32 | return v;
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65 | 02cb1585 | aurel32 | } |
66 | 30aa5c0d | aurel32 | |
67 | 02cb1585 | aurel32 | static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) |
68 | 02cb1585 | aurel32 | { |
69 | 02cb1585 | aurel32 | uint32_t v; |
70 | 02cb1585 | aurel32 | v = nvram_readb(opaque, addr); |
71 | 02cb1585 | aurel32 | v |= nvram_readb(opaque, addr + 1) << 8; |
72 | 02cb1585 | aurel32 | v |= nvram_readb(opaque, addr + 2) << 16; |
73 | 02cb1585 | aurel32 | v |= nvram_readb(opaque, addr + 3) << 24; |
74 | 02cb1585 | aurel32 | return v;
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75 | 30aa5c0d | aurel32 | } |
76 | 30aa5c0d | aurel32 | |
77 | 02cb1585 | aurel32 | static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val) |
78 | 30aa5c0d | aurel32 | { |
79 | 02cb1585 | aurel32 | ds1225y_t *s = opaque; |
80 | 30aa5c0d | aurel32 | int64_t pos; |
81 | 30aa5c0d | aurel32 | |
82 | 02cb1585 | aurel32 | #ifdef DEBUG_NVRAM
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83 | 02cb1585 | aurel32 | printf("nvram: write 0x%x at " TARGET_FMT_lx "\n", val, addr); |
84 | 02cb1585 | aurel32 | #endif
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85 | 02cb1585 | aurel32 | |
86 | 02cb1585 | aurel32 | pos = addr - s->mem_base; |
87 | 02cb1585 | aurel32 | s->contents[pos] = val & 0xff;
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88 | 02cb1585 | aurel32 | if (s->file) {
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89 | 02cb1585 | aurel32 | qemu_fseek(s->file, pos, SEEK_SET); |
90 | 02cb1585 | aurel32 | qemu_put_byte(s->file, (int)val);
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91 | 02cb1585 | aurel32 | qemu_fflush(s->file); |
92 | 30aa5c0d | aurel32 | } |
93 | 30aa5c0d | aurel32 | } |
94 | 30aa5c0d | aurel32 | |
95 | 02cb1585 | aurel32 | static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t val) |
96 | 02cb1585 | aurel32 | { |
97 | 02cb1585 | aurel32 | nvram_writeb(opaque, addr, val & 0xff);
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98 | 02cb1585 | aurel32 | nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
99 | 02cb1585 | aurel32 | } |
100 | 02cb1585 | aurel32 | |
101 | 02cb1585 | aurel32 | static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t val) |
102 | 02cb1585 | aurel32 | { |
103 | 02cb1585 | aurel32 | nvram_writeb(opaque, addr, val & 0xff);
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104 | 02cb1585 | aurel32 | nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
105 | 02cb1585 | aurel32 | nvram_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
106 | 02cb1585 | aurel32 | nvram_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
107 | 02cb1585 | aurel32 | } |
108 | 02cb1585 | aurel32 | |
109 | 02cb1585 | aurel32 | static void nvram_writeb_protected (void *opaque, target_phys_addr_t addr, uint32_t val) |
110 | 02cb1585 | aurel32 | { |
111 | 02cb1585 | aurel32 | ds1225y_t *s = opaque; |
112 | 02cb1585 | aurel32 | |
113 | 02cb1585 | aurel32 | if (s->protection != 7) { |
114 | 02cb1585 | aurel32 | #ifdef DEBUG_NVRAM
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115 | 02cb1585 | aurel32 | printf("nvram: prevent write of 0x%x at " TARGET_FMT_lx "\n", val, addr); |
116 | 02cb1585 | aurel32 | #endif
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117 | 02cb1585 | aurel32 | return;
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118 | 02cb1585 | aurel32 | } |
119 | 02cb1585 | aurel32 | |
120 | 02cb1585 | aurel32 | nvram_writeb(opaque, addr - s->chip_size, val); |
121 | 02cb1585 | aurel32 | } |
122 | 02cb1585 | aurel32 | |
123 | 02cb1585 | aurel32 | static void nvram_writew_protected (void *opaque, target_phys_addr_t addr, uint32_t val) |
124 | 02cb1585 | aurel32 | { |
125 | 02cb1585 | aurel32 | nvram_writeb_protected(opaque, addr, val & 0xff);
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126 | 02cb1585 | aurel32 | nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff); |
127 | 02cb1585 | aurel32 | } |
128 | 02cb1585 | aurel32 | |
129 | 02cb1585 | aurel32 | static void nvram_writel_protected (void *opaque, target_phys_addr_t addr, uint32_t val) |
130 | 02cb1585 | aurel32 | { |
131 | 02cb1585 | aurel32 | nvram_writeb_protected(opaque, addr, val & 0xff);
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132 | 02cb1585 | aurel32 | nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff); |
133 | 02cb1585 | aurel32 | nvram_writeb_protected(opaque, addr + 2, (val >> 16) & 0xff); |
134 | 02cb1585 | aurel32 | nvram_writeb_protected(opaque, addr + 3, (val >> 24) & 0xff); |
135 | 02cb1585 | aurel32 | } |
136 | 02cb1585 | aurel32 | |
137 | 30aa5c0d | aurel32 | static CPUReadMemoryFunc *nvram_read[] = {
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138 | 30aa5c0d | aurel32 | &nvram_readb, |
139 | 02cb1585 | aurel32 | &nvram_readw, |
140 | 02cb1585 | aurel32 | &nvram_readl, |
141 | 30aa5c0d | aurel32 | }; |
142 | 30aa5c0d | aurel32 | |
143 | 30aa5c0d | aurel32 | static CPUWriteMemoryFunc *nvram_write[] = {
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144 | 30aa5c0d | aurel32 | &nvram_writeb, |
145 | 02cb1585 | aurel32 | &nvram_writew, |
146 | 02cb1585 | aurel32 | &nvram_writel, |
147 | 30aa5c0d | aurel32 | }; |
148 | 30aa5c0d | aurel32 | |
149 | 02cb1585 | aurel32 | static CPUWriteMemoryFunc *nvram_write_protected[] = {
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150 | 02cb1585 | aurel32 | &nvram_writeb_protected, |
151 | 02cb1585 | aurel32 | &nvram_writew_protected, |
152 | 02cb1585 | aurel32 | &nvram_writel_protected, |
153 | 30aa5c0d | aurel32 | }; |
154 | 30aa5c0d | aurel32 | |
155 | 30aa5c0d | aurel32 | /* Initialisation routine */
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156 | 02cb1585 | aurel32 | void *ds1225y_init(target_phys_addr_t mem_base, const char *filename) |
157 | 30aa5c0d | aurel32 | { |
158 | 30aa5c0d | aurel32 | ds1225y_t *s; |
159 | 02cb1585 | aurel32 | int mem_indexRW, mem_indexRP;
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160 | 02cb1585 | aurel32 | QEMUFile *file; |
161 | 30aa5c0d | aurel32 | |
162 | 30aa5c0d | aurel32 | s = qemu_mallocz(sizeof(ds1225y_t));
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163 | 30aa5c0d | aurel32 | if (!s)
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164 | 30aa5c0d | aurel32 | return NULL; |
165 | 02cb1585 | aurel32 | s->chip_size = 0x2000; /* Fixed for ds1225y chip: 8 KiB */ |
166 | 02cb1585 | aurel32 | s->contents = qemu_mallocz(s->chip_size); |
167 | 02cb1585 | aurel32 | if (!s->contents) {
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168 | 02cb1585 | aurel32 | return NULL; |
169 | 02cb1585 | aurel32 | } |
170 | 30aa5c0d | aurel32 | s->mem_base = mem_base; |
171 | 02cb1585 | aurel32 | s->protection = 7;
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172 | 02cb1585 | aurel32 | |
173 | 02cb1585 | aurel32 | /* Read current file */
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174 | 02cb1585 | aurel32 | file = qemu_fopen(filename, "rb");
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175 | 02cb1585 | aurel32 | if (file) {
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176 | 02cb1585 | aurel32 | /* Read nvram contents */
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177 | 02cb1585 | aurel32 | qemu_get_buffer(file, s->contents, s->chip_size); |
178 | 02cb1585 | aurel32 | qemu_fclose(file); |
179 | 02cb1585 | aurel32 | } |
180 | 02cb1585 | aurel32 | s->file = qemu_fopen(filename, "wb");
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181 | 02cb1585 | aurel32 | if (s->file) {
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182 | 02cb1585 | aurel32 | /* Write back contents, as 'wb' mode cleaned the file */
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183 | 02cb1585 | aurel32 | qemu_put_buffer(s->file, s->contents, s->chip_size); |
184 | 02cb1585 | aurel32 | qemu_fflush(s->file); |
185 | 02cb1585 | aurel32 | } |
186 | 30aa5c0d | aurel32 | |
187 | 30aa5c0d | aurel32 | /* Read/write memory */
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188 | 02cb1585 | aurel32 | mem_indexRW = cpu_register_io_memory(0, nvram_read, nvram_write, s);
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189 | 02cb1585 | aurel32 | cpu_register_physical_memory(mem_base, s->chip_size, mem_indexRW); |
190 | 02cb1585 | aurel32 | /* Read/write protected memory */
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191 | 02cb1585 | aurel32 | mem_indexRP = cpu_register_io_memory(0, nvram_read, nvram_write_protected, s);
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192 | 02cb1585 | aurel32 | cpu_register_physical_memory(mem_base + s->chip_size, s->chip_size, mem_indexRP); |
193 | 30aa5c0d | aurel32 | return s;
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194 | 30aa5c0d | aurel32 | } |