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1 | ef056e43 | balrog | /*
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2 | ef056e43 | balrog | * PXA270-based Intel Mainstone platforms.
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3 | ef056e43 | balrog | *
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4 | ef056e43 | balrog | * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
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5 | ef056e43 | balrog | * <akuster@mvista.com>
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6 | ef056e43 | balrog | *
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7 | ef056e43 | balrog | * Code based on spitz platform by Andrzej Zaborowski <balrog@zabor.org>
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8 | ef056e43 | balrog | *
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9 | ef056e43 | balrog | * This code is licensed under the GNU GPL v2.
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10 | ef056e43 | balrog | */
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11 | ef056e43 | balrog | #include "hw.h" |
12 | ef056e43 | balrog | #include "pxa.h" |
13 | ef056e43 | balrog | #include "arm-misc.h" |
14 | ef056e43 | balrog | #include "net.h" |
15 | ef056e43 | balrog | #include "devices.h" |
16 | ef056e43 | balrog | #include "boards.h" |
17 | 7233b355 | ths | #include "mainstone.h" |
18 | 7233b355 | ths | #include "sysemu.h" |
19 | 7233b355 | ths | #include "flash.h" |
20 | ef056e43 | balrog | |
21 | bd464c2e | balrog | static struct keymap map[0xE0] = { |
22 | bd464c2e | balrog | [0 ... 0xDF] = { -1, -1 }, |
23 | bd464c2e | balrog | [0x1e] = {0,0}, /* a */ |
24 | bd464c2e | balrog | [0x30] = {0,1}, /* b */ |
25 | bd464c2e | balrog | [0x2e] = {0,2}, /* c */ |
26 | bd464c2e | balrog | [0x20] = {0,3}, /* d */ |
27 | bd464c2e | balrog | [0x12] = {0,4}, /* e */ |
28 | bd464c2e | balrog | [0x21] = {0,5}, /* f */ |
29 | bd464c2e | balrog | [0x22] = {1,0}, /* g */ |
30 | bd464c2e | balrog | [0x23] = {1,1}, /* h */ |
31 | bd464c2e | balrog | [0x17] = {1,2}, /* i */ |
32 | bd464c2e | balrog | [0x24] = {1,3}, /* j */ |
33 | bd464c2e | balrog | [0x25] = {1,4}, /* k */ |
34 | bd464c2e | balrog | [0x26] = {1,5}, /* l */ |
35 | bd464c2e | balrog | [0x32] = {2,0}, /* m */ |
36 | bd464c2e | balrog | [0x31] = {2,1}, /* n */ |
37 | bd464c2e | balrog | [0x18] = {2,2}, /* o */ |
38 | bd464c2e | balrog | [0x19] = {2,3}, /* p */ |
39 | bd464c2e | balrog | [0x10] = {2,4}, /* q */ |
40 | bd464c2e | balrog | [0x13] = {2,5}, /* r */ |
41 | bd464c2e | balrog | [0x1f] = {3,0}, /* s */ |
42 | bd464c2e | balrog | [0x14] = {3,1}, /* t */ |
43 | bd464c2e | balrog | [0x16] = {3,2}, /* u */ |
44 | bd464c2e | balrog | [0x2f] = {3,3}, /* v */ |
45 | bd464c2e | balrog | [0x11] = {3,4}, /* w */ |
46 | bd464c2e | balrog | [0x2d] = {3,5}, /* x */ |
47 | bd464c2e | balrog | [0x15] = {4,2}, /* y */ |
48 | bd464c2e | balrog | [0x2c] = {4,3}, /* z */ |
49 | bd464c2e | balrog | [0xc7] = {5,0}, /* Home */ |
50 | bd464c2e | balrog | [0x2a] = {5,1}, /* shift */ |
51 | bd464c2e | balrog | [0x39] = {5,2}, /* space */ |
52 | bd464c2e | balrog | [0x39] = {5,3}, /* space */ |
53 | bd464c2e | balrog | [0x1c] = {5,5}, /* enter */ |
54 | bd464c2e | balrog | [0xc8] = {6,0}, /* up */ |
55 | bd464c2e | balrog | [0xd0] = {6,1}, /* down */ |
56 | bd464c2e | balrog | [0xcb] = {6,2}, /* left */ |
57 | bd464c2e | balrog | [0xcd] = {6,3}, /* right */ |
58 | bd464c2e | balrog | }; |
59 | bd464c2e | balrog | |
60 | ef056e43 | balrog | enum mainstone_model_e { mainstone };
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61 | ef056e43 | balrog | |
62 | 7fb4fdcf | balrog | #define MAINSTONE_RAM 0x04000000 |
63 | 7fb4fdcf | balrog | #define MAINSTONE_ROM 0x00800000 |
64 | 7fb4fdcf | balrog | #define MAINSTONE_FLASH 0x02000000 |
65 | 7fb4fdcf | balrog | |
66 | f93eb9ff | balrog | static struct arm_boot_info mainstone_binfo = { |
67 | f93eb9ff | balrog | .loader_start = PXA2XX_SDRAM_BASE, |
68 | f93eb9ff | balrog | .ram_size = 0x04000000,
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69 | f93eb9ff | balrog | }; |
70 | f93eb9ff | balrog | |
71 | 00f82b8a | aurel32 | static void mainstone_common_init(ram_addr_t ram_size, int vga_ram_size, |
72 | ef056e43 | balrog | DisplayState *ds, const char *kernel_filename, |
73 | ef056e43 | balrog | const char *kernel_cmdline, const char *initrd_filename, |
74 | ef056e43 | balrog | const char *cpu_model, enum mainstone_model_e model, int arm_id) |
75 | ef056e43 | balrog | { |
76 | 6d1f1778 | balrog | uint32_t sector_len = 256 * 1024; |
77 | 6d1f1778 | balrog | target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 }; |
78 | ef056e43 | balrog | struct pxa2xx_state_s *cpu;
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79 | ef056e43 | balrog | qemu_irq *mst_irq; |
80 | 6d1f1778 | balrog | int i, index;
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81 | ef056e43 | balrog | |
82 | ef056e43 | balrog | if (!cpu_model)
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83 | ef056e43 | balrog | cpu_model = "pxa270-c5";
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84 | ef056e43 | balrog | |
85 | ef056e43 | balrog | /* Setup CPU & memory */
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86 | 7fb4fdcf | balrog | if (ram_size < MAINSTONE_RAM + MAINSTONE_ROM + 2 * MAINSTONE_FLASH + |
87 | 6d1f1778 | balrog | PXA2XX_INTERNAL_SIZE) { |
88 | ef056e43 | balrog | fprintf(stderr, "This platform requires %i bytes of memory\n",
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89 | 7fb4fdcf | balrog | MAINSTONE_RAM + MAINSTONE_ROM + 2 * MAINSTONE_FLASH +
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90 | 6d1f1778 | balrog | PXA2XX_INTERNAL_SIZE); |
91 | ef056e43 | balrog | exit(1);
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92 | ef056e43 | balrog | } |
93 | ef056e43 | balrog | |
94 | 7fb4fdcf | balrog | cpu = pxa270_init(mainstone_binfo.ram_size, ds, cpu_model); |
95 | 7fb4fdcf | balrog | cpu_register_physical_memory(0, MAINSTONE_ROM,
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96 | 7fb4fdcf | balrog | qemu_ram_alloc(MAINSTONE_ROM) | IO_MEM_ROM); |
97 | ef056e43 | balrog | |
98 | ef056e43 | balrog | /* Setup initial (reset) machine state */
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99 | f93eb9ff | balrog | cpu->env->regs[15] = mainstone_binfo.loader_start;
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100 | ef056e43 | balrog | |
101 | e4bcb14c | ths | /* There are two 32MiB flash devices on the board */
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102 | 6d1f1778 | balrog | for (i = 0; i < 2; i ++) { |
103 | 6d1f1778 | balrog | index = drive_get_index(IF_PFLASH, 0, i);
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104 | 6d1f1778 | balrog | if (index == -1) { |
105 | 6d1f1778 | balrog | fprintf(stderr, "Two flash images must be given with the "
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106 | 6d1f1778 | balrog | "'pflash' parameter\n");
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107 | 6d1f1778 | balrog | exit(1);
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108 | 6d1f1778 | balrog | } |
109 | 6d1f1778 | balrog | |
110 | 6d1f1778 | balrog | if (!pflash_cfi01_register(mainstone_flash_base[i],
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111 | 7fb4fdcf | balrog | qemu_ram_alloc(MAINSTONE_FLASH), |
112 | 6d1f1778 | balrog | drives_table[index].bdrv, sector_len, |
113 | 7fb4fdcf | balrog | MAINSTONE_FLASH / sector_len, 4, 0, 0, 0, 0)) { |
114 | 6d1f1778 | balrog | fprintf(stderr, "qemu: Error registering flash memory.\n");
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115 | 6d1f1778 | balrog | exit(1);
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116 | 6d1f1778 | balrog | } |
117 | e4bcb14c | ths | } |
118 | 7233b355 | ths | |
119 | 7233b355 | ths | mst_irq = mst_irq_init(cpu, MST_FPGA_PHYS, PXA2XX_PIC_GPIO_0); |
120 | f1de1334 | ths | |
121 | bd464c2e | balrog | /* setup keypad */
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122 | bd464c2e | balrog | printf("map addr %p\n", &map);
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123 | bd464c2e | balrog | pxa27x_register_keypad(cpu->kp, map, 0xe0);
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124 | bd464c2e | balrog | |
125 | f1de1334 | ths | /* MMC/SD host */
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126 | 8543243c | balrog | pxa2xx_mmci_handlers(cpu->mmc, NULL, mst_irq[MMC_IRQ]);
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127 | f1de1334 | ths | |
128 | ef056e43 | balrog | smc91c111_init(&nd_table[0], MST_ETH_PHYS, mst_irq[ETHERNET_IRQ]);
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129 | ef056e43 | balrog | |
130 | f93eb9ff | balrog | mainstone_binfo.kernel_filename = kernel_filename; |
131 | f93eb9ff | balrog | mainstone_binfo.kernel_cmdline = kernel_cmdline; |
132 | f93eb9ff | balrog | mainstone_binfo.initrd_filename = initrd_filename; |
133 | f93eb9ff | balrog | mainstone_binfo.board_id = arm_id; |
134 | f93eb9ff | balrog | arm_load_kernel(cpu->env, &mainstone_binfo); |
135 | ef056e43 | balrog | } |
136 | ef056e43 | balrog | |
137 | 00f82b8a | aurel32 | static void mainstone_init(ram_addr_t ram_size, int vga_ram_size, |
138 | ef056e43 | balrog | const char *boot_device, DisplayState *ds, |
139 | ef056e43 | balrog | const char *kernel_filename, const char *kernel_cmdline, |
140 | ef056e43 | balrog | const char *initrd_filename, const char *cpu_model) |
141 | ef056e43 | balrog | { |
142 | ef056e43 | balrog | mainstone_common_init(ram_size, vga_ram_size, ds, kernel_filename, |
143 | ef056e43 | balrog | kernel_cmdline, initrd_filename, cpu_model, mainstone, 0x196);
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144 | ef056e43 | balrog | } |
145 | ef056e43 | balrog | |
146 | ef056e43 | balrog | QEMUMachine mainstone2_machine = { |
147 | ef056e43 | balrog | "mainstone",
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148 | ef056e43 | balrog | "Mainstone II (PXA27x)",
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149 | ef056e43 | balrog | mainstone_init, |
150 | 7fb4fdcf | balrog | (MAINSTONE_RAM + MAINSTONE_ROM + 2 * MAINSTONE_FLASH +
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151 | 7fb4fdcf | balrog | PXA2XX_INTERNAL_SIZE) | RAMSIZE_FIXED, |
152 | ef056e43 | balrog | }; |