root / hw / musicpal.c @ c75a823c
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1 | 24859b68 | balrog | /*
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2 | 24859b68 | balrog | * Marvell MV88W8618 / Freecom MusicPal emulation.
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3 | 24859b68 | balrog | *
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4 | 24859b68 | balrog | * Copyright (c) 2008 Jan Kiszka
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5 | 24859b68 | balrog | *
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6 | 24859b68 | balrog | * This code is licenced under the GNU GPL v2.
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7 | 24859b68 | balrog | */
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8 | 24859b68 | balrog | |
9 | 24859b68 | balrog | #include "hw.h" |
10 | 24859b68 | balrog | #include "arm-misc.h" |
11 | 24859b68 | balrog | #include "devices.h" |
12 | 24859b68 | balrog | #include "net.h" |
13 | 24859b68 | balrog | #include "sysemu.h" |
14 | 24859b68 | balrog | #include "boards.h" |
15 | 24859b68 | balrog | #include "pc.h" |
16 | 24859b68 | balrog | #include "qemu-timer.h" |
17 | 24859b68 | balrog | #include "block.h" |
18 | 24859b68 | balrog | #include "flash.h" |
19 | 24859b68 | balrog | #include "console.h" |
20 | 24859b68 | balrog | #include "audio/audio.h" |
21 | 24859b68 | balrog | #include "i2c.h" |
22 | 24859b68 | balrog | |
23 | 24859b68 | balrog | #define MP_ETH_BASE 0x80008000 |
24 | 24859b68 | balrog | #define MP_ETH_SIZE 0x00001000 |
25 | 24859b68 | balrog | |
26 | 24859b68 | balrog | #define MP_UART1_BASE 0x8000C840 |
27 | 24859b68 | balrog | #define MP_UART2_BASE 0x8000C940 |
28 | 24859b68 | balrog | |
29 | 24859b68 | balrog | #define MP_FLASHCFG_BASE 0x90006000 |
30 | 24859b68 | balrog | #define MP_FLASHCFG_SIZE 0x00001000 |
31 | 24859b68 | balrog | |
32 | 24859b68 | balrog | #define MP_AUDIO_BASE 0x90007000 |
33 | 24859b68 | balrog | #define MP_AUDIO_SIZE 0x00001000 |
34 | 24859b68 | balrog | |
35 | 24859b68 | balrog | #define MP_PIC_BASE 0x90008000 |
36 | 24859b68 | balrog | #define MP_PIC_SIZE 0x00001000 |
37 | 24859b68 | balrog | |
38 | 24859b68 | balrog | #define MP_PIT_BASE 0x90009000 |
39 | 24859b68 | balrog | #define MP_PIT_SIZE 0x00001000 |
40 | 24859b68 | balrog | |
41 | 24859b68 | balrog | #define MP_LCD_BASE 0x9000c000 |
42 | 24859b68 | balrog | #define MP_LCD_SIZE 0x00001000 |
43 | 24859b68 | balrog | |
44 | 24859b68 | balrog | #define MP_SRAM_BASE 0xC0000000 |
45 | 24859b68 | balrog | #define MP_SRAM_SIZE 0x00020000 |
46 | 24859b68 | balrog | |
47 | 24859b68 | balrog | #define MP_RAM_DEFAULT_SIZE 32*1024*1024 |
48 | 24859b68 | balrog | #define MP_FLASH_SIZE_MAX 32*1024*1024 |
49 | 24859b68 | balrog | |
50 | 24859b68 | balrog | #define MP_TIMER1_IRQ 4 |
51 | 24859b68 | balrog | /* ... */
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52 | 24859b68 | balrog | #define MP_TIMER4_IRQ 7 |
53 | 24859b68 | balrog | #define MP_EHCI_IRQ 8 |
54 | 24859b68 | balrog | #define MP_ETH_IRQ 9 |
55 | 24859b68 | balrog | #define MP_UART1_IRQ 11 |
56 | 24859b68 | balrog | #define MP_UART2_IRQ 11 |
57 | 24859b68 | balrog | #define MP_GPIO_IRQ 12 |
58 | 24859b68 | balrog | #define MP_RTC_IRQ 28 |
59 | 24859b68 | balrog | #define MP_AUDIO_IRQ 30 |
60 | 24859b68 | balrog | |
61 | 24859b68 | balrog | static uint32_t gpio_in_state = 0xffffffff; |
62 | 24859b68 | balrog | static uint32_t gpio_out_state;
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63 | 24859b68 | balrog | static ram_addr_t sram_off;
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64 | 24859b68 | balrog | |
65 | 24859b68 | balrog | /* Address conversion helpers */
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66 | 24859b68 | balrog | static void *target2host_addr(uint32_t addr) |
67 | 24859b68 | balrog | { |
68 | 24859b68 | balrog | if (addr < MP_SRAM_BASE) {
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69 | 24859b68 | balrog | if (addr >= MP_RAM_DEFAULT_SIZE)
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70 | 24859b68 | balrog | return NULL; |
71 | 24859b68 | balrog | return (void *)(phys_ram_base + addr); |
72 | 24859b68 | balrog | } else {
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73 | 24859b68 | balrog | if (addr >= MP_SRAM_BASE + MP_SRAM_SIZE)
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74 | 24859b68 | balrog | return NULL; |
75 | 24859b68 | balrog | return (void *)(phys_ram_base + sram_off + addr - MP_SRAM_BASE); |
76 | 24859b68 | balrog | } |
77 | 24859b68 | balrog | } |
78 | 24859b68 | balrog | |
79 | 24859b68 | balrog | static uint32_t host2target_addr(void *addr) |
80 | 24859b68 | balrog | { |
81 | 24859b68 | balrog | if (addr < ((void *)phys_ram_base) + sram_off) |
82 | 24859b68 | balrog | return (unsigned long)addr - (unsigned long)phys_ram_base; |
83 | 24859b68 | balrog | else
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84 | 24859b68 | balrog | return (unsigned long)addr - (unsigned long)phys_ram_base - |
85 | 24859b68 | balrog | sram_off + MP_SRAM_BASE; |
86 | 24859b68 | balrog | } |
87 | 24859b68 | balrog | |
88 | 24859b68 | balrog | |
89 | 24859b68 | balrog | typedef enum i2c_state { |
90 | 24859b68 | balrog | STOPPED = 0,
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91 | 24859b68 | balrog | INITIALIZING, |
92 | 24859b68 | balrog | SENDING_BIT7, |
93 | 24859b68 | balrog | SENDING_BIT6, |
94 | 24859b68 | balrog | SENDING_BIT5, |
95 | 24859b68 | balrog | SENDING_BIT4, |
96 | 24859b68 | balrog | SENDING_BIT3, |
97 | 24859b68 | balrog | SENDING_BIT2, |
98 | 24859b68 | balrog | SENDING_BIT1, |
99 | 24859b68 | balrog | SENDING_BIT0, |
100 | 24859b68 | balrog | WAITING_FOR_ACK, |
101 | 24859b68 | balrog | RECEIVING_BIT7, |
102 | 24859b68 | balrog | RECEIVING_BIT6, |
103 | 24859b68 | balrog | RECEIVING_BIT5, |
104 | 24859b68 | balrog | RECEIVING_BIT4, |
105 | 24859b68 | balrog | RECEIVING_BIT3, |
106 | 24859b68 | balrog | RECEIVING_BIT2, |
107 | 24859b68 | balrog | RECEIVING_BIT1, |
108 | 24859b68 | balrog | RECEIVING_BIT0, |
109 | 24859b68 | balrog | SENDING_ACK |
110 | 24859b68 | balrog | } i2c_state; |
111 | 24859b68 | balrog | |
112 | 24859b68 | balrog | typedef struct i2c_interface { |
113 | 24859b68 | balrog | i2c_bus *bus; |
114 | 24859b68 | balrog | i2c_state state; |
115 | 24859b68 | balrog | int last_data;
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116 | 24859b68 | balrog | int last_clock;
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117 | 24859b68 | balrog | uint8_t buffer; |
118 | 24859b68 | balrog | int current_addr;
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119 | 24859b68 | balrog | } i2c_interface; |
120 | 24859b68 | balrog | |
121 | 24859b68 | balrog | static void i2c_enter_stop(i2c_interface *i2c) |
122 | 24859b68 | balrog | { |
123 | 24859b68 | balrog | if (i2c->current_addr >= 0) |
124 | 24859b68 | balrog | i2c_end_transfer(i2c->bus); |
125 | 24859b68 | balrog | i2c->current_addr = -1;
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126 | 24859b68 | balrog | i2c->state = STOPPED; |
127 | 24859b68 | balrog | } |
128 | 24859b68 | balrog | |
129 | 24859b68 | balrog | static void i2c_state_update(i2c_interface *i2c, int data, int clock) |
130 | 24859b68 | balrog | { |
131 | 24859b68 | balrog | if (!i2c)
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132 | 24859b68 | balrog | return;
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133 | 24859b68 | balrog | |
134 | 24859b68 | balrog | switch (i2c->state) {
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135 | 24859b68 | balrog | case STOPPED:
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136 | 24859b68 | balrog | if (data == 0 && i2c->last_data == 1 && clock == 1) |
137 | 24859b68 | balrog | i2c->state = INITIALIZING; |
138 | 24859b68 | balrog | break;
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139 | 24859b68 | balrog | |
140 | 24859b68 | balrog | case INITIALIZING:
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141 | 24859b68 | balrog | if (clock == 0 && i2c->last_clock == 1 && data == 0) |
142 | 24859b68 | balrog | i2c->state = SENDING_BIT7; |
143 | 24859b68 | balrog | else
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144 | 24859b68 | balrog | i2c_enter_stop(i2c); |
145 | 24859b68 | balrog | break;
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146 | 24859b68 | balrog | |
147 | 24859b68 | balrog | case SENDING_BIT7 ... SENDING_BIT0:
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148 | 24859b68 | balrog | if (clock == 0 && i2c->last_clock == 1) { |
149 | 24859b68 | balrog | i2c->buffer = (i2c->buffer << 1) | data;
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150 | 24859b68 | balrog | i2c->state++; /* will end up in WAITING_FOR_ACK */
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151 | 24859b68 | balrog | } else if (data == 1 && i2c->last_data == 0 && clock == 1) |
152 | 24859b68 | balrog | i2c_enter_stop(i2c); |
153 | 24859b68 | balrog | break;
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154 | 24859b68 | balrog | |
155 | 24859b68 | balrog | case WAITING_FOR_ACK:
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156 | 24859b68 | balrog | if (clock == 0 && i2c->last_clock == 1) { |
157 | 24859b68 | balrog | if (i2c->current_addr < 0) { |
158 | 24859b68 | balrog | i2c->current_addr = i2c->buffer; |
159 | 24859b68 | balrog | i2c_start_transfer(i2c->bus, i2c->current_addr & 0xfe,
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160 | 24859b68 | balrog | i2c->buffer & 1);
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161 | 24859b68 | balrog | } else
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162 | 24859b68 | balrog | i2c_send(i2c->bus, i2c->buffer); |
163 | 24859b68 | balrog | if (i2c->current_addr & 1) { |
164 | 24859b68 | balrog | i2c->state = RECEIVING_BIT7; |
165 | 24859b68 | balrog | i2c->buffer = i2c_recv(i2c->bus); |
166 | 24859b68 | balrog | } else
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167 | 24859b68 | balrog | i2c->state = SENDING_BIT7; |
168 | 24859b68 | balrog | } else if (data == 1 && i2c->last_data == 0 && clock == 1) |
169 | 24859b68 | balrog | i2c_enter_stop(i2c); |
170 | 24859b68 | balrog | break;
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171 | 24859b68 | balrog | |
172 | 24859b68 | balrog | case RECEIVING_BIT7 ... RECEIVING_BIT0:
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173 | 24859b68 | balrog | if (clock == 0 && i2c->last_clock == 1) { |
174 | 24859b68 | balrog | i2c->state++; /* will end up in SENDING_ACK */
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175 | 24859b68 | balrog | i2c->buffer <<= 1;
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176 | 24859b68 | balrog | } else if (data == 1 && i2c->last_data == 0 && clock == 1) |
177 | 24859b68 | balrog | i2c_enter_stop(i2c); |
178 | 24859b68 | balrog | break;
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179 | 24859b68 | balrog | |
180 | 24859b68 | balrog | case SENDING_ACK:
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181 | 24859b68 | balrog | if (clock == 0 && i2c->last_clock == 1) { |
182 | 24859b68 | balrog | i2c->state = RECEIVING_BIT7; |
183 | 24859b68 | balrog | if (data == 0) |
184 | 24859b68 | balrog | i2c->buffer = i2c_recv(i2c->bus); |
185 | 24859b68 | balrog | else
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186 | 24859b68 | balrog | i2c_nack(i2c->bus); |
187 | 24859b68 | balrog | } else if (data == 1 && i2c->last_data == 0 && clock == 1) |
188 | 24859b68 | balrog | i2c_enter_stop(i2c); |
189 | 24859b68 | balrog | break;
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190 | 24859b68 | balrog | } |
191 | 24859b68 | balrog | |
192 | 24859b68 | balrog | i2c->last_data = data; |
193 | 24859b68 | balrog | i2c->last_clock = clock; |
194 | 24859b68 | balrog | } |
195 | 24859b68 | balrog | |
196 | 24859b68 | balrog | static int i2c_get_data(i2c_interface *i2c) |
197 | 24859b68 | balrog | { |
198 | 24859b68 | balrog | if (!i2c)
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199 | 24859b68 | balrog | return 0; |
200 | 24859b68 | balrog | |
201 | 24859b68 | balrog | switch (i2c->state) {
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202 | 24859b68 | balrog | case RECEIVING_BIT7 ... RECEIVING_BIT0:
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203 | 24859b68 | balrog | return (i2c->buffer >> 7); |
204 | 24859b68 | balrog | |
205 | 24859b68 | balrog | case WAITING_FOR_ACK:
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206 | 24859b68 | balrog | default:
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207 | 24859b68 | balrog | return 0; |
208 | 24859b68 | balrog | } |
209 | 24859b68 | balrog | } |
210 | 24859b68 | balrog | |
211 | 24859b68 | balrog | static i2c_interface *mixer_i2c;
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212 | 24859b68 | balrog | |
213 | 24859b68 | balrog | #ifdef HAS_AUDIO
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214 | 24859b68 | balrog | |
215 | 24859b68 | balrog | /* Audio register offsets */
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216 | 24859b68 | balrog | #define MP_AUDIO_PLAYBACK_MODE 0x00 |
217 | 24859b68 | balrog | #define MP_AUDIO_CLOCK_DIV 0x18 |
218 | 24859b68 | balrog | #define MP_AUDIO_IRQ_STATUS 0x20 |
219 | 24859b68 | balrog | #define MP_AUDIO_IRQ_ENABLE 0x24 |
220 | 24859b68 | balrog | #define MP_AUDIO_TX_START_LO 0x28 |
221 | 24859b68 | balrog | #define MP_AUDIO_TX_THRESHOLD 0x2C |
222 | 24859b68 | balrog | #define MP_AUDIO_TX_STATUS 0x38 |
223 | 24859b68 | balrog | #define MP_AUDIO_TX_START_HI 0x40 |
224 | 24859b68 | balrog | |
225 | 24859b68 | balrog | /* Status register and IRQ enable bits */
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226 | 24859b68 | balrog | #define MP_AUDIO_TX_HALF (1 << 6) |
227 | 24859b68 | balrog | #define MP_AUDIO_TX_FULL (1 << 7) |
228 | 24859b68 | balrog | |
229 | 24859b68 | balrog | /* Playback mode bits */
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230 | 24859b68 | balrog | #define MP_AUDIO_16BIT_SAMPLE (1 << 0) |
231 | 24859b68 | balrog | #define MP_AUDIO_PLAYBACK_EN (1 << 7) |
232 | 24859b68 | balrog | #define MP_AUDIO_CLOCK_24MHZ (1 << 9) |
233 | 24859b68 | balrog | |
234 | 24859b68 | balrog | /* Wolfson 8750 I2C address */
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235 | 24859b68 | balrog | #define MP_WM_ADDR 0x34 |
236 | 24859b68 | balrog | |
237 | 24859b68 | balrog | const char audio_name[] = "mv88w8618"; |
238 | 24859b68 | balrog | |
239 | 24859b68 | balrog | typedef struct musicpal_audio_state { |
240 | 24859b68 | balrog | uint32_t base; |
241 | 24859b68 | balrog | qemu_irq irq; |
242 | 24859b68 | balrog | uint32_t playback_mode; |
243 | 24859b68 | balrog | uint32_t status; |
244 | 24859b68 | balrog | uint32_t irq_enable; |
245 | 24859b68 | balrog | unsigned long phys_buf; |
246 | 24859b68 | balrog | void *target_buffer;
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247 | 24859b68 | balrog | unsigned int threshold; |
248 | 24859b68 | balrog | unsigned int play_pos; |
249 | 24859b68 | balrog | unsigned int last_free; |
250 | 24859b68 | balrog | uint32_t clock_div; |
251 | 24859b68 | balrog | i2c_slave *wm; |
252 | 24859b68 | balrog | } musicpal_audio_state; |
253 | 24859b68 | balrog | |
254 | 24859b68 | balrog | static void audio_callback(void *opaque, int free_out, int free_in) |
255 | 24859b68 | balrog | { |
256 | 24859b68 | balrog | musicpal_audio_state *s = opaque; |
257 | 662caa6f | balrog | int16_t *codec_buffer; |
258 | 24859b68 | balrog | int pos, block_size;
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259 | 24859b68 | balrog | |
260 | 24859b68 | balrog | if (!(s->playback_mode & MP_AUDIO_PLAYBACK_EN))
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261 | 24859b68 | balrog | return;
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262 | 24859b68 | balrog | |
263 | 24859b68 | balrog | if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE)
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264 | 24859b68 | balrog | free_out <<= 2;
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265 | 24859b68 | balrog | else
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266 | 24859b68 | balrog | free_out <<= 1;
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267 | 24859b68 | balrog | |
268 | 24859b68 | balrog | block_size = s->threshold/2;
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269 | 24859b68 | balrog | if (free_out - s->last_free < block_size)
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270 | 24859b68 | balrog | return;
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271 | 24859b68 | balrog | |
272 | 24859b68 | balrog | if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE)
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273 | aa923101 | balrog | memcpy(wm8750_dac_buffer(s->wm, block_size >> 2),
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274 | 662caa6f | balrog | (uint32_t *)(s->target_buffer + s->play_pos), |
275 | 662caa6f | balrog | block_size); |
276 | 662caa6f | balrog | else {
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277 | 662caa6f | balrog | codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
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278 | 24859b68 | balrog | for (pos = 0; pos < block_size; pos += 2) { |
279 | aa923101 | balrog | *codec_buffer++ = cpu_to_le16(256 *
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280 | 24859b68 | balrog | *(int8_t *)(s->target_buffer + s->play_pos + pos)); |
281 | aa923101 | balrog | *codec_buffer++ = cpu_to_le16(256 *
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282 | 24859b68 | balrog | *(int8_t *)(s->target_buffer + s->play_pos + pos + 1));
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283 | 24859b68 | balrog | } |
284 | 662caa6f | balrog | } |
285 | 662caa6f | balrog | wm8750_dac_commit(s->wm); |
286 | 24859b68 | balrog | |
287 | 24859b68 | balrog | s->last_free = free_out - block_size; |
288 | 24859b68 | balrog | |
289 | 24859b68 | balrog | if (s->play_pos == 0) { |
290 | 24859b68 | balrog | s->status |= MP_AUDIO_TX_HALF; |
291 | 24859b68 | balrog | s->play_pos = block_size; |
292 | 24859b68 | balrog | } else {
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293 | 24859b68 | balrog | s->status |= MP_AUDIO_TX_FULL; |
294 | 24859b68 | balrog | s->play_pos = 0;
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295 | 24859b68 | balrog | } |
296 | 24859b68 | balrog | |
297 | 24859b68 | balrog | if (s->status & s->irq_enable)
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298 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
299 | 24859b68 | balrog | } |
300 | 24859b68 | balrog | |
301 | 24859b68 | balrog | static uint32_t musicpal_audio_read(void *opaque, target_phys_addr_t offset) |
302 | 24859b68 | balrog | { |
303 | 24859b68 | balrog | musicpal_audio_state *s = opaque; |
304 | 24859b68 | balrog | |
305 | 24859b68 | balrog | offset -= s->base; |
306 | 24859b68 | balrog | switch (offset) {
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307 | 24859b68 | balrog | case MP_AUDIO_PLAYBACK_MODE:
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308 | 24859b68 | balrog | return s->playback_mode;
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309 | 24859b68 | balrog | |
310 | 24859b68 | balrog | case MP_AUDIO_CLOCK_DIV:
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311 | 24859b68 | balrog | return s->clock_div;
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312 | 24859b68 | balrog | |
313 | 24859b68 | balrog | case MP_AUDIO_IRQ_STATUS:
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314 | 24859b68 | balrog | return s->status;
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315 | 24859b68 | balrog | |
316 | 24859b68 | balrog | case MP_AUDIO_IRQ_ENABLE:
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317 | 24859b68 | balrog | return s->irq_enable;
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318 | 24859b68 | balrog | |
319 | 24859b68 | balrog | case MP_AUDIO_TX_STATUS:
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320 | 24859b68 | balrog | return s->play_pos >> 2; |
321 | 24859b68 | balrog | |
322 | 24859b68 | balrog | default:
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323 | 24859b68 | balrog | return 0; |
324 | 24859b68 | balrog | } |
325 | 24859b68 | balrog | } |
326 | 24859b68 | balrog | |
327 | 24859b68 | balrog | static void musicpal_audio_write(void *opaque, target_phys_addr_t offset, |
328 | 24859b68 | balrog | uint32_t value) |
329 | 24859b68 | balrog | { |
330 | 24859b68 | balrog | musicpal_audio_state *s = opaque; |
331 | 24859b68 | balrog | |
332 | 24859b68 | balrog | offset -= s->base; |
333 | 24859b68 | balrog | switch (offset) {
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334 | 24859b68 | balrog | case MP_AUDIO_PLAYBACK_MODE:
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335 | 24859b68 | balrog | if (value & MP_AUDIO_PLAYBACK_EN &&
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336 | 24859b68 | balrog | !(s->playback_mode & MP_AUDIO_PLAYBACK_EN)) { |
337 | 24859b68 | balrog | s->status = 0;
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338 | 24859b68 | balrog | s->last_free = 0;
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339 | 24859b68 | balrog | s->play_pos = 0;
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340 | 24859b68 | balrog | } |
341 | 24859b68 | balrog | s->playback_mode = value; |
342 | 24859b68 | balrog | break;
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343 | 24859b68 | balrog | |
344 | 24859b68 | balrog | case MP_AUDIO_CLOCK_DIV:
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345 | 24859b68 | balrog | s->clock_div = value; |
346 | 24859b68 | balrog | s->last_free = 0;
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347 | 24859b68 | balrog | s->play_pos = 0;
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348 | 24859b68 | balrog | break;
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349 | 24859b68 | balrog | |
350 | 24859b68 | balrog | case MP_AUDIO_IRQ_STATUS:
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351 | 24859b68 | balrog | s->status &= ~value; |
352 | 24859b68 | balrog | break;
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353 | 24859b68 | balrog | |
354 | 24859b68 | balrog | case MP_AUDIO_IRQ_ENABLE:
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355 | 24859b68 | balrog | s->irq_enable = value; |
356 | 24859b68 | balrog | if (s->status & s->irq_enable)
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357 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
358 | 24859b68 | balrog | break;
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359 | 24859b68 | balrog | |
360 | 24859b68 | balrog | case MP_AUDIO_TX_START_LO:
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361 | 24859b68 | balrog | s->phys_buf = (s->phys_buf & 0xFFFF0000) | (value & 0xFFFF); |
362 | 24859b68 | balrog | s->target_buffer = target2host_addr(s->phys_buf); |
363 | 24859b68 | balrog | s->play_pos = 0;
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364 | 24859b68 | balrog | s->last_free = 0;
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365 | 24859b68 | balrog | break;
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366 | 24859b68 | balrog | |
367 | 24859b68 | balrog | case MP_AUDIO_TX_THRESHOLD:
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368 | 24859b68 | balrog | s->threshold = (value + 1) * 4; |
369 | 24859b68 | balrog | break;
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370 | 24859b68 | balrog | |
371 | 24859b68 | balrog | case MP_AUDIO_TX_START_HI:
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372 | 24859b68 | balrog | s->phys_buf = (s->phys_buf & 0xFFFF) | (value << 16); |
373 | 24859b68 | balrog | s->target_buffer = target2host_addr(s->phys_buf); |
374 | 24859b68 | balrog | s->play_pos = 0;
|
375 | 24859b68 | balrog | s->last_free = 0;
|
376 | 24859b68 | balrog | break;
|
377 | 24859b68 | balrog | } |
378 | 24859b68 | balrog | } |
379 | 24859b68 | balrog | |
380 | 24859b68 | balrog | static void musicpal_audio_reset(void *opaque) |
381 | 24859b68 | balrog | { |
382 | 24859b68 | balrog | musicpal_audio_state *s = opaque; |
383 | 24859b68 | balrog | |
384 | 24859b68 | balrog | s->playback_mode = 0;
|
385 | 24859b68 | balrog | s->status = 0;
|
386 | 24859b68 | balrog | s->irq_enable = 0;
|
387 | 24859b68 | balrog | } |
388 | 24859b68 | balrog | |
389 | 24859b68 | balrog | static CPUReadMemoryFunc *musicpal_audio_readfn[] = {
|
390 | 24859b68 | balrog | musicpal_audio_read, |
391 | 24859b68 | balrog | musicpal_audio_read, |
392 | 24859b68 | balrog | musicpal_audio_read |
393 | 24859b68 | balrog | }; |
394 | 24859b68 | balrog | |
395 | 24859b68 | balrog | static CPUWriteMemoryFunc *musicpal_audio_writefn[] = {
|
396 | 24859b68 | balrog | musicpal_audio_write, |
397 | 24859b68 | balrog | musicpal_audio_write, |
398 | 24859b68 | balrog | musicpal_audio_write |
399 | 24859b68 | balrog | }; |
400 | 24859b68 | balrog | |
401 | 24859b68 | balrog | static i2c_interface *musicpal_audio_init(uint32_t base, qemu_irq irq)
|
402 | 24859b68 | balrog | { |
403 | 24859b68 | balrog | AudioState *audio; |
404 | 24859b68 | balrog | musicpal_audio_state *s; |
405 | 24859b68 | balrog | i2c_interface *i2c; |
406 | 24859b68 | balrog | int iomemtype;
|
407 | 24859b68 | balrog | |
408 | 24859b68 | balrog | audio = AUD_init(); |
409 | 24859b68 | balrog | if (!audio) {
|
410 | 24859b68 | balrog | AUD_log(audio_name, "No audio state\n");
|
411 | 24859b68 | balrog | return NULL; |
412 | 24859b68 | balrog | } |
413 | 24859b68 | balrog | |
414 | 24859b68 | balrog | s = qemu_mallocz(sizeof(musicpal_audio_state));
|
415 | 24859b68 | balrog | if (!s)
|
416 | 24859b68 | balrog | return NULL; |
417 | 24859b68 | balrog | s->base = base; |
418 | 24859b68 | balrog | s->irq = irq; |
419 | 24859b68 | balrog | |
420 | 24859b68 | balrog | i2c = qemu_mallocz(sizeof(i2c_interface));
|
421 | 24859b68 | balrog | if (!i2c)
|
422 | 24859b68 | balrog | return NULL; |
423 | 24859b68 | balrog | i2c->bus = i2c_init_bus(); |
424 | 24859b68 | balrog | i2c->current_addr = -1;
|
425 | 24859b68 | balrog | |
426 | 24859b68 | balrog | s->wm = wm8750_init(i2c->bus, audio); |
427 | 24859b68 | balrog | if (!s->wm)
|
428 | 24859b68 | balrog | return NULL; |
429 | 24859b68 | balrog | i2c_set_slave_address(s->wm, MP_WM_ADDR); |
430 | 24859b68 | balrog | wm8750_data_req_set(s->wm, audio_callback, s); |
431 | 24859b68 | balrog | |
432 | 24859b68 | balrog | iomemtype = cpu_register_io_memory(0, musicpal_audio_readfn,
|
433 | 24859b68 | balrog | musicpal_audio_writefn, s); |
434 | 24859b68 | balrog | cpu_register_physical_memory(base, MP_AUDIO_SIZE, iomemtype); |
435 | 24859b68 | balrog | |
436 | 24859b68 | balrog | qemu_register_reset(musicpal_audio_reset, s); |
437 | 24859b68 | balrog | |
438 | 24859b68 | balrog | return i2c;
|
439 | 24859b68 | balrog | } |
440 | 24859b68 | balrog | #else /* !HAS_AUDIO */ |
441 | 24859b68 | balrog | static i2c_interface *musicpal_audio_init(uint32_t base, qemu_irq irq)
|
442 | 24859b68 | balrog | { |
443 | 24859b68 | balrog | return NULL; |
444 | 24859b68 | balrog | } |
445 | 24859b68 | balrog | #endif /* !HAS_AUDIO */ |
446 | 24859b68 | balrog | |
447 | 24859b68 | balrog | /* Ethernet register offsets */
|
448 | 24859b68 | balrog | #define MP_ETH_SMIR 0x010 |
449 | 24859b68 | balrog | #define MP_ETH_PCXR 0x408 |
450 | 24859b68 | balrog | #define MP_ETH_SDCMR 0x448 |
451 | 24859b68 | balrog | #define MP_ETH_ICR 0x450 |
452 | 24859b68 | balrog | #define MP_ETH_IMR 0x458 |
453 | 24859b68 | balrog | #define MP_ETH_FRDP0 0x480 |
454 | 24859b68 | balrog | #define MP_ETH_FRDP1 0x484 |
455 | 24859b68 | balrog | #define MP_ETH_FRDP2 0x488 |
456 | 24859b68 | balrog | #define MP_ETH_FRDP3 0x48C |
457 | 24859b68 | balrog | #define MP_ETH_CRDP0 0x4A0 |
458 | 24859b68 | balrog | #define MP_ETH_CRDP1 0x4A4 |
459 | 24859b68 | balrog | #define MP_ETH_CRDP2 0x4A8 |
460 | 24859b68 | balrog | #define MP_ETH_CRDP3 0x4AC |
461 | 24859b68 | balrog | #define MP_ETH_CTDP0 0x4E0 |
462 | 24859b68 | balrog | #define MP_ETH_CTDP1 0x4E4 |
463 | 24859b68 | balrog | #define MP_ETH_CTDP2 0x4E8 |
464 | 24859b68 | balrog | #define MP_ETH_CTDP3 0x4EC |
465 | 24859b68 | balrog | |
466 | 24859b68 | balrog | /* MII PHY access */
|
467 | 24859b68 | balrog | #define MP_ETH_SMIR_DATA 0x0000FFFF |
468 | 24859b68 | balrog | #define MP_ETH_SMIR_ADDR 0x03FF0000 |
469 | 24859b68 | balrog | #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */ |
470 | 24859b68 | balrog | #define MP_ETH_SMIR_RDVALID (1 << 27) |
471 | 24859b68 | balrog | |
472 | 24859b68 | balrog | /* PHY registers */
|
473 | 24859b68 | balrog | #define MP_ETH_PHY1_BMSR 0x00210000 |
474 | 24859b68 | balrog | #define MP_ETH_PHY1_PHYSID1 0x00410000 |
475 | 24859b68 | balrog | #define MP_ETH_PHY1_PHYSID2 0x00610000 |
476 | 24859b68 | balrog | |
477 | 24859b68 | balrog | #define MP_PHY_BMSR_LINK 0x0004 |
478 | 24859b68 | balrog | #define MP_PHY_BMSR_AUTONEG 0x0008 |
479 | 24859b68 | balrog | |
480 | 24859b68 | balrog | #define MP_PHY_88E3015 0x01410E20 |
481 | 24859b68 | balrog | |
482 | 24859b68 | balrog | /* TX descriptor status */
|
483 | 24859b68 | balrog | #define MP_ETH_TX_OWN (1 << 31) |
484 | 24859b68 | balrog | |
485 | 24859b68 | balrog | /* RX descriptor status */
|
486 | 24859b68 | balrog | #define MP_ETH_RX_OWN (1 << 31) |
487 | 24859b68 | balrog | |
488 | 24859b68 | balrog | /* Interrupt cause/mask bits */
|
489 | 24859b68 | balrog | #define MP_ETH_IRQ_RX_BIT 0 |
490 | 24859b68 | balrog | #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT) |
491 | 24859b68 | balrog | #define MP_ETH_IRQ_TXHI_BIT 2 |
492 | 24859b68 | balrog | #define MP_ETH_IRQ_TXLO_BIT 3 |
493 | 24859b68 | balrog | |
494 | 24859b68 | balrog | /* Port config bits */
|
495 | 24859b68 | balrog | #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */ |
496 | 24859b68 | balrog | |
497 | 24859b68 | balrog | /* SDMA command bits */
|
498 | 24859b68 | balrog | #define MP_ETH_CMD_TXHI (1 << 23) |
499 | 24859b68 | balrog | #define MP_ETH_CMD_TXLO (1 << 22) |
500 | 24859b68 | balrog | |
501 | 24859b68 | balrog | typedef struct mv88w8618_tx_desc { |
502 | 24859b68 | balrog | uint32_t cmdstat; |
503 | 24859b68 | balrog | uint16_t res; |
504 | 24859b68 | balrog | uint16_t bytes; |
505 | 24859b68 | balrog | uint32_t buffer; |
506 | 24859b68 | balrog | uint32_t next; |
507 | 24859b68 | balrog | } mv88w8618_tx_desc; |
508 | 24859b68 | balrog | |
509 | 24859b68 | balrog | typedef struct mv88w8618_rx_desc { |
510 | 24859b68 | balrog | uint32_t cmdstat; |
511 | 24859b68 | balrog | uint16_t bytes; |
512 | 24859b68 | balrog | uint16_t buffer_size; |
513 | 24859b68 | balrog | uint32_t buffer; |
514 | 24859b68 | balrog | uint32_t next; |
515 | 24859b68 | balrog | } mv88w8618_rx_desc; |
516 | 24859b68 | balrog | |
517 | 24859b68 | balrog | typedef struct mv88w8618_eth_state { |
518 | 24859b68 | balrog | uint32_t base; |
519 | 24859b68 | balrog | qemu_irq irq; |
520 | 24859b68 | balrog | uint32_t smir; |
521 | 24859b68 | balrog | uint32_t icr; |
522 | 24859b68 | balrog | uint32_t imr; |
523 | 24859b68 | balrog | int vlan_header;
|
524 | 24859b68 | balrog | mv88w8618_tx_desc *tx_queue[2];
|
525 | 24859b68 | balrog | mv88w8618_rx_desc *rx_queue[4];
|
526 | 24859b68 | balrog | mv88w8618_rx_desc *frx_queue[4];
|
527 | 24859b68 | balrog | mv88w8618_rx_desc *cur_rx[4];
|
528 | 24859b68 | balrog | VLANClientState *vc; |
529 | 24859b68 | balrog | } mv88w8618_eth_state; |
530 | 24859b68 | balrog | |
531 | 24859b68 | balrog | static int eth_can_receive(void *opaque) |
532 | 24859b68 | balrog | { |
533 | 24859b68 | balrog | return 1; |
534 | 24859b68 | balrog | } |
535 | 24859b68 | balrog | |
536 | 24859b68 | balrog | static void eth_receive(void *opaque, const uint8_t *buf, int size) |
537 | 24859b68 | balrog | { |
538 | 24859b68 | balrog | mv88w8618_eth_state *s = opaque; |
539 | 24859b68 | balrog | mv88w8618_rx_desc *desc; |
540 | 24859b68 | balrog | int i;
|
541 | 24859b68 | balrog | |
542 | 24859b68 | balrog | for (i = 0; i < 4; i++) { |
543 | 24859b68 | balrog | desc = s->cur_rx[i]; |
544 | 24859b68 | balrog | if (!desc)
|
545 | 24859b68 | balrog | continue;
|
546 | 24859b68 | balrog | do {
|
547 | 24859b68 | balrog | if (le32_to_cpu(desc->cmdstat) & MP_ETH_RX_OWN &&
|
548 | 24859b68 | balrog | le16_to_cpu(desc->buffer_size) >= size) { |
549 | 24859b68 | balrog | memcpy(target2host_addr(le32_to_cpu(desc->buffer) + |
550 | 24859b68 | balrog | s->vlan_header), |
551 | 24859b68 | balrog | buf, size); |
552 | 24859b68 | balrog | desc->bytes = cpu_to_le16(size + s->vlan_header); |
553 | 24859b68 | balrog | desc->cmdstat &= cpu_to_le32(~MP_ETH_RX_OWN); |
554 | 24859b68 | balrog | s->cur_rx[i] = target2host_addr(le32_to_cpu(desc->next)); |
555 | 24859b68 | balrog | |
556 | 24859b68 | balrog | s->icr |= MP_ETH_IRQ_RX; |
557 | 24859b68 | balrog | if (s->icr & s->imr)
|
558 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
559 | 24859b68 | balrog | return;
|
560 | 24859b68 | balrog | } |
561 | 24859b68 | balrog | desc = target2host_addr(le32_to_cpu(desc->next)); |
562 | 24859b68 | balrog | } while (desc != s->rx_queue[i]);
|
563 | 24859b68 | balrog | } |
564 | 24859b68 | balrog | } |
565 | 24859b68 | balrog | |
566 | 24859b68 | balrog | static void eth_send(mv88w8618_eth_state *s, int queue_index) |
567 | 24859b68 | balrog | { |
568 | 24859b68 | balrog | mv88w8618_tx_desc *desc = s->tx_queue[queue_index]; |
569 | 24859b68 | balrog | |
570 | 24859b68 | balrog | do {
|
571 | 24859b68 | balrog | if (le32_to_cpu(desc->cmdstat) & MP_ETH_TX_OWN) {
|
572 | 24859b68 | balrog | qemu_send_packet(s->vc, |
573 | 24859b68 | balrog | target2host_addr(le32_to_cpu(desc->buffer)), |
574 | 24859b68 | balrog | le16_to_cpu(desc->bytes)); |
575 | 24859b68 | balrog | desc->cmdstat &= cpu_to_le32(~MP_ETH_TX_OWN); |
576 | 24859b68 | balrog | s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
|
577 | 24859b68 | balrog | } |
578 | 24859b68 | balrog | desc = target2host_addr(le32_to_cpu(desc->next)); |
579 | 24859b68 | balrog | } while (desc != s->tx_queue[queue_index]);
|
580 | 24859b68 | balrog | } |
581 | 24859b68 | balrog | |
582 | 24859b68 | balrog | static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset) |
583 | 24859b68 | balrog | { |
584 | 24859b68 | balrog | mv88w8618_eth_state *s = opaque; |
585 | 24859b68 | balrog | |
586 | 24859b68 | balrog | offset -= s->base; |
587 | 24859b68 | balrog | switch (offset) {
|
588 | 24859b68 | balrog | case MP_ETH_SMIR:
|
589 | 24859b68 | balrog | if (s->smir & MP_ETH_SMIR_OPCODE) {
|
590 | 24859b68 | balrog | switch (s->smir & MP_ETH_SMIR_ADDR) {
|
591 | 24859b68 | balrog | case MP_ETH_PHY1_BMSR:
|
592 | 24859b68 | balrog | return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
|
593 | 24859b68 | balrog | MP_ETH_SMIR_RDVALID; |
594 | 24859b68 | balrog | case MP_ETH_PHY1_PHYSID1:
|
595 | 24859b68 | balrog | return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID; |
596 | 24859b68 | balrog | case MP_ETH_PHY1_PHYSID2:
|
597 | 24859b68 | balrog | return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID; |
598 | 24859b68 | balrog | default:
|
599 | 24859b68 | balrog | return MP_ETH_SMIR_RDVALID;
|
600 | 24859b68 | balrog | } |
601 | 24859b68 | balrog | } |
602 | 24859b68 | balrog | return 0; |
603 | 24859b68 | balrog | |
604 | 24859b68 | balrog | case MP_ETH_ICR:
|
605 | 24859b68 | balrog | return s->icr;
|
606 | 24859b68 | balrog | |
607 | 24859b68 | balrog | case MP_ETH_IMR:
|
608 | 24859b68 | balrog | return s->imr;
|
609 | 24859b68 | balrog | |
610 | 24859b68 | balrog | case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
|
611 | 24859b68 | balrog | return host2target_addr(s->frx_queue[(offset - MP_ETH_FRDP0)/4]); |
612 | 24859b68 | balrog | |
613 | 24859b68 | balrog | case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
|
614 | 24859b68 | balrog | return host2target_addr(s->rx_queue[(offset - MP_ETH_CRDP0)/4]); |
615 | 24859b68 | balrog | |
616 | 24859b68 | balrog | case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
|
617 | 24859b68 | balrog | return host2target_addr(s->tx_queue[(offset - MP_ETH_CTDP0)/4]); |
618 | 24859b68 | balrog | |
619 | 24859b68 | balrog | default:
|
620 | 24859b68 | balrog | return 0; |
621 | 24859b68 | balrog | } |
622 | 24859b68 | balrog | } |
623 | 24859b68 | balrog | |
624 | 24859b68 | balrog | static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset, |
625 | 24859b68 | balrog | uint32_t value) |
626 | 24859b68 | balrog | { |
627 | 24859b68 | balrog | mv88w8618_eth_state *s = opaque; |
628 | 24859b68 | balrog | |
629 | 24859b68 | balrog | offset -= s->base; |
630 | 24859b68 | balrog | switch (offset) {
|
631 | 24859b68 | balrog | case MP_ETH_SMIR:
|
632 | 24859b68 | balrog | s->smir = value; |
633 | 24859b68 | balrog | break;
|
634 | 24859b68 | balrog | |
635 | 24859b68 | balrog | case MP_ETH_PCXR:
|
636 | 24859b68 | balrog | s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2; |
637 | 24859b68 | balrog | break;
|
638 | 24859b68 | balrog | |
639 | 24859b68 | balrog | case MP_ETH_SDCMR:
|
640 | 24859b68 | balrog | if (value & MP_ETH_CMD_TXHI)
|
641 | 24859b68 | balrog | eth_send(s, 1);
|
642 | 24859b68 | balrog | if (value & MP_ETH_CMD_TXLO)
|
643 | 24859b68 | balrog | eth_send(s, 0);
|
644 | 24859b68 | balrog | if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr)
|
645 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
646 | 24859b68 | balrog | break;
|
647 | 24859b68 | balrog | |
648 | 24859b68 | balrog | case MP_ETH_ICR:
|
649 | 24859b68 | balrog | s->icr &= value; |
650 | 24859b68 | balrog | break;
|
651 | 24859b68 | balrog | |
652 | 24859b68 | balrog | case MP_ETH_IMR:
|
653 | 24859b68 | balrog | s->imr = value; |
654 | 24859b68 | balrog | if (s->icr & s->imr)
|
655 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
656 | 24859b68 | balrog | break;
|
657 | 24859b68 | balrog | |
658 | 24859b68 | balrog | case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
|
659 | 24859b68 | balrog | s->frx_queue[(offset - MP_ETH_FRDP0)/4] = target2host_addr(value);
|
660 | 24859b68 | balrog | break;
|
661 | 24859b68 | balrog | |
662 | 24859b68 | balrog | case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
|
663 | 24859b68 | balrog | s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
|
664 | 24859b68 | balrog | s->cur_rx[(offset - MP_ETH_CRDP0)/4] = target2host_addr(value);
|
665 | 24859b68 | balrog | break;
|
666 | 24859b68 | balrog | |
667 | 24859b68 | balrog | case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
|
668 | 24859b68 | balrog | s->tx_queue[(offset - MP_ETH_CTDP0)/4] = target2host_addr(value);
|
669 | 24859b68 | balrog | break;
|
670 | 24859b68 | balrog | } |
671 | 24859b68 | balrog | } |
672 | 24859b68 | balrog | |
673 | 24859b68 | balrog | static CPUReadMemoryFunc *mv88w8618_eth_readfn[] = {
|
674 | 24859b68 | balrog | mv88w8618_eth_read, |
675 | 24859b68 | balrog | mv88w8618_eth_read, |
676 | 24859b68 | balrog | mv88w8618_eth_read |
677 | 24859b68 | balrog | }; |
678 | 24859b68 | balrog | |
679 | 24859b68 | balrog | static CPUWriteMemoryFunc *mv88w8618_eth_writefn[] = {
|
680 | 24859b68 | balrog | mv88w8618_eth_write, |
681 | 24859b68 | balrog | mv88w8618_eth_write, |
682 | 24859b68 | balrog | mv88w8618_eth_write |
683 | 24859b68 | balrog | }; |
684 | 24859b68 | balrog | |
685 | 24859b68 | balrog | static void mv88w8618_eth_init(NICInfo *nd, uint32_t base, qemu_irq irq) |
686 | 24859b68 | balrog | { |
687 | 24859b68 | balrog | mv88w8618_eth_state *s; |
688 | 24859b68 | balrog | int iomemtype;
|
689 | 24859b68 | balrog | |
690 | 24859b68 | balrog | s = qemu_mallocz(sizeof(mv88w8618_eth_state));
|
691 | 24859b68 | balrog | if (!s)
|
692 | 24859b68 | balrog | return;
|
693 | 24859b68 | balrog | s->base = base; |
694 | 24859b68 | balrog | s->irq = irq; |
695 | 24859b68 | balrog | s->vc = qemu_new_vlan_client(nd->vlan, eth_receive, eth_can_receive, s); |
696 | 24859b68 | balrog | iomemtype = cpu_register_io_memory(0, mv88w8618_eth_readfn,
|
697 | 24859b68 | balrog | mv88w8618_eth_writefn, s); |
698 | 24859b68 | balrog | cpu_register_physical_memory(base, MP_ETH_SIZE, iomemtype); |
699 | 24859b68 | balrog | } |
700 | 24859b68 | balrog | |
701 | 24859b68 | balrog | /* LCD register offsets */
|
702 | 24859b68 | balrog | #define MP_LCD_IRQCTRL 0x180 |
703 | 24859b68 | balrog | #define MP_LCD_IRQSTAT 0x184 |
704 | 24859b68 | balrog | #define MP_LCD_SPICTRL 0x1ac |
705 | 24859b68 | balrog | #define MP_LCD_INST 0x1bc |
706 | 24859b68 | balrog | #define MP_LCD_DATA 0x1c0 |
707 | 24859b68 | balrog | |
708 | 24859b68 | balrog | /* Mode magics */
|
709 | 24859b68 | balrog | #define MP_LCD_SPI_DATA 0x00100011 |
710 | 24859b68 | balrog | #define MP_LCD_SPI_CMD 0x00104011 |
711 | 24859b68 | balrog | #define MP_LCD_SPI_INVALID 0x00000000 |
712 | 24859b68 | balrog | |
713 | 24859b68 | balrog | /* Commmands */
|
714 | 24859b68 | balrog | #define MP_LCD_INST_SETPAGE0 0xB0 |
715 | 24859b68 | balrog | /* ... */
|
716 | 24859b68 | balrog | #define MP_LCD_INST_SETPAGE7 0xB7 |
717 | 24859b68 | balrog | |
718 | 24859b68 | balrog | #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */ |
719 | 24859b68 | balrog | |
720 | 24859b68 | balrog | typedef struct musicpal_lcd_state { |
721 | 24859b68 | balrog | uint32_t base; |
722 | 24859b68 | balrog | uint32_t mode; |
723 | 24859b68 | balrog | uint32_t irqctrl; |
724 | 24859b68 | balrog | int page;
|
725 | 24859b68 | balrog | int page_off;
|
726 | 24859b68 | balrog | DisplayState *ds; |
727 | 24859b68 | balrog | uint8_t video_ram[128*64/8]; |
728 | 24859b68 | balrog | } musicpal_lcd_state; |
729 | 24859b68 | balrog | |
730 | 24859b68 | balrog | static uint32_t lcd_brightness;
|
731 | 24859b68 | balrog | |
732 | 24859b68 | balrog | static uint8_t scale_lcd_color(uint8_t col)
|
733 | 24859b68 | balrog | { |
734 | 24859b68 | balrog | int tmp = col;
|
735 | 24859b68 | balrog | |
736 | 24859b68 | balrog | switch (lcd_brightness) {
|
737 | 24859b68 | balrog | case 0x00000007: /* 0 */ |
738 | 24859b68 | balrog | return 0; |
739 | 24859b68 | balrog | |
740 | 24859b68 | balrog | case 0x00020000: /* 1 */ |
741 | 24859b68 | balrog | return (tmp * 1) / 7; |
742 | 24859b68 | balrog | |
743 | 24859b68 | balrog | case 0x00020001: /* 2 */ |
744 | 24859b68 | balrog | return (tmp * 2) / 7; |
745 | 24859b68 | balrog | |
746 | 24859b68 | balrog | case 0x00040000: /* 3 */ |
747 | 24859b68 | balrog | return (tmp * 3) / 7; |
748 | 24859b68 | balrog | |
749 | 24859b68 | balrog | case 0x00010006: /* 4 */ |
750 | 24859b68 | balrog | return (tmp * 4) / 7; |
751 | 24859b68 | balrog | |
752 | 24859b68 | balrog | case 0x00020005: /* 5 */ |
753 | 24859b68 | balrog | return (tmp * 5) / 7; |
754 | 24859b68 | balrog | |
755 | 24859b68 | balrog | case 0x00040003: /* 6 */ |
756 | 24859b68 | balrog | return (tmp * 6) / 7; |
757 | 24859b68 | balrog | |
758 | 24859b68 | balrog | case 0x00030004: /* 7 */ |
759 | 24859b68 | balrog | default:
|
760 | 24859b68 | balrog | return col;
|
761 | 24859b68 | balrog | } |
762 | 24859b68 | balrog | } |
763 | 24859b68 | balrog | |
764 | 0266f2c7 | balrog | #define SET_LCD_PIXEL(depth, type) \
|
765 | 0266f2c7 | balrog | static inline void glue(set_lcd_pixel, depth) \ |
766 | 0266f2c7 | balrog | (musicpal_lcd_state *s, int x, int y, type col) \ |
767 | 0266f2c7 | balrog | { \ |
768 | 0266f2c7 | balrog | int dx, dy; \
|
769 | 0266f2c7 | balrog | type *pixel = &((type *) s->ds->data)[(y * 128 * 3 + x) * 3]; \ |
770 | 0266f2c7 | balrog | \ |
771 | 0266f2c7 | balrog | for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \ |
772 | 0266f2c7 | balrog | for (dx = 0; dx < 3; dx++, pixel++) \ |
773 | 0266f2c7 | balrog | *pixel = col; \ |
774 | 24859b68 | balrog | } |
775 | 0266f2c7 | balrog | SET_LCD_PIXEL(8, uint8_t)
|
776 | 0266f2c7 | balrog | SET_LCD_PIXEL(16, uint16_t)
|
777 | 0266f2c7 | balrog | SET_LCD_PIXEL(32, uint32_t)
|
778 | 0266f2c7 | balrog | |
779 | 0266f2c7 | balrog | #include "pixel_ops.h" |
780 | 24859b68 | balrog | |
781 | 24859b68 | balrog | static void lcd_refresh(void *opaque) |
782 | 24859b68 | balrog | { |
783 | 24859b68 | balrog | musicpal_lcd_state *s = opaque; |
784 | 0266f2c7 | balrog | int x, y, col;
|
785 | 24859b68 | balrog | |
786 | 0266f2c7 | balrog | switch (s->ds->depth) {
|
787 | 0266f2c7 | balrog | case 0: |
788 | 0266f2c7 | balrog | return;
|
789 | 0266f2c7 | balrog | #define LCD_REFRESH(depth, func) \
|
790 | 0266f2c7 | balrog | case depth: \
|
791 | 0266f2c7 | balrog | col = func(scale_lcd_color((MP_LCD_TEXTCOLOR >> 16) & 0xff), \ |
792 | 0266f2c7 | balrog | scale_lcd_color((MP_LCD_TEXTCOLOR >> 8) & 0xff), \ |
793 | 0266f2c7 | balrog | scale_lcd_color(MP_LCD_TEXTCOLOR & 0xff)); \
|
794 | 0266f2c7 | balrog | for (x = 0; x < 128; x++) \ |
795 | 0266f2c7 | balrog | for (y = 0; y < 64; y++) \ |
796 | 0266f2c7 | balrog | if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) \ |
797 | 0266f2c7 | balrog | glue(set_lcd_pixel, depth)(s, x, y, col); \ |
798 | 0266f2c7 | balrog | else \
|
799 | 0266f2c7 | balrog | glue(set_lcd_pixel, depth)(s, x, y, 0); \
|
800 | 0266f2c7 | balrog | break;
|
801 | 0266f2c7 | balrog | LCD_REFRESH(8, rgb_to_pixel8)
|
802 | 0266f2c7 | balrog | LCD_REFRESH(16, rgb_to_pixel16)
|
803 | 0266f2c7 | balrog | LCD_REFRESH(32, (s->ds->bgr ? rgb_to_pixel32bgr : rgb_to_pixel32))
|
804 | 0266f2c7 | balrog | default:
|
805 | 0266f2c7 | balrog | cpu_abort(cpu_single_env, "unsupported colour depth %i\n",
|
806 | 0266f2c7 | balrog | s->ds->depth); |
807 | 0266f2c7 | balrog | } |
808 | 24859b68 | balrog | |
809 | 24859b68 | balrog | dpy_update(s->ds, 0, 0, 128*3, 64*3); |
810 | 24859b68 | balrog | } |
811 | 24859b68 | balrog | |
812 | 24859b68 | balrog | static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset) |
813 | 24859b68 | balrog | { |
814 | 24859b68 | balrog | musicpal_lcd_state *s = opaque; |
815 | 24859b68 | balrog | |
816 | 24859b68 | balrog | offset -= s->base; |
817 | 24859b68 | balrog | switch (offset) {
|
818 | 24859b68 | balrog | case MP_LCD_IRQCTRL:
|
819 | 24859b68 | balrog | return s->irqctrl;
|
820 | 24859b68 | balrog | |
821 | 24859b68 | balrog | default:
|
822 | 24859b68 | balrog | return 0; |
823 | 24859b68 | balrog | } |
824 | 24859b68 | balrog | } |
825 | 24859b68 | balrog | |
826 | 24859b68 | balrog | static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset, |
827 | 24859b68 | balrog | uint32_t value) |
828 | 24859b68 | balrog | { |
829 | 24859b68 | balrog | musicpal_lcd_state *s = opaque; |
830 | 24859b68 | balrog | |
831 | 24859b68 | balrog | offset -= s->base; |
832 | 24859b68 | balrog | switch (offset) {
|
833 | 24859b68 | balrog | case MP_LCD_IRQCTRL:
|
834 | 24859b68 | balrog | s->irqctrl = value; |
835 | 24859b68 | balrog | break;
|
836 | 24859b68 | balrog | |
837 | 24859b68 | balrog | case MP_LCD_SPICTRL:
|
838 | 24859b68 | balrog | if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD)
|
839 | 24859b68 | balrog | s->mode = value; |
840 | 24859b68 | balrog | else
|
841 | 24859b68 | balrog | s->mode = MP_LCD_SPI_INVALID; |
842 | 24859b68 | balrog | break;
|
843 | 24859b68 | balrog | |
844 | 24859b68 | balrog | case MP_LCD_INST:
|
845 | 24859b68 | balrog | if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
|
846 | 24859b68 | balrog | s->page = value - MP_LCD_INST_SETPAGE0; |
847 | 24859b68 | balrog | s->page_off = 0;
|
848 | 24859b68 | balrog | } |
849 | 24859b68 | balrog | break;
|
850 | 24859b68 | balrog | |
851 | 24859b68 | balrog | case MP_LCD_DATA:
|
852 | 24859b68 | balrog | if (s->mode == MP_LCD_SPI_CMD) {
|
853 | 24859b68 | balrog | if (value >= MP_LCD_INST_SETPAGE0 &&
|
854 | 24859b68 | balrog | value <= MP_LCD_INST_SETPAGE7) { |
855 | 24859b68 | balrog | s->page = value - MP_LCD_INST_SETPAGE0; |
856 | 24859b68 | balrog | s->page_off = 0;
|
857 | 24859b68 | balrog | } |
858 | 24859b68 | balrog | } else if (s->mode == MP_LCD_SPI_DATA) { |
859 | 24859b68 | balrog | s->video_ram[s->page*128 + s->page_off] = value;
|
860 | 24859b68 | balrog | s->page_off = (s->page_off + 1) & 127; |
861 | 24859b68 | balrog | } |
862 | 24859b68 | balrog | break;
|
863 | 24859b68 | balrog | } |
864 | 24859b68 | balrog | } |
865 | 24859b68 | balrog | |
866 | 24859b68 | balrog | static CPUReadMemoryFunc *musicpal_lcd_readfn[] = {
|
867 | 24859b68 | balrog | musicpal_lcd_read, |
868 | 24859b68 | balrog | musicpal_lcd_read, |
869 | 24859b68 | balrog | musicpal_lcd_read |
870 | 24859b68 | balrog | }; |
871 | 24859b68 | balrog | |
872 | 24859b68 | balrog | static CPUWriteMemoryFunc *musicpal_lcd_writefn[] = {
|
873 | 24859b68 | balrog | musicpal_lcd_write, |
874 | 24859b68 | balrog | musicpal_lcd_write, |
875 | 24859b68 | balrog | musicpal_lcd_write |
876 | 24859b68 | balrog | }; |
877 | 24859b68 | balrog | |
878 | 24859b68 | balrog | static void musicpal_lcd_init(DisplayState *ds, uint32_t base) |
879 | 24859b68 | balrog | { |
880 | 24859b68 | balrog | musicpal_lcd_state *s; |
881 | 24859b68 | balrog | int iomemtype;
|
882 | 24859b68 | balrog | |
883 | 24859b68 | balrog | s = qemu_mallocz(sizeof(musicpal_lcd_state));
|
884 | 24859b68 | balrog | if (!s)
|
885 | 24859b68 | balrog | return;
|
886 | 24859b68 | balrog | s->base = base; |
887 | 24859b68 | balrog | s->ds = ds; |
888 | 24859b68 | balrog | iomemtype = cpu_register_io_memory(0, musicpal_lcd_readfn,
|
889 | 24859b68 | balrog | musicpal_lcd_writefn, s); |
890 | 24859b68 | balrog | cpu_register_physical_memory(base, MP_LCD_SIZE, iomemtype); |
891 | 24859b68 | balrog | |
892 | 24859b68 | balrog | graphic_console_init(ds, lcd_refresh, NULL, NULL, NULL, s); |
893 | 24859b68 | balrog | dpy_resize(ds, 128*3, 64*3); |
894 | 24859b68 | balrog | } |
895 | 24859b68 | balrog | |
896 | 24859b68 | balrog | /* PIC register offsets */
|
897 | 24859b68 | balrog | #define MP_PIC_STATUS 0x00 |
898 | 24859b68 | balrog | #define MP_PIC_ENABLE_SET 0x08 |
899 | 24859b68 | balrog | #define MP_PIC_ENABLE_CLR 0x0C |
900 | 24859b68 | balrog | |
901 | 24859b68 | balrog | typedef struct mv88w8618_pic_state |
902 | 24859b68 | balrog | { |
903 | 24859b68 | balrog | uint32_t base; |
904 | 24859b68 | balrog | uint32_t level; |
905 | 24859b68 | balrog | uint32_t enabled; |
906 | 24859b68 | balrog | qemu_irq parent_irq; |
907 | 24859b68 | balrog | } mv88w8618_pic_state; |
908 | 24859b68 | balrog | |
909 | 24859b68 | balrog | static void mv88w8618_pic_update(mv88w8618_pic_state *s) |
910 | 24859b68 | balrog | { |
911 | 24859b68 | balrog | qemu_set_irq(s->parent_irq, (s->level & s->enabled)); |
912 | 24859b68 | balrog | } |
913 | 24859b68 | balrog | |
914 | 24859b68 | balrog | static void mv88w8618_pic_set_irq(void *opaque, int irq, int level) |
915 | 24859b68 | balrog | { |
916 | 24859b68 | balrog | mv88w8618_pic_state *s = opaque; |
917 | 24859b68 | balrog | |
918 | 24859b68 | balrog | if (level)
|
919 | 24859b68 | balrog | s->level |= 1 << irq;
|
920 | 24859b68 | balrog | else
|
921 | 24859b68 | balrog | s->level &= ~(1 << irq);
|
922 | 24859b68 | balrog | mv88w8618_pic_update(s); |
923 | 24859b68 | balrog | } |
924 | 24859b68 | balrog | |
925 | 24859b68 | balrog | static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset) |
926 | 24859b68 | balrog | { |
927 | 24859b68 | balrog | mv88w8618_pic_state *s = opaque; |
928 | 24859b68 | balrog | |
929 | 24859b68 | balrog | offset -= s->base; |
930 | 24859b68 | balrog | switch (offset) {
|
931 | 24859b68 | balrog | case MP_PIC_STATUS:
|
932 | 24859b68 | balrog | return s->level & s->enabled;
|
933 | 24859b68 | balrog | |
934 | 24859b68 | balrog | default:
|
935 | 24859b68 | balrog | return 0; |
936 | 24859b68 | balrog | } |
937 | 24859b68 | balrog | } |
938 | 24859b68 | balrog | |
939 | 24859b68 | balrog | static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset, |
940 | 24859b68 | balrog | uint32_t value) |
941 | 24859b68 | balrog | { |
942 | 24859b68 | balrog | mv88w8618_pic_state *s = opaque; |
943 | 24859b68 | balrog | |
944 | 24859b68 | balrog | offset -= s->base; |
945 | 24859b68 | balrog | switch (offset) {
|
946 | 24859b68 | balrog | case MP_PIC_ENABLE_SET:
|
947 | 24859b68 | balrog | s->enabled |= value; |
948 | 24859b68 | balrog | break;
|
949 | 24859b68 | balrog | |
950 | 24859b68 | balrog | case MP_PIC_ENABLE_CLR:
|
951 | 24859b68 | balrog | s->enabled &= ~value; |
952 | 24859b68 | balrog | s->level &= ~value; |
953 | 24859b68 | balrog | break;
|
954 | 24859b68 | balrog | } |
955 | 24859b68 | balrog | mv88w8618_pic_update(s); |
956 | 24859b68 | balrog | } |
957 | 24859b68 | balrog | |
958 | 24859b68 | balrog | static void mv88w8618_pic_reset(void *opaque) |
959 | 24859b68 | balrog | { |
960 | 24859b68 | balrog | mv88w8618_pic_state *s = opaque; |
961 | 24859b68 | balrog | |
962 | 24859b68 | balrog | s->level = 0;
|
963 | 24859b68 | balrog | s->enabled = 0;
|
964 | 24859b68 | balrog | } |
965 | 24859b68 | balrog | |
966 | 24859b68 | balrog | static CPUReadMemoryFunc *mv88w8618_pic_readfn[] = {
|
967 | 24859b68 | balrog | mv88w8618_pic_read, |
968 | 24859b68 | balrog | mv88w8618_pic_read, |
969 | 24859b68 | balrog | mv88w8618_pic_read |
970 | 24859b68 | balrog | }; |
971 | 24859b68 | balrog | |
972 | 24859b68 | balrog | static CPUWriteMemoryFunc *mv88w8618_pic_writefn[] = {
|
973 | 24859b68 | balrog | mv88w8618_pic_write, |
974 | 24859b68 | balrog | mv88w8618_pic_write, |
975 | 24859b68 | balrog | mv88w8618_pic_write |
976 | 24859b68 | balrog | }; |
977 | 24859b68 | balrog | |
978 | 24859b68 | balrog | static qemu_irq *mv88w8618_pic_init(uint32_t base, qemu_irq parent_irq)
|
979 | 24859b68 | balrog | { |
980 | 24859b68 | balrog | mv88w8618_pic_state *s; |
981 | 24859b68 | balrog | int iomemtype;
|
982 | 24859b68 | balrog | qemu_irq *qi; |
983 | 24859b68 | balrog | |
984 | 24859b68 | balrog | s = qemu_mallocz(sizeof(mv88w8618_pic_state));
|
985 | 24859b68 | balrog | if (!s)
|
986 | 24859b68 | balrog | return NULL; |
987 | 24859b68 | balrog | qi = qemu_allocate_irqs(mv88w8618_pic_set_irq, s, 32);
|
988 | 24859b68 | balrog | s->base = base; |
989 | 24859b68 | balrog | s->parent_irq = parent_irq; |
990 | 24859b68 | balrog | iomemtype = cpu_register_io_memory(0, mv88w8618_pic_readfn,
|
991 | 24859b68 | balrog | mv88w8618_pic_writefn, s); |
992 | 24859b68 | balrog | cpu_register_physical_memory(base, MP_PIC_SIZE, iomemtype); |
993 | 24859b68 | balrog | |
994 | 24859b68 | balrog | qemu_register_reset(mv88w8618_pic_reset, s); |
995 | 24859b68 | balrog | |
996 | 24859b68 | balrog | return qi;
|
997 | 24859b68 | balrog | } |
998 | 24859b68 | balrog | |
999 | 24859b68 | balrog | /* PIT register offsets */
|
1000 | 24859b68 | balrog | #define MP_PIT_TIMER1_LENGTH 0x00 |
1001 | 24859b68 | balrog | /* ... */
|
1002 | 24859b68 | balrog | #define MP_PIT_TIMER4_LENGTH 0x0C |
1003 | 24859b68 | balrog | #define MP_PIT_CONTROL 0x10 |
1004 | 24859b68 | balrog | #define MP_PIT_TIMER1_VALUE 0x14 |
1005 | 24859b68 | balrog | /* ... */
|
1006 | 24859b68 | balrog | #define MP_PIT_TIMER4_VALUE 0x20 |
1007 | 24859b68 | balrog | #define MP_BOARD_RESET 0x34 |
1008 | 24859b68 | balrog | |
1009 | 24859b68 | balrog | /* Magic board reset value (probably some watchdog behind it) */
|
1010 | 24859b68 | balrog | #define MP_BOARD_RESET_MAGIC 0x10000 |
1011 | 24859b68 | balrog | |
1012 | 24859b68 | balrog | typedef struct mv88w8618_timer_state { |
1013 | 24859b68 | balrog | ptimer_state *timer; |
1014 | 24859b68 | balrog | uint32_t limit; |
1015 | 24859b68 | balrog | int freq;
|
1016 | 24859b68 | balrog | qemu_irq irq; |
1017 | 24859b68 | balrog | } mv88w8618_timer_state; |
1018 | 24859b68 | balrog | |
1019 | 24859b68 | balrog | typedef struct mv88w8618_pit_state { |
1020 | 24859b68 | balrog | void *timer[4]; |
1021 | 24859b68 | balrog | uint32_t control; |
1022 | 24859b68 | balrog | uint32_t base; |
1023 | 24859b68 | balrog | } mv88w8618_pit_state; |
1024 | 24859b68 | balrog | |
1025 | 24859b68 | balrog | static void mv88w8618_timer_tick(void *opaque) |
1026 | 24859b68 | balrog | { |
1027 | 24859b68 | balrog | mv88w8618_timer_state *s = opaque; |
1028 | 24859b68 | balrog | |
1029 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
1030 | 24859b68 | balrog | } |
1031 | 24859b68 | balrog | |
1032 | 24859b68 | balrog | static void *mv88w8618_timer_init(uint32_t freq, qemu_irq irq) |
1033 | 24859b68 | balrog | { |
1034 | 24859b68 | balrog | mv88w8618_timer_state *s; |
1035 | 24859b68 | balrog | QEMUBH *bh; |
1036 | 24859b68 | balrog | |
1037 | 24859b68 | balrog | s = qemu_mallocz(sizeof(mv88w8618_timer_state));
|
1038 | 24859b68 | balrog | s->irq = irq; |
1039 | 24859b68 | balrog | s->freq = freq; |
1040 | 24859b68 | balrog | |
1041 | 24859b68 | balrog | bh = qemu_bh_new(mv88w8618_timer_tick, s); |
1042 | 24859b68 | balrog | s->timer = ptimer_init(bh); |
1043 | 24859b68 | balrog | |
1044 | 24859b68 | balrog | return s;
|
1045 | 24859b68 | balrog | } |
1046 | 24859b68 | balrog | |
1047 | 24859b68 | balrog | static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset) |
1048 | 24859b68 | balrog | { |
1049 | 24859b68 | balrog | mv88w8618_pit_state *s = opaque; |
1050 | 24859b68 | balrog | mv88w8618_timer_state *t; |
1051 | 24859b68 | balrog | |
1052 | 24859b68 | balrog | offset -= s->base; |
1053 | 24859b68 | balrog | switch (offset) {
|
1054 | 24859b68 | balrog | case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
|
1055 | 24859b68 | balrog | t = s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
|
1056 | 24859b68 | balrog | return ptimer_get_count(t->timer);
|
1057 | 24859b68 | balrog | |
1058 | 24859b68 | balrog | default:
|
1059 | 24859b68 | balrog | return 0; |
1060 | 24859b68 | balrog | } |
1061 | 24859b68 | balrog | } |
1062 | 24859b68 | balrog | |
1063 | 24859b68 | balrog | static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset, |
1064 | 24859b68 | balrog | uint32_t value) |
1065 | 24859b68 | balrog | { |
1066 | 24859b68 | balrog | mv88w8618_pit_state *s = opaque; |
1067 | 24859b68 | balrog | mv88w8618_timer_state *t; |
1068 | 24859b68 | balrog | int i;
|
1069 | 24859b68 | balrog | |
1070 | 24859b68 | balrog | offset -= s->base; |
1071 | 24859b68 | balrog | switch (offset) {
|
1072 | 24859b68 | balrog | case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
|
1073 | 24859b68 | balrog | t = s->timer[offset >> 2];
|
1074 | 24859b68 | balrog | t->limit = value; |
1075 | 24859b68 | balrog | ptimer_set_limit(t->timer, t->limit, 1);
|
1076 | 24859b68 | balrog | break;
|
1077 | 24859b68 | balrog | |
1078 | 24859b68 | balrog | case MP_PIT_CONTROL:
|
1079 | 24859b68 | balrog | for (i = 0; i < 4; i++) { |
1080 | 24859b68 | balrog | if (value & 0xf) { |
1081 | 24859b68 | balrog | t = s->timer[i]; |
1082 | 24859b68 | balrog | ptimer_set_limit(t->timer, t->limit, 0);
|
1083 | 24859b68 | balrog | ptimer_set_freq(t->timer, t->freq); |
1084 | 24859b68 | balrog | ptimer_run(t->timer, 0);
|
1085 | 24859b68 | balrog | } |
1086 | 24859b68 | balrog | value >>= 4;
|
1087 | 24859b68 | balrog | } |
1088 | 24859b68 | balrog | break;
|
1089 | 24859b68 | balrog | |
1090 | 24859b68 | balrog | case MP_BOARD_RESET:
|
1091 | 24859b68 | balrog | if (value == MP_BOARD_RESET_MAGIC)
|
1092 | 24859b68 | balrog | qemu_system_reset_request(); |
1093 | 24859b68 | balrog | break;
|
1094 | 24859b68 | balrog | } |
1095 | 24859b68 | balrog | } |
1096 | 24859b68 | balrog | |
1097 | 24859b68 | balrog | static CPUReadMemoryFunc *mv88w8618_pit_readfn[] = {
|
1098 | 24859b68 | balrog | mv88w8618_pit_read, |
1099 | 24859b68 | balrog | mv88w8618_pit_read, |
1100 | 24859b68 | balrog | mv88w8618_pit_read |
1101 | 24859b68 | balrog | }; |
1102 | 24859b68 | balrog | |
1103 | 24859b68 | balrog | static CPUWriteMemoryFunc *mv88w8618_pit_writefn[] = {
|
1104 | 24859b68 | balrog | mv88w8618_pit_write, |
1105 | 24859b68 | balrog | mv88w8618_pit_write, |
1106 | 24859b68 | balrog | mv88w8618_pit_write |
1107 | 24859b68 | balrog | }; |
1108 | 24859b68 | balrog | |
1109 | 24859b68 | balrog | static void mv88w8618_pit_init(uint32_t base, qemu_irq *pic, int irq) |
1110 | 24859b68 | balrog | { |
1111 | 24859b68 | balrog | int iomemtype;
|
1112 | 24859b68 | balrog | mv88w8618_pit_state *s; |
1113 | 24859b68 | balrog | |
1114 | 24859b68 | balrog | s = qemu_mallocz(sizeof(mv88w8618_pit_state));
|
1115 | 24859b68 | balrog | if (!s)
|
1116 | 24859b68 | balrog | return;
|
1117 | 24859b68 | balrog | |
1118 | 24859b68 | balrog | s->base = base; |
1119 | 24859b68 | balrog | /* Letting them all run at 1 MHz is likely just a pragmatic
|
1120 | 24859b68 | balrog | * simplification. */
|
1121 | 24859b68 | balrog | s->timer[0] = mv88w8618_timer_init(1000000, pic[irq]); |
1122 | 24859b68 | balrog | s->timer[1] = mv88w8618_timer_init(1000000, pic[irq + 1]); |
1123 | 24859b68 | balrog | s->timer[2] = mv88w8618_timer_init(1000000, pic[irq + 2]); |
1124 | 24859b68 | balrog | s->timer[3] = mv88w8618_timer_init(1000000, pic[irq + 3]); |
1125 | 24859b68 | balrog | |
1126 | 24859b68 | balrog | iomemtype = cpu_register_io_memory(0, mv88w8618_pit_readfn,
|
1127 | 24859b68 | balrog | mv88w8618_pit_writefn, s); |
1128 | 24859b68 | balrog | cpu_register_physical_memory(base, MP_PIT_SIZE, iomemtype); |
1129 | 24859b68 | balrog | } |
1130 | 24859b68 | balrog | |
1131 | 24859b68 | balrog | /* Flash config register offsets */
|
1132 | 24859b68 | balrog | #define MP_FLASHCFG_CFGR0 0x04 |
1133 | 24859b68 | balrog | |
1134 | 24859b68 | balrog | typedef struct mv88w8618_flashcfg_state { |
1135 | 24859b68 | balrog | uint32_t base; |
1136 | 24859b68 | balrog | uint32_t cfgr0; |
1137 | 24859b68 | balrog | } mv88w8618_flashcfg_state; |
1138 | 24859b68 | balrog | |
1139 | 24859b68 | balrog | static uint32_t mv88w8618_flashcfg_read(void *opaque, |
1140 | 24859b68 | balrog | target_phys_addr_t offset) |
1141 | 24859b68 | balrog | { |
1142 | 24859b68 | balrog | mv88w8618_flashcfg_state *s = opaque; |
1143 | 24859b68 | balrog | |
1144 | 24859b68 | balrog | offset -= s->base; |
1145 | 24859b68 | balrog | switch (offset) {
|
1146 | 24859b68 | balrog | case MP_FLASHCFG_CFGR0:
|
1147 | 24859b68 | balrog | return s->cfgr0;
|
1148 | 24859b68 | balrog | |
1149 | 24859b68 | balrog | default:
|
1150 | 24859b68 | balrog | return 0; |
1151 | 24859b68 | balrog | } |
1152 | 24859b68 | balrog | } |
1153 | 24859b68 | balrog | |
1154 | 24859b68 | balrog | static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset, |
1155 | 24859b68 | balrog | uint32_t value) |
1156 | 24859b68 | balrog | { |
1157 | 24859b68 | balrog | mv88w8618_flashcfg_state *s = opaque; |
1158 | 24859b68 | balrog | |
1159 | 24859b68 | balrog | offset -= s->base; |
1160 | 24859b68 | balrog | switch (offset) {
|
1161 | 24859b68 | balrog | case MP_FLASHCFG_CFGR0:
|
1162 | 24859b68 | balrog | s->cfgr0 = value; |
1163 | 24859b68 | balrog | break;
|
1164 | 24859b68 | balrog | } |
1165 | 24859b68 | balrog | } |
1166 | 24859b68 | balrog | |
1167 | 24859b68 | balrog | static CPUReadMemoryFunc *mv88w8618_flashcfg_readfn[] = {
|
1168 | 24859b68 | balrog | mv88w8618_flashcfg_read, |
1169 | 24859b68 | balrog | mv88w8618_flashcfg_read, |
1170 | 24859b68 | balrog | mv88w8618_flashcfg_read |
1171 | 24859b68 | balrog | }; |
1172 | 24859b68 | balrog | |
1173 | 24859b68 | balrog | static CPUWriteMemoryFunc *mv88w8618_flashcfg_writefn[] = {
|
1174 | 24859b68 | balrog | mv88w8618_flashcfg_write, |
1175 | 24859b68 | balrog | mv88w8618_flashcfg_write, |
1176 | 24859b68 | balrog | mv88w8618_flashcfg_write |
1177 | 24859b68 | balrog | }; |
1178 | 24859b68 | balrog | |
1179 | 24859b68 | balrog | static void mv88w8618_flashcfg_init(uint32_t base) |
1180 | 24859b68 | balrog | { |
1181 | 24859b68 | balrog | int iomemtype;
|
1182 | 24859b68 | balrog | mv88w8618_flashcfg_state *s; |
1183 | 24859b68 | balrog | |
1184 | 24859b68 | balrog | s = qemu_mallocz(sizeof(mv88w8618_flashcfg_state));
|
1185 | 24859b68 | balrog | if (!s)
|
1186 | 24859b68 | balrog | return;
|
1187 | 24859b68 | balrog | |
1188 | 24859b68 | balrog | s->base = base; |
1189 | 24859b68 | balrog | s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */ |
1190 | 24859b68 | balrog | iomemtype = cpu_register_io_memory(0, mv88w8618_flashcfg_readfn,
|
1191 | 24859b68 | balrog | mv88w8618_flashcfg_writefn, s); |
1192 | 24859b68 | balrog | cpu_register_physical_memory(base, MP_FLASHCFG_SIZE, iomemtype); |
1193 | 24859b68 | balrog | } |
1194 | 24859b68 | balrog | |
1195 | 24859b68 | balrog | /* Various registers in the 0x80000000 domain */
|
1196 | 24859b68 | balrog | #define MP_BOARD_REVISION 0x2018 |
1197 | 24859b68 | balrog | |
1198 | 24859b68 | balrog | #define MP_WLAN_MAGIC1 0xc11c |
1199 | 24859b68 | balrog | #define MP_WLAN_MAGIC2 0xc124 |
1200 | 24859b68 | balrog | |
1201 | 24859b68 | balrog | #define MP_GPIO_OE_LO 0xd008 |
1202 | 24859b68 | balrog | #define MP_GPIO_OUT_LO 0xd00c |
1203 | 24859b68 | balrog | #define MP_GPIO_IN_LO 0xd010 |
1204 | 24859b68 | balrog | #define MP_GPIO_ISR_LO 0xd020 |
1205 | 24859b68 | balrog | #define MP_GPIO_OE_HI 0xd508 |
1206 | 24859b68 | balrog | #define MP_GPIO_OUT_HI 0xd50c |
1207 | 24859b68 | balrog | #define MP_GPIO_IN_HI 0xd510 |
1208 | 24859b68 | balrog | #define MP_GPIO_ISR_HI 0xd520 |
1209 | 24859b68 | balrog | |
1210 | 24859b68 | balrog | /* GPIO bits & masks */
|
1211 | 24859b68 | balrog | #define MP_GPIO_WHEEL_VOL (1 << 8) |
1212 | 24859b68 | balrog | #define MP_GPIO_WHEEL_VOL_INV (1 << 9) |
1213 | 24859b68 | balrog | #define MP_GPIO_WHEEL_NAV (1 << 10) |
1214 | 24859b68 | balrog | #define MP_GPIO_WHEEL_NAV_INV (1 << 11) |
1215 | 24859b68 | balrog | #define MP_GPIO_LCD_BRIGHTNESS 0x00070000 |
1216 | 24859b68 | balrog | #define MP_GPIO_BTN_FAVORITS (1 << 19) |
1217 | 24859b68 | balrog | #define MP_GPIO_BTN_MENU (1 << 20) |
1218 | 24859b68 | balrog | #define MP_GPIO_BTN_VOLUME (1 << 21) |
1219 | 24859b68 | balrog | #define MP_GPIO_BTN_NAVIGATION (1 << 22) |
1220 | 24859b68 | balrog | #define MP_GPIO_I2C_DATA_BIT 29 |
1221 | 24859b68 | balrog | #define MP_GPIO_I2C_DATA (1 << MP_GPIO_I2C_DATA_BIT) |
1222 | 24859b68 | balrog | #define MP_GPIO_I2C_CLOCK_BIT 30 |
1223 | 24859b68 | balrog | |
1224 | 24859b68 | balrog | /* LCD brightness bits in GPIO_OE_HI */
|
1225 | 24859b68 | balrog | #define MP_OE_LCD_BRIGHTNESS 0x0007 |
1226 | 24859b68 | balrog | |
1227 | 24859b68 | balrog | static uint32_t musicpal_read(void *opaque, target_phys_addr_t offset) |
1228 | 24859b68 | balrog | { |
1229 | 24859b68 | balrog | offset -= 0x80000000;
|
1230 | 24859b68 | balrog | switch (offset) {
|
1231 | 24859b68 | balrog | case MP_BOARD_REVISION:
|
1232 | 24859b68 | balrog | return 0x0031; |
1233 | 24859b68 | balrog | |
1234 | 24859b68 | balrog | case MP_GPIO_OE_HI: /* used for LCD brightness control */ |
1235 | 24859b68 | balrog | return lcd_brightness & MP_OE_LCD_BRIGHTNESS;
|
1236 | 24859b68 | balrog | |
1237 | 24859b68 | balrog | case MP_GPIO_OUT_LO:
|
1238 | 24859b68 | balrog | return gpio_out_state & 0xFFFF; |
1239 | 24859b68 | balrog | case MP_GPIO_OUT_HI:
|
1240 | 24859b68 | balrog | return gpio_out_state >> 16; |
1241 | 24859b68 | balrog | |
1242 | 24859b68 | balrog | case MP_GPIO_IN_LO:
|
1243 | 24859b68 | balrog | return gpio_in_state & 0xFFFF; |
1244 | 24859b68 | balrog | case MP_GPIO_IN_HI:
|
1245 | 24859b68 | balrog | /* Update received I2C data */
|
1246 | 24859b68 | balrog | gpio_in_state = (gpio_in_state & ~MP_GPIO_I2C_DATA) | |
1247 | 24859b68 | balrog | (i2c_get_data(mixer_i2c) << MP_GPIO_I2C_DATA_BIT); |
1248 | 24859b68 | balrog | return gpio_in_state >> 16; |
1249 | 24859b68 | balrog | |
1250 | 24859b68 | balrog | /* This is a simplification of reality */
|
1251 | 24859b68 | balrog | case MP_GPIO_ISR_LO:
|
1252 | 24859b68 | balrog | return ~gpio_in_state & 0xFFFF; |
1253 | 24859b68 | balrog | case MP_GPIO_ISR_HI:
|
1254 | 24859b68 | balrog | return ~gpio_in_state >> 16; |
1255 | 24859b68 | balrog | |
1256 | 24859b68 | balrog | /* Workaround to allow loading the binary-only wlandrv.ko crap
|
1257 | 24859b68 | balrog | * from the original Freecom firmware. */
|
1258 | 24859b68 | balrog | case MP_WLAN_MAGIC1:
|
1259 | 24859b68 | balrog | return ~3; |
1260 | 24859b68 | balrog | case MP_WLAN_MAGIC2:
|
1261 | 24859b68 | balrog | return -1; |
1262 | 24859b68 | balrog | |
1263 | 24859b68 | balrog | default:
|
1264 | 24859b68 | balrog | return 0; |
1265 | 24859b68 | balrog | } |
1266 | 24859b68 | balrog | } |
1267 | 24859b68 | balrog | |
1268 | 24859b68 | balrog | static void musicpal_write(void *opaque, target_phys_addr_t offset, |
1269 | 24859b68 | balrog | uint32_t value) |
1270 | 24859b68 | balrog | { |
1271 | 24859b68 | balrog | offset -= 0x80000000;
|
1272 | 24859b68 | balrog | switch (offset) {
|
1273 | 24859b68 | balrog | case MP_GPIO_OE_HI: /* used for LCD brightness control */ |
1274 | 24859b68 | balrog | lcd_brightness = (lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) | |
1275 | 24859b68 | balrog | (value & MP_OE_LCD_BRIGHTNESS); |
1276 | 24859b68 | balrog | break;
|
1277 | 24859b68 | balrog | |
1278 | 24859b68 | balrog | case MP_GPIO_OUT_LO:
|
1279 | 24859b68 | balrog | gpio_out_state = (gpio_out_state & 0xFFFF0000) | (value & 0xFFFF); |
1280 | 24859b68 | balrog | break;
|
1281 | 24859b68 | balrog | case MP_GPIO_OUT_HI:
|
1282 | 24859b68 | balrog | gpio_out_state = (gpio_out_state & 0xFFFF) | (value << 16); |
1283 | 24859b68 | balrog | lcd_brightness = (lcd_brightness & 0xFFFF) |
|
1284 | 24859b68 | balrog | (gpio_out_state & MP_GPIO_LCD_BRIGHTNESS); |
1285 | 24859b68 | balrog | i2c_state_update(mixer_i2c, |
1286 | 24859b68 | balrog | (gpio_out_state >> MP_GPIO_I2C_DATA_BIT) & 1,
|
1287 | 24859b68 | balrog | (gpio_out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
|
1288 | 24859b68 | balrog | break;
|
1289 | 24859b68 | balrog | |
1290 | 24859b68 | balrog | } |
1291 | 24859b68 | balrog | } |
1292 | 24859b68 | balrog | |
1293 | 24859b68 | balrog | /* Keyboard codes & masks */
|
1294 | 24859b68 | balrog | #define KEY_PRESSED 0x80 |
1295 | 24859b68 | balrog | #define KEY_CODE 0x7f |
1296 | 24859b68 | balrog | |
1297 | 24859b68 | balrog | #define KEYCODE_TAB 0x0f |
1298 | 24859b68 | balrog | #define KEYCODE_ENTER 0x1c |
1299 | 24859b68 | balrog | #define KEYCODE_F 0x21 |
1300 | 24859b68 | balrog | #define KEYCODE_M 0x32 |
1301 | 24859b68 | balrog | |
1302 | 24859b68 | balrog | #define KEYCODE_EXTENDED 0xe0 |
1303 | 24859b68 | balrog | #define KEYCODE_UP 0x48 |
1304 | 24859b68 | balrog | #define KEYCODE_DOWN 0x50 |
1305 | 24859b68 | balrog | #define KEYCODE_LEFT 0x4b |
1306 | 24859b68 | balrog | #define KEYCODE_RIGHT 0x4d |
1307 | 24859b68 | balrog | |
1308 | 24859b68 | balrog | static void musicpal_key_event(void *opaque, int keycode) |
1309 | 24859b68 | balrog | { |
1310 | 24859b68 | balrog | qemu_irq irq = opaque; |
1311 | 24859b68 | balrog | uint32_t event = 0;
|
1312 | 24859b68 | balrog | static int kbd_extended; |
1313 | 24859b68 | balrog | |
1314 | 24859b68 | balrog | if (keycode == KEYCODE_EXTENDED) {
|
1315 | 24859b68 | balrog | kbd_extended = 1;
|
1316 | 24859b68 | balrog | return;
|
1317 | 24859b68 | balrog | } |
1318 | 24859b68 | balrog | |
1319 | 24859b68 | balrog | if (kbd_extended)
|
1320 | 24859b68 | balrog | switch (keycode & KEY_CODE) {
|
1321 | 24859b68 | balrog | case KEYCODE_UP:
|
1322 | 24859b68 | balrog | event = MP_GPIO_WHEEL_NAV | MP_GPIO_WHEEL_NAV_INV; |
1323 | 24859b68 | balrog | break;
|
1324 | 24859b68 | balrog | |
1325 | 24859b68 | balrog | case KEYCODE_DOWN:
|
1326 | 24859b68 | balrog | event = MP_GPIO_WHEEL_NAV; |
1327 | 24859b68 | balrog | break;
|
1328 | 24859b68 | balrog | |
1329 | 24859b68 | balrog | case KEYCODE_LEFT:
|
1330 | 24859b68 | balrog | event = MP_GPIO_WHEEL_VOL | MP_GPIO_WHEEL_VOL_INV; |
1331 | 24859b68 | balrog | break;
|
1332 | 24859b68 | balrog | |
1333 | 24859b68 | balrog | case KEYCODE_RIGHT:
|
1334 | 24859b68 | balrog | event = MP_GPIO_WHEEL_VOL; |
1335 | 24859b68 | balrog | break;
|
1336 | 24859b68 | balrog | } |
1337 | 24859b68 | balrog | else
|
1338 | 24859b68 | balrog | switch (keycode & KEY_CODE) {
|
1339 | 24859b68 | balrog | case KEYCODE_F:
|
1340 | 24859b68 | balrog | event = MP_GPIO_BTN_FAVORITS; |
1341 | 24859b68 | balrog | break;
|
1342 | 24859b68 | balrog | |
1343 | 24859b68 | balrog | case KEYCODE_TAB:
|
1344 | 24859b68 | balrog | event = MP_GPIO_BTN_VOLUME; |
1345 | 24859b68 | balrog | break;
|
1346 | 24859b68 | balrog | |
1347 | 24859b68 | balrog | case KEYCODE_ENTER:
|
1348 | 24859b68 | balrog | event = MP_GPIO_BTN_NAVIGATION; |
1349 | 24859b68 | balrog | break;
|
1350 | 24859b68 | balrog | |
1351 | 24859b68 | balrog | case KEYCODE_M:
|
1352 | 24859b68 | balrog | event = MP_GPIO_BTN_MENU; |
1353 | 24859b68 | balrog | break;
|
1354 | 24859b68 | balrog | } |
1355 | 24859b68 | balrog | |
1356 | 24859b68 | balrog | if (keycode & KEY_PRESSED)
|
1357 | 24859b68 | balrog | gpio_in_state |= event; |
1358 | 24859b68 | balrog | else if (gpio_in_state & event) { |
1359 | 24859b68 | balrog | gpio_in_state &= ~event; |
1360 | 24859b68 | balrog | qemu_irq_raise(irq); |
1361 | 24859b68 | balrog | } |
1362 | 24859b68 | balrog | |
1363 | 24859b68 | balrog | kbd_extended = 0;
|
1364 | 24859b68 | balrog | } |
1365 | 24859b68 | balrog | |
1366 | 24859b68 | balrog | static CPUReadMemoryFunc *musicpal_readfn[] = {
|
1367 | 24859b68 | balrog | musicpal_read, |
1368 | 24859b68 | balrog | musicpal_read, |
1369 | 24859b68 | balrog | musicpal_read, |
1370 | 24859b68 | balrog | }; |
1371 | 24859b68 | balrog | |
1372 | 24859b68 | balrog | static CPUWriteMemoryFunc *musicpal_writefn[] = {
|
1373 | 24859b68 | balrog | musicpal_write, |
1374 | 24859b68 | balrog | musicpal_write, |
1375 | 24859b68 | balrog | musicpal_write, |
1376 | 24859b68 | balrog | }; |
1377 | 24859b68 | balrog | |
1378 | 24859b68 | balrog | static struct arm_boot_info musicpal_binfo = { |
1379 | 24859b68 | balrog | .loader_start = 0x0,
|
1380 | 24859b68 | balrog | .board_id = 0x20e,
|
1381 | 24859b68 | balrog | }; |
1382 | 24859b68 | balrog | |
1383 | b0f6edb1 | balrog | static void musicpal_init(ram_addr_t ram_size, int vga_ram_size, |
1384 | 24859b68 | balrog | const char *boot_device, DisplayState *ds, |
1385 | 24859b68 | balrog | const char *kernel_filename, const char *kernel_cmdline, |
1386 | 24859b68 | balrog | const char *initrd_filename, const char *cpu_model) |
1387 | 24859b68 | balrog | { |
1388 | 24859b68 | balrog | CPUState *env; |
1389 | 24859b68 | balrog | qemu_irq *pic; |
1390 | 24859b68 | balrog | int index;
|
1391 | 24859b68 | balrog | int iomemtype;
|
1392 | 24859b68 | balrog | unsigned long flash_size; |
1393 | 24859b68 | balrog | |
1394 | 24859b68 | balrog | if (!cpu_model)
|
1395 | 24859b68 | balrog | cpu_model = "arm926";
|
1396 | 24859b68 | balrog | |
1397 | 24859b68 | balrog | env = cpu_init(cpu_model); |
1398 | 24859b68 | balrog | if (!env) {
|
1399 | 24859b68 | balrog | fprintf(stderr, "Unable to find CPU definition\n");
|
1400 | 24859b68 | balrog | exit(1);
|
1401 | 24859b68 | balrog | } |
1402 | 24859b68 | balrog | pic = arm_pic_init_cpu(env); |
1403 | 24859b68 | balrog | |
1404 | 24859b68 | balrog | /* For now we use a fixed - the original - RAM size */
|
1405 | 24859b68 | balrog | cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
|
1406 | 24859b68 | balrog | qemu_ram_alloc(MP_RAM_DEFAULT_SIZE)); |
1407 | 24859b68 | balrog | |
1408 | 24859b68 | balrog | sram_off = qemu_ram_alloc(MP_SRAM_SIZE); |
1409 | 24859b68 | balrog | cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off); |
1410 | 24859b68 | balrog | |
1411 | 24859b68 | balrog | /* Catch various stuff not handled by separate subsystems */
|
1412 | 24859b68 | balrog | iomemtype = cpu_register_io_memory(0, musicpal_readfn,
|
1413 | b0f6edb1 | balrog | musicpal_writefn, env); |
1414 | 24859b68 | balrog | cpu_register_physical_memory(0x80000000, 0x10000, iomemtype); |
1415 | 24859b68 | balrog | |
1416 | 24859b68 | balrog | pic = mv88w8618_pic_init(MP_PIC_BASE, pic[ARM_PIC_CPU_IRQ]); |
1417 | 24859b68 | balrog | mv88w8618_pit_init(MP_PIT_BASE, pic, MP_TIMER1_IRQ); |
1418 | 24859b68 | balrog | |
1419 | 24859b68 | balrog | if (serial_hds[0]) |
1420 | 24859b68 | balrog | serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], /*1825000,*/ |
1421 | 24859b68 | balrog | serial_hds[0], 1); |
1422 | 24859b68 | balrog | if (serial_hds[1]) |
1423 | 24859b68 | balrog | serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], /*1825000,*/ |
1424 | 24859b68 | balrog | serial_hds[1], 1); |
1425 | 24859b68 | balrog | |
1426 | 24859b68 | balrog | /* Register flash */
|
1427 | 24859b68 | balrog | index = drive_get_index(IF_PFLASH, 0, 0); |
1428 | 24859b68 | balrog | if (index != -1) { |
1429 | 24859b68 | balrog | flash_size = bdrv_getlength(drives_table[index].bdrv); |
1430 | 24859b68 | balrog | if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 && |
1431 | 24859b68 | balrog | flash_size != 32*1024*1024) { |
1432 | 24859b68 | balrog | fprintf(stderr, "Invalid flash image size\n");
|
1433 | 24859b68 | balrog | exit(1);
|
1434 | 24859b68 | balrog | } |
1435 | 24859b68 | balrog | |
1436 | 24859b68 | balrog | /*
|
1437 | 24859b68 | balrog | * The original U-Boot accesses the flash at 0xFE000000 instead of
|
1438 | 24859b68 | balrog | * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
|
1439 | 24859b68 | balrog | * image is smaller than 32 MB.
|
1440 | 24859b68 | balrog | */
|
1441 | 24859b68 | balrog | pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
|
1442 | 24859b68 | balrog | drives_table[index].bdrv, 0x10000,
|
1443 | 24859b68 | balrog | (flash_size + 0xffff) >> 16, |
1444 | 24859b68 | balrog | MP_FLASH_SIZE_MAX / flash_size, |
1445 | 24859b68 | balrog | 2, 0x00BF, 0x236D, 0x0000, 0x0000, |
1446 | 24859b68 | balrog | 0x5555, 0x2AAA); |
1447 | 24859b68 | balrog | } |
1448 | 24859b68 | balrog | mv88w8618_flashcfg_init(MP_FLASHCFG_BASE); |
1449 | 24859b68 | balrog | |
1450 | 24859b68 | balrog | musicpal_lcd_init(ds, MP_LCD_BASE); |
1451 | 24859b68 | balrog | |
1452 | 24859b68 | balrog | qemu_add_kbd_event_handler(musicpal_key_event, pic[MP_GPIO_IRQ]); |
1453 | 24859b68 | balrog | |
1454 | 24859b68 | balrog | /*
|
1455 | 24859b68 | balrog | * Wait a bit to catch menu button during U-Boot start-up
|
1456 | 24859b68 | balrog | * (to trigger emergency update).
|
1457 | 24859b68 | balrog | */
|
1458 | 24859b68 | balrog | sleep(1);
|
1459 | 24859b68 | balrog | |
1460 | 24859b68 | balrog | mv88w8618_eth_init(&nd_table[0], MP_ETH_BASE, pic[MP_ETH_IRQ]);
|
1461 | 24859b68 | balrog | |
1462 | 24859b68 | balrog | mixer_i2c = musicpal_audio_init(MP_AUDIO_BASE, pic[MP_AUDIO_IRQ]); |
1463 | 24859b68 | balrog | |
1464 | 24859b68 | balrog | musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; |
1465 | 24859b68 | balrog | musicpal_binfo.kernel_filename = kernel_filename; |
1466 | 24859b68 | balrog | musicpal_binfo.kernel_cmdline = kernel_cmdline; |
1467 | 24859b68 | balrog | musicpal_binfo.initrd_filename = initrd_filename; |
1468 | b0f6edb1 | balrog | arm_load_kernel(env, &musicpal_binfo); |
1469 | 24859b68 | balrog | } |
1470 | 24859b68 | balrog | |
1471 | 24859b68 | balrog | QEMUMachine musicpal_machine = { |
1472 | 24859b68 | balrog | "musicpal",
|
1473 | 24859b68 | balrog | "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
|
1474 | 24859b68 | balrog | musicpal_init, |
1475 | 24859b68 | balrog | MP_RAM_DEFAULT_SIZE + MP_SRAM_SIZE + MP_FLASH_SIZE_MAX + RAMSIZE_FIXED |
1476 | 24859b68 | balrog | }; |