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1 | d34cab9f | ths | /*
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2 | d34cab9f | ths | * QEMU VMware-SVGA "chipset".
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3 | d34cab9f | ths | *
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4 | d34cab9f | ths | * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
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5 | d34cab9f | ths | *
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6 | d34cab9f | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | d34cab9f | ths | * of this software and associated documentation files (the "Software"), to deal
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8 | d34cab9f | ths | * in the Software without restriction, including without limitation the rights
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9 | d34cab9f | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | d34cab9f | ths | * copies of the Software, and to permit persons to whom the Software is
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11 | d34cab9f | ths | * furnished to do so, subject to the following conditions:
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12 | d34cab9f | ths | *
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13 | d34cab9f | ths | * The above copyright notice and this permission notice shall be included in
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14 | d34cab9f | ths | * all copies or substantial portions of the Software.
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15 | d34cab9f | ths | *
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16 | d34cab9f | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | d34cab9f | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | d34cab9f | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | d34cab9f | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | d34cab9f | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | d34cab9f | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | d34cab9f | ths | * THE SOFTWARE.
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23 | d34cab9f | ths | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "console.h" |
26 | 87ecb68b | pbrook | #include "pci.h" |
27 | d34cab9f | ths | |
28 | d34cab9f | ths | #define VERBOSE
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29 | d34cab9f | ths | #define EMBED_STDVGA
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30 | d34cab9f | ths | #undef DIRECT_VRAM
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31 | d34cab9f | ths | #define HW_RECT_ACCEL
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32 | d34cab9f | ths | #define HW_FILL_ACCEL
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33 | d34cab9f | ths | #define HW_MOUSE_ACCEL
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34 | d34cab9f | ths | |
35 | d34cab9f | ths | #ifdef EMBED_STDVGA
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36 | d34cab9f | ths | # include "vga_int.h" |
37 | d34cab9f | ths | #endif
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38 | d34cab9f | ths | |
39 | d34cab9f | ths | struct vmsvga_state_s {
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40 | d34cab9f | ths | #ifdef EMBED_STDVGA
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41 | d34cab9f | ths | VGA_STATE_COMMON |
42 | d34cab9f | ths | #endif
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43 | d34cab9f | ths | |
44 | d34cab9f | ths | int width;
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45 | d34cab9f | ths | int height;
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46 | d34cab9f | ths | int invalidated;
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47 | d34cab9f | ths | int depth;
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48 | d34cab9f | ths | int bypp;
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49 | d34cab9f | ths | int enable;
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50 | d34cab9f | ths | int config;
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51 | d34cab9f | ths | struct {
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52 | d34cab9f | ths | int id;
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53 | d34cab9f | ths | int x;
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54 | d34cab9f | ths | int y;
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55 | d34cab9f | ths | int on;
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56 | d34cab9f | ths | } cursor; |
57 | d34cab9f | ths | |
58 | d34cab9f | ths | #ifndef EMBED_STDVGA
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59 | d34cab9f | ths | DisplayState *ds; |
60 | d34cab9f | ths | int vram_size;
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61 | 6f9bc132 | balrog | ram_addr_t vram_offset; |
62 | d34cab9f | ths | #endif
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63 | d34cab9f | ths | uint8_t *vram; |
64 | 3016d80b | balrog | target_phys_addr_t vram_base; |
65 | d34cab9f | ths | |
66 | d34cab9f | ths | int index;
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67 | d34cab9f | ths | int scratch_size;
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68 | d34cab9f | ths | uint32_t *scratch; |
69 | d34cab9f | ths | int new_width;
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70 | d34cab9f | ths | int new_height;
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71 | d34cab9f | ths | uint32_t guest; |
72 | d34cab9f | ths | uint32_t svgaid; |
73 | d34cab9f | ths | uint32_t wred; |
74 | d34cab9f | ths | uint32_t wgreen; |
75 | d34cab9f | ths | uint32_t wblue; |
76 | d34cab9f | ths | int syncing;
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77 | d34cab9f | ths | int fb_size;
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78 | d34cab9f | ths | |
79 | d34cab9f | ths | union {
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80 | d34cab9f | ths | uint32_t *fifo; |
81 | d34cab9f | ths | struct __attribute__((__packed__)) {
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82 | d34cab9f | ths | uint32_t min; |
83 | d34cab9f | ths | uint32_t max; |
84 | d34cab9f | ths | uint32_t next_cmd; |
85 | d34cab9f | ths | uint32_t stop; |
86 | d34cab9f | ths | /* Add registers here when adding capabilities. */
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87 | d34cab9f | ths | uint32_t fifo[0];
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88 | d34cab9f | ths | } *cmd; |
89 | d34cab9f | ths | }; |
90 | d34cab9f | ths | |
91 | d34cab9f | ths | #define REDRAW_FIFO_LEN 512 |
92 | d34cab9f | ths | struct vmsvga_rect_s {
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93 | d34cab9f | ths | int x, y, w, h;
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94 | d34cab9f | ths | } redraw_fifo[REDRAW_FIFO_LEN]; |
95 | d34cab9f | ths | int redraw_fifo_first, redraw_fifo_last;
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96 | d34cab9f | ths | }; |
97 | d34cab9f | ths | |
98 | d34cab9f | ths | struct pci_vmsvga_state_s {
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99 | d34cab9f | ths | PCIDevice card; |
100 | d34cab9f | ths | struct vmsvga_state_s chip;
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101 | d34cab9f | ths | }; |
102 | d34cab9f | ths | |
103 | d34cab9f | ths | #define SVGA_MAGIC 0x900000UL |
104 | d34cab9f | ths | #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) |
105 | d34cab9f | ths | #define SVGA_ID_0 SVGA_MAKE_ID(0) |
106 | d34cab9f | ths | #define SVGA_ID_1 SVGA_MAKE_ID(1) |
107 | d34cab9f | ths | #define SVGA_ID_2 SVGA_MAKE_ID(2) |
108 | d34cab9f | ths | |
109 | d34cab9f | ths | #define SVGA_LEGACY_BASE_PORT 0x4560 |
110 | d34cab9f | ths | #define SVGA_INDEX_PORT 0x0 |
111 | d34cab9f | ths | #define SVGA_VALUE_PORT 0x1 |
112 | d34cab9f | ths | #define SVGA_BIOS_PORT 0x2 |
113 | d34cab9f | ths | |
114 | d34cab9f | ths | #define SVGA_VERSION_2
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115 | d34cab9f | ths | |
116 | d34cab9f | ths | #ifdef SVGA_VERSION_2
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117 | d34cab9f | ths | # define SVGA_ID SVGA_ID_2
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118 | d34cab9f | ths | # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
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119 | d34cab9f | ths | # define SVGA_IO_MUL 1 |
120 | d34cab9f | ths | # define SVGA_FIFO_SIZE 0x10000 |
121 | 1f72aae5 | balrog | # define SVGA_MEM_BASE 0xe0000000 |
122 | d34cab9f | ths | # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
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123 | d34cab9f | ths | #else
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124 | d34cab9f | ths | # define SVGA_ID SVGA_ID_1
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125 | d34cab9f | ths | # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
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126 | d34cab9f | ths | # define SVGA_IO_MUL 4 |
127 | d34cab9f | ths | # define SVGA_FIFO_SIZE 0x10000 |
128 | 1f72aae5 | balrog | # define SVGA_MEM_BASE 0xe0000000 |
129 | d34cab9f | ths | # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
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130 | d34cab9f | ths | #endif
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131 | d34cab9f | ths | |
132 | d34cab9f | ths | enum {
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133 | d34cab9f | ths | /* ID 0, 1 and 2 registers */
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134 | d34cab9f | ths | SVGA_REG_ID = 0,
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135 | d34cab9f | ths | SVGA_REG_ENABLE = 1,
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136 | d34cab9f | ths | SVGA_REG_WIDTH = 2,
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137 | d34cab9f | ths | SVGA_REG_HEIGHT = 3,
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138 | d34cab9f | ths | SVGA_REG_MAX_WIDTH = 4,
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139 | d34cab9f | ths | SVGA_REG_MAX_HEIGHT = 5,
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140 | d34cab9f | ths | SVGA_REG_DEPTH = 6,
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141 | d34cab9f | ths | SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ |
142 | d34cab9f | ths | SVGA_REG_PSEUDOCOLOR = 8,
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143 | d34cab9f | ths | SVGA_REG_RED_MASK = 9,
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144 | d34cab9f | ths | SVGA_REG_GREEN_MASK = 10,
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145 | d34cab9f | ths | SVGA_REG_BLUE_MASK = 11,
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146 | d34cab9f | ths | SVGA_REG_BYTES_PER_LINE = 12,
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147 | d34cab9f | ths | SVGA_REG_FB_START = 13,
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148 | d34cab9f | ths | SVGA_REG_FB_OFFSET = 14,
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149 | d34cab9f | ths | SVGA_REG_VRAM_SIZE = 15,
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150 | d34cab9f | ths | SVGA_REG_FB_SIZE = 16,
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151 | d34cab9f | ths | |
152 | d34cab9f | ths | /* ID 1 and 2 registers */
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153 | d34cab9f | ths | SVGA_REG_CAPABILITIES = 17,
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154 | d34cab9f | ths | SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ |
155 | d34cab9f | ths | SVGA_REG_MEM_SIZE = 19,
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156 | d34cab9f | ths | SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ |
157 | d34cab9f | ths | SVGA_REG_SYNC = 21, /* Write to force synchronization */ |
158 | d34cab9f | ths | SVGA_REG_BUSY = 22, /* Read to check if sync is done */ |
159 | d34cab9f | ths | SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ |
160 | d34cab9f | ths | SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ |
161 | d34cab9f | ths | SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ |
162 | d34cab9f | ths | SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ |
163 | d34cab9f | ths | SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ |
164 | d34cab9f | ths | SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ |
165 | d34cab9f | ths | SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ |
166 | d34cab9f | ths | SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ |
167 | d34cab9f | ths | SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ |
168 | d34cab9f | ths | SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ |
169 | d34cab9f | ths | |
170 | d34cab9f | ths | SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ |
171 | d34cab9f | ths | SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
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172 | d34cab9f | ths | SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
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173 | d34cab9f | ths | }; |
174 | d34cab9f | ths | |
175 | d34cab9f | ths | #define SVGA_CAP_NONE 0 |
176 | d34cab9f | ths | #define SVGA_CAP_RECT_FILL (1 << 0) |
177 | d34cab9f | ths | #define SVGA_CAP_RECT_COPY (1 << 1) |
178 | d34cab9f | ths | #define SVGA_CAP_RECT_PAT_FILL (1 << 2) |
179 | d34cab9f | ths | #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) |
180 | d34cab9f | ths | #define SVGA_CAP_RASTER_OP (1 << 4) |
181 | d34cab9f | ths | #define SVGA_CAP_CURSOR (1 << 5) |
182 | d34cab9f | ths | #define SVGA_CAP_CURSOR_BYPASS (1 << 6) |
183 | d34cab9f | ths | #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) |
184 | d34cab9f | ths | #define SVGA_CAP_8BIT_EMULATION (1 << 8) |
185 | d34cab9f | ths | #define SVGA_CAP_ALPHA_CURSOR (1 << 9) |
186 | d34cab9f | ths | #define SVGA_CAP_GLYPH (1 << 10) |
187 | d34cab9f | ths | #define SVGA_CAP_GLYPH_CLIPPING (1 << 11) |
188 | d34cab9f | ths | #define SVGA_CAP_OFFSCREEN_1 (1 << 12) |
189 | d34cab9f | ths | #define SVGA_CAP_ALPHA_BLEND (1 << 13) |
190 | d34cab9f | ths | #define SVGA_CAP_3D (1 << 14) |
191 | d34cab9f | ths | #define SVGA_CAP_EXTENDED_FIFO (1 << 15) |
192 | d34cab9f | ths | #define SVGA_CAP_MULTIMON (1 << 16) |
193 | d34cab9f | ths | #define SVGA_CAP_PITCHLOCK (1 << 17) |
194 | d34cab9f | ths | |
195 | d34cab9f | ths | /*
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196 | d34cab9f | ths | * FIFO offsets (seen as an array of 32-bit words)
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197 | d34cab9f | ths | */
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198 | d34cab9f | ths | enum {
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199 | d34cab9f | ths | /*
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200 | d34cab9f | ths | * The original defined FIFO offsets
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201 | d34cab9f | ths | */
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202 | d34cab9f | ths | SVGA_FIFO_MIN = 0,
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203 | d34cab9f | ths | SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
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204 | d34cab9f | ths | SVGA_FIFO_NEXT_CMD, |
205 | d34cab9f | ths | SVGA_FIFO_STOP, |
206 | d34cab9f | ths | |
207 | d34cab9f | ths | /*
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208 | d34cab9f | ths | * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
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209 | d34cab9f | ths | */
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210 | d34cab9f | ths | SVGA_FIFO_CAPABILITIES = 4,
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211 | d34cab9f | ths | SVGA_FIFO_FLAGS, |
212 | d34cab9f | ths | SVGA_FIFO_FENCE, |
213 | d34cab9f | ths | SVGA_FIFO_3D_HWVERSION, |
214 | d34cab9f | ths | SVGA_FIFO_PITCHLOCK, |
215 | d34cab9f | ths | }; |
216 | d34cab9f | ths | |
217 | d34cab9f | ths | #define SVGA_FIFO_CAP_NONE 0 |
218 | d34cab9f | ths | #define SVGA_FIFO_CAP_FENCE (1 << 0) |
219 | d34cab9f | ths | #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) |
220 | d34cab9f | ths | #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) |
221 | d34cab9f | ths | |
222 | d34cab9f | ths | #define SVGA_FIFO_FLAG_NONE 0 |
223 | d34cab9f | ths | #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) |
224 | d34cab9f | ths | |
225 | d34cab9f | ths | /* These values can probably be changed arbitrarily. */
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226 | d34cab9f | ths | #define SVGA_SCRATCH_SIZE 0x8000 |
227 | d34cab9f | ths | #define SVGA_MAX_WIDTH 2360 |
228 | d34cab9f | ths | #define SVGA_MAX_HEIGHT 1770 |
229 | d34cab9f | ths | |
230 | d34cab9f | ths | #ifdef VERBOSE
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231 | d34cab9f | ths | # define GUEST_OS_BASE 0x5001 |
232 | d34cab9f | ths | static const char *vmsvga_guest_id[] = { |
233 | f707cfba | balrog | [0x00 ... 0x15] = "an unknown OS", |
234 | f707cfba | balrog | [0x00] = "Dos", |
235 | f707cfba | balrog | [0x01] = "Windows 3.1", |
236 | f707cfba | balrog | [0x02] = "Windows 95", |
237 | f707cfba | balrog | [0x03] = "Windows 98", |
238 | f707cfba | balrog | [0x04] = "Windows ME", |
239 | f707cfba | balrog | [0x05] = "Windows NT", |
240 | f707cfba | balrog | [0x06] = "Windows 2000", |
241 | f707cfba | balrog | [0x07] = "Linux", |
242 | f707cfba | balrog | [0x08] = "OS/2", |
243 | f707cfba | balrog | [0x0a] = "BSD", |
244 | f707cfba | balrog | [0x0b] = "Whistler", |
245 | f707cfba | balrog | [0x15] = "Windows 2003", |
246 | d34cab9f | ths | }; |
247 | d34cab9f | ths | #endif
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248 | d34cab9f | ths | |
249 | d34cab9f | ths | enum {
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250 | d34cab9f | ths | SVGA_CMD_INVALID_CMD = 0,
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251 | d34cab9f | ths | SVGA_CMD_UPDATE = 1,
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252 | d34cab9f | ths | SVGA_CMD_RECT_FILL = 2,
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253 | d34cab9f | ths | SVGA_CMD_RECT_COPY = 3,
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254 | d34cab9f | ths | SVGA_CMD_DEFINE_BITMAP = 4,
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255 | d34cab9f | ths | SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
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256 | d34cab9f | ths | SVGA_CMD_DEFINE_PIXMAP = 6,
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257 | d34cab9f | ths | SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
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258 | d34cab9f | ths | SVGA_CMD_RECT_BITMAP_FILL = 8,
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259 | d34cab9f | ths | SVGA_CMD_RECT_PIXMAP_FILL = 9,
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260 | d34cab9f | ths | SVGA_CMD_RECT_BITMAP_COPY = 10,
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261 | d34cab9f | ths | SVGA_CMD_RECT_PIXMAP_COPY = 11,
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262 | d34cab9f | ths | SVGA_CMD_FREE_OBJECT = 12,
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263 | d34cab9f | ths | SVGA_CMD_RECT_ROP_FILL = 13,
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264 | d34cab9f | ths | SVGA_CMD_RECT_ROP_COPY = 14,
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265 | d34cab9f | ths | SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
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266 | d34cab9f | ths | SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
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267 | d34cab9f | ths | SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
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268 | d34cab9f | ths | SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
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269 | d34cab9f | ths | SVGA_CMD_DEFINE_CURSOR = 19,
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270 | d34cab9f | ths | SVGA_CMD_DISPLAY_CURSOR = 20,
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271 | d34cab9f | ths | SVGA_CMD_MOVE_CURSOR = 21,
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272 | d34cab9f | ths | SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
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273 | d34cab9f | ths | SVGA_CMD_DRAW_GLYPH = 23,
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274 | d34cab9f | ths | SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
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275 | d34cab9f | ths | SVGA_CMD_UPDATE_VERBOSE = 25,
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276 | d34cab9f | ths | SVGA_CMD_SURFACE_FILL = 26,
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277 | d34cab9f | ths | SVGA_CMD_SURFACE_COPY = 27,
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278 | d34cab9f | ths | SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
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279 | d34cab9f | ths | SVGA_CMD_FRONT_ROP_FILL = 29,
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280 | d34cab9f | ths | SVGA_CMD_FENCE = 30,
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281 | d34cab9f | ths | }; |
282 | d34cab9f | ths | |
283 | d34cab9f | ths | /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
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284 | d34cab9f | ths | enum {
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285 | d34cab9f | ths | SVGA_CURSOR_ON_HIDE = 0,
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286 | d34cab9f | ths | SVGA_CURSOR_ON_SHOW = 1,
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287 | d34cab9f | ths | SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
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288 | d34cab9f | ths | SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
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289 | d34cab9f | ths | }; |
290 | d34cab9f | ths | |
291 | d34cab9f | ths | static inline void vmsvga_update_rect(struct vmsvga_state_s *s, |
292 | d34cab9f | ths | int x, int y, int w, int h) |
293 | d34cab9f | ths | { |
294 | d34cab9f | ths | #ifndef DIRECT_VRAM
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295 | a8fbaf96 | balrog | int line;
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296 | a8fbaf96 | balrog | int bypl;
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297 | a8fbaf96 | balrog | int width;
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298 | a8fbaf96 | balrog | int start;
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299 | a8fbaf96 | balrog | uint8_t *src; |
300 | a8fbaf96 | balrog | uint8_t *dst; |
301 | a8fbaf96 | balrog | |
302 | a8fbaf96 | balrog | if (x + w > s->width) {
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303 | a8fbaf96 | balrog | fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
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304 | a8fbaf96 | balrog | __FUNCTION__, x, w); |
305 | a8fbaf96 | balrog | x = MIN(x, s->width); |
306 | a8fbaf96 | balrog | w = s->width - x; |
307 | a8fbaf96 | balrog | } |
308 | a8fbaf96 | balrog | |
309 | a8fbaf96 | balrog | if (y + h > s->height) {
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310 | a8fbaf96 | balrog | fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
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311 | a8fbaf96 | balrog | __FUNCTION__, y, h); |
312 | a8fbaf96 | balrog | y = MIN(y, s->height); |
313 | a8fbaf96 | balrog | h = s->height - y; |
314 | a8fbaf96 | balrog | } |
315 | a8fbaf96 | balrog | |
316 | a8fbaf96 | balrog | line = h; |
317 | a8fbaf96 | balrog | bypl = s->bypp * s->width; |
318 | a8fbaf96 | balrog | width = s->bypp * w; |
319 | a8fbaf96 | balrog | start = s->bypp * x + bypl * y; |
320 | a8fbaf96 | balrog | src = s->vram + start; |
321 | a8fbaf96 | balrog | dst = s->ds->data + start; |
322 | d34cab9f | ths | |
323 | d34cab9f | ths | for (; line > 0; line --, src += bypl, dst += bypl) |
324 | d34cab9f | ths | memcpy(dst, src, width); |
325 | d34cab9f | ths | #endif
|
326 | d34cab9f | ths | |
327 | d34cab9f | ths | dpy_update(s->ds, x, y, w, h); |
328 | d34cab9f | ths | } |
329 | d34cab9f | ths | |
330 | d34cab9f | ths | static inline void vmsvga_update_screen(struct vmsvga_state_s *s) |
331 | d34cab9f | ths | { |
332 | d34cab9f | ths | #ifndef DIRECT_VRAM
|
333 | d34cab9f | ths | memcpy(s->ds->data, s->vram, s->bypp * s->width * s->height); |
334 | d34cab9f | ths | #endif
|
335 | d34cab9f | ths | |
336 | d34cab9f | ths | dpy_update(s->ds, 0, 0, s->width, s->height); |
337 | d34cab9f | ths | } |
338 | d34cab9f | ths | |
339 | d34cab9f | ths | #ifdef DIRECT_VRAM
|
340 | d34cab9f | ths | # define vmsvga_update_rect_delayed vmsvga_update_rect
|
341 | d34cab9f | ths | #else
|
342 | d34cab9f | ths | static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, |
343 | d34cab9f | ths | int x, int y, int w, int h) |
344 | d34cab9f | ths | { |
345 | d34cab9f | ths | struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
|
346 | d34cab9f | ths | s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
|
347 | d34cab9f | ths | rect->x = x; |
348 | d34cab9f | ths | rect->y = y; |
349 | d34cab9f | ths | rect->w = w; |
350 | d34cab9f | ths | rect->h = h; |
351 | d34cab9f | ths | } |
352 | d34cab9f | ths | #endif
|
353 | d34cab9f | ths | |
354 | d34cab9f | ths | static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) |
355 | d34cab9f | ths | { |
356 | d34cab9f | ths | struct vmsvga_rect_s *rect;
|
357 | d34cab9f | ths | if (s->invalidated) {
|
358 | d34cab9f | ths | s->redraw_fifo_first = s->redraw_fifo_last; |
359 | d34cab9f | ths | return;
|
360 | d34cab9f | ths | } |
361 | d34cab9f | ths | /* Overlapping region updates can be optimised out here - if someone
|
362 | d34cab9f | ths | * knows a smart algorithm to do that, please share. */
|
363 | d34cab9f | ths | while (s->redraw_fifo_first != s->redraw_fifo_last) {
|
364 | d34cab9f | ths | rect = &s->redraw_fifo[s->redraw_fifo_first ++]; |
365 | d34cab9f | ths | s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
|
366 | d34cab9f | ths | vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h); |
367 | d34cab9f | ths | } |
368 | d34cab9f | ths | } |
369 | d34cab9f | ths | |
370 | d34cab9f | ths | #ifdef HW_RECT_ACCEL
|
371 | d34cab9f | ths | static inline void vmsvga_copy_rect(struct vmsvga_state_s *s, |
372 | d34cab9f | ths | int x0, int y0, int x1, int y1, int w, int h) |
373 | d34cab9f | ths | { |
374 | d34cab9f | ths | # ifdef DIRECT_VRAM
|
375 | d34cab9f | ths | uint8_t *vram = s->ds->data; |
376 | d34cab9f | ths | # else
|
377 | d34cab9f | ths | uint8_t *vram = s->vram; |
378 | d34cab9f | ths | # endif
|
379 | d34cab9f | ths | int bypl = s->bypp * s->width;
|
380 | d34cab9f | ths | int width = s->bypp * w;
|
381 | d34cab9f | ths | int line = h;
|
382 | d34cab9f | ths | uint8_t *ptr[2];
|
383 | d34cab9f | ths | |
384 | d34cab9f | ths | # ifdef DIRECT_VRAM
|
385 | d34cab9f | ths | if (s->ds->dpy_copy)
|
386 | d34cab9f | ths | s->ds->dpy_copy(s->ds, x0, y0, x1, y1, w, h); |
387 | d34cab9f | ths | else
|
388 | d34cab9f | ths | # endif
|
389 | d34cab9f | ths | { |
390 | d34cab9f | ths | if (y1 > y0) {
|
391 | d34cab9f | ths | ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1); |
392 | d34cab9f | ths | ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1); |
393 | d34cab9f | ths | for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) |
394 | d34cab9f | ths | memmove(ptr[1], ptr[0], width); |
395 | d34cab9f | ths | } else {
|
396 | d34cab9f | ths | ptr[0] = vram + s->bypp * x0 + bypl * y0;
|
397 | d34cab9f | ths | ptr[1] = vram + s->bypp * x1 + bypl * y1;
|
398 | d34cab9f | ths | for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) |
399 | d34cab9f | ths | memmove(ptr[1], ptr[0], width); |
400 | d34cab9f | ths | } |
401 | d34cab9f | ths | } |
402 | d34cab9f | ths | |
403 | d34cab9f | ths | vmsvga_update_rect_delayed(s, x1, y1, w, h); |
404 | d34cab9f | ths | } |
405 | d34cab9f | ths | #endif
|
406 | d34cab9f | ths | |
407 | d34cab9f | ths | #ifdef HW_FILL_ACCEL
|
408 | d34cab9f | ths | static inline void vmsvga_fill_rect(struct vmsvga_state_s *s, |
409 | d34cab9f | ths | uint32_t c, int x, int y, int w, int h) |
410 | d34cab9f | ths | { |
411 | d34cab9f | ths | # ifdef DIRECT_VRAM
|
412 | d34cab9f | ths | uint8_t *vram = s->ds->data; |
413 | d34cab9f | ths | # else
|
414 | d34cab9f | ths | uint8_t *vram = s->vram; |
415 | d34cab9f | ths | # endif
|
416 | d34cab9f | ths | int bypp = s->bypp;
|
417 | d34cab9f | ths | int bypl = bypp * s->width;
|
418 | d34cab9f | ths | int width = bypp * w;
|
419 | d34cab9f | ths | int line = h;
|
420 | d34cab9f | ths | int column;
|
421 | d34cab9f | ths | uint8_t *fst = vram + bypp * x + bypl * y; |
422 | d34cab9f | ths | uint8_t *dst; |
423 | d34cab9f | ths | uint8_t *src; |
424 | d34cab9f | ths | uint8_t col[4];
|
425 | d34cab9f | ths | |
426 | d34cab9f | ths | # ifdef DIRECT_VRAM
|
427 | d34cab9f | ths | if (s->ds->dpy_fill)
|
428 | d34cab9f | ths | s->ds->dpy_fill(s->ds, x, y, w, h, c); |
429 | d34cab9f | ths | else
|
430 | d34cab9f | ths | # endif
|
431 | d34cab9f | ths | { |
432 | d34cab9f | ths | col[0] = c;
|
433 | d34cab9f | ths | col[1] = c >> 8; |
434 | d34cab9f | ths | col[2] = c >> 16; |
435 | d34cab9f | ths | col[3] = c >> 24; |
436 | d34cab9f | ths | |
437 | d34cab9f | ths | if (line --) {
|
438 | d34cab9f | ths | dst = fst; |
439 | d34cab9f | ths | src = col; |
440 | d34cab9f | ths | for (column = width; column > 0; column --) { |
441 | d34cab9f | ths | *(dst ++) = *(src ++); |
442 | d34cab9f | ths | if (src - col == bypp)
|
443 | d34cab9f | ths | src = col; |
444 | d34cab9f | ths | } |
445 | d34cab9f | ths | dst = fst; |
446 | d34cab9f | ths | for (; line > 0; line --) { |
447 | d34cab9f | ths | dst += bypl; |
448 | d34cab9f | ths | memcpy(dst, fst, width); |
449 | d34cab9f | ths | } |
450 | d34cab9f | ths | } |
451 | d34cab9f | ths | } |
452 | d34cab9f | ths | |
453 | d34cab9f | ths | vmsvga_update_rect_delayed(s, x, y, w, h); |
454 | d34cab9f | ths | } |
455 | d34cab9f | ths | #endif
|
456 | d34cab9f | ths | |
457 | d34cab9f | ths | struct vmsvga_cursor_definition_s {
|
458 | d34cab9f | ths | int width;
|
459 | d34cab9f | ths | int height;
|
460 | d34cab9f | ths | int id;
|
461 | d34cab9f | ths | int bpp;
|
462 | d34cab9f | ths | int hot_x;
|
463 | d34cab9f | ths | int hot_y;
|
464 | d34cab9f | ths | uint32_t mask[1024];
|
465 | d34cab9f | ths | uint32_t image[1024];
|
466 | d34cab9f | ths | }; |
467 | d34cab9f | ths | |
468 | d34cab9f | ths | #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) |
469 | d34cab9f | ths | #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) |
470 | d34cab9f | ths | |
471 | d34cab9f | ths | #ifdef HW_MOUSE_ACCEL
|
472 | d34cab9f | ths | static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, |
473 | d34cab9f | ths | struct vmsvga_cursor_definition_s *c)
|
474 | d34cab9f | ths | { |
475 | d34cab9f | ths | int i;
|
476 | d34cab9f | ths | for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --) |
477 | d34cab9f | ths | c->mask[i] = ~c->mask[i]; |
478 | d34cab9f | ths | |
479 | d34cab9f | ths | if (s->ds->cursor_define)
|
480 | d34cab9f | ths | s->ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y, |
481 | d34cab9f | ths | (uint8_t *) c->image, (uint8_t *) c->mask); |
482 | d34cab9f | ths | } |
483 | d34cab9f | ths | #endif
|
484 | d34cab9f | ths | |
485 | d34cab9f | ths | static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s) |
486 | d34cab9f | ths | { |
487 | d34cab9f | ths | if (!s->config || !s->enable)
|
488 | f707cfba | balrog | return 1; |
489 | d34cab9f | ths | return (s->cmd->next_cmd == s->cmd->stop);
|
490 | d34cab9f | ths | } |
491 | d34cab9f | ths | |
492 | d34cab9f | ths | static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s) |
493 | d34cab9f | ths | { |
494 | d34cab9f | ths | uint32_t cmd = s->fifo[s->cmd->stop >> 2];
|
495 | d34cab9f | ths | s->cmd->stop += 4;
|
496 | d34cab9f | ths | if (s->cmd->stop >= s->cmd->max)
|
497 | d34cab9f | ths | s->cmd->stop = s->cmd->min; |
498 | d34cab9f | ths | return cmd;
|
499 | d34cab9f | ths | } |
500 | d34cab9f | ths | |
501 | d34cab9f | ths | static void vmsvga_fifo_run(struct vmsvga_state_s *s) |
502 | d34cab9f | ths | { |
503 | d34cab9f | ths | uint32_t cmd, colour; |
504 | d34cab9f | ths | int args = 0; |
505 | d34cab9f | ths | int x, y, dx, dy, width, height;
|
506 | d34cab9f | ths | struct vmsvga_cursor_definition_s cursor;
|
507 | d34cab9f | ths | while (!vmsvga_fifo_empty(s))
|
508 | d34cab9f | ths | switch (cmd = vmsvga_fifo_read(s)) {
|
509 | d34cab9f | ths | case SVGA_CMD_UPDATE:
|
510 | d34cab9f | ths | case SVGA_CMD_UPDATE_VERBOSE:
|
511 | d34cab9f | ths | x = vmsvga_fifo_read(s); |
512 | d34cab9f | ths | y = vmsvga_fifo_read(s); |
513 | d34cab9f | ths | width = vmsvga_fifo_read(s); |
514 | d34cab9f | ths | height = vmsvga_fifo_read(s); |
515 | d34cab9f | ths | vmsvga_update_rect_delayed(s, x, y, width, height); |
516 | d34cab9f | ths | break;
|
517 | d34cab9f | ths | |
518 | d34cab9f | ths | case SVGA_CMD_RECT_FILL:
|
519 | d34cab9f | ths | colour = vmsvga_fifo_read(s); |
520 | d34cab9f | ths | x = vmsvga_fifo_read(s); |
521 | d34cab9f | ths | y = vmsvga_fifo_read(s); |
522 | d34cab9f | ths | width = vmsvga_fifo_read(s); |
523 | d34cab9f | ths | height = vmsvga_fifo_read(s); |
524 | d34cab9f | ths | #ifdef HW_FILL_ACCEL
|
525 | d34cab9f | ths | vmsvga_fill_rect(s, colour, x, y, width, height); |
526 | d34cab9f | ths | break;
|
527 | d34cab9f | ths | #else
|
528 | d34cab9f | ths | goto badcmd;
|
529 | d34cab9f | ths | #endif
|
530 | d34cab9f | ths | |
531 | d34cab9f | ths | case SVGA_CMD_RECT_COPY:
|
532 | d34cab9f | ths | x = vmsvga_fifo_read(s); |
533 | d34cab9f | ths | y = vmsvga_fifo_read(s); |
534 | d34cab9f | ths | dx = vmsvga_fifo_read(s); |
535 | d34cab9f | ths | dy = vmsvga_fifo_read(s); |
536 | d34cab9f | ths | width = vmsvga_fifo_read(s); |
537 | d34cab9f | ths | height = vmsvga_fifo_read(s); |
538 | d34cab9f | ths | #ifdef HW_RECT_ACCEL
|
539 | d34cab9f | ths | vmsvga_copy_rect(s, x, y, dx, dy, width, height); |
540 | d34cab9f | ths | break;
|
541 | d34cab9f | ths | #else
|
542 | d34cab9f | ths | goto badcmd;
|
543 | d34cab9f | ths | #endif
|
544 | d34cab9f | ths | |
545 | d34cab9f | ths | case SVGA_CMD_DEFINE_CURSOR:
|
546 | d34cab9f | ths | cursor.id = vmsvga_fifo_read(s); |
547 | d34cab9f | ths | cursor.hot_x = vmsvga_fifo_read(s); |
548 | d34cab9f | ths | cursor.hot_y = vmsvga_fifo_read(s); |
549 | d34cab9f | ths | cursor.width = x = vmsvga_fifo_read(s); |
550 | d34cab9f | ths | cursor.height = y = vmsvga_fifo_read(s); |
551 | d34cab9f | ths | vmsvga_fifo_read(s); |
552 | d34cab9f | ths | cursor.bpp = vmsvga_fifo_read(s); |
553 | d34cab9f | ths | for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++) |
554 | d34cab9f | ths | cursor.mask[args] = vmsvga_fifo_read(s); |
555 | d34cab9f | ths | for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++) |
556 | d34cab9f | ths | cursor.image[args] = vmsvga_fifo_read(s); |
557 | d34cab9f | ths | #ifdef HW_MOUSE_ACCEL
|
558 | d34cab9f | ths | vmsvga_cursor_define(s, &cursor); |
559 | d34cab9f | ths | break;
|
560 | d34cab9f | ths | #else
|
561 | d34cab9f | ths | args = 0;
|
562 | d34cab9f | ths | goto badcmd;
|
563 | d34cab9f | ths | #endif
|
564 | d34cab9f | ths | |
565 | d34cab9f | ths | /*
|
566 | d34cab9f | ths | * Other commands that we at least know the number of arguments
|
567 | d34cab9f | ths | * for so we can avoid FIFO desync if driver uses them illegally.
|
568 | d34cab9f | ths | */
|
569 | d34cab9f | ths | case SVGA_CMD_DEFINE_ALPHA_CURSOR:
|
570 | d34cab9f | ths | vmsvga_fifo_read(s); |
571 | d34cab9f | ths | vmsvga_fifo_read(s); |
572 | d34cab9f | ths | vmsvga_fifo_read(s); |
573 | d34cab9f | ths | x = vmsvga_fifo_read(s); |
574 | d34cab9f | ths | y = vmsvga_fifo_read(s); |
575 | d34cab9f | ths | args = x * y; |
576 | d34cab9f | ths | goto badcmd;
|
577 | d34cab9f | ths | case SVGA_CMD_RECT_ROP_FILL:
|
578 | d34cab9f | ths | args = 6;
|
579 | d34cab9f | ths | goto badcmd;
|
580 | d34cab9f | ths | case SVGA_CMD_RECT_ROP_COPY:
|
581 | d34cab9f | ths | args = 7;
|
582 | d34cab9f | ths | goto badcmd;
|
583 | d34cab9f | ths | case SVGA_CMD_DRAW_GLYPH_CLIPPED:
|
584 | d34cab9f | ths | vmsvga_fifo_read(s); |
585 | d34cab9f | ths | vmsvga_fifo_read(s); |
586 | d34cab9f | ths | args = 7 + (vmsvga_fifo_read(s) >> 2); |
587 | d34cab9f | ths | goto badcmd;
|
588 | d34cab9f | ths | case SVGA_CMD_SURFACE_ALPHA_BLEND:
|
589 | d34cab9f | ths | args = 12;
|
590 | d34cab9f | ths | goto badcmd;
|
591 | d34cab9f | ths | |
592 | d34cab9f | ths | /*
|
593 | d34cab9f | ths | * Other commands that are not listed as depending on any
|
594 | d34cab9f | ths | * CAPABILITIES bits, but are not described in the README either.
|
595 | d34cab9f | ths | */
|
596 | d34cab9f | ths | case SVGA_CMD_SURFACE_FILL:
|
597 | d34cab9f | ths | case SVGA_CMD_SURFACE_COPY:
|
598 | d34cab9f | ths | case SVGA_CMD_FRONT_ROP_FILL:
|
599 | d34cab9f | ths | case SVGA_CMD_FENCE:
|
600 | d34cab9f | ths | case SVGA_CMD_INVALID_CMD:
|
601 | d34cab9f | ths | break; /* Nop */ |
602 | d34cab9f | ths | |
603 | d34cab9f | ths | default:
|
604 | d34cab9f | ths | badcmd:
|
605 | d34cab9f | ths | while (args --)
|
606 | d34cab9f | ths | vmsvga_fifo_read(s); |
607 | d34cab9f | ths | printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
|
608 | d34cab9f | ths | __FUNCTION__, cmd); |
609 | d34cab9f | ths | break;
|
610 | d34cab9f | ths | } |
611 | d34cab9f | ths | |
612 | d34cab9f | ths | s->syncing = 0;
|
613 | d34cab9f | ths | } |
614 | d34cab9f | ths | |
615 | d34cab9f | ths | static uint32_t vmsvga_index_read(void *opaque, uint32_t address) |
616 | d34cab9f | ths | { |
617 | d34cab9f | ths | struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
618 | d34cab9f | ths | return s->index;
|
619 | d34cab9f | ths | } |
620 | d34cab9f | ths | |
621 | d34cab9f | ths | static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index) |
622 | d34cab9f | ths | { |
623 | d34cab9f | ths | struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
624 | d34cab9f | ths | s->index = index; |
625 | d34cab9f | ths | } |
626 | d34cab9f | ths | |
627 | d34cab9f | ths | static uint32_t vmsvga_value_read(void *opaque, uint32_t address) |
628 | d34cab9f | ths | { |
629 | d34cab9f | ths | uint32_t caps; |
630 | d34cab9f | ths | struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
631 | d34cab9f | ths | switch (s->index) {
|
632 | d34cab9f | ths | case SVGA_REG_ID:
|
633 | d34cab9f | ths | return s->svgaid;
|
634 | d34cab9f | ths | |
635 | d34cab9f | ths | case SVGA_REG_ENABLE:
|
636 | d34cab9f | ths | return s->enable;
|
637 | d34cab9f | ths | |
638 | d34cab9f | ths | case SVGA_REG_WIDTH:
|
639 | d34cab9f | ths | return s->width;
|
640 | d34cab9f | ths | |
641 | d34cab9f | ths | case SVGA_REG_HEIGHT:
|
642 | d34cab9f | ths | return s->height;
|
643 | d34cab9f | ths | |
644 | d34cab9f | ths | case SVGA_REG_MAX_WIDTH:
|
645 | d34cab9f | ths | return SVGA_MAX_WIDTH;
|
646 | d34cab9f | ths | |
647 | d34cab9f | ths | case SVGA_REG_MAX_HEIGHT:
|
648 | f707cfba | balrog | return SVGA_MAX_HEIGHT;
|
649 | d34cab9f | ths | |
650 | d34cab9f | ths | case SVGA_REG_DEPTH:
|
651 | d34cab9f | ths | return s->depth;
|
652 | d34cab9f | ths | |
653 | d34cab9f | ths | case SVGA_REG_BITS_PER_PIXEL:
|
654 | d34cab9f | ths | return (s->depth + 7) & ~7; |
655 | d34cab9f | ths | |
656 | d34cab9f | ths | case SVGA_REG_PSEUDOCOLOR:
|
657 | d34cab9f | ths | return 0x0; |
658 | d34cab9f | ths | |
659 | d34cab9f | ths | case SVGA_REG_RED_MASK:
|
660 | d34cab9f | ths | return s->wred;
|
661 | d34cab9f | ths | case SVGA_REG_GREEN_MASK:
|
662 | d34cab9f | ths | return s->wgreen;
|
663 | d34cab9f | ths | case SVGA_REG_BLUE_MASK:
|
664 | d34cab9f | ths | return s->wblue;
|
665 | d34cab9f | ths | |
666 | d34cab9f | ths | case SVGA_REG_BYTES_PER_LINE:
|
667 | d34cab9f | ths | return ((s->depth + 7) >> 3) * s->new_width; |
668 | d34cab9f | ths | |
669 | d34cab9f | ths | case SVGA_REG_FB_START:
|
670 | 3016d80b | balrog | return s->vram_base;
|
671 | d34cab9f | ths | |
672 | d34cab9f | ths | case SVGA_REG_FB_OFFSET:
|
673 | d34cab9f | ths | return 0x0; |
674 | d34cab9f | ths | |
675 | d34cab9f | ths | case SVGA_REG_VRAM_SIZE:
|
676 | d34cab9f | ths | return s->vram_size - SVGA_FIFO_SIZE;
|
677 | d34cab9f | ths | |
678 | d34cab9f | ths | case SVGA_REG_FB_SIZE:
|
679 | d34cab9f | ths | return s->fb_size;
|
680 | d34cab9f | ths | |
681 | d34cab9f | ths | case SVGA_REG_CAPABILITIES:
|
682 | d34cab9f | ths | caps = SVGA_CAP_NONE; |
683 | d34cab9f | ths | #ifdef HW_RECT_ACCEL
|
684 | d34cab9f | ths | caps |= SVGA_CAP_RECT_COPY; |
685 | d34cab9f | ths | #endif
|
686 | d34cab9f | ths | #ifdef HW_FILL_ACCEL
|
687 | d34cab9f | ths | caps |= SVGA_CAP_RECT_FILL; |
688 | d34cab9f | ths | #endif
|
689 | d34cab9f | ths | #ifdef HW_MOUSE_ACCEL
|
690 | d34cab9f | ths | if (s->ds->mouse_set)
|
691 | d34cab9f | ths | caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | |
692 | d34cab9f | ths | SVGA_CAP_CURSOR_BYPASS; |
693 | d34cab9f | ths | #endif
|
694 | d34cab9f | ths | return caps;
|
695 | d34cab9f | ths | |
696 | d34cab9f | ths | case SVGA_REG_MEM_START:
|
697 | 3016d80b | balrog | return s->vram_base + s->vram_size - SVGA_FIFO_SIZE;
|
698 | d34cab9f | ths | |
699 | d34cab9f | ths | case SVGA_REG_MEM_SIZE:
|
700 | d34cab9f | ths | return SVGA_FIFO_SIZE;
|
701 | d34cab9f | ths | |
702 | d34cab9f | ths | case SVGA_REG_CONFIG_DONE:
|
703 | d34cab9f | ths | return s->config;
|
704 | d34cab9f | ths | |
705 | d34cab9f | ths | case SVGA_REG_SYNC:
|
706 | d34cab9f | ths | case SVGA_REG_BUSY:
|
707 | d34cab9f | ths | return s->syncing;
|
708 | d34cab9f | ths | |
709 | d34cab9f | ths | case SVGA_REG_GUEST_ID:
|
710 | d34cab9f | ths | return s->guest;
|
711 | d34cab9f | ths | |
712 | d34cab9f | ths | case SVGA_REG_CURSOR_ID:
|
713 | d34cab9f | ths | return s->cursor.id;
|
714 | d34cab9f | ths | |
715 | d34cab9f | ths | case SVGA_REG_CURSOR_X:
|
716 | d34cab9f | ths | return s->cursor.x;
|
717 | d34cab9f | ths | |
718 | d34cab9f | ths | case SVGA_REG_CURSOR_Y:
|
719 | d34cab9f | ths | return s->cursor.x;
|
720 | d34cab9f | ths | |
721 | d34cab9f | ths | case SVGA_REG_CURSOR_ON:
|
722 | d34cab9f | ths | return s->cursor.on;
|
723 | d34cab9f | ths | |
724 | d34cab9f | ths | case SVGA_REG_HOST_BITS_PER_PIXEL:
|
725 | d34cab9f | ths | return (s->depth + 7) & ~7; |
726 | d34cab9f | ths | |
727 | d34cab9f | ths | case SVGA_REG_SCRATCH_SIZE:
|
728 | d34cab9f | ths | return s->scratch_size;
|
729 | d34cab9f | ths | |
730 | d34cab9f | ths | case SVGA_REG_MEM_REGS:
|
731 | d34cab9f | ths | case SVGA_REG_NUM_DISPLAYS:
|
732 | d34cab9f | ths | case SVGA_REG_PITCHLOCK:
|
733 | d34cab9f | ths | case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
|
734 | d34cab9f | ths | return 0; |
735 | d34cab9f | ths | |
736 | d34cab9f | ths | default:
|
737 | d34cab9f | ths | if (s->index >= SVGA_SCRATCH_BASE &&
|
738 | d34cab9f | ths | s->index < SVGA_SCRATCH_BASE + s->scratch_size) |
739 | d34cab9f | ths | return s->scratch[s->index - SVGA_SCRATCH_BASE];
|
740 | d34cab9f | ths | printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
|
741 | d34cab9f | ths | } |
742 | d34cab9f | ths | |
743 | d34cab9f | ths | return 0; |
744 | d34cab9f | ths | } |
745 | d34cab9f | ths | |
746 | d34cab9f | ths | static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) |
747 | d34cab9f | ths | { |
748 | d34cab9f | ths | struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
749 | d34cab9f | ths | switch (s->index) {
|
750 | d34cab9f | ths | case SVGA_REG_ID:
|
751 | d34cab9f | ths | if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
|
752 | d34cab9f | ths | s->svgaid = value; |
753 | d34cab9f | ths | break;
|
754 | d34cab9f | ths | |
755 | d34cab9f | ths | case SVGA_REG_ENABLE:
|
756 | f707cfba | balrog | s->enable = value; |
757 | f707cfba | balrog | s->config &= !!value; |
758 | d34cab9f | ths | s->width = -1;
|
759 | d34cab9f | ths | s->height = -1;
|
760 | d34cab9f | ths | s->invalidated = 1;
|
761 | d34cab9f | ths | #ifdef EMBED_STDVGA
|
762 | d34cab9f | ths | s->invalidate(opaque); |
763 | d34cab9f | ths | #endif
|
764 | d34cab9f | ths | if (s->enable)
|
765 | d34cab9f | ths | s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height; |
766 | d34cab9f | ths | break;
|
767 | d34cab9f | ths | |
768 | d34cab9f | ths | case SVGA_REG_WIDTH:
|
769 | d34cab9f | ths | s->new_width = value; |
770 | d34cab9f | ths | s->invalidated = 1;
|
771 | d34cab9f | ths | break;
|
772 | d34cab9f | ths | |
773 | d34cab9f | ths | case SVGA_REG_HEIGHT:
|
774 | d34cab9f | ths | s->new_height = value; |
775 | d34cab9f | ths | s->invalidated = 1;
|
776 | d34cab9f | ths | break;
|
777 | d34cab9f | ths | |
778 | d34cab9f | ths | case SVGA_REG_DEPTH:
|
779 | d34cab9f | ths | case SVGA_REG_BITS_PER_PIXEL:
|
780 | d34cab9f | ths | if (value != s->depth) {
|
781 | d34cab9f | ths | printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
|
782 | d34cab9f | ths | s->config = 0;
|
783 | d34cab9f | ths | } |
784 | d34cab9f | ths | break;
|
785 | d34cab9f | ths | |
786 | d34cab9f | ths | case SVGA_REG_CONFIG_DONE:
|
787 | d34cab9f | ths | if (value) {
|
788 | d34cab9f | ths | s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE]; |
789 | d34cab9f | ths | /* Check range and alignment. */
|
790 | d34cab9f | ths | if ((s->cmd->min | s->cmd->max |
|
791 | d34cab9f | ths | s->cmd->next_cmd | s->cmd->stop) & 3)
|
792 | d34cab9f | ths | break;
|
793 | d34cab9f | ths | if (s->cmd->min < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
|
794 | d34cab9f | ths | break;
|
795 | d34cab9f | ths | if (s->cmd->max > SVGA_FIFO_SIZE)
|
796 | d34cab9f | ths | break;
|
797 | d34cab9f | ths | if (s->cmd->max < s->cmd->min + 10 * 1024) |
798 | d34cab9f | ths | break;
|
799 | d34cab9f | ths | } |
800 | f707cfba | balrog | s->config = !!value; |
801 | d34cab9f | ths | break;
|
802 | d34cab9f | ths | |
803 | d34cab9f | ths | case SVGA_REG_SYNC:
|
804 | d34cab9f | ths | s->syncing = 1;
|
805 | d34cab9f | ths | vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
|
806 | d34cab9f | ths | break;
|
807 | d34cab9f | ths | |
808 | d34cab9f | ths | case SVGA_REG_GUEST_ID:
|
809 | d34cab9f | ths | s->guest = value; |
810 | d34cab9f | ths | #ifdef VERBOSE
|
811 | d34cab9f | ths | if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
|
812 | d34cab9f | ths | sizeof(vmsvga_guest_id) / sizeof(*vmsvga_guest_id)) |
813 | d34cab9f | ths | printf("%s: guest runs %s.\n", __FUNCTION__,
|
814 | d34cab9f | ths | vmsvga_guest_id[value - GUEST_OS_BASE]); |
815 | d34cab9f | ths | #endif
|
816 | d34cab9f | ths | break;
|
817 | d34cab9f | ths | |
818 | d34cab9f | ths | case SVGA_REG_CURSOR_ID:
|
819 | d34cab9f | ths | s->cursor.id = value; |
820 | d34cab9f | ths | break;
|
821 | d34cab9f | ths | |
822 | d34cab9f | ths | case SVGA_REG_CURSOR_X:
|
823 | d34cab9f | ths | s->cursor.x = value; |
824 | d34cab9f | ths | break;
|
825 | d34cab9f | ths | |
826 | d34cab9f | ths | case SVGA_REG_CURSOR_Y:
|
827 | d34cab9f | ths | s->cursor.y = value; |
828 | d34cab9f | ths | break;
|
829 | d34cab9f | ths | |
830 | d34cab9f | ths | case SVGA_REG_CURSOR_ON:
|
831 | d34cab9f | ths | s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); |
832 | d34cab9f | ths | s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); |
833 | d34cab9f | ths | #ifdef HW_MOUSE_ACCEL
|
834 | d34cab9f | ths | if (s->ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
|
835 | d34cab9f | ths | s->ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on); |
836 | d34cab9f | ths | #endif
|
837 | d34cab9f | ths | break;
|
838 | d34cab9f | ths | |
839 | d34cab9f | ths | case SVGA_REG_MEM_REGS:
|
840 | d34cab9f | ths | case SVGA_REG_NUM_DISPLAYS:
|
841 | d34cab9f | ths | case SVGA_REG_PITCHLOCK:
|
842 | d34cab9f | ths | case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
|
843 | d34cab9f | ths | break;
|
844 | d34cab9f | ths | |
845 | d34cab9f | ths | default:
|
846 | d34cab9f | ths | if (s->index >= SVGA_SCRATCH_BASE &&
|
847 | d34cab9f | ths | s->index < SVGA_SCRATCH_BASE + s->scratch_size) { |
848 | d34cab9f | ths | s->scratch[s->index - SVGA_SCRATCH_BASE] = value; |
849 | d34cab9f | ths | break;
|
850 | d34cab9f | ths | } |
851 | d34cab9f | ths | printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
|
852 | d34cab9f | ths | } |
853 | d34cab9f | ths | } |
854 | d34cab9f | ths | |
855 | d34cab9f | ths | static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) |
856 | d34cab9f | ths | { |
857 | d34cab9f | ths | printf("%s: what are we supposed to return?\n", __FUNCTION__);
|
858 | d34cab9f | ths | return 0xcafe; |
859 | d34cab9f | ths | } |
860 | d34cab9f | ths | |
861 | d34cab9f | ths | static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) |
862 | d34cab9f | ths | { |
863 | d34cab9f | ths | printf("%s: what are we supposed to do with (%08x)?\n",
|
864 | d34cab9f | ths | __FUNCTION__, data); |
865 | d34cab9f | ths | } |
866 | d34cab9f | ths | |
867 | d34cab9f | ths | static inline void vmsvga_size(struct vmsvga_state_s *s) |
868 | d34cab9f | ths | { |
869 | d34cab9f | ths | if (s->new_width != s->width || s->new_height != s->height) {
|
870 | d34cab9f | ths | s->width = s->new_width; |
871 | d34cab9f | ths | s->height = s->new_height; |
872 | d34cab9f | ths | dpy_resize(s->ds, s->width, s->height); |
873 | d34cab9f | ths | s->invalidated = 1;
|
874 | d34cab9f | ths | } |
875 | d34cab9f | ths | } |
876 | d34cab9f | ths | |
877 | d34cab9f | ths | static void vmsvga_update_display(void *opaque) |
878 | d34cab9f | ths | { |
879 | d34cab9f | ths | struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
880 | d34cab9f | ths | if (!s->enable) {
|
881 | d34cab9f | ths | #ifdef EMBED_STDVGA
|
882 | d34cab9f | ths | s->update(opaque); |
883 | d34cab9f | ths | #endif
|
884 | d34cab9f | ths | return;
|
885 | d34cab9f | ths | } |
886 | d34cab9f | ths | |
887 | d34cab9f | ths | vmsvga_size(s); |
888 | d34cab9f | ths | |
889 | d34cab9f | ths | vmsvga_fifo_run(s); |
890 | d34cab9f | ths | vmsvga_update_rect_flush(s); |
891 | d34cab9f | ths | |
892 | d34cab9f | ths | /*
|
893 | d34cab9f | ths | * Is it more efficient to look at vram VGA-dirty bits or wait
|
894 | d34cab9f | ths | * for the driver to issue SVGA_CMD_UPDATE?
|
895 | d34cab9f | ths | */
|
896 | d34cab9f | ths | if (s->invalidated) {
|
897 | d34cab9f | ths | s->invalidated = 0;
|
898 | d34cab9f | ths | vmsvga_update_screen(s); |
899 | d34cab9f | ths | } |
900 | d34cab9f | ths | } |
901 | d34cab9f | ths | |
902 | d34cab9f | ths | static void vmsvga_reset(struct vmsvga_state_s *s) |
903 | d34cab9f | ths | { |
904 | d34cab9f | ths | s->index = 0;
|
905 | d34cab9f | ths | s->enable = 0;
|
906 | d34cab9f | ths | s->config = 0;
|
907 | d34cab9f | ths | s->width = -1;
|
908 | d34cab9f | ths | s->height = -1;
|
909 | d34cab9f | ths | s->svgaid = SVGA_ID; |
910 | d34cab9f | ths | s->depth = s->ds->depth ? s->ds->depth : 24;
|
911 | d34cab9f | ths | s->bypp = (s->depth + 7) >> 3; |
912 | d34cab9f | ths | s->cursor.on = 0;
|
913 | d34cab9f | ths | s->redraw_fifo_first = 0;
|
914 | d34cab9f | ths | s->redraw_fifo_last = 0;
|
915 | d34cab9f | ths | switch (s->depth) {
|
916 | d34cab9f | ths | case 8: |
917 | d34cab9f | ths | s->wred = 0x00000007;
|
918 | d34cab9f | ths | s->wgreen = 0x00000038;
|
919 | d34cab9f | ths | s->wblue = 0x000000c0;
|
920 | d34cab9f | ths | break;
|
921 | d34cab9f | ths | case 15: |
922 | d34cab9f | ths | s->wred = 0x0000001f;
|
923 | d34cab9f | ths | s->wgreen = 0x000003e0;
|
924 | d34cab9f | ths | s->wblue = 0x00007c00;
|
925 | d34cab9f | ths | break;
|
926 | d34cab9f | ths | case 16: |
927 | d34cab9f | ths | s->wred = 0x0000001f;
|
928 | d34cab9f | ths | s->wgreen = 0x000007e0;
|
929 | d34cab9f | ths | s->wblue = 0x0000f800;
|
930 | d34cab9f | ths | break;
|
931 | d34cab9f | ths | case 24: |
932 | f707cfba | balrog | s->wred = 0x00ff0000;
|
933 | d34cab9f | ths | s->wgreen = 0x0000ff00;
|
934 | f707cfba | balrog | s->wblue = 0x000000ff;
|
935 | d34cab9f | ths | break;
|
936 | d34cab9f | ths | case 32: |
937 | f707cfba | balrog | s->wred = 0x00ff0000;
|
938 | d34cab9f | ths | s->wgreen = 0x0000ff00;
|
939 | f707cfba | balrog | s->wblue = 0x000000ff;
|
940 | d34cab9f | ths | break;
|
941 | d34cab9f | ths | } |
942 | d34cab9f | ths | s->syncing = 0;
|
943 | d34cab9f | ths | } |
944 | d34cab9f | ths | |
945 | d34cab9f | ths | static void vmsvga_invalidate_display(void *opaque) |
946 | d34cab9f | ths | { |
947 | d34cab9f | ths | struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
948 | d34cab9f | ths | if (!s->enable) {
|
949 | d34cab9f | ths | #ifdef EMBED_STDVGA
|
950 | d34cab9f | ths | s->invalidate(opaque); |
951 | d34cab9f | ths | #endif
|
952 | d34cab9f | ths | return;
|
953 | d34cab9f | ths | } |
954 | d34cab9f | ths | |
955 | d34cab9f | ths | s->invalidated = 1;
|
956 | d34cab9f | ths | } |
957 | d34cab9f | ths | |
958 | f707cfba | balrog | /* save the vga display in a PPM image even if no display is
|
959 | f707cfba | balrog | available */
|
960 | d34cab9f | ths | static void vmsvga_screen_dump(void *opaque, const char *filename) |
961 | d34cab9f | ths | { |
962 | d34cab9f | ths | struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
963 | d34cab9f | ths | if (!s->enable) {
|
964 | d34cab9f | ths | #ifdef EMBED_STDVGA
|
965 | d34cab9f | ths | s->screen_dump(opaque, filename); |
966 | d34cab9f | ths | #endif
|
967 | d34cab9f | ths | return;
|
968 | d34cab9f | ths | } |
969 | d34cab9f | ths | |
970 | f707cfba | balrog | if (s->depth == 32) { |
971 | f707cfba | balrog | ppm_save(filename, s->vram, s->width, s->height, s->ds->linesize); |
972 | f707cfba | balrog | } |
973 | d34cab9f | ths | } |
974 | d34cab9f | ths | |
975 | 4d3b6f6e | balrog | static void vmsvga_text_update(void *opaque, console_ch_t *chardata) |
976 | 4d3b6f6e | balrog | { |
977 | 4d3b6f6e | balrog | struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
978 | 4d3b6f6e | balrog | |
979 | 4d3b6f6e | balrog | if (s->text_update)
|
980 | 4d3b6f6e | balrog | s->text_update(opaque, chardata); |
981 | 4d3b6f6e | balrog | } |
982 | 4d3b6f6e | balrog | |
983 | d34cab9f | ths | #ifdef DIRECT_VRAM
|
984 | d34cab9f | ths | static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr) |
985 | d34cab9f | ths | { |
986 | d34cab9f | ths | struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
987 | 3016d80b | balrog | addr -= s->vram_base; |
988 | d34cab9f | ths | if (addr < s->fb_size)
|
989 | d34cab9f | ths | return *(uint8_t *) (s->ds->data + addr);
|
990 | d34cab9f | ths | else
|
991 | d34cab9f | ths | return *(uint8_t *) (s->vram + addr);
|
992 | d34cab9f | ths | } |
993 | d34cab9f | ths | |
994 | d34cab9f | ths | static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr) |
995 | d34cab9f | ths | { |
996 | d34cab9f | ths | struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
997 | 3016d80b | balrog | addr -= s->vram_base; |
998 | d34cab9f | ths | if (addr < s->fb_size)
|
999 | d34cab9f | ths | return *(uint16_t *) (s->ds->data + addr);
|
1000 | d34cab9f | ths | else
|
1001 | d34cab9f | ths | return *(uint16_t *) (s->vram + addr);
|
1002 | d34cab9f | ths | } |
1003 | d34cab9f | ths | |
1004 | d34cab9f | ths | static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr) |
1005 | d34cab9f | ths | { |
1006 | d34cab9f | ths | struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
1007 | 3016d80b | balrog | addr -= s->vram_base; |
1008 | d34cab9f | ths | if (addr < s->fb_size)
|
1009 | d34cab9f | ths | return *(uint32_t *) (s->ds->data + addr);
|
1010 | d34cab9f | ths | else
|
1011 | d34cab9f | ths | return *(uint32_t *) (s->vram + addr);
|
1012 | d34cab9f | ths | } |
1013 | d34cab9f | ths | |
1014 | d34cab9f | ths | static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr, |
1015 | d34cab9f | ths | uint32_t value) |
1016 | d34cab9f | ths | { |
1017 | d34cab9f | ths | struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
1018 | 3016d80b | balrog | addr -= s->vram_base; |
1019 | d34cab9f | ths | if (addr < s->fb_size)
|
1020 | d34cab9f | ths | *(uint8_t *) (s->ds->data + addr) = value; |
1021 | d34cab9f | ths | else
|
1022 | d34cab9f | ths | *(uint8_t *) (s->vram + addr) = value; |
1023 | d34cab9f | ths | } |
1024 | d34cab9f | ths | |
1025 | d34cab9f | ths | static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr, |
1026 | d34cab9f | ths | uint32_t value) |
1027 | d34cab9f | ths | { |
1028 | d34cab9f | ths | struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
1029 | 3016d80b | balrog | addr -= s->vram_base; |
1030 | d34cab9f | ths | if (addr < s->fb_size)
|
1031 | d34cab9f | ths | *(uint16_t *) (s->ds->data + addr) = value; |
1032 | d34cab9f | ths | else
|
1033 | d34cab9f | ths | *(uint16_t *) (s->vram + addr) = value; |
1034 | d34cab9f | ths | } |
1035 | d34cab9f | ths | |
1036 | d34cab9f | ths | static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr, |
1037 | d34cab9f | ths | uint32_t value) |
1038 | d34cab9f | ths | { |
1039 | d34cab9f | ths | struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; |
1040 | 3016d80b | balrog | addr -= s->vram_base; |
1041 | d34cab9f | ths | if (addr < s->fb_size)
|
1042 | d34cab9f | ths | *(uint32_t *) (s->ds->data + addr) = value; |
1043 | d34cab9f | ths | else
|
1044 | d34cab9f | ths | *(uint32_t *) (s->vram + addr) = value; |
1045 | d34cab9f | ths | } |
1046 | d34cab9f | ths | |
1047 | d34cab9f | ths | static CPUReadMemoryFunc *vmsvga_vram_read[] = {
|
1048 | d34cab9f | ths | vmsvga_vram_readb, |
1049 | d34cab9f | ths | vmsvga_vram_readw, |
1050 | d34cab9f | ths | vmsvga_vram_readl, |
1051 | d34cab9f | ths | }; |
1052 | d34cab9f | ths | |
1053 | d34cab9f | ths | static CPUWriteMemoryFunc *vmsvga_vram_write[] = {
|
1054 | d34cab9f | ths | vmsvga_vram_writeb, |
1055 | d34cab9f | ths | vmsvga_vram_writew, |
1056 | d34cab9f | ths | vmsvga_vram_writel, |
1057 | d34cab9f | ths | }; |
1058 | d34cab9f | ths | #endif
|
1059 | d34cab9f | ths | |
1060 | d34cab9f | ths | static void vmsvga_save(struct vmsvga_state_s *s, QEMUFile *f) |
1061 | d34cab9f | ths | { |
1062 | bee8d684 | ths | qemu_put_be32(f, s->depth); |
1063 | bee8d684 | ths | qemu_put_be32(f, s->enable); |
1064 | bee8d684 | ths | qemu_put_be32(f, s->config); |
1065 | bee8d684 | ths | qemu_put_be32(f, s->cursor.id); |
1066 | bee8d684 | ths | qemu_put_be32(f, s->cursor.x); |
1067 | bee8d684 | ths | qemu_put_be32(f, s->cursor.y); |
1068 | bee8d684 | ths | qemu_put_be32(f, s->cursor.on); |
1069 | bee8d684 | ths | qemu_put_be32(f, s->index); |
1070 | d34cab9f | ths | qemu_put_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
|
1071 | bee8d684 | ths | qemu_put_be32(f, s->new_width); |
1072 | bee8d684 | ths | qemu_put_be32(f, s->new_height); |
1073 | d34cab9f | ths | qemu_put_be32s(f, &s->guest); |
1074 | d34cab9f | ths | qemu_put_be32s(f, &s->svgaid); |
1075 | bee8d684 | ths | qemu_put_be32(f, s->syncing); |
1076 | bee8d684 | ths | qemu_put_be32(f, s->fb_size); |
1077 | d34cab9f | ths | } |
1078 | d34cab9f | ths | |
1079 | d34cab9f | ths | static int vmsvga_load(struct vmsvga_state_s *s, QEMUFile *f) |
1080 | d34cab9f | ths | { |
1081 | d34cab9f | ths | int depth;
|
1082 | bee8d684 | ths | depth=qemu_get_be32(f); |
1083 | bee8d684 | ths | s->enable=qemu_get_be32(f); |
1084 | bee8d684 | ths | s->config=qemu_get_be32(f); |
1085 | bee8d684 | ths | s->cursor.id=qemu_get_be32(f); |
1086 | bee8d684 | ths | s->cursor.x=qemu_get_be32(f); |
1087 | bee8d684 | ths | s->cursor.y=qemu_get_be32(f); |
1088 | bee8d684 | ths | s->cursor.on=qemu_get_be32(f); |
1089 | bee8d684 | ths | s->index=qemu_get_be32(f); |
1090 | d34cab9f | ths | qemu_get_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
|
1091 | bee8d684 | ths | s->new_width=qemu_get_be32(f); |
1092 | bee8d684 | ths | s->new_height=qemu_get_be32(f); |
1093 | d34cab9f | ths | qemu_get_be32s(f, &s->guest); |
1094 | d34cab9f | ths | qemu_get_be32s(f, &s->svgaid); |
1095 | bee8d684 | ths | s->syncing=qemu_get_be32(f); |
1096 | bee8d684 | ths | s->fb_size=qemu_get_be32(f); |
1097 | d34cab9f | ths | |
1098 | d34cab9f | ths | if (s->enable && depth != s->depth) {
|
1099 | d34cab9f | ths | printf("%s: need colour depth of %i bits to resume operation.\n",
|
1100 | d34cab9f | ths | __FUNCTION__, depth); |
1101 | d34cab9f | ths | return -EINVAL;
|
1102 | d34cab9f | ths | } |
1103 | d34cab9f | ths | |
1104 | d34cab9f | ths | s->invalidated = 1;
|
1105 | d34cab9f | ths | if (s->config)
|
1106 | d34cab9f | ths | s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE]; |
1107 | d34cab9f | ths | |
1108 | d34cab9f | ths | return 0; |
1109 | d34cab9f | ths | } |
1110 | d34cab9f | ths | |
1111 | d34cab9f | ths | static void vmsvga_init(struct vmsvga_state_s *s, DisplayState *ds, |
1112 | d34cab9f | ths | uint8_t *vga_ram_base, unsigned long vga_ram_offset, |
1113 | d34cab9f | ths | int vga_ram_size)
|
1114 | d34cab9f | ths | { |
1115 | d34cab9f | ths | s->ds = ds; |
1116 | d34cab9f | ths | s->vram = vga_ram_base; |
1117 | d34cab9f | ths | s->vram_size = vga_ram_size; |
1118 | 6f9bc132 | balrog | s->vram_offset = vga_ram_offset; |
1119 | d34cab9f | ths | |
1120 | d34cab9f | ths | s->scratch_size = SVGA_SCRATCH_SIZE; |
1121 | d34cab9f | ths | s->scratch = (uint32_t *) qemu_malloc(s->scratch_size * 4);
|
1122 | d34cab9f | ths | |
1123 | d34cab9f | ths | vmsvga_reset(s); |
1124 | d34cab9f | ths | |
1125 | d34cab9f | ths | graphic_console_init(ds, vmsvga_update_display, |
1126 | 4d3b6f6e | balrog | vmsvga_invalidate_display, vmsvga_screen_dump, |
1127 | 4d3b6f6e | balrog | vmsvga_text_update, s); |
1128 | d34cab9f | ths | |
1129 | d34cab9f | ths | #ifdef EMBED_STDVGA
|
1130 | d34cab9f | ths | vga_common_init((VGAState *) s, ds, |
1131 | d34cab9f | ths | vga_ram_base, vga_ram_offset, vga_ram_size); |
1132 | d34cab9f | ths | vga_init((VGAState *) s); |
1133 | d34cab9f | ths | #endif
|
1134 | d34cab9f | ths | } |
1135 | d34cab9f | ths | |
1136 | d34cab9f | ths | static void pci_vmsvga_save(QEMUFile *f, void *opaque) |
1137 | d34cab9f | ths | { |
1138 | d34cab9f | ths | struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque; |
1139 | d34cab9f | ths | pci_device_save(&s->card, f); |
1140 | d34cab9f | ths | vmsvga_save(&s->chip, f); |
1141 | d34cab9f | ths | } |
1142 | d34cab9f | ths | |
1143 | d34cab9f | ths | static int pci_vmsvga_load(QEMUFile *f, void *opaque, int version_id) |
1144 | d34cab9f | ths | { |
1145 | d34cab9f | ths | struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque; |
1146 | d34cab9f | ths | int ret;
|
1147 | d34cab9f | ths | |
1148 | d34cab9f | ths | ret = pci_device_load(&s->card, f); |
1149 | d34cab9f | ths | if (ret < 0) |
1150 | d34cab9f | ths | return ret;
|
1151 | d34cab9f | ths | |
1152 | d34cab9f | ths | ret = vmsvga_load(&s->chip, f); |
1153 | d34cab9f | ths | if (ret < 0) |
1154 | d34cab9f | ths | return ret;
|
1155 | d34cab9f | ths | |
1156 | d34cab9f | ths | return 0; |
1157 | d34cab9f | ths | } |
1158 | d34cab9f | ths | |
1159 | 1492a3c4 | balrog | static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num, |
1160 | 1492a3c4 | balrog | uint32_t addr, uint32_t size, int type)
|
1161 | 1492a3c4 | balrog | { |
1162 | 1492a3c4 | balrog | struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev; |
1163 | 1492a3c4 | balrog | struct vmsvga_state_s *s = &d->chip;
|
1164 | 1492a3c4 | balrog | |
1165 | 1492a3c4 | balrog | register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT, |
1166 | 1492a3c4 | balrog | 1, 4, vmsvga_index_read, s); |
1167 | 1492a3c4 | balrog | register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT, |
1168 | 1492a3c4 | balrog | 1, 4, vmsvga_index_write, s); |
1169 | 1492a3c4 | balrog | register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT, |
1170 | 1492a3c4 | balrog | 1, 4, vmsvga_value_read, s); |
1171 | 1492a3c4 | balrog | register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT, |
1172 | 1492a3c4 | balrog | 1, 4, vmsvga_value_write, s); |
1173 | 1492a3c4 | balrog | register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT, |
1174 | 1492a3c4 | balrog | 1, 4, vmsvga_bios_read, s); |
1175 | 1492a3c4 | balrog | register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT, |
1176 | 1492a3c4 | balrog | 1, 4, vmsvga_bios_write, s); |
1177 | 1492a3c4 | balrog | } |
1178 | 1492a3c4 | balrog | |
1179 | 3016d80b | balrog | static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num, |
1180 | 3016d80b | balrog | uint32_t addr, uint32_t size, int type)
|
1181 | 3016d80b | balrog | { |
1182 | 3016d80b | balrog | struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev; |
1183 | 3016d80b | balrog | struct vmsvga_state_s *s = &d->chip;
|
1184 | 3016d80b | balrog | int iomemtype;
|
1185 | 3016d80b | balrog | |
1186 | 3016d80b | balrog | s->vram_base = addr; |
1187 | 3016d80b | balrog | #ifdef DIRECT_VRAM
|
1188 | 3016d80b | balrog | iomemtype = cpu_register_io_memory(0, vmsvga_vram_read,
|
1189 | 3016d80b | balrog | vmsvga_vram_write, s); |
1190 | 3016d80b | balrog | #else
|
1191 | 6f9bc132 | balrog | iomemtype = s->vram_offset | IO_MEM_RAM; |
1192 | 3016d80b | balrog | #endif
|
1193 | 3016d80b | balrog | cpu_register_physical_memory(s->vram_base, s->vram_size, |
1194 | 3016d80b | balrog | iomemtype); |
1195 | 3016d80b | balrog | } |
1196 | 3016d80b | balrog | |
1197 | d34cab9f | ths | #define PCI_VENDOR_ID_VMWARE 0x15ad |
1198 | d34cab9f | ths | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 |
1199 | d34cab9f | ths | #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 |
1200 | d34cab9f | ths | #define PCI_DEVICE_ID_VMWARE_NET 0x0720 |
1201 | d34cab9f | ths | #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 |
1202 | d34cab9f | ths | #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 |
1203 | d34cab9f | ths | #define PCI_CLASS_BASE_DISPLAY 0x03 |
1204 | d34cab9f | ths | #define PCI_CLASS_SUB_VGA 0x00 |
1205 | d34cab9f | ths | #define PCI_CLASS_HEADERTYPE_00h 0x00 |
1206 | d34cab9f | ths | |
1207 | d34cab9f | ths | void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
|
1208 | d34cab9f | ths | unsigned long vga_ram_offset, int vga_ram_size) |
1209 | d34cab9f | ths | { |
1210 | d34cab9f | ths | struct pci_vmsvga_state_s *s;
|
1211 | d34cab9f | ths | |
1212 | d34cab9f | ths | /* Setup PCI configuration */
|
1213 | d34cab9f | ths | s = (struct pci_vmsvga_state_s *)
|
1214 | d34cab9f | ths | pci_register_device(bus, "QEMUware SVGA",
|
1215 | d34cab9f | ths | sizeof(struct pci_vmsvga_state_s), -1, 0, 0); |
1216 | d34cab9f | ths | s->card.config[PCI_VENDOR_ID] = PCI_VENDOR_ID_VMWARE & 0xff;
|
1217 | d34cab9f | ths | s->card.config[PCI_VENDOR_ID + 1] = PCI_VENDOR_ID_VMWARE >> 8; |
1218 | d34cab9f | ths | s->card.config[PCI_DEVICE_ID] = SVGA_PCI_DEVICE_ID & 0xff;
|
1219 | d34cab9f | ths | s->card.config[PCI_DEVICE_ID + 1] = SVGA_PCI_DEVICE_ID >> 8; |
1220 | d34cab9f | ths | s->card.config[PCI_COMMAND] = 0x07; /* I/O + Memory */ |
1221 | d34cab9f | ths | s->card.config[PCI_CLASS_DEVICE] = PCI_CLASS_SUB_VGA; |
1222 | d34cab9f | ths | s->card.config[0x0b] = PCI_CLASS_BASE_DISPLAY;
|
1223 | d34cab9f | ths | s->card.config[0x0c] = 0x08; /* Cache line size */ |
1224 | d34cab9f | ths | s->card.config[0x0d] = 0x40; /* Latency timer */ |
1225 | d34cab9f | ths | s->card.config[0x0e] = PCI_CLASS_HEADERTYPE_00h;
|
1226 | d34cab9f | ths | s->card.config[0x10] = ((SVGA_IO_BASE >> 0) & 0xff) | 1; |
1227 | d34cab9f | ths | s->card.config[0x11] = (SVGA_IO_BASE >> 8) & 0xff; |
1228 | d34cab9f | ths | s->card.config[0x12] = (SVGA_IO_BASE >> 16) & 0xff; |
1229 | d34cab9f | ths | s->card.config[0x13] = (SVGA_IO_BASE >> 24) & 0xff; |
1230 | d34cab9f | ths | s->card.config[0x18] = (SVGA_MEM_BASE >> 0) & 0xff; |
1231 | d34cab9f | ths | s->card.config[0x19] = (SVGA_MEM_BASE >> 8) & 0xff; |
1232 | d34cab9f | ths | s->card.config[0x1a] = (SVGA_MEM_BASE >> 16) & 0xff; |
1233 | d34cab9f | ths | s->card.config[0x1b] = (SVGA_MEM_BASE >> 24) & 0xff; |
1234 | d34cab9f | ths | s->card.config[0x2c] = PCI_VENDOR_ID_VMWARE & 0xff; |
1235 | d34cab9f | ths | s->card.config[0x2d] = PCI_VENDOR_ID_VMWARE >> 8; |
1236 | d34cab9f | ths | s->card.config[0x2e] = SVGA_PCI_DEVICE_ID & 0xff; |
1237 | d34cab9f | ths | s->card.config[0x2f] = SVGA_PCI_DEVICE_ID >> 8; |
1238 | d34cab9f | ths | s->card.config[0x3c] = 0xff; /* End */ |
1239 | d34cab9f | ths | |
1240 | 1492a3c4 | balrog | pci_register_io_region(&s->card, 0, 0x10, |
1241 | 1492a3c4 | balrog | PCI_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport); |
1242 | 2408b77b | aurel32 | pci_register_io_region(&s->card, 1, vga_ram_size,
|
1243 | 3016d80b | balrog | PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_vmsvga_map_mem); |
1244 | 1492a3c4 | balrog | |
1245 | d34cab9f | ths | vmsvga_init(&s->chip, ds, vga_ram_base, vga_ram_offset, vga_ram_size); |
1246 | d34cab9f | ths | |
1247 | d34cab9f | ths | register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s); |
1248 | d34cab9f | ths | } |