root / hw / omap_clk.c @ c75a823c
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/*
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* OMAP clocks.
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*
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* Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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*
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* Clocks data comes in part from arch/arm/mach-omap1/clock.h in Linux.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "hw.h" |
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#include "omap.h" |
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struct clk {
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const char *name; |
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const char *alias; |
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struct clk *parent;
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struct clk *child1;
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struct clk *sibling;
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#define ALWAYS_ENABLED (1 << 0) |
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#define CLOCK_IN_OMAP310 (1 << 10) |
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#define CLOCK_IN_OMAP730 (1 << 11) |
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#define CLOCK_IN_OMAP1510 (1 << 12) |
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#define CLOCK_IN_OMAP16XX (1 << 13) |
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#define CLOCK_IN_OMAP242X (1 << 14) |
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#define CLOCK_IN_OMAP243X (1 << 15) |
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#define CLOCK_IN_OMAP343X (1 << 16) |
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uint32_t flags; |
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int id;
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int running; /* Is currently ticking */ |
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int enabled; /* Is enabled, regardless of its input clk */ |
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unsigned long rate; /* Current rate (if .running) */ |
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unsigned int divisor; /* Rate relative to input (if .enabled) */ |
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unsigned int multiplier; /* Rate relative to input (if .enabled) */ |
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qemu_irq users[16]; /* Who to notify on change */ |
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int usecount; /* Automatically idle when unused */ |
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}; |
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static struct clk xtal_osc12m = { |
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.name = "xtal_osc_12m",
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.rate = 12000000,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
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}; |
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static struct clk xtal_osc32k = { |
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.name = "xtal_osc_32k",
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.rate = 32768,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
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CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
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}; |
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static struct clk ck_ref = { |
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.name = "ck_ref",
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.alias = "clkin",
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.parent = &xtal_osc12m, |
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
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ALWAYS_ENABLED, |
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}; |
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/* If a dpll is disabled it becomes a bypass, child clocks don't stop */
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static struct clk dpll1 = { |
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.name = "dpll1",
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.parent = &ck_ref, |
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
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ALWAYS_ENABLED, |
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}; |
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static struct clk dpll2 = { |
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.name = "dpll2",
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.parent = &ck_ref, |
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.flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
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}; |
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static struct clk dpll3 = { |
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.name = "dpll3",
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.parent = &ck_ref, |
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.flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
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}; |
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static struct clk dpll4 = { |
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.name = "dpll4",
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.parent = &ck_ref, |
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.multiplier = 4,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
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}; |
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static struct clk apll = { |
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.name = "apll",
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.parent = &ck_ref, |
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.multiplier = 48,
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.divisor = 12,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
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}; |
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static struct clk ck_48m = { |
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.name = "ck_48m",
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.parent = &dpll4, /* either dpll4 or apll */
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
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}; |
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static struct clk ck_dpll1out = { |
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.name = "ck_dpll1out",
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.parent = &dpll1, |
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.flags = CLOCK_IN_OMAP16XX, |
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}; |
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static struct clk sossi_ck = { |
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.name = "ck_sossi",
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.parent = &ck_dpll1out, |
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.flags = CLOCK_IN_OMAP16XX, |
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}; |
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static struct clk clkm1 = { |
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.name = "clkm1",
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.alias = "ck_gen1",
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.parent = &dpll1, |
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
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ALWAYS_ENABLED, |
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}; |
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static struct clk clkm2 = { |
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.name = "clkm2",
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.alias = "ck_gen2",
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.parent = &dpll1, |
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
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ALWAYS_ENABLED, |
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}; |
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static struct clk clkm3 = { |
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.name = "clkm3",
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.alias = "ck_gen3",
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.parent = &dpll1, /* either dpll1 or ck_ref */
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
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ALWAYS_ENABLED, |
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}; |
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static struct clk arm_ck = { |
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.name = "arm_ck",
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.alias = "mpu_ck",
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.parent = &clkm1, |
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
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ALWAYS_ENABLED, |
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}; |
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static struct clk armper_ck = { |
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.name = "armper_ck",
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.alias = "mpuper_ck",
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.parent = &clkm1, |
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
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}; |
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static struct clk arm_gpio_ck = { |
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.name = "arm_gpio_ck",
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.alias = "mpu_gpio_ck",
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.parent = &clkm1, |
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.divisor = 1,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
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}; |
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static struct clk armxor_ck = { |
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.name = "armxor_ck",
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.alias = "mpuxor_ck",
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.parent = &ck_ref, |
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
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}; |
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static struct clk armtim_ck = { |
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.name = "armtim_ck",
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.alias = "mputim_ck",
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.parent = &ck_ref, /* either CLKIN or DPLL1 */
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
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}; |
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static struct clk armwdt_ck = { |
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.name = "armwdt_ck",
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.alias = "mpuwd_ck",
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.parent = &clkm1, |
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.divisor = 14,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
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ALWAYS_ENABLED, |
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}; |
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static struct clk arminth_ck16xx = { |
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.name = "arminth_ck",
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.parent = &arm_ck, |
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.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
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/* Note: On 16xx the frequency can be divided by 2 by programming
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* ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
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*
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* 1510 version is in TC clocks.
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*/
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}; |
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static struct clk dsp_ck = { |
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.name = "dsp_ck",
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.parent = &clkm2, |
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
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}; |
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static struct clk dspmmu_ck = { |
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.name = "dspmmu_ck",
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.parent = &clkm2, |
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
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ALWAYS_ENABLED, |
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}; |
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static struct clk dspper_ck = { |
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.name = "dspper_ck",
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.parent = &clkm2, |
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
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}; |
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static struct clk dspxor_ck = { |
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.name = "dspxor_ck",
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.parent = &ck_ref, |
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
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}; |
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static struct clk dsptim_ck = { |
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.name = "dsptim_ck",
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.parent = &ck_ref, |
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
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}; |
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static struct clk tc_ck = { |
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.name = "tc_ck",
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.parent = &clkm3, |
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
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CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 | |
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ALWAYS_ENABLED, |
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}; |
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static struct clk arminth_ck15xx = { |
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.name = "arminth_ck",
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.parent = &tc_ck, |
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
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/* Note: On 1510 the frequency follows TC_CK
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*
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* 16xx version is in MPU clocks.
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*/
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}; |
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static struct clk tipb_ck = { |
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/* No-idle controlled by "tc_ck" */
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.name = "tipb_ck",
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.parent = &tc_ck, |
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
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}; |
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static struct clk l3_ocpi_ck = { |
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/* No-idle controlled by "tc_ck" */
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.name = "l3_ocpi_ck",
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.parent = &tc_ck, |
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.flags = CLOCK_IN_OMAP16XX, |
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}; |
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static struct clk tc1_ck = { |
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.name = "tc1_ck",
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.parent = &tc_ck, |
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.flags = CLOCK_IN_OMAP16XX, |
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}; |
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static struct clk tc2_ck = { |
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.name = "tc2_ck",
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.parent = &tc_ck, |
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.flags = CLOCK_IN_OMAP16XX, |
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}; |
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static struct clk dma_ck = { |
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/* No-idle controlled by "tc_ck" */
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.name = "dma_ck",
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.parent = &tc_ck, |
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
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ALWAYS_ENABLED, |
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}; |
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static struct clk dma_lcdfree_ck = { |
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.name = "dma_lcdfree_ck",
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.parent = &tc_ck, |
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.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
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}; |
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static struct clk api_ck = { |
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.name = "api_ck",
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.alias = "mpui_ck",
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.parent = &tc_ck, |
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
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}; |
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static struct clk lb_ck = { |
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.name = "lb_ck",
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.parent = &tc_ck, |
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
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}; |
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static struct clk lbfree_ck = { |
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.name = "lbfree_ck",
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.parent = &tc_ck, |
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
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}; |
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static struct clk hsab_ck = { |
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.name = "hsab_ck",
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.parent = &tc_ck, |
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
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}; |
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static struct clk rhea1_ck = { |
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.name = "rhea1_ck",
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.parent = &tc_ck, |
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.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
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}; |
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static struct clk rhea2_ck = { |
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.name = "rhea2_ck",
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.parent = &tc_ck, |
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.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
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}; |
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static struct clk lcd_ck_16xx = { |
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.name = "lcd_ck",
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.parent = &clkm3, |
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.flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730, |
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}; |
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static struct clk lcd_ck_1510 = { |
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.name = "lcd_ck",
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.parent = &clkm3, |
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
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}; |
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static struct clk uart1_1510 = { |
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.name = "uart1_ck",
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/* Direct from ULPD, no real parent */
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.parent = &armper_ck, /* either armper_ck or dpll4 */
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.rate = 12000000,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
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}; |
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static struct clk uart1_16xx = { |
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.name = "uart1_ck",
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/* Direct from ULPD, no real parent */
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.parent = &armper_ck, |
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.rate = 48000000,
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.flags = CLOCK_IN_OMAP16XX, |
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}; |
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static struct clk uart2_ck = { |
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.name = "uart2_ck",
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/* Direct from ULPD, no real parent */
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.parent = &armper_ck, /* either armper_ck or dpll4 */
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.rate = 12000000,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
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ALWAYS_ENABLED, |
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}; |
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static struct clk uart3_1510 = { |
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.name = "uart3_ck",
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/* Direct from ULPD, no real parent */
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.parent = &armper_ck, /* either armper_ck or dpll4 */
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.rate = 12000000,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
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}; |
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static struct clk uart3_16xx = { |
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.name = "uart3_ck",
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/* Direct from ULPD, no real parent */
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.parent = &armper_ck, |
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.rate = 48000000,
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.flags = CLOCK_IN_OMAP16XX, |
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}; |
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static struct clk usb_clk0 = { /* 6 MHz output on W4_USB_CLK0 */ |
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.name = "usb_clk0",
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.alias = "usb.clko",
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/* Direct from ULPD, no parent */
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.rate = 6000000,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
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}; |
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static struct clk usb_hhc_ck1510 = { |
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.name = "usb_hhc_ck",
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/* Direct from ULPD, no parent */
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.rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ |
398 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
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}; |
400 |
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static struct clk usb_hhc_ck16xx = { |
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.name = "usb_hhc_ck",
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/* Direct from ULPD, no parent */
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.rate = 48000000,
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/* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
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.flags = CLOCK_IN_OMAP16XX, |
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}; |
408 |
|
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static struct clk usb_w2fc_mclk = { |
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.name = "usb_w2fc_mclk",
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.alias = "usb_w2fc_ck",
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.parent = &ck_48m, |
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.rate = 48000000,
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
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}; |
416 |
|
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static struct clk mclk_1510 = { |
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.name = "mclk",
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/* Direct from ULPD, no parent. May be enabled by ext hardware. */
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.rate = 12000000,
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.flags = CLOCK_IN_OMAP1510, |
422 |
}; |
423 |
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static struct clk bclk_310 = { |
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.name = "bt_mclk_out", /* Alias midi_mclk_out? */ |
426 |
.parent = &armper_ck, |
427 |
.flags = CLOCK_IN_OMAP310, |
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}; |
429 |
|
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static struct clk mclk_310 = { |
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.name = "com_mclk_out",
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.parent = &armper_ck, |
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.flags = CLOCK_IN_OMAP310, |
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}; |
435 |
|
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static struct clk mclk_16xx = { |
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.name = "mclk",
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/* Direct from ULPD, no parent. May be enabled by ext hardware. */
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.flags = CLOCK_IN_OMAP16XX, |
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}; |
441 |
|
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static struct clk bclk_1510 = { |
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.name = "bclk",
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/* Direct from ULPD, no parent. May be enabled by ext hardware. */
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.rate = 12000000,
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.flags = CLOCK_IN_OMAP1510, |
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}; |
448 |
|
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static struct clk bclk_16xx = { |
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.name = "bclk",
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/* Direct from ULPD, no parent. May be enabled by ext hardware. */
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.flags = CLOCK_IN_OMAP16XX, |
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}; |
454 |
|
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static struct clk mmc1_ck = { |
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.name = "mmc_ck",
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.id = 1,
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/* Functional clock is direct from ULPD, interface clock is ARMPER */
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.parent = &armper_ck, /* either armper_ck or dpll4 */
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.rate = 48000000,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
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}; |
463 |
|
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static struct clk mmc2_ck = { |
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.name = "mmc_ck",
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.id = 2,
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/* Functional clock is direct from ULPD, interface clock is ARMPER */
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.parent = &armper_ck, |
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.rate = 48000000,
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.flags = CLOCK_IN_OMAP16XX, |
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}; |
472 |
|
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static struct clk cam_mclk = { |
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.name = "cam.mclk",
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
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.rate = 12000000,
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}; |
478 |
|
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static struct clk cam_exclk = { |
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.name = "cam.exclk",
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
482 |
/* Either 12M from cam.mclk or 48M from dpll4 */
|
483 |
.parent = &cam_mclk, |
484 |
}; |
485 |
|
486 |
static struct clk cam_lclk = { |
487 |
.name = "cam.lclk",
|
488 |
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
489 |
}; |
490 |
|
491 |
static struct clk i2c_fck = { |
492 |
.name = "i2c_fck",
|
493 |
.id = 1,
|
494 |
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
495 |
ALWAYS_ENABLED, |
496 |
.parent = &armxor_ck, |
497 |
}; |
498 |
|
499 |
static struct clk i2c_ick = { |
500 |
.name = "i2c_ick",
|
501 |
.id = 1,
|
502 |
.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
503 |
.parent = &armper_ck, |
504 |
}; |
505 |
|
506 |
static struct clk clk32k = { |
507 |
.name = "clk32-kHz",
|
508 |
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
509 |
CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
510 |
.parent = &xtal_osc32k, |
511 |
}; |
512 |
|
513 |
static struct clk apll_96m = { |
514 |
.name = "apll_96m",
|
515 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
516 |
.rate = 96000000,
|
517 |
/*.parent = sys.xtalin */
|
518 |
}; |
519 |
|
520 |
static struct clk apll_54m = { |
521 |
.name = "apll_54m",
|
522 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
523 |
.rate = 54000000,
|
524 |
/*.parent = sys.xtalin */
|
525 |
}; |
526 |
|
527 |
static struct clk sys_clk = { |
528 |
.name = "sys_clk",
|
529 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
530 |
.rate = 32768,
|
531 |
/*.parent = sys.xtalin */
|
532 |
}; |
533 |
|
534 |
static struct clk sleep_clk = { |
535 |
.name = "sleep_clk",
|
536 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
537 |
.rate = 32768,
|
538 |
/*.parent = sys.xtalin */
|
539 |
}; |
540 |
|
541 |
static struct clk dpll_ck = { |
542 |
.name = "dpll",
|
543 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
544 |
/*.parent = sys.xtalin */
|
545 |
}; |
546 |
|
547 |
static struct clk dpll_x2_ck = { |
548 |
.name = "dpll_x2",
|
549 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
550 |
/*.parent = sys.xtalin */
|
551 |
}; |
552 |
|
553 |
static struct clk wdt1_sys_clk = { |
554 |
.name = "wdt1_sys_clk",
|
555 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
556 |
.rate = 32768,
|
557 |
/*.parent = sys.xtalin */
|
558 |
}; |
559 |
|
560 |
static struct clk func_96m_clk = { |
561 |
.name = "func_96m_clk",
|
562 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
563 |
.divisor = 1,
|
564 |
.parent = &apll_96m, |
565 |
}; |
566 |
|
567 |
static struct clk func_48m_clk = { |
568 |
.name = "func_48m_clk",
|
569 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
570 |
.divisor = 2,
|
571 |
.parent = &apll_96m, |
572 |
}; |
573 |
|
574 |
static struct clk func_12m_clk = { |
575 |
.name = "func_12m_clk",
|
576 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
577 |
.divisor = 8,
|
578 |
.parent = &apll_96m, |
579 |
}; |
580 |
|
581 |
static struct clk func_54m_clk = { |
582 |
.name = "func_54m_clk",
|
583 |
.flags = CLOCK_IN_OMAP242X, |
584 |
.divisor = 1,
|
585 |
.parent = &apll_54m, |
586 |
}; |
587 |
|
588 |
static struct clk sys_clkout = { |
589 |
.name = "clkout",
|
590 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
591 |
.parent = &sys_clk, |
592 |
}; |
593 |
|
594 |
static struct clk sys_clkout2 = { |
595 |
.name = "clkout2",
|
596 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
597 |
.parent = &sys_clk, |
598 |
}; |
599 |
|
600 |
static struct clk core_clk = { |
601 |
.name = "core_clk",
|
602 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
603 |
.parent = &dpll_ck, |
604 |
}; |
605 |
|
606 |
static struct clk l3_clk = { |
607 |
.name = "l3_clk",
|
608 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
609 |
.parent = &core_clk, |
610 |
}; |
611 |
|
612 |
static struct clk core_l4_iclk = { |
613 |
.name = "core_l4_iclk",
|
614 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
615 |
.parent = &l3_clk, |
616 |
}; |
617 |
|
618 |
static struct clk wu_l4_iclk = { |
619 |
.name = "wu_l4_iclk",
|
620 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
621 |
.parent = &l3_clk, |
622 |
}; |
623 |
|
624 |
static struct clk core_l3_iclk = { |
625 |
.name = "core_l3_iclk",
|
626 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
627 |
.parent = &core_clk, |
628 |
}; |
629 |
|
630 |
static struct clk core_l4_usb_clk = { |
631 |
.name = "core_l4_usb_clk",
|
632 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
633 |
.parent = &l3_clk, |
634 |
}; |
635 |
|
636 |
static struct clk wu_gpt1_clk = { |
637 |
.name = "wu_gpt1_clk",
|
638 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
639 |
.parent = &sys_clk, |
640 |
}; |
641 |
|
642 |
static struct clk wu_32k_clk = { |
643 |
.name = "wu_32k_clk",
|
644 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
645 |
.parent = &sys_clk, |
646 |
}; |
647 |
|
648 |
static struct clk uart1_fclk = { |
649 |
.name = "uart1_fclk",
|
650 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
651 |
.parent = &func_48m_clk, |
652 |
}; |
653 |
|
654 |
static struct clk uart1_iclk = { |
655 |
.name = "uart1_iclk",
|
656 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
657 |
.parent = &core_l4_iclk, |
658 |
}; |
659 |
|
660 |
static struct clk uart2_fclk = { |
661 |
.name = "uart2_fclk",
|
662 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
663 |
.parent = &func_48m_clk, |
664 |
}; |
665 |
|
666 |
static struct clk uart2_iclk = { |
667 |
.name = "uart2_iclk",
|
668 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
669 |
.parent = &core_l4_iclk, |
670 |
}; |
671 |
|
672 |
static struct clk uart3_fclk = { |
673 |
.name = "uart3_fclk",
|
674 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
675 |
.parent = &func_48m_clk, |
676 |
}; |
677 |
|
678 |
static struct clk uart3_iclk = { |
679 |
.name = "uart3_iclk",
|
680 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
681 |
.parent = &core_l4_iclk, |
682 |
}; |
683 |
|
684 |
static struct clk mpu_fclk = { |
685 |
.name = "mpu_fclk",
|
686 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
687 |
.parent = &core_clk, |
688 |
}; |
689 |
|
690 |
static struct clk mpu_iclk = { |
691 |
.name = "mpu_iclk",
|
692 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
693 |
.parent = &core_clk, |
694 |
}; |
695 |
|
696 |
static struct clk int_m_fclk = { |
697 |
.name = "int_m_fclk",
|
698 |
.alias = "mpu_intc_fclk",
|
699 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
700 |
.parent = &core_clk, |
701 |
}; |
702 |
|
703 |
static struct clk int_m_iclk = { |
704 |
.name = "int_m_iclk",
|
705 |
.alias = "mpu_intc_iclk",
|
706 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
707 |
.parent = &core_clk, |
708 |
}; |
709 |
|
710 |
static struct clk core_gpt2_clk = { |
711 |
.name = "core_gpt2_clk",
|
712 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
713 |
.parent = &sys_clk, |
714 |
}; |
715 |
|
716 |
static struct clk core_gpt3_clk = { |
717 |
.name = "core_gpt3_clk",
|
718 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
719 |
.parent = &sys_clk, |
720 |
}; |
721 |
|
722 |
static struct clk core_gpt4_clk = { |
723 |
.name = "core_gpt4_clk",
|
724 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
725 |
.parent = &sys_clk, |
726 |
}; |
727 |
|
728 |
static struct clk core_gpt5_clk = { |
729 |
.name = "core_gpt5_clk",
|
730 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
731 |
.parent = &sys_clk, |
732 |
}; |
733 |
|
734 |
static struct clk core_gpt6_clk = { |
735 |
.name = "core_gpt6_clk",
|
736 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
737 |
.parent = &sys_clk, |
738 |
}; |
739 |
|
740 |
static struct clk core_gpt7_clk = { |
741 |
.name = "core_gpt7_clk",
|
742 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
743 |
.parent = &sys_clk, |
744 |
}; |
745 |
|
746 |
static struct clk core_gpt8_clk = { |
747 |
.name = "core_gpt8_clk",
|
748 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
749 |
.parent = &sys_clk, |
750 |
}; |
751 |
|
752 |
static struct clk core_gpt9_clk = { |
753 |
.name = "core_gpt9_clk",
|
754 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
755 |
.parent = &sys_clk, |
756 |
}; |
757 |
|
758 |
static struct clk core_gpt10_clk = { |
759 |
.name = "core_gpt10_clk",
|
760 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
761 |
.parent = &sys_clk, |
762 |
}; |
763 |
|
764 |
static struct clk core_gpt11_clk = { |
765 |
.name = "core_gpt11_clk",
|
766 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
767 |
.parent = &sys_clk, |
768 |
}; |
769 |
|
770 |
static struct clk core_gpt12_clk = { |
771 |
.name = "core_gpt12_clk",
|
772 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
773 |
.parent = &sys_clk, |
774 |
}; |
775 |
|
776 |
static struct clk mcbsp1_clk = { |
777 |
.name = "mcbsp1_cg",
|
778 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
779 |
.divisor = 2,
|
780 |
.parent = &func_96m_clk, |
781 |
}; |
782 |
|
783 |
static struct clk mcbsp2_clk = { |
784 |
.name = "mcbsp2_cg",
|
785 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
786 |
.divisor = 2,
|
787 |
.parent = &func_96m_clk, |
788 |
}; |
789 |
|
790 |
static struct clk emul_clk = { |
791 |
.name = "emul_ck",
|
792 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
793 |
.parent = &func_54m_clk, |
794 |
}; |
795 |
|
796 |
static struct clk sdma_fclk = { |
797 |
.name = "sdma_fclk",
|
798 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
799 |
.parent = &l3_clk, |
800 |
}; |
801 |
|
802 |
static struct clk sdma_iclk = { |
803 |
.name = "sdma_iclk",
|
804 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
805 |
.parent = &core_l3_iclk, /* core_l4_iclk for the configuration port */
|
806 |
}; |
807 |
|
808 |
static struct clk i2c1_fclk = { |
809 |
.name = "i2c1.fclk",
|
810 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
811 |
.parent = &func_12m_clk, |
812 |
.divisor = 1,
|
813 |
}; |
814 |
|
815 |
static struct clk i2c1_iclk = { |
816 |
.name = "i2c1.iclk",
|
817 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
818 |
.parent = &core_l4_iclk, |
819 |
}; |
820 |
|
821 |
static struct clk i2c2_fclk = { |
822 |
.name = "i2c2.fclk",
|
823 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
824 |
.parent = &func_12m_clk, |
825 |
.divisor = 1,
|
826 |
}; |
827 |
|
828 |
static struct clk i2c2_iclk = { |
829 |
.name = "i2c2.iclk",
|
830 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
831 |
.parent = &core_l4_iclk, |
832 |
}; |
833 |
|
834 |
static struct clk gpio_dbclk[4] = { |
835 |
{ |
836 |
.name = "gpio1_dbclk",
|
837 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
838 |
.parent = &wu_32k_clk, |
839 |
}, { |
840 |
.name = "gpio2_dbclk",
|
841 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
842 |
.parent = &wu_32k_clk, |
843 |
}, { |
844 |
.name = "gpio3_dbclk",
|
845 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
846 |
.parent = &wu_32k_clk, |
847 |
}, { |
848 |
.name = "gpio4_dbclk",
|
849 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
850 |
.parent = &wu_32k_clk, |
851 |
}, |
852 |
}; |
853 |
|
854 |
static struct clk gpio_iclk = { |
855 |
.name = "gpio_iclk",
|
856 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
857 |
.parent = &wu_l4_iclk, |
858 |
}; |
859 |
|
860 |
static struct clk mmc_fck = { |
861 |
.name = "mmc_fclk",
|
862 |
.flags = CLOCK_IN_OMAP242X, |
863 |
.parent = &func_96m_clk, |
864 |
}; |
865 |
|
866 |
static struct clk mmc_ick = { |
867 |
.name = "mmc_iclk",
|
868 |
.flags = CLOCK_IN_OMAP242X, |
869 |
.parent = &core_l4_iclk, |
870 |
}; |
871 |
|
872 |
static struct clk spi_fclk[3] = { |
873 |
{ |
874 |
.name = "spi1_fclk",
|
875 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
876 |
.parent = &func_48m_clk, |
877 |
}, { |
878 |
.name = "spi2_fclk",
|
879 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
880 |
.parent = &func_48m_clk, |
881 |
}, { |
882 |
.name = "spi3_fclk",
|
883 |
.flags = CLOCK_IN_OMAP243X, |
884 |
.parent = &func_48m_clk, |
885 |
}, |
886 |
}; |
887 |
|
888 |
static struct clk dss_clk[2] = { |
889 |
{ |
890 |
.name = "dss_clk1",
|
891 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
892 |
.parent = &core_clk, |
893 |
}, { |
894 |
.name = "dss_clk2",
|
895 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
896 |
.parent = &sys_clk, |
897 |
}, |
898 |
}; |
899 |
|
900 |
static struct clk dss_54m_clk = { |
901 |
.name = "dss_54m_clk",
|
902 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
903 |
.parent = &func_54m_clk, |
904 |
}; |
905 |
|
906 |
static struct clk dss_l3_iclk = { |
907 |
.name = "dss_l3_iclk",
|
908 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
909 |
.parent = &core_l3_iclk, |
910 |
}; |
911 |
|
912 |
static struct clk dss_l4_iclk = { |
913 |
.name = "dss_l4_iclk",
|
914 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
915 |
.parent = &core_l4_iclk, |
916 |
}; |
917 |
|
918 |
static struct clk spi_iclk[3] = { |
919 |
{ |
920 |
.name = "spi1_iclk",
|
921 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
922 |
.parent = &core_l4_iclk, |
923 |
}, { |
924 |
.name = "spi2_iclk",
|
925 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
926 |
.parent = &core_l4_iclk, |
927 |
}, { |
928 |
.name = "spi3_iclk",
|
929 |
.flags = CLOCK_IN_OMAP243X, |
930 |
.parent = &core_l4_iclk, |
931 |
}, |
932 |
}; |
933 |
|
934 |
static struct clk omapctrl_clk = { |
935 |
.name = "omapctrl_iclk",
|
936 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
937 |
/* XXX Should be in WKUP domain */
|
938 |
.parent = &core_l4_iclk, |
939 |
}; |
940 |
|
941 |
static struct clk *onchip_clks[] = { |
942 |
/* OMAP 1 */
|
943 |
|
944 |
/* non-ULPD clocks */
|
945 |
&xtal_osc12m, |
946 |
&xtal_osc32k, |
947 |
&ck_ref, |
948 |
&dpll1, |
949 |
&dpll2, |
950 |
&dpll3, |
951 |
&dpll4, |
952 |
&apll, |
953 |
&ck_48m, |
954 |
/* CK_GEN1 clocks */
|
955 |
&clkm1, |
956 |
&ck_dpll1out, |
957 |
&sossi_ck, |
958 |
&arm_ck, |
959 |
&armper_ck, |
960 |
&arm_gpio_ck, |
961 |
&armxor_ck, |
962 |
&armtim_ck, |
963 |
&armwdt_ck, |
964 |
&arminth_ck15xx, &arminth_ck16xx, |
965 |
/* CK_GEN2 clocks */
|
966 |
&clkm2, |
967 |
&dsp_ck, |
968 |
&dspmmu_ck, |
969 |
&dspper_ck, |
970 |
&dspxor_ck, |
971 |
&dsptim_ck, |
972 |
/* CK_GEN3 clocks */
|
973 |
&clkm3, |
974 |
&tc_ck, |
975 |
&tipb_ck, |
976 |
&l3_ocpi_ck, |
977 |
&tc1_ck, |
978 |
&tc2_ck, |
979 |
&dma_ck, |
980 |
&dma_lcdfree_ck, |
981 |
&api_ck, |
982 |
&lb_ck, |
983 |
&lbfree_ck, |
984 |
&hsab_ck, |
985 |
&rhea1_ck, |
986 |
&rhea2_ck, |
987 |
&lcd_ck_16xx, |
988 |
&lcd_ck_1510, |
989 |
/* ULPD clocks */
|
990 |
&uart1_1510, |
991 |
&uart1_16xx, |
992 |
&uart2_ck, |
993 |
&uart3_1510, |
994 |
&uart3_16xx, |
995 |
&usb_clk0, |
996 |
&usb_hhc_ck1510, &usb_hhc_ck16xx, |
997 |
&mclk_1510, &mclk_16xx, &mclk_310, |
998 |
&bclk_1510, &bclk_16xx, &bclk_310, |
999 |
&mmc1_ck, |
1000 |
&mmc2_ck, |
1001 |
&cam_mclk, |
1002 |
&cam_exclk, |
1003 |
&cam_lclk, |
1004 |
&clk32k, |
1005 |
&usb_w2fc_mclk, |
1006 |
/* Virtual clocks */
|
1007 |
&i2c_fck, |
1008 |
&i2c_ick, |
1009 |
|
1010 |
/* OMAP 2 */
|
1011 |
|
1012 |
&apll_96m, |
1013 |
&apll_54m, |
1014 |
&sys_clk, |
1015 |
&sleep_clk, |
1016 |
&dpll_ck, |
1017 |
&dpll_x2_ck, |
1018 |
&wdt1_sys_clk, |
1019 |
&func_96m_clk, |
1020 |
&func_48m_clk, |
1021 |
&func_12m_clk, |
1022 |
&func_54m_clk, |
1023 |
&sys_clkout, |
1024 |
&sys_clkout2, |
1025 |
&core_clk, |
1026 |
&l3_clk, |
1027 |
&core_l4_iclk, |
1028 |
&wu_l4_iclk, |
1029 |
&core_l3_iclk, |
1030 |
&core_l4_usb_clk, |
1031 |
&wu_gpt1_clk, |
1032 |
&wu_32k_clk, |
1033 |
&uart1_fclk, |
1034 |
&uart1_iclk, |
1035 |
&uart2_fclk, |
1036 |
&uart2_iclk, |
1037 |
&uart3_fclk, |
1038 |
&uart3_iclk, |
1039 |
&mpu_fclk, |
1040 |
&mpu_iclk, |
1041 |
&int_m_fclk, |
1042 |
&int_m_iclk, |
1043 |
&core_gpt2_clk, |
1044 |
&core_gpt3_clk, |
1045 |
&core_gpt4_clk, |
1046 |
&core_gpt5_clk, |
1047 |
&core_gpt6_clk, |
1048 |
&core_gpt7_clk, |
1049 |
&core_gpt8_clk, |
1050 |
&core_gpt9_clk, |
1051 |
&core_gpt10_clk, |
1052 |
&core_gpt11_clk, |
1053 |
&core_gpt12_clk, |
1054 |
&mcbsp1_clk, |
1055 |
&mcbsp2_clk, |
1056 |
&emul_clk, |
1057 |
&sdma_fclk, |
1058 |
&sdma_iclk, |
1059 |
&i2c1_fclk, |
1060 |
&i2c1_iclk, |
1061 |
&i2c2_fclk, |
1062 |
&i2c2_iclk, |
1063 |
&gpio_dbclk[0],
|
1064 |
&gpio_dbclk[1],
|
1065 |
&gpio_dbclk[2],
|
1066 |
&gpio_dbclk[3],
|
1067 |
&gpio_iclk, |
1068 |
&mmc_fck, |
1069 |
&mmc_ick, |
1070 |
&spi_fclk[0],
|
1071 |
&spi_iclk[0],
|
1072 |
&spi_fclk[1],
|
1073 |
&spi_iclk[1],
|
1074 |
&spi_fclk[2],
|
1075 |
&spi_iclk[2],
|
1076 |
&dss_clk[0],
|
1077 |
&dss_clk[1],
|
1078 |
&dss_54m_clk, |
1079 |
&dss_l3_iclk, |
1080 |
&dss_l4_iclk, |
1081 |
&omapctrl_clk, |
1082 |
|
1083 |
0
|
1084 |
}; |
1085 |
|
1086 |
void omap_clk_adduser(struct clk *clk, qemu_irq user) |
1087 |
{ |
1088 |
qemu_irq *i; |
1089 |
|
1090 |
for (i = clk->users; *i; i ++);
|
1091 |
*i = user; |
1092 |
} |
1093 |
|
1094 |
/* If a clock is allowed to idle, it is disabled automatically when
|
1095 |
* all of clock domains using it are disabled. */
|
1096 |
int omap_clk_is_idle(struct clk *clk) |
1097 |
{ |
1098 |
struct clk *chld;
|
1099 |
|
1100 |
if (!clk->enabled && (!clk->usecount || !(clk->flags && ALWAYS_ENABLED)))
|
1101 |
return 1; |
1102 |
if (clk->usecount)
|
1103 |
return 0; |
1104 |
|
1105 |
for (chld = clk->child1; chld; chld = chld->sibling)
|
1106 |
if (!omap_clk_is_idle(chld))
|
1107 |
return 0; |
1108 |
return 1; |
1109 |
} |
1110 |
|
1111 |
struct clk *omap_findclk(struct omap_mpu_state_s *mpu, const char *name) |
1112 |
{ |
1113 |
struct clk *i;
|
1114 |
|
1115 |
for (i = mpu->clks; i->name; i ++)
|
1116 |
if (!strcmp(i->name, name) || (i->alias && !strcmp(i->alias, name)))
|
1117 |
return i;
|
1118 |
cpu_abort(mpu->env, "%s: %s not found\n", __FUNCTION__, name);
|
1119 |
} |
1120 |
|
1121 |
void omap_clk_get(struct clk *clk) |
1122 |
{ |
1123 |
clk->usecount ++; |
1124 |
} |
1125 |
|
1126 |
void omap_clk_put(struct clk *clk) |
1127 |
{ |
1128 |
if (!(clk->usecount --))
|
1129 |
cpu_abort(cpu_single_env, "%s: %s is not in use\n",
|
1130 |
__FUNCTION__, clk->name); |
1131 |
} |
1132 |
|
1133 |
static void omap_clk_update(struct clk *clk) |
1134 |
{ |
1135 |
int parent, running;
|
1136 |
qemu_irq *user; |
1137 |
struct clk *i;
|
1138 |
|
1139 |
if (clk->parent)
|
1140 |
parent = clk->parent->running; |
1141 |
else
|
1142 |
parent = 1;
|
1143 |
|
1144 |
running = parent && (clk->enabled || |
1145 |
((clk->flags & ALWAYS_ENABLED) && clk->usecount)); |
1146 |
if (clk->running != running) {
|
1147 |
clk->running = running; |
1148 |
for (user = clk->users; *user; user ++)
|
1149 |
qemu_set_irq(*user, running); |
1150 |
for (i = clk->child1; i; i = i->sibling)
|
1151 |
omap_clk_update(i); |
1152 |
} |
1153 |
} |
1154 |
|
1155 |
static void omap_clk_rate_update_full(struct clk *clk, unsigned long int rate, |
1156 |
unsigned long int div, unsigned long int mult) |
1157 |
{ |
1158 |
struct clk *i;
|
1159 |
qemu_irq *user; |
1160 |
|
1161 |
clk->rate = muldiv64(rate, mult, div); |
1162 |
if (clk->running)
|
1163 |
for (user = clk->users; *user; user ++)
|
1164 |
qemu_irq_raise(*user); |
1165 |
for (i = clk->child1; i; i = i->sibling)
|
1166 |
omap_clk_rate_update_full(i, rate, |
1167 |
div * i->divisor, mult * i->multiplier); |
1168 |
} |
1169 |
|
1170 |
static void omap_clk_rate_update(struct clk *clk) |
1171 |
{ |
1172 |
struct clk *i;
|
1173 |
unsigned long int div, mult = div = 1; |
1174 |
|
1175 |
for (i = clk; i->parent; i = i->parent) {
|
1176 |
div *= i->divisor; |
1177 |
mult *= i->multiplier; |
1178 |
} |
1179 |
|
1180 |
omap_clk_rate_update_full(clk, i->rate, div, mult); |
1181 |
} |
1182 |
|
1183 |
void omap_clk_reparent(struct clk *clk, struct clk *parent) |
1184 |
{ |
1185 |
struct clk **p;
|
1186 |
|
1187 |
if (clk->parent) {
|
1188 |
for (p = &clk->parent->child1; *p != clk; p = &(*p)->sibling);
|
1189 |
*p = clk->sibling; |
1190 |
} |
1191 |
|
1192 |
clk->parent = parent; |
1193 |
if (parent) {
|
1194 |
clk->sibling = parent->child1; |
1195 |
parent->child1 = clk; |
1196 |
omap_clk_update(clk); |
1197 |
omap_clk_rate_update(clk); |
1198 |
} else
|
1199 |
clk->sibling = 0;
|
1200 |
} |
1201 |
|
1202 |
void omap_clk_onoff(struct clk *clk, int on) |
1203 |
{ |
1204 |
clk->enabled = on; |
1205 |
omap_clk_update(clk); |
1206 |
} |
1207 |
|
1208 |
void omap_clk_canidle(struct clk *clk, int can) |
1209 |
{ |
1210 |
if (can)
|
1211 |
omap_clk_put(clk); |
1212 |
else
|
1213 |
omap_clk_get(clk); |
1214 |
} |
1215 |
|
1216 |
void omap_clk_setrate(struct clk *clk, int divide, int multiply) |
1217 |
{ |
1218 |
clk->divisor = divide; |
1219 |
clk->multiplier = multiply; |
1220 |
omap_clk_rate_update(clk); |
1221 |
} |
1222 |
|
1223 |
int64_t omap_clk_getrate(omap_clk clk) |
1224 |
{ |
1225 |
return clk->rate;
|
1226 |
} |
1227 |
|
1228 |
void omap_clk_init(struct omap_mpu_state_s *mpu) |
1229 |
{ |
1230 |
struct clk **i, *j, *k;
|
1231 |
int count;
|
1232 |
int flag;
|
1233 |
|
1234 |
if (cpu_is_omap310(mpu))
|
1235 |
flag = CLOCK_IN_OMAP310; |
1236 |
else if (cpu_is_omap1510(mpu)) |
1237 |
flag = CLOCK_IN_OMAP1510; |
1238 |
else if (cpu_is_omap2410(mpu) || cpu_is_omap2420(mpu)) |
1239 |
flag = CLOCK_IN_OMAP242X; |
1240 |
else if (cpu_is_omap2430(mpu)) |
1241 |
flag = CLOCK_IN_OMAP243X; |
1242 |
else if (cpu_is_omap3430(mpu)) |
1243 |
flag = CLOCK_IN_OMAP243X; |
1244 |
else
|
1245 |
return;
|
1246 |
|
1247 |
for (i = onchip_clks, count = 0; *i; i ++) |
1248 |
if ((*i)->flags & flag)
|
1249 |
count ++; |
1250 |
mpu->clks = (struct clk *) qemu_mallocz(sizeof(struct clk) * (count + 1)); |
1251 |
for (i = onchip_clks, j = mpu->clks; *i; i ++)
|
1252 |
if ((*i)->flags & flag) {
|
1253 |
memcpy(j, *i, sizeof(struct clk)); |
1254 |
for (k = mpu->clks; k < j; k ++)
|
1255 |
if (j->parent && !strcmp(j->parent->name, k->name)) {
|
1256 |
j->parent = k; |
1257 |
j->sibling = k->child1; |
1258 |
k->child1 = j; |
1259 |
} else if (k->parent && !strcmp(k->parent->name, j->name)) { |
1260 |
k->parent = j; |
1261 |
k->sibling = j->child1; |
1262 |
j->child1 = k; |
1263 |
} |
1264 |
j->divisor = j->divisor ?: 1;
|
1265 |
j->multiplier = j->multiplier ?: 1;
|
1266 |
j ++; |
1267 |
} |
1268 |
for (j = mpu->clks; count --; j ++) {
|
1269 |
omap_clk_update(j); |
1270 |
omap_clk_rate_update(j); |
1271 |
} |
1272 |
} |