root / hw / ppc405_uc.c @ c76ee25d
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| 1 | 8ecc7913 | j_mayer | /*
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|---|---|---|---|
| 2 | 8ecc7913 | j_mayer | * QEMU PowerPC 405 embedded processors emulation
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| 3 | 5fafdf24 | ths | *
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| 4 | 8ecc7913 | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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| 5 | 5fafdf24 | ths | *
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| 6 | 8ecc7913 | j_mayer | * Permission is hereby granted, free of charge, to any person obtaining a copy
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| 7 | 8ecc7913 | j_mayer | * of this software and associated documentation files (the "Software"), to deal
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| 8 | 8ecc7913 | j_mayer | * in the Software without restriction, including without limitation the rights
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| 9 | 8ecc7913 | j_mayer | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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| 10 | 8ecc7913 | j_mayer | * copies of the Software, and to permit persons to whom the Software is
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| 11 | 8ecc7913 | j_mayer | * furnished to do so, subject to the following conditions:
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| 12 | 8ecc7913 | j_mayer | *
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| 13 | 8ecc7913 | j_mayer | * The above copyright notice and this permission notice shall be included in
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| 14 | 8ecc7913 | j_mayer | * all copies or substantial portions of the Software.
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| 15 | 8ecc7913 | j_mayer | *
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| 16 | 8ecc7913 | j_mayer | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 17 | 8ecc7913 | j_mayer | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 18 | 8ecc7913 | j_mayer | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 19 | 8ecc7913 | j_mayer | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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| 20 | 8ecc7913 | j_mayer | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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| 21 | 8ecc7913 | j_mayer | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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| 22 | 8ecc7913 | j_mayer | * THE SOFTWARE.
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| 23 | 8ecc7913 | j_mayer | */
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| 24 | 87ecb68b | pbrook | #include "hw.h" |
| 25 | 87ecb68b | pbrook | #include "ppc.h" |
| 26 | 04f20795 | j_mayer | #include "ppc405.h" |
| 27 | 87ecb68b | pbrook | #include "pc.h" |
| 28 | 87ecb68b | pbrook | #include "qemu-timer.h" |
| 29 | 87ecb68b | pbrook | #include "sysemu.h" |
| 30 | 3b3fb322 | blueswir1 | #include "qemu-log.h" |
| 31 | 8ecc7913 | j_mayer | |
| 32 | 8ecc7913 | j_mayer | #define DEBUG_OPBA
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| 33 | 8ecc7913 | j_mayer | #define DEBUG_SDRAM
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| 34 | 8ecc7913 | j_mayer | #define DEBUG_GPIO
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| 35 | 8ecc7913 | j_mayer | #define DEBUG_SERIAL
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| 36 | 8ecc7913 | j_mayer | #define DEBUG_OCM
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| 37 | 9c02f1a2 | j_mayer | //#define DEBUG_I2C
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| 38 | 9c02f1a2 | j_mayer | #define DEBUG_GPT
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| 39 | 9c02f1a2 | j_mayer | #define DEBUG_MAL
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| 40 | 8ecc7913 | j_mayer | #define DEBUG_CLOCKS
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| 41 | aae9366a | j_mayer | //#define DEBUG_CLOCKS_LL
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| 42 | 8ecc7913 | j_mayer | |
| 43 | b8d3f5d1 | j_mayer | ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, |
| 44 | b8d3f5d1 | j_mayer | uint32_t flags) |
| 45 | 04f20795 | j_mayer | {
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| 46 | 04f20795 | j_mayer | ram_addr_t bdloc; |
| 47 | 04f20795 | j_mayer | int i, n;
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| 48 | 04f20795 | j_mayer | |
| 49 | 04f20795 | j_mayer | /* We put the bd structure at the top of memory */
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| 50 | be58fc7c | j_mayer | if (bd->bi_memsize >= 0x01000000UL) |
| 51 | be58fc7c | j_mayer | bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); |
| 52 | be58fc7c | j_mayer | else
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| 53 | be58fc7c | j_mayer | bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); |
| 54 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x00, bd->bi_memstart);
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| 55 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x04, bd->bi_memsize);
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| 56 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x08, bd->bi_flashstart);
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| 57 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x0C, bd->bi_flashsize);
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| 58 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x10, bd->bi_flashoffset);
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| 59 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x14, bd->bi_sramstart);
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| 60 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x18, bd->bi_sramsize);
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| 61 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x1C, bd->bi_bootflags);
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| 62 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x20, bd->bi_ipaddr);
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| 63 | 04f20795 | j_mayer | for (i = 0; i < 6; i++) |
| 64 | 04f20795 | j_mayer | stb_raw(phys_ram_base + bdloc + 0x24 + i, bd->bi_enetaddr[i]);
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| 65 | 04f20795 | j_mayer | stw_raw(phys_ram_base + bdloc + 0x2A, bd->bi_ethspeed);
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| 66 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x2C, bd->bi_intfreq);
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| 67 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x30, bd->bi_busfreq);
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| 68 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x34, bd->bi_baudrate);
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| 69 | 04f20795 | j_mayer | for (i = 0; i < 4; i++) |
| 70 | 04f20795 | j_mayer | stb_raw(phys_ram_base + bdloc + 0x38 + i, bd->bi_s_version[i]);
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| 71 | 04f20795 | j_mayer | for (i = 0; i < 32; i++) |
| 72 | 04f20795 | j_mayer | stb_raw(phys_ram_base + bdloc + 0x3C + i, bd->bi_s_version[i]);
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| 73 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x5C, bd->bi_plb_busfreq);
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| 74 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x60, bd->bi_pci_busfreq);
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| 75 | 04f20795 | j_mayer | for (i = 0; i < 6; i++) |
| 76 | 04f20795 | j_mayer | stb_raw(phys_ram_base + bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
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| 77 | 04f20795 | j_mayer | n = 0x6A;
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| 78 | b8d3f5d1 | j_mayer | if (flags & 0x00000001) { |
| 79 | 04f20795 | j_mayer | for (i = 0; i < 6; i++) |
| 80 | 04f20795 | j_mayer | stb_raw(phys_ram_base + bdloc + n++, bd->bi_pci_enetaddr2[i]); |
| 81 | 04f20795 | j_mayer | } |
| 82 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + n, bd->bi_opbfreq); |
| 83 | 04f20795 | j_mayer | n += 4;
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| 84 | 04f20795 | j_mayer | for (i = 0; i < 2; i++) { |
| 85 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + n, bd->bi_iic_fast[i]); |
| 86 | 04f20795 | j_mayer | n += 4;
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| 87 | 04f20795 | j_mayer | } |
| 88 | 04f20795 | j_mayer | |
| 89 | 04f20795 | j_mayer | return bdloc;
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| 90 | 04f20795 | j_mayer | } |
| 91 | 04f20795 | j_mayer | |
| 92 | 8ecc7913 | j_mayer | /*****************************************************************************/
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| 93 | 8ecc7913 | j_mayer | /* Shared peripherals */
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| 94 | 8ecc7913 | j_mayer | |
| 95 | 8ecc7913 | j_mayer | /*****************************************************************************/
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| 96 | 8ecc7913 | j_mayer | /* Peripheral local bus arbitrer */
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| 97 | 8ecc7913 | j_mayer | enum {
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| 98 | 8ecc7913 | j_mayer | PLB0_BESR = 0x084,
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| 99 | 8ecc7913 | j_mayer | PLB0_BEAR = 0x086,
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| 100 | 8ecc7913 | j_mayer | PLB0_ACR = 0x087,
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| 101 | 8ecc7913 | j_mayer | }; |
| 102 | 8ecc7913 | j_mayer | |
| 103 | 8ecc7913 | j_mayer | typedef struct ppc4xx_plb_t ppc4xx_plb_t; |
| 104 | 8ecc7913 | j_mayer | struct ppc4xx_plb_t {
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| 105 | 8ecc7913 | j_mayer | uint32_t acr; |
| 106 | 8ecc7913 | j_mayer | uint32_t bear; |
| 107 | 8ecc7913 | j_mayer | uint32_t besr; |
| 108 | 8ecc7913 | j_mayer | }; |
| 109 | 8ecc7913 | j_mayer | |
| 110 | 8ecc7913 | j_mayer | static target_ulong dcr_read_plb (void *opaque, int dcrn) |
| 111 | 8ecc7913 | j_mayer | {
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| 112 | 8ecc7913 | j_mayer | ppc4xx_plb_t *plb; |
| 113 | 8ecc7913 | j_mayer | target_ulong ret; |
| 114 | 8ecc7913 | j_mayer | |
| 115 | 8ecc7913 | j_mayer | plb = opaque; |
| 116 | 8ecc7913 | j_mayer | switch (dcrn) {
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| 117 | 8ecc7913 | j_mayer | case PLB0_ACR:
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| 118 | 8ecc7913 | j_mayer | ret = plb->acr; |
| 119 | 8ecc7913 | j_mayer | break;
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| 120 | 8ecc7913 | j_mayer | case PLB0_BEAR:
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| 121 | 8ecc7913 | j_mayer | ret = plb->bear; |
| 122 | 8ecc7913 | j_mayer | break;
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| 123 | 8ecc7913 | j_mayer | case PLB0_BESR:
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| 124 | 8ecc7913 | j_mayer | ret = plb->besr; |
| 125 | 8ecc7913 | j_mayer | break;
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| 126 | 8ecc7913 | j_mayer | default:
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| 127 | 8ecc7913 | j_mayer | /* Avoid gcc warning */
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| 128 | 8ecc7913 | j_mayer | ret = 0;
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| 129 | 8ecc7913 | j_mayer | break;
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| 130 | 8ecc7913 | j_mayer | } |
| 131 | 8ecc7913 | j_mayer | |
| 132 | 8ecc7913 | j_mayer | return ret;
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| 133 | 8ecc7913 | j_mayer | } |
| 134 | 8ecc7913 | j_mayer | |
| 135 | 8ecc7913 | j_mayer | static void dcr_write_plb (void *opaque, int dcrn, target_ulong val) |
| 136 | 8ecc7913 | j_mayer | {
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| 137 | 8ecc7913 | j_mayer | ppc4xx_plb_t *plb; |
| 138 | 8ecc7913 | j_mayer | |
| 139 | 8ecc7913 | j_mayer | plb = opaque; |
| 140 | 8ecc7913 | j_mayer | switch (dcrn) {
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| 141 | 8ecc7913 | j_mayer | case PLB0_ACR:
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| 142 | 9c02f1a2 | j_mayer | /* We don't care about the actual parameters written as
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| 143 | 9c02f1a2 | j_mayer | * we don't manage any priorities on the bus
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| 144 | 9c02f1a2 | j_mayer | */
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| 145 | 9c02f1a2 | j_mayer | plb->acr = val & 0xF8000000;
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| 146 | 8ecc7913 | j_mayer | break;
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| 147 | 8ecc7913 | j_mayer | case PLB0_BEAR:
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| 148 | 8ecc7913 | j_mayer | /* Read only */
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| 149 | 8ecc7913 | j_mayer | break;
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| 150 | 8ecc7913 | j_mayer | case PLB0_BESR:
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| 151 | 8ecc7913 | j_mayer | /* Write-clear */
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| 152 | 8ecc7913 | j_mayer | plb->besr &= ~val; |
| 153 | 8ecc7913 | j_mayer | break;
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| 154 | 8ecc7913 | j_mayer | } |
| 155 | 8ecc7913 | j_mayer | } |
| 156 | 8ecc7913 | j_mayer | |
| 157 | 8ecc7913 | j_mayer | static void ppc4xx_plb_reset (void *opaque) |
| 158 | 8ecc7913 | j_mayer | {
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| 159 | 8ecc7913 | j_mayer | ppc4xx_plb_t *plb; |
| 160 | 8ecc7913 | j_mayer | |
| 161 | 8ecc7913 | j_mayer | plb = opaque; |
| 162 | 8ecc7913 | j_mayer | plb->acr = 0x00000000;
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| 163 | 8ecc7913 | j_mayer | plb->bear = 0x00000000;
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| 164 | 8ecc7913 | j_mayer | plb->besr = 0x00000000;
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| 165 | 8ecc7913 | j_mayer | } |
| 166 | 8ecc7913 | j_mayer | |
| 167 | 8ecc7913 | j_mayer | void ppc4xx_plb_init (CPUState *env)
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| 168 | 8ecc7913 | j_mayer | {
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| 169 | 8ecc7913 | j_mayer | ppc4xx_plb_t *plb; |
| 170 | 8ecc7913 | j_mayer | |
| 171 | 8ecc7913 | j_mayer | plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
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| 172 | 8ecc7913 | j_mayer | if (plb != NULL) { |
| 173 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); |
| 174 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); |
| 175 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); |
| 176 | 8ecc7913 | j_mayer | ppc4xx_plb_reset(plb); |
| 177 | 8ecc7913 | j_mayer | qemu_register_reset(ppc4xx_plb_reset, plb); |
| 178 | 8ecc7913 | j_mayer | } |
| 179 | 8ecc7913 | j_mayer | } |
| 180 | 8ecc7913 | j_mayer | |
| 181 | 8ecc7913 | j_mayer | /*****************************************************************************/
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| 182 | 8ecc7913 | j_mayer | /* PLB to OPB bridge */
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| 183 | 8ecc7913 | j_mayer | enum {
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| 184 | 8ecc7913 | j_mayer | POB0_BESR0 = 0x0A0,
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| 185 | 8ecc7913 | j_mayer | POB0_BESR1 = 0x0A2,
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| 186 | 8ecc7913 | j_mayer | POB0_BEAR = 0x0A4,
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| 187 | 8ecc7913 | j_mayer | }; |
| 188 | 8ecc7913 | j_mayer | |
| 189 | 8ecc7913 | j_mayer | typedef struct ppc4xx_pob_t ppc4xx_pob_t; |
| 190 | 8ecc7913 | j_mayer | struct ppc4xx_pob_t {
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| 191 | 8ecc7913 | j_mayer | uint32_t bear; |
| 192 | 8ecc7913 | j_mayer | uint32_t besr[2];
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| 193 | 8ecc7913 | j_mayer | }; |
| 194 | 8ecc7913 | j_mayer | |
| 195 | 8ecc7913 | j_mayer | static target_ulong dcr_read_pob (void *opaque, int dcrn) |
| 196 | 8ecc7913 | j_mayer | {
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| 197 | 8ecc7913 | j_mayer | ppc4xx_pob_t *pob; |
| 198 | 8ecc7913 | j_mayer | target_ulong ret; |
| 199 | 8ecc7913 | j_mayer | |
| 200 | 8ecc7913 | j_mayer | pob = opaque; |
| 201 | 8ecc7913 | j_mayer | switch (dcrn) {
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| 202 | 8ecc7913 | j_mayer | case POB0_BEAR:
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| 203 | 8ecc7913 | j_mayer | ret = pob->bear; |
| 204 | 8ecc7913 | j_mayer | break;
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| 205 | 8ecc7913 | j_mayer | case POB0_BESR0:
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| 206 | 8ecc7913 | j_mayer | case POB0_BESR1:
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| 207 | 8ecc7913 | j_mayer | ret = pob->besr[dcrn - POB0_BESR0]; |
| 208 | 8ecc7913 | j_mayer | break;
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| 209 | 8ecc7913 | j_mayer | default:
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| 210 | 8ecc7913 | j_mayer | /* Avoid gcc warning */
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| 211 | 8ecc7913 | j_mayer | ret = 0;
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| 212 | 8ecc7913 | j_mayer | break;
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| 213 | 8ecc7913 | j_mayer | } |
| 214 | 8ecc7913 | j_mayer | |
| 215 | 8ecc7913 | j_mayer | return ret;
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| 216 | 8ecc7913 | j_mayer | } |
| 217 | 8ecc7913 | j_mayer | |
| 218 | 8ecc7913 | j_mayer | static void dcr_write_pob (void *opaque, int dcrn, target_ulong val) |
| 219 | 8ecc7913 | j_mayer | {
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| 220 | 8ecc7913 | j_mayer | ppc4xx_pob_t *pob; |
| 221 | 8ecc7913 | j_mayer | |
| 222 | 8ecc7913 | j_mayer | pob = opaque; |
| 223 | 8ecc7913 | j_mayer | switch (dcrn) {
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| 224 | 8ecc7913 | j_mayer | case POB0_BEAR:
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| 225 | 8ecc7913 | j_mayer | /* Read only */
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| 226 | 8ecc7913 | j_mayer | break;
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| 227 | 8ecc7913 | j_mayer | case POB0_BESR0:
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| 228 | 8ecc7913 | j_mayer | case POB0_BESR1:
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| 229 | 8ecc7913 | j_mayer | /* Write-clear */
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| 230 | 8ecc7913 | j_mayer | pob->besr[dcrn - POB0_BESR0] &= ~val; |
| 231 | 8ecc7913 | j_mayer | break;
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| 232 | 8ecc7913 | j_mayer | } |
| 233 | 8ecc7913 | j_mayer | } |
| 234 | 8ecc7913 | j_mayer | |
| 235 | 8ecc7913 | j_mayer | static void ppc4xx_pob_reset (void *opaque) |
| 236 | 8ecc7913 | j_mayer | {
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| 237 | 8ecc7913 | j_mayer | ppc4xx_pob_t *pob; |
| 238 | 8ecc7913 | j_mayer | |
| 239 | 8ecc7913 | j_mayer | pob = opaque; |
| 240 | 8ecc7913 | j_mayer | /* No error */
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| 241 | 8ecc7913 | j_mayer | pob->bear = 0x00000000;
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| 242 | 8ecc7913 | j_mayer | pob->besr[0] = 0x0000000; |
| 243 | 8ecc7913 | j_mayer | pob->besr[1] = 0x0000000; |
| 244 | 8ecc7913 | j_mayer | } |
| 245 | 8ecc7913 | j_mayer | |
| 246 | 8ecc7913 | j_mayer | void ppc4xx_pob_init (CPUState *env)
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| 247 | 8ecc7913 | j_mayer | {
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| 248 | 8ecc7913 | j_mayer | ppc4xx_pob_t *pob; |
| 249 | 8ecc7913 | j_mayer | |
| 250 | 8ecc7913 | j_mayer | pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
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| 251 | 8ecc7913 | j_mayer | if (pob != NULL) { |
| 252 | 8ecc7913 | j_mayer | ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); |
| 253 | 8ecc7913 | j_mayer | ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); |
| 254 | 8ecc7913 | j_mayer | ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); |
| 255 | 8ecc7913 | j_mayer | qemu_register_reset(ppc4xx_pob_reset, pob); |
| 256 | 8ecc7913 | j_mayer | ppc4xx_pob_reset(env); |
| 257 | 8ecc7913 | j_mayer | } |
| 258 | 8ecc7913 | j_mayer | } |
| 259 | 8ecc7913 | j_mayer | |
| 260 | 8ecc7913 | j_mayer | /*****************************************************************************/
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| 261 | 8ecc7913 | j_mayer | /* OPB arbitrer */
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| 262 | 8ecc7913 | j_mayer | typedef struct ppc4xx_opba_t ppc4xx_opba_t; |
| 263 | 8ecc7913 | j_mayer | struct ppc4xx_opba_t {
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| 264 | 9c02f1a2 | j_mayer | target_phys_addr_t base; |
| 265 | 8ecc7913 | j_mayer | uint8_t cr; |
| 266 | 8ecc7913 | j_mayer | uint8_t pr; |
| 267 | 8ecc7913 | j_mayer | }; |
| 268 | 8ecc7913 | j_mayer | |
| 269 | 8ecc7913 | j_mayer | static uint32_t opba_readb (void *opaque, target_phys_addr_t addr) |
| 270 | 8ecc7913 | j_mayer | {
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| 271 | 8ecc7913 | j_mayer | ppc4xx_opba_t *opba; |
| 272 | 8ecc7913 | j_mayer | uint32_t ret; |
| 273 | 8ecc7913 | j_mayer | |
| 274 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
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| 275 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
| 276 | 8ecc7913 | j_mayer | #endif
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| 277 | 8ecc7913 | j_mayer | opba = opaque; |
| 278 | 8ecc7913 | j_mayer | switch (addr - opba->base) {
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| 279 | 8ecc7913 | j_mayer | case 0x00: |
| 280 | 8ecc7913 | j_mayer | ret = opba->cr; |
| 281 | 8ecc7913 | j_mayer | break;
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| 282 | 8ecc7913 | j_mayer | case 0x01: |
| 283 | 8ecc7913 | j_mayer | ret = opba->pr; |
| 284 | 8ecc7913 | j_mayer | break;
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| 285 | 8ecc7913 | j_mayer | default:
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| 286 | 8ecc7913 | j_mayer | ret = 0x00;
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| 287 | 8ecc7913 | j_mayer | break;
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| 288 | 8ecc7913 | j_mayer | } |
| 289 | 8ecc7913 | j_mayer | |
| 290 | 8ecc7913 | j_mayer | return ret;
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| 291 | 8ecc7913 | j_mayer | } |
| 292 | 8ecc7913 | j_mayer | |
| 293 | 8ecc7913 | j_mayer | static void opba_writeb (void *opaque, |
| 294 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
| 295 | 8ecc7913 | j_mayer | {
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| 296 | 8ecc7913 | j_mayer | ppc4xx_opba_t *opba; |
| 297 | 8ecc7913 | j_mayer | |
| 298 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
|
| 299 | aae9366a | j_mayer | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 300 | 8ecc7913 | j_mayer | #endif
|
| 301 | 8ecc7913 | j_mayer | opba = opaque; |
| 302 | 8ecc7913 | j_mayer | switch (addr - opba->base) {
|
| 303 | 8ecc7913 | j_mayer | case 0x00: |
| 304 | 8ecc7913 | j_mayer | opba->cr = value & 0xF8;
|
| 305 | 8ecc7913 | j_mayer | break;
|
| 306 | 8ecc7913 | j_mayer | case 0x01: |
| 307 | 8ecc7913 | j_mayer | opba->pr = value & 0xFF;
|
| 308 | 8ecc7913 | j_mayer | break;
|
| 309 | 8ecc7913 | j_mayer | default:
|
| 310 | 8ecc7913 | j_mayer | break;
|
| 311 | 8ecc7913 | j_mayer | } |
| 312 | 8ecc7913 | j_mayer | } |
| 313 | 8ecc7913 | j_mayer | |
| 314 | 8ecc7913 | j_mayer | static uint32_t opba_readw (void *opaque, target_phys_addr_t addr) |
| 315 | 8ecc7913 | j_mayer | {
|
| 316 | 8ecc7913 | j_mayer | uint32_t ret; |
| 317 | 8ecc7913 | j_mayer | |
| 318 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
|
| 319 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
| 320 | 8ecc7913 | j_mayer | #endif
|
| 321 | 8ecc7913 | j_mayer | ret = opba_readb(opaque, addr) << 8;
|
| 322 | 8ecc7913 | j_mayer | ret |= opba_readb(opaque, addr + 1);
|
| 323 | 8ecc7913 | j_mayer | |
| 324 | 8ecc7913 | j_mayer | return ret;
|
| 325 | 8ecc7913 | j_mayer | } |
| 326 | 8ecc7913 | j_mayer | |
| 327 | 8ecc7913 | j_mayer | static void opba_writew (void *opaque, |
| 328 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
| 329 | 8ecc7913 | j_mayer | {
|
| 330 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
|
| 331 | aae9366a | j_mayer | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 332 | 8ecc7913 | j_mayer | #endif
|
| 333 | 8ecc7913 | j_mayer | opba_writeb(opaque, addr, value >> 8);
|
| 334 | 8ecc7913 | j_mayer | opba_writeb(opaque, addr + 1, value);
|
| 335 | 8ecc7913 | j_mayer | } |
| 336 | 8ecc7913 | j_mayer | |
| 337 | 8ecc7913 | j_mayer | static uint32_t opba_readl (void *opaque, target_phys_addr_t addr) |
| 338 | 8ecc7913 | j_mayer | {
|
| 339 | 8ecc7913 | j_mayer | uint32_t ret; |
| 340 | 8ecc7913 | j_mayer | |
| 341 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
|
| 342 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
| 343 | 8ecc7913 | j_mayer | #endif
|
| 344 | 8ecc7913 | j_mayer | ret = opba_readb(opaque, addr) << 24;
|
| 345 | 8ecc7913 | j_mayer | ret |= opba_readb(opaque, addr + 1) << 16; |
| 346 | 8ecc7913 | j_mayer | |
| 347 | 8ecc7913 | j_mayer | return ret;
|
| 348 | 8ecc7913 | j_mayer | } |
| 349 | 8ecc7913 | j_mayer | |
| 350 | 8ecc7913 | j_mayer | static void opba_writel (void *opaque, |
| 351 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
| 352 | 8ecc7913 | j_mayer | {
|
| 353 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
|
| 354 | aae9366a | j_mayer | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 355 | 8ecc7913 | j_mayer | #endif
|
| 356 | 8ecc7913 | j_mayer | opba_writeb(opaque, addr, value >> 24);
|
| 357 | 8ecc7913 | j_mayer | opba_writeb(opaque, addr + 1, value >> 16); |
| 358 | 8ecc7913 | j_mayer | } |
| 359 | 8ecc7913 | j_mayer | |
| 360 | 8ecc7913 | j_mayer | static CPUReadMemoryFunc *opba_read[] = {
|
| 361 | 8ecc7913 | j_mayer | &opba_readb, |
| 362 | 8ecc7913 | j_mayer | &opba_readw, |
| 363 | 8ecc7913 | j_mayer | &opba_readl, |
| 364 | 8ecc7913 | j_mayer | }; |
| 365 | 8ecc7913 | j_mayer | |
| 366 | 8ecc7913 | j_mayer | static CPUWriteMemoryFunc *opba_write[] = {
|
| 367 | 8ecc7913 | j_mayer | &opba_writeb, |
| 368 | 8ecc7913 | j_mayer | &opba_writew, |
| 369 | 8ecc7913 | j_mayer | &opba_writel, |
| 370 | 8ecc7913 | j_mayer | }; |
| 371 | 8ecc7913 | j_mayer | |
| 372 | 8ecc7913 | j_mayer | static void ppc4xx_opba_reset (void *opaque) |
| 373 | 8ecc7913 | j_mayer | {
|
| 374 | 8ecc7913 | j_mayer | ppc4xx_opba_t *opba; |
| 375 | 8ecc7913 | j_mayer | |
| 376 | 8ecc7913 | j_mayer | opba = opaque; |
| 377 | 8ecc7913 | j_mayer | opba->cr = 0x00; /* No dynamic priorities - park disabled */ |
| 378 | 8ecc7913 | j_mayer | opba->pr = 0x11;
|
| 379 | 8ecc7913 | j_mayer | } |
| 380 | 8ecc7913 | j_mayer | |
| 381 | 9c02f1a2 | j_mayer | void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
| 382 | 9c02f1a2 | j_mayer | target_phys_addr_t offset) |
| 383 | 8ecc7913 | j_mayer | {
|
| 384 | 8ecc7913 | j_mayer | ppc4xx_opba_t *opba; |
| 385 | 8ecc7913 | j_mayer | |
| 386 | 8ecc7913 | j_mayer | opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
|
| 387 | 8ecc7913 | j_mayer | if (opba != NULL) { |
| 388 | 9c02f1a2 | j_mayer | opba->base = offset; |
| 389 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
|
| 390 | aae9366a | j_mayer | printf("%s: offset " PADDRX "\n", __func__, offset); |
| 391 | 8ecc7913 | j_mayer | #endif
|
| 392 | 8ecc7913 | j_mayer | ppc4xx_mmio_register(env, mmio, offset, 0x002,
|
| 393 | 8ecc7913 | j_mayer | opba_read, opba_write, opba); |
| 394 | 8ecc7913 | j_mayer | qemu_register_reset(ppc4xx_opba_reset, opba); |
| 395 | 8ecc7913 | j_mayer | ppc4xx_opba_reset(opba); |
| 396 | 8ecc7913 | j_mayer | } |
| 397 | 8ecc7913 | j_mayer | } |
| 398 | 8ecc7913 | j_mayer | |
| 399 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
| 400 | 8ecc7913 | j_mayer | /* Code decompression controller */
|
| 401 | 8ecc7913 | j_mayer | /* XXX: TODO */
|
| 402 | 8ecc7913 | j_mayer | |
| 403 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
| 404 | 8ecc7913 | j_mayer | /* Peripheral controller */
|
| 405 | 8ecc7913 | j_mayer | typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; |
| 406 | 8ecc7913 | j_mayer | struct ppc4xx_ebc_t {
|
| 407 | 8ecc7913 | j_mayer | uint32_t addr; |
| 408 | 8ecc7913 | j_mayer | uint32_t bcr[8];
|
| 409 | 8ecc7913 | j_mayer | uint32_t bap[8];
|
| 410 | 8ecc7913 | j_mayer | uint32_t bear; |
| 411 | 8ecc7913 | j_mayer | uint32_t besr0; |
| 412 | 8ecc7913 | j_mayer | uint32_t besr1; |
| 413 | 8ecc7913 | j_mayer | uint32_t cfg; |
| 414 | 8ecc7913 | j_mayer | }; |
| 415 | 8ecc7913 | j_mayer | |
| 416 | 8ecc7913 | j_mayer | enum {
|
| 417 | 8ecc7913 | j_mayer | EBC0_CFGADDR = 0x012,
|
| 418 | 8ecc7913 | j_mayer | EBC0_CFGDATA = 0x013,
|
| 419 | 8ecc7913 | j_mayer | }; |
| 420 | 8ecc7913 | j_mayer | |
| 421 | 8ecc7913 | j_mayer | static target_ulong dcr_read_ebc (void *opaque, int dcrn) |
| 422 | 8ecc7913 | j_mayer | {
|
| 423 | 8ecc7913 | j_mayer | ppc4xx_ebc_t *ebc; |
| 424 | 8ecc7913 | j_mayer | target_ulong ret; |
| 425 | 8ecc7913 | j_mayer | |
| 426 | 8ecc7913 | j_mayer | ebc = opaque; |
| 427 | 8ecc7913 | j_mayer | switch (dcrn) {
|
| 428 | 8ecc7913 | j_mayer | case EBC0_CFGADDR:
|
| 429 | 8ecc7913 | j_mayer | ret = ebc->addr; |
| 430 | 8ecc7913 | j_mayer | break;
|
| 431 | 8ecc7913 | j_mayer | case EBC0_CFGDATA:
|
| 432 | 8ecc7913 | j_mayer | switch (ebc->addr) {
|
| 433 | 8ecc7913 | j_mayer | case 0x00: /* B0CR */ |
| 434 | 8ecc7913 | j_mayer | ret = ebc->bcr[0];
|
| 435 | 8ecc7913 | j_mayer | break;
|
| 436 | 8ecc7913 | j_mayer | case 0x01: /* B1CR */ |
| 437 | 8ecc7913 | j_mayer | ret = ebc->bcr[1];
|
| 438 | 8ecc7913 | j_mayer | break;
|
| 439 | 8ecc7913 | j_mayer | case 0x02: /* B2CR */ |
| 440 | 8ecc7913 | j_mayer | ret = ebc->bcr[2];
|
| 441 | 8ecc7913 | j_mayer | break;
|
| 442 | 8ecc7913 | j_mayer | case 0x03: /* B3CR */ |
| 443 | 8ecc7913 | j_mayer | ret = ebc->bcr[3];
|
| 444 | 8ecc7913 | j_mayer | break;
|
| 445 | 8ecc7913 | j_mayer | case 0x04: /* B4CR */ |
| 446 | 8ecc7913 | j_mayer | ret = ebc->bcr[4];
|
| 447 | 8ecc7913 | j_mayer | break;
|
| 448 | 8ecc7913 | j_mayer | case 0x05: /* B5CR */ |
| 449 | 8ecc7913 | j_mayer | ret = ebc->bcr[5];
|
| 450 | 8ecc7913 | j_mayer | break;
|
| 451 | 8ecc7913 | j_mayer | case 0x06: /* B6CR */ |
| 452 | 8ecc7913 | j_mayer | ret = ebc->bcr[6];
|
| 453 | 8ecc7913 | j_mayer | break;
|
| 454 | 8ecc7913 | j_mayer | case 0x07: /* B7CR */ |
| 455 | 8ecc7913 | j_mayer | ret = ebc->bcr[7];
|
| 456 | 8ecc7913 | j_mayer | break;
|
| 457 | 8ecc7913 | j_mayer | case 0x10: /* B0AP */ |
| 458 | 8ecc7913 | j_mayer | ret = ebc->bap[0];
|
| 459 | 8ecc7913 | j_mayer | break;
|
| 460 | 8ecc7913 | j_mayer | case 0x11: /* B1AP */ |
| 461 | 8ecc7913 | j_mayer | ret = ebc->bap[1];
|
| 462 | 8ecc7913 | j_mayer | break;
|
| 463 | 8ecc7913 | j_mayer | case 0x12: /* B2AP */ |
| 464 | 8ecc7913 | j_mayer | ret = ebc->bap[2];
|
| 465 | 8ecc7913 | j_mayer | break;
|
| 466 | 8ecc7913 | j_mayer | case 0x13: /* B3AP */ |
| 467 | 8ecc7913 | j_mayer | ret = ebc->bap[3];
|
| 468 | 8ecc7913 | j_mayer | break;
|
| 469 | 8ecc7913 | j_mayer | case 0x14: /* B4AP */ |
| 470 | 8ecc7913 | j_mayer | ret = ebc->bap[4];
|
| 471 | 8ecc7913 | j_mayer | break;
|
| 472 | 8ecc7913 | j_mayer | case 0x15: /* B5AP */ |
| 473 | 8ecc7913 | j_mayer | ret = ebc->bap[5];
|
| 474 | 8ecc7913 | j_mayer | break;
|
| 475 | 8ecc7913 | j_mayer | case 0x16: /* B6AP */ |
| 476 | 8ecc7913 | j_mayer | ret = ebc->bap[6];
|
| 477 | 8ecc7913 | j_mayer | break;
|
| 478 | 8ecc7913 | j_mayer | case 0x17: /* B7AP */ |
| 479 | 8ecc7913 | j_mayer | ret = ebc->bap[7];
|
| 480 | 8ecc7913 | j_mayer | break;
|
| 481 | 8ecc7913 | j_mayer | case 0x20: /* BEAR */ |
| 482 | 8ecc7913 | j_mayer | ret = ebc->bear; |
| 483 | 8ecc7913 | j_mayer | break;
|
| 484 | 8ecc7913 | j_mayer | case 0x21: /* BESR0 */ |
| 485 | 8ecc7913 | j_mayer | ret = ebc->besr0; |
| 486 | 8ecc7913 | j_mayer | break;
|
| 487 | 8ecc7913 | j_mayer | case 0x22: /* BESR1 */ |
| 488 | 8ecc7913 | j_mayer | ret = ebc->besr1; |
| 489 | 8ecc7913 | j_mayer | break;
|
| 490 | 8ecc7913 | j_mayer | case 0x23: /* CFG */ |
| 491 | 8ecc7913 | j_mayer | ret = ebc->cfg; |
| 492 | 8ecc7913 | j_mayer | break;
|
| 493 | 8ecc7913 | j_mayer | default:
|
| 494 | 8ecc7913 | j_mayer | ret = 0x00000000;
|
| 495 | 8ecc7913 | j_mayer | break;
|
| 496 | 8ecc7913 | j_mayer | } |
| 497 | 8ecc7913 | j_mayer | default:
|
| 498 | 8ecc7913 | j_mayer | ret = 0x00000000;
|
| 499 | 8ecc7913 | j_mayer | break;
|
| 500 | 8ecc7913 | j_mayer | } |
| 501 | 8ecc7913 | j_mayer | |
| 502 | 8ecc7913 | j_mayer | return ret;
|
| 503 | 8ecc7913 | j_mayer | } |
| 504 | 8ecc7913 | j_mayer | |
| 505 | 8ecc7913 | j_mayer | static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val) |
| 506 | 8ecc7913 | j_mayer | {
|
| 507 | 8ecc7913 | j_mayer | ppc4xx_ebc_t *ebc; |
| 508 | 8ecc7913 | j_mayer | |
| 509 | 8ecc7913 | j_mayer | ebc = opaque; |
| 510 | 8ecc7913 | j_mayer | switch (dcrn) {
|
| 511 | 8ecc7913 | j_mayer | case EBC0_CFGADDR:
|
| 512 | 8ecc7913 | j_mayer | ebc->addr = val; |
| 513 | 8ecc7913 | j_mayer | break;
|
| 514 | 8ecc7913 | j_mayer | case EBC0_CFGDATA:
|
| 515 | 8ecc7913 | j_mayer | switch (ebc->addr) {
|
| 516 | 8ecc7913 | j_mayer | case 0x00: /* B0CR */ |
| 517 | 8ecc7913 | j_mayer | break;
|
| 518 | 8ecc7913 | j_mayer | case 0x01: /* B1CR */ |
| 519 | 8ecc7913 | j_mayer | break;
|
| 520 | 8ecc7913 | j_mayer | case 0x02: /* B2CR */ |
| 521 | 8ecc7913 | j_mayer | break;
|
| 522 | 8ecc7913 | j_mayer | case 0x03: /* B3CR */ |
| 523 | 8ecc7913 | j_mayer | break;
|
| 524 | 8ecc7913 | j_mayer | case 0x04: /* B4CR */ |
| 525 | 8ecc7913 | j_mayer | break;
|
| 526 | 8ecc7913 | j_mayer | case 0x05: /* B5CR */ |
| 527 | 8ecc7913 | j_mayer | break;
|
| 528 | 8ecc7913 | j_mayer | case 0x06: /* B6CR */ |
| 529 | 8ecc7913 | j_mayer | break;
|
| 530 | 8ecc7913 | j_mayer | case 0x07: /* B7CR */ |
| 531 | 8ecc7913 | j_mayer | break;
|
| 532 | 8ecc7913 | j_mayer | case 0x10: /* B0AP */ |
| 533 | 8ecc7913 | j_mayer | break;
|
| 534 | 8ecc7913 | j_mayer | case 0x11: /* B1AP */ |
| 535 | 8ecc7913 | j_mayer | break;
|
| 536 | 8ecc7913 | j_mayer | case 0x12: /* B2AP */ |
| 537 | 8ecc7913 | j_mayer | break;
|
| 538 | 8ecc7913 | j_mayer | case 0x13: /* B3AP */ |
| 539 | 8ecc7913 | j_mayer | break;
|
| 540 | 8ecc7913 | j_mayer | case 0x14: /* B4AP */ |
| 541 | 8ecc7913 | j_mayer | break;
|
| 542 | 8ecc7913 | j_mayer | case 0x15: /* B5AP */ |
| 543 | 8ecc7913 | j_mayer | break;
|
| 544 | 8ecc7913 | j_mayer | case 0x16: /* B6AP */ |
| 545 | 8ecc7913 | j_mayer | break;
|
| 546 | 8ecc7913 | j_mayer | case 0x17: /* B7AP */ |
| 547 | 8ecc7913 | j_mayer | break;
|
| 548 | 8ecc7913 | j_mayer | case 0x20: /* BEAR */ |
| 549 | 8ecc7913 | j_mayer | break;
|
| 550 | 8ecc7913 | j_mayer | case 0x21: /* BESR0 */ |
| 551 | 8ecc7913 | j_mayer | break;
|
| 552 | 8ecc7913 | j_mayer | case 0x22: /* BESR1 */ |
| 553 | 8ecc7913 | j_mayer | break;
|
| 554 | 8ecc7913 | j_mayer | case 0x23: /* CFG */ |
| 555 | 8ecc7913 | j_mayer | break;
|
| 556 | 8ecc7913 | j_mayer | default:
|
| 557 | 8ecc7913 | j_mayer | break;
|
| 558 | 8ecc7913 | j_mayer | } |
| 559 | 8ecc7913 | j_mayer | break;
|
| 560 | 8ecc7913 | j_mayer | default:
|
| 561 | 8ecc7913 | j_mayer | break;
|
| 562 | 8ecc7913 | j_mayer | } |
| 563 | 8ecc7913 | j_mayer | } |
| 564 | 8ecc7913 | j_mayer | |
| 565 | 8ecc7913 | j_mayer | static void ebc_reset (void *opaque) |
| 566 | 8ecc7913 | j_mayer | {
|
| 567 | 8ecc7913 | j_mayer | ppc4xx_ebc_t *ebc; |
| 568 | 8ecc7913 | j_mayer | int i;
|
| 569 | 8ecc7913 | j_mayer | |
| 570 | 8ecc7913 | j_mayer | ebc = opaque; |
| 571 | 8ecc7913 | j_mayer | ebc->addr = 0x00000000;
|
| 572 | 8ecc7913 | j_mayer | ebc->bap[0] = 0x7F8FFE80; |
| 573 | 8ecc7913 | j_mayer | ebc->bcr[0] = 0xFFE28000; |
| 574 | 8ecc7913 | j_mayer | for (i = 0; i < 8; i++) { |
| 575 | 8ecc7913 | j_mayer | ebc->bap[i] = 0x00000000;
|
| 576 | 8ecc7913 | j_mayer | ebc->bcr[i] = 0x00000000;
|
| 577 | 8ecc7913 | j_mayer | } |
| 578 | 8ecc7913 | j_mayer | ebc->besr0 = 0x00000000;
|
| 579 | 8ecc7913 | j_mayer | ebc->besr1 = 0x00000000;
|
| 580 | 9c02f1a2 | j_mayer | ebc->cfg = 0x80400000;
|
| 581 | 8ecc7913 | j_mayer | } |
| 582 | 8ecc7913 | j_mayer | |
| 583 | 8ecc7913 | j_mayer | void ppc405_ebc_init (CPUState *env)
|
| 584 | 8ecc7913 | j_mayer | {
|
| 585 | 8ecc7913 | j_mayer | ppc4xx_ebc_t *ebc; |
| 586 | 8ecc7913 | j_mayer | |
| 587 | 8ecc7913 | j_mayer | ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
|
| 588 | 8ecc7913 | j_mayer | if (ebc != NULL) { |
| 589 | 8ecc7913 | j_mayer | ebc_reset(ebc); |
| 590 | 8ecc7913 | j_mayer | qemu_register_reset(&ebc_reset, ebc); |
| 591 | 8ecc7913 | j_mayer | ppc_dcr_register(env, EBC0_CFGADDR, |
| 592 | 8ecc7913 | j_mayer | ebc, &dcr_read_ebc, &dcr_write_ebc); |
| 593 | 8ecc7913 | j_mayer | ppc_dcr_register(env, EBC0_CFGDATA, |
| 594 | 8ecc7913 | j_mayer | ebc, &dcr_read_ebc, &dcr_write_ebc); |
| 595 | 8ecc7913 | j_mayer | } |
| 596 | 8ecc7913 | j_mayer | } |
| 597 | 8ecc7913 | j_mayer | |
| 598 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
| 599 | 8ecc7913 | j_mayer | /* DMA controller */
|
| 600 | 8ecc7913 | j_mayer | enum {
|
| 601 | 8ecc7913 | j_mayer | DMA0_CR0 = 0x100,
|
| 602 | 8ecc7913 | j_mayer | DMA0_CT0 = 0x101,
|
| 603 | 8ecc7913 | j_mayer | DMA0_DA0 = 0x102,
|
| 604 | 8ecc7913 | j_mayer | DMA0_SA0 = 0x103,
|
| 605 | 8ecc7913 | j_mayer | DMA0_SG0 = 0x104,
|
| 606 | 8ecc7913 | j_mayer | DMA0_CR1 = 0x108,
|
| 607 | 8ecc7913 | j_mayer | DMA0_CT1 = 0x109,
|
| 608 | 8ecc7913 | j_mayer | DMA0_DA1 = 0x10A,
|
| 609 | 8ecc7913 | j_mayer | DMA0_SA1 = 0x10B,
|
| 610 | 8ecc7913 | j_mayer | DMA0_SG1 = 0x10C,
|
| 611 | 8ecc7913 | j_mayer | DMA0_CR2 = 0x110,
|
| 612 | 8ecc7913 | j_mayer | DMA0_CT2 = 0x111,
|
| 613 | 8ecc7913 | j_mayer | DMA0_DA2 = 0x112,
|
| 614 | 8ecc7913 | j_mayer | DMA0_SA2 = 0x113,
|
| 615 | 8ecc7913 | j_mayer | DMA0_SG2 = 0x114,
|
| 616 | 8ecc7913 | j_mayer | DMA0_CR3 = 0x118,
|
| 617 | 8ecc7913 | j_mayer | DMA0_CT3 = 0x119,
|
| 618 | 8ecc7913 | j_mayer | DMA0_DA3 = 0x11A,
|
| 619 | 8ecc7913 | j_mayer | DMA0_SA3 = 0x11B,
|
| 620 | 8ecc7913 | j_mayer | DMA0_SG3 = 0x11C,
|
| 621 | 8ecc7913 | j_mayer | DMA0_SR = 0x120,
|
| 622 | 8ecc7913 | j_mayer | DMA0_SGC = 0x123,
|
| 623 | 8ecc7913 | j_mayer | DMA0_SLP = 0x125,
|
| 624 | 8ecc7913 | j_mayer | DMA0_POL = 0x126,
|
| 625 | 8ecc7913 | j_mayer | }; |
| 626 | 8ecc7913 | j_mayer | |
| 627 | 8ecc7913 | j_mayer | typedef struct ppc405_dma_t ppc405_dma_t; |
| 628 | 8ecc7913 | j_mayer | struct ppc405_dma_t {
|
| 629 | 8ecc7913 | j_mayer | qemu_irq irqs[4];
|
| 630 | 8ecc7913 | j_mayer | uint32_t cr[4];
|
| 631 | 8ecc7913 | j_mayer | uint32_t ct[4];
|
| 632 | 8ecc7913 | j_mayer | uint32_t da[4];
|
| 633 | 8ecc7913 | j_mayer | uint32_t sa[4];
|
| 634 | 8ecc7913 | j_mayer | uint32_t sg[4];
|
| 635 | 8ecc7913 | j_mayer | uint32_t sr; |
| 636 | 8ecc7913 | j_mayer | uint32_t sgc; |
| 637 | 8ecc7913 | j_mayer | uint32_t slp; |
| 638 | 8ecc7913 | j_mayer | uint32_t pol; |
| 639 | 8ecc7913 | j_mayer | }; |
| 640 | 8ecc7913 | j_mayer | |
| 641 | 8ecc7913 | j_mayer | static target_ulong dcr_read_dma (void *opaque, int dcrn) |
| 642 | 8ecc7913 | j_mayer | {
|
| 643 | 8ecc7913 | j_mayer | ppc405_dma_t *dma; |
| 644 | 8ecc7913 | j_mayer | |
| 645 | 8ecc7913 | j_mayer | dma = opaque; |
| 646 | 8ecc7913 | j_mayer | |
| 647 | 8ecc7913 | j_mayer | return 0; |
| 648 | 8ecc7913 | j_mayer | } |
| 649 | 8ecc7913 | j_mayer | |
| 650 | 8ecc7913 | j_mayer | static void dcr_write_dma (void *opaque, int dcrn, target_ulong val) |
| 651 | 8ecc7913 | j_mayer | {
|
| 652 | 8ecc7913 | j_mayer | ppc405_dma_t *dma; |
| 653 | 8ecc7913 | j_mayer | |
| 654 | 8ecc7913 | j_mayer | dma = opaque; |
| 655 | 8ecc7913 | j_mayer | } |
| 656 | 8ecc7913 | j_mayer | |
| 657 | 8ecc7913 | j_mayer | static void ppc405_dma_reset (void *opaque) |
| 658 | 8ecc7913 | j_mayer | {
|
| 659 | 8ecc7913 | j_mayer | ppc405_dma_t *dma; |
| 660 | 8ecc7913 | j_mayer | int i;
|
| 661 | 8ecc7913 | j_mayer | |
| 662 | 8ecc7913 | j_mayer | dma = opaque; |
| 663 | 8ecc7913 | j_mayer | for (i = 0; i < 4; i++) { |
| 664 | 8ecc7913 | j_mayer | dma->cr[i] = 0x00000000;
|
| 665 | 8ecc7913 | j_mayer | dma->ct[i] = 0x00000000;
|
| 666 | 8ecc7913 | j_mayer | dma->da[i] = 0x00000000;
|
| 667 | 8ecc7913 | j_mayer | dma->sa[i] = 0x00000000;
|
| 668 | 8ecc7913 | j_mayer | dma->sg[i] = 0x00000000;
|
| 669 | 8ecc7913 | j_mayer | } |
| 670 | 8ecc7913 | j_mayer | dma->sr = 0x00000000;
|
| 671 | 8ecc7913 | j_mayer | dma->sgc = 0x00000000;
|
| 672 | 8ecc7913 | j_mayer | dma->slp = 0x7C000000;
|
| 673 | 8ecc7913 | j_mayer | dma->pol = 0x00000000;
|
| 674 | 8ecc7913 | j_mayer | } |
| 675 | 8ecc7913 | j_mayer | |
| 676 | 8ecc7913 | j_mayer | void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]) |
| 677 | 8ecc7913 | j_mayer | {
|
| 678 | 8ecc7913 | j_mayer | ppc405_dma_t *dma; |
| 679 | 8ecc7913 | j_mayer | |
| 680 | 8ecc7913 | j_mayer | dma = qemu_mallocz(sizeof(ppc405_dma_t));
|
| 681 | 8ecc7913 | j_mayer | if (dma != NULL) { |
| 682 | 8ecc7913 | j_mayer | memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); |
| 683 | 8ecc7913 | j_mayer | ppc405_dma_reset(dma); |
| 684 | 8ecc7913 | j_mayer | qemu_register_reset(&ppc405_dma_reset, dma); |
| 685 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_CR0, |
| 686 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 687 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_CT0, |
| 688 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 689 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_DA0, |
| 690 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 691 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SA0, |
| 692 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 693 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SG0, |
| 694 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 695 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_CR1, |
| 696 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 697 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_CT1, |
| 698 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 699 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_DA1, |
| 700 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 701 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SA1, |
| 702 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 703 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SG1, |
| 704 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 705 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_CR2, |
| 706 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 707 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_CT2, |
| 708 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 709 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_DA2, |
| 710 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 711 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SA2, |
| 712 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 713 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SG2, |
| 714 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 715 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_CR3, |
| 716 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 717 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_CT3, |
| 718 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 719 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_DA3, |
| 720 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 721 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SA3, |
| 722 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 723 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SG3, |
| 724 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 725 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SR, |
| 726 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 727 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SGC, |
| 728 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 729 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SLP, |
| 730 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 731 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_POL, |
| 732 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
| 733 | 8ecc7913 | j_mayer | } |
| 734 | 8ecc7913 | j_mayer | } |
| 735 | 8ecc7913 | j_mayer | |
| 736 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
| 737 | 8ecc7913 | j_mayer | /* GPIO */
|
| 738 | 8ecc7913 | j_mayer | typedef struct ppc405_gpio_t ppc405_gpio_t; |
| 739 | 8ecc7913 | j_mayer | struct ppc405_gpio_t {
|
| 740 | 9c02f1a2 | j_mayer | target_phys_addr_t base; |
| 741 | 8ecc7913 | j_mayer | uint32_t or; |
| 742 | 8ecc7913 | j_mayer | uint32_t tcr; |
| 743 | 8ecc7913 | j_mayer | uint32_t osrh; |
| 744 | 8ecc7913 | j_mayer | uint32_t osrl; |
| 745 | 8ecc7913 | j_mayer | uint32_t tsrh; |
| 746 | 8ecc7913 | j_mayer | uint32_t tsrl; |
| 747 | 8ecc7913 | j_mayer | uint32_t odr; |
| 748 | 8ecc7913 | j_mayer | uint32_t ir; |
| 749 | 8ecc7913 | j_mayer | uint32_t rr1; |
| 750 | 8ecc7913 | j_mayer | uint32_t isr1h; |
| 751 | 8ecc7913 | j_mayer | uint32_t isr1l; |
| 752 | 8ecc7913 | j_mayer | }; |
| 753 | 8ecc7913 | j_mayer | |
| 754 | 8ecc7913 | j_mayer | static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr) |
| 755 | 8ecc7913 | j_mayer | {
|
| 756 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
| 757 | 8ecc7913 | j_mayer | |
| 758 | 8ecc7913 | j_mayer | gpio = opaque; |
| 759 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
| 760 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
| 761 | 8ecc7913 | j_mayer | #endif
|
| 762 | 8ecc7913 | j_mayer | |
| 763 | 8ecc7913 | j_mayer | return 0; |
| 764 | 8ecc7913 | j_mayer | } |
| 765 | 8ecc7913 | j_mayer | |
| 766 | 8ecc7913 | j_mayer | static void ppc405_gpio_writeb (void *opaque, |
| 767 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
| 768 | 8ecc7913 | j_mayer | {
|
| 769 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
| 770 | 8ecc7913 | j_mayer | |
| 771 | 8ecc7913 | j_mayer | gpio = opaque; |
| 772 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
| 773 | aae9366a | j_mayer | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 774 | 8ecc7913 | j_mayer | #endif
|
| 775 | 8ecc7913 | j_mayer | } |
| 776 | 8ecc7913 | j_mayer | |
| 777 | 8ecc7913 | j_mayer | static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr) |
| 778 | 8ecc7913 | j_mayer | {
|
| 779 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
| 780 | 8ecc7913 | j_mayer | |
| 781 | 8ecc7913 | j_mayer | gpio = opaque; |
| 782 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
| 783 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
| 784 | 8ecc7913 | j_mayer | #endif
|
| 785 | 8ecc7913 | j_mayer | |
| 786 | 8ecc7913 | j_mayer | return 0; |
| 787 | 8ecc7913 | j_mayer | } |
| 788 | 8ecc7913 | j_mayer | |
| 789 | 8ecc7913 | j_mayer | static void ppc405_gpio_writew (void *opaque, |
| 790 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
| 791 | 8ecc7913 | j_mayer | {
|
| 792 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
| 793 | 8ecc7913 | j_mayer | |
| 794 | 8ecc7913 | j_mayer | gpio = opaque; |
| 795 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
| 796 | aae9366a | j_mayer | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 797 | 8ecc7913 | j_mayer | #endif
|
| 798 | 8ecc7913 | j_mayer | } |
| 799 | 8ecc7913 | j_mayer | |
| 800 | 8ecc7913 | j_mayer | static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr) |
| 801 | 8ecc7913 | j_mayer | {
|
| 802 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
| 803 | 8ecc7913 | j_mayer | |
| 804 | 8ecc7913 | j_mayer | gpio = opaque; |
| 805 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
| 806 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
| 807 | 8ecc7913 | j_mayer | #endif
|
| 808 | 8ecc7913 | j_mayer | |
| 809 | 8ecc7913 | j_mayer | return 0; |
| 810 | 8ecc7913 | j_mayer | } |
| 811 | 8ecc7913 | j_mayer | |
| 812 | 8ecc7913 | j_mayer | static void ppc405_gpio_writel (void *opaque, |
| 813 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
| 814 | 8ecc7913 | j_mayer | {
|
| 815 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
| 816 | 8ecc7913 | j_mayer | |
| 817 | 8ecc7913 | j_mayer | gpio = opaque; |
| 818 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
| 819 | aae9366a | j_mayer | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 820 | 8ecc7913 | j_mayer | #endif
|
| 821 | 8ecc7913 | j_mayer | } |
| 822 | 8ecc7913 | j_mayer | |
| 823 | 8ecc7913 | j_mayer | static CPUReadMemoryFunc *ppc405_gpio_read[] = {
|
| 824 | 8ecc7913 | j_mayer | &ppc405_gpio_readb, |
| 825 | 8ecc7913 | j_mayer | &ppc405_gpio_readw, |
| 826 | 8ecc7913 | j_mayer | &ppc405_gpio_readl, |
| 827 | 8ecc7913 | j_mayer | }; |
| 828 | 8ecc7913 | j_mayer | |
| 829 | 8ecc7913 | j_mayer | static CPUWriteMemoryFunc *ppc405_gpio_write[] = {
|
| 830 | 8ecc7913 | j_mayer | &ppc405_gpio_writeb, |
| 831 | 8ecc7913 | j_mayer | &ppc405_gpio_writew, |
| 832 | 8ecc7913 | j_mayer | &ppc405_gpio_writel, |
| 833 | 8ecc7913 | j_mayer | }; |
| 834 | 8ecc7913 | j_mayer | |
| 835 | 8ecc7913 | j_mayer | static void ppc405_gpio_reset (void *opaque) |
| 836 | 8ecc7913 | j_mayer | {
|
| 837 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
| 838 | 8ecc7913 | j_mayer | |
| 839 | 8ecc7913 | j_mayer | gpio = opaque; |
| 840 | 8ecc7913 | j_mayer | } |
| 841 | 8ecc7913 | j_mayer | |
| 842 | 9c02f1a2 | j_mayer | void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
| 843 | 9c02f1a2 | j_mayer | target_phys_addr_t offset) |
| 844 | 8ecc7913 | j_mayer | {
|
| 845 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
| 846 | 8ecc7913 | j_mayer | |
| 847 | 8ecc7913 | j_mayer | gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
|
| 848 | 8ecc7913 | j_mayer | if (gpio != NULL) { |
| 849 | 9c02f1a2 | j_mayer | gpio->base = offset; |
| 850 | 8ecc7913 | j_mayer | ppc405_gpio_reset(gpio); |
| 851 | 8ecc7913 | j_mayer | qemu_register_reset(&ppc405_gpio_reset, gpio); |
| 852 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
| 853 | aae9366a | j_mayer | printf("%s: offset " PADDRX "\n", __func__, offset); |
| 854 | 8ecc7913 | j_mayer | #endif
|
| 855 | 8ecc7913 | j_mayer | ppc4xx_mmio_register(env, mmio, offset, 0x038,
|
| 856 | 8ecc7913 | j_mayer | ppc405_gpio_read, ppc405_gpio_write, gpio); |
| 857 | 8ecc7913 | j_mayer | } |
| 858 | 8ecc7913 | j_mayer | } |
| 859 | 8ecc7913 | j_mayer | |
| 860 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
| 861 | 8ecc7913 | j_mayer | /* Serial ports */
|
| 862 | 8ecc7913 | j_mayer | static CPUReadMemoryFunc *serial_mm_read[] = {
|
| 863 | 8ecc7913 | j_mayer | &serial_mm_readb, |
| 864 | 8ecc7913 | j_mayer | &serial_mm_readw, |
| 865 | 8ecc7913 | j_mayer | &serial_mm_readl, |
| 866 | 8ecc7913 | j_mayer | }; |
| 867 | 8ecc7913 | j_mayer | |
| 868 | 8ecc7913 | j_mayer | static CPUWriteMemoryFunc *serial_mm_write[] = {
|
| 869 | 8ecc7913 | j_mayer | &serial_mm_writeb, |
| 870 | 8ecc7913 | j_mayer | &serial_mm_writew, |
| 871 | 8ecc7913 | j_mayer | &serial_mm_writel, |
| 872 | 8ecc7913 | j_mayer | }; |
| 873 | 8ecc7913 | j_mayer | |
| 874 | 8ecc7913 | j_mayer | void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
| 875 | 9c02f1a2 | j_mayer | target_phys_addr_t offset, qemu_irq irq, |
| 876 | 8ecc7913 | j_mayer | CharDriverState *chr) |
| 877 | 8ecc7913 | j_mayer | {
|
| 878 | 8ecc7913 | j_mayer | void *serial;
|
| 879 | 8ecc7913 | j_mayer | |
| 880 | 8ecc7913 | j_mayer | #ifdef DEBUG_SERIAL
|
| 881 | aae9366a | j_mayer | printf("%s: offset " PADDRX "\n", __func__, offset); |
| 882 | 8ecc7913 | j_mayer | #endif
|
| 883 | b6cd0ea1 | aurel32 | serial = serial_mm_init(offset, 0, irq, 399193, chr, 0); |
| 884 | 8ecc7913 | j_mayer | ppc4xx_mmio_register(env, mmio, offset, 0x008,
|
| 885 | 8ecc7913 | j_mayer | serial_mm_read, serial_mm_write, serial); |
| 886 | 8ecc7913 | j_mayer | } |
| 887 | 8ecc7913 | j_mayer | |
| 888 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
| 889 | 8ecc7913 | j_mayer | /* On Chip Memory */
|
| 890 | 8ecc7913 | j_mayer | enum {
|
| 891 | 8ecc7913 | j_mayer | OCM0_ISARC = 0x018,
|
| 892 | 8ecc7913 | j_mayer | OCM0_ISACNTL = 0x019,
|
| 893 | 8ecc7913 | j_mayer | OCM0_DSARC = 0x01A,
|
| 894 | 8ecc7913 | j_mayer | OCM0_DSACNTL = 0x01B,
|
| 895 | 8ecc7913 | j_mayer | }; |
| 896 | 8ecc7913 | j_mayer | |
| 897 | 8ecc7913 | j_mayer | typedef struct ppc405_ocm_t ppc405_ocm_t; |
| 898 | 8ecc7913 | j_mayer | struct ppc405_ocm_t {
|
| 899 | 8ecc7913 | j_mayer | target_ulong offset; |
| 900 | 8ecc7913 | j_mayer | uint32_t isarc; |
| 901 | 8ecc7913 | j_mayer | uint32_t isacntl; |
| 902 | 8ecc7913 | j_mayer | uint32_t dsarc; |
| 903 | 8ecc7913 | j_mayer | uint32_t dsacntl; |
| 904 | 8ecc7913 | j_mayer | }; |
| 905 | 8ecc7913 | j_mayer | |
| 906 | 8ecc7913 | j_mayer | static void ocm_update_mappings (ppc405_ocm_t *ocm, |
| 907 | 8ecc7913 | j_mayer | uint32_t isarc, uint32_t isacntl, |
| 908 | 8ecc7913 | j_mayer | uint32_t dsarc, uint32_t dsacntl) |
| 909 | 8ecc7913 | j_mayer | {
|
| 910 | 8ecc7913 | j_mayer | #ifdef DEBUG_OCM
|
| 911 | aae9366a | j_mayer | printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32 |
| 912 | aae9366a | j_mayer | " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32 |
| 913 | aae9366a | j_mayer | " (%08" PRIx32 " %08" PRIx32 ")\n", |
| 914 | 8ecc7913 | j_mayer | isarc, isacntl, dsarc, dsacntl, |
| 915 | 8ecc7913 | j_mayer | ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); |
| 916 | 8ecc7913 | j_mayer | #endif
|
| 917 | 8ecc7913 | j_mayer | if (ocm->isarc != isarc ||
|
| 918 | 8ecc7913 | j_mayer | (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { |
| 919 | 8ecc7913 | j_mayer | if (ocm->isacntl & 0x80000000) { |
| 920 | 8ecc7913 | j_mayer | /* Unmap previously assigned memory region */
|
| 921 | aae9366a | j_mayer | printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); |
| 922 | 8ecc7913 | j_mayer | cpu_register_physical_memory(ocm->isarc, 0x04000000,
|
| 923 | 8ecc7913 | j_mayer | IO_MEM_UNASSIGNED); |
| 924 | 8ecc7913 | j_mayer | } |
| 925 | 8ecc7913 | j_mayer | if (isacntl & 0x80000000) { |
| 926 | 8ecc7913 | j_mayer | /* Map new instruction memory region */
|
| 927 | 8ecc7913 | j_mayer | #ifdef DEBUG_OCM
|
| 928 | aae9366a | j_mayer | printf("OCM map ISA %08" PRIx32 "\n", isarc); |
| 929 | 8ecc7913 | j_mayer | #endif
|
| 930 | 8ecc7913 | j_mayer | cpu_register_physical_memory(isarc, 0x04000000,
|
| 931 | 8ecc7913 | j_mayer | ocm->offset | IO_MEM_RAM); |
| 932 | 8ecc7913 | j_mayer | } |
| 933 | 8ecc7913 | j_mayer | } |
| 934 | 8ecc7913 | j_mayer | if (ocm->dsarc != dsarc ||
|
| 935 | 8ecc7913 | j_mayer | (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { |
| 936 | 8ecc7913 | j_mayer | if (ocm->dsacntl & 0x80000000) { |
| 937 | 8ecc7913 | j_mayer | /* Beware not to unmap the region we just mapped */
|
| 938 | 8ecc7913 | j_mayer | if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { |
| 939 | 8ecc7913 | j_mayer | /* Unmap previously assigned memory region */
|
| 940 | 8ecc7913 | j_mayer | #ifdef DEBUG_OCM
|
| 941 | aae9366a | j_mayer | printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); |
| 942 | 8ecc7913 | j_mayer | #endif
|
| 943 | 8ecc7913 | j_mayer | cpu_register_physical_memory(ocm->dsarc, 0x04000000,
|
| 944 | 8ecc7913 | j_mayer | IO_MEM_UNASSIGNED); |
| 945 | 8ecc7913 | j_mayer | } |
| 946 | 8ecc7913 | j_mayer | } |
| 947 | 8ecc7913 | j_mayer | if (dsacntl & 0x80000000) { |
| 948 | 8ecc7913 | j_mayer | /* Beware not to remap the region we just mapped */
|
| 949 | 8ecc7913 | j_mayer | if (!(isacntl & 0x80000000) || dsarc != isarc) { |
| 950 | 8ecc7913 | j_mayer | /* Map new data memory region */
|
| 951 | 8ecc7913 | j_mayer | #ifdef DEBUG_OCM
|
| 952 | aae9366a | j_mayer | printf("OCM map DSA %08" PRIx32 "\n", dsarc); |
| 953 | 8ecc7913 | j_mayer | #endif
|
| 954 | 8ecc7913 | j_mayer | cpu_register_physical_memory(dsarc, 0x04000000,
|
| 955 | 8ecc7913 | j_mayer | ocm->offset | IO_MEM_RAM); |
| 956 | 8ecc7913 | j_mayer | } |
| 957 | 8ecc7913 | j_mayer | } |
| 958 | 8ecc7913 | j_mayer | } |
| 959 | 8ecc7913 | j_mayer | } |
| 960 | 8ecc7913 | j_mayer | |
| 961 | 8ecc7913 | j_mayer | static target_ulong dcr_read_ocm (void *opaque, int dcrn) |
| 962 | 8ecc7913 | j_mayer | {
|
| 963 | 8ecc7913 | j_mayer | ppc405_ocm_t *ocm; |
| 964 | 8ecc7913 | j_mayer | target_ulong ret; |
| 965 | 8ecc7913 | j_mayer | |
| 966 | 8ecc7913 | j_mayer | ocm = opaque; |
| 967 | 8ecc7913 | j_mayer | switch (dcrn) {
|
| 968 | 8ecc7913 | j_mayer | case OCM0_ISARC:
|
| 969 | 8ecc7913 | j_mayer | ret = ocm->isarc; |
| 970 | 8ecc7913 | j_mayer | break;
|
| 971 | 8ecc7913 | j_mayer | case OCM0_ISACNTL:
|
| 972 | 8ecc7913 | j_mayer | ret = ocm->isacntl; |
| 973 | 8ecc7913 | j_mayer | break;
|
| 974 | 8ecc7913 | j_mayer | case OCM0_DSARC:
|
| 975 | 8ecc7913 | j_mayer | ret = ocm->dsarc; |
| 976 | 8ecc7913 | j_mayer | break;
|
| 977 | 8ecc7913 | j_mayer | case OCM0_DSACNTL:
|
| 978 | 8ecc7913 | j_mayer | ret = ocm->dsacntl; |
| 979 | 8ecc7913 | j_mayer | break;
|
| 980 | 8ecc7913 | j_mayer | default:
|
| 981 | 8ecc7913 | j_mayer | ret = 0;
|
| 982 | 8ecc7913 | j_mayer | break;
|
| 983 | 8ecc7913 | j_mayer | } |
| 984 | 8ecc7913 | j_mayer | |
| 985 | 8ecc7913 | j_mayer | return ret;
|
| 986 | 8ecc7913 | j_mayer | } |
| 987 | 8ecc7913 | j_mayer | |
| 988 | 8ecc7913 | j_mayer | static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val) |
| 989 | 8ecc7913 | j_mayer | {
|
| 990 | 8ecc7913 | j_mayer | ppc405_ocm_t *ocm; |
| 991 | 8ecc7913 | j_mayer | uint32_t isarc, dsarc, isacntl, dsacntl; |
| 992 | 8ecc7913 | j_mayer | |
| 993 | 8ecc7913 | j_mayer | ocm = opaque; |
| 994 | 8ecc7913 | j_mayer | isarc = ocm->isarc; |
| 995 | 8ecc7913 | j_mayer | dsarc = ocm->dsarc; |
| 996 | 8ecc7913 | j_mayer | isacntl = ocm->isacntl; |
| 997 | 8ecc7913 | j_mayer | dsacntl = ocm->dsacntl; |
| 998 | 8ecc7913 | j_mayer | switch (dcrn) {
|
| 999 | 8ecc7913 | j_mayer | case OCM0_ISARC:
|
| 1000 | 8ecc7913 | j_mayer | isarc = val & 0xFC000000;
|
| 1001 | 8ecc7913 | j_mayer | break;
|
| 1002 | 8ecc7913 | j_mayer | case OCM0_ISACNTL:
|
| 1003 | 8ecc7913 | j_mayer | isacntl = val & 0xC0000000;
|
| 1004 | 8ecc7913 | j_mayer | break;
|
| 1005 | 8ecc7913 | j_mayer | case OCM0_DSARC:
|
| 1006 | 8ecc7913 | j_mayer | isarc = val & 0xFC000000;
|
| 1007 | 8ecc7913 | j_mayer | break;
|
| 1008 | 8ecc7913 | j_mayer | case OCM0_DSACNTL:
|
| 1009 | 8ecc7913 | j_mayer | isacntl = val & 0xC0000000;
|
| 1010 | 8ecc7913 | j_mayer | break;
|
| 1011 | 8ecc7913 | j_mayer | } |
| 1012 | 8ecc7913 | j_mayer | ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); |
| 1013 | 8ecc7913 | j_mayer | ocm->isarc = isarc; |
| 1014 | 8ecc7913 | j_mayer | ocm->dsarc = dsarc; |
| 1015 | 8ecc7913 | j_mayer | ocm->isacntl = isacntl; |
| 1016 | 8ecc7913 | j_mayer | ocm->dsacntl = dsacntl; |
| 1017 | 8ecc7913 | j_mayer | } |
| 1018 | 8ecc7913 | j_mayer | |
| 1019 | 8ecc7913 | j_mayer | static void ocm_reset (void *opaque) |
| 1020 | 8ecc7913 | j_mayer | {
|
| 1021 | 8ecc7913 | j_mayer | ppc405_ocm_t *ocm; |
| 1022 | 8ecc7913 | j_mayer | uint32_t isarc, dsarc, isacntl, dsacntl; |
| 1023 | 8ecc7913 | j_mayer | |
| 1024 | 8ecc7913 | j_mayer | ocm = opaque; |
| 1025 | 8ecc7913 | j_mayer | isarc = 0x00000000;
|
| 1026 | 8ecc7913 | j_mayer | isacntl = 0x00000000;
|
| 1027 | 8ecc7913 | j_mayer | dsarc = 0x00000000;
|
| 1028 | 8ecc7913 | j_mayer | dsacntl = 0x00000000;
|
| 1029 | 8ecc7913 | j_mayer | ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); |
| 1030 | 8ecc7913 | j_mayer | ocm->isarc = isarc; |
| 1031 | 8ecc7913 | j_mayer | ocm->dsarc = dsarc; |
| 1032 | 8ecc7913 | j_mayer | ocm->isacntl = isacntl; |
| 1033 | 8ecc7913 | j_mayer | ocm->dsacntl = dsacntl; |
| 1034 | 8ecc7913 | j_mayer | } |
| 1035 | 8ecc7913 | j_mayer | |
| 1036 | 8ecc7913 | j_mayer | void ppc405_ocm_init (CPUState *env, unsigned long offset) |
| 1037 | 8ecc7913 | j_mayer | {
|
| 1038 | 8ecc7913 | j_mayer | ppc405_ocm_t *ocm; |
| 1039 | 8ecc7913 | j_mayer | |
| 1040 | 8ecc7913 | j_mayer | ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
|
| 1041 | 8ecc7913 | j_mayer | if (ocm != NULL) { |
| 1042 | 8ecc7913 | j_mayer | ocm->offset = offset; |
| 1043 | 8ecc7913 | j_mayer | ocm_reset(ocm); |
| 1044 | 8ecc7913 | j_mayer | qemu_register_reset(&ocm_reset, ocm); |
| 1045 | 8ecc7913 | j_mayer | ppc_dcr_register(env, OCM0_ISARC, |
| 1046 | 8ecc7913 | j_mayer | ocm, &dcr_read_ocm, &dcr_write_ocm); |
| 1047 | 8ecc7913 | j_mayer | ppc_dcr_register(env, OCM0_ISACNTL, |
| 1048 | 8ecc7913 | j_mayer | ocm, &dcr_read_ocm, &dcr_write_ocm); |
| 1049 | 8ecc7913 | j_mayer | ppc_dcr_register(env, OCM0_DSARC, |
| 1050 | 8ecc7913 | j_mayer | ocm, &dcr_read_ocm, &dcr_write_ocm); |
| 1051 | 8ecc7913 | j_mayer | ppc_dcr_register(env, OCM0_DSACNTL, |
| 1052 | 8ecc7913 | j_mayer | ocm, &dcr_read_ocm, &dcr_write_ocm); |
| 1053 | 8ecc7913 | j_mayer | } |
| 1054 | 8ecc7913 | j_mayer | } |
| 1055 | 8ecc7913 | j_mayer | |
| 1056 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
| 1057 | 8ecc7913 | j_mayer | /* I2C controller */
|
| 1058 | 8ecc7913 | j_mayer | typedef struct ppc4xx_i2c_t ppc4xx_i2c_t; |
| 1059 | 8ecc7913 | j_mayer | struct ppc4xx_i2c_t {
|
| 1060 | 9c02f1a2 | j_mayer | target_phys_addr_t base; |
| 1061 | 9c02f1a2 | j_mayer | qemu_irq irq; |
| 1062 | 8ecc7913 | j_mayer | uint8_t mdata; |
| 1063 | 8ecc7913 | j_mayer | uint8_t lmadr; |
| 1064 | 8ecc7913 | j_mayer | uint8_t hmadr; |
| 1065 | 8ecc7913 | j_mayer | uint8_t cntl; |
| 1066 | 8ecc7913 | j_mayer | uint8_t mdcntl; |
| 1067 | 8ecc7913 | j_mayer | uint8_t sts; |
| 1068 | 8ecc7913 | j_mayer | uint8_t extsts; |
| 1069 | 8ecc7913 | j_mayer | uint8_t sdata; |
| 1070 | 8ecc7913 | j_mayer | uint8_t lsadr; |
| 1071 | 8ecc7913 | j_mayer | uint8_t hsadr; |
| 1072 | 8ecc7913 | j_mayer | uint8_t clkdiv; |
| 1073 | 8ecc7913 | j_mayer | uint8_t intrmsk; |
| 1074 | 8ecc7913 | j_mayer | uint8_t xfrcnt; |
| 1075 | 8ecc7913 | j_mayer | uint8_t xtcntlss; |
| 1076 | 8ecc7913 | j_mayer | uint8_t directcntl; |
| 1077 | 8ecc7913 | j_mayer | }; |
| 1078 | 8ecc7913 | j_mayer | |
| 1079 | 8ecc7913 | j_mayer | static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr) |
| 1080 | 8ecc7913 | j_mayer | {
|
| 1081 | 8ecc7913 | j_mayer | ppc4xx_i2c_t *i2c; |
| 1082 | 8ecc7913 | j_mayer | uint32_t ret; |
| 1083 | 8ecc7913 | j_mayer | |
| 1084 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
| 1085 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
| 1086 | 8ecc7913 | j_mayer | #endif
|
| 1087 | 8ecc7913 | j_mayer | i2c = opaque; |
| 1088 | 8ecc7913 | j_mayer | switch (addr - i2c->base) {
|
| 1089 | 8ecc7913 | j_mayer | case 0x00: |
| 1090 | 8ecc7913 | j_mayer | // i2c_readbyte(&i2c->mdata);
|
| 1091 | 8ecc7913 | j_mayer | ret = i2c->mdata; |
| 1092 | 8ecc7913 | j_mayer | break;
|
| 1093 | 8ecc7913 | j_mayer | case 0x02: |
| 1094 | 8ecc7913 | j_mayer | ret = i2c->sdata; |
| 1095 | 8ecc7913 | j_mayer | break;
|
| 1096 | 8ecc7913 | j_mayer | case 0x04: |
| 1097 | 8ecc7913 | j_mayer | ret = i2c->lmadr; |
| 1098 | 8ecc7913 | j_mayer | break;
|
| 1099 | 8ecc7913 | j_mayer | case 0x05: |
| 1100 | 8ecc7913 | j_mayer | ret = i2c->hmadr; |
| 1101 | 8ecc7913 | j_mayer | break;
|
| 1102 | 8ecc7913 | j_mayer | case 0x06: |
| 1103 | 8ecc7913 | j_mayer | ret = i2c->cntl; |
| 1104 | 8ecc7913 | j_mayer | break;
|
| 1105 | 8ecc7913 | j_mayer | case 0x07: |
| 1106 | 8ecc7913 | j_mayer | ret = i2c->mdcntl; |
| 1107 | 8ecc7913 | j_mayer | break;
|
| 1108 | 8ecc7913 | j_mayer | case 0x08: |
| 1109 | 8ecc7913 | j_mayer | ret = i2c->sts; |
| 1110 | 8ecc7913 | j_mayer | break;
|
| 1111 | 8ecc7913 | j_mayer | case 0x09: |
| 1112 | 8ecc7913 | j_mayer | ret = i2c->extsts; |
| 1113 | 8ecc7913 | j_mayer | break;
|
| 1114 | 8ecc7913 | j_mayer | case 0x0A: |
| 1115 | 8ecc7913 | j_mayer | ret = i2c->lsadr; |
| 1116 | 8ecc7913 | j_mayer | break;
|
| 1117 | 8ecc7913 | j_mayer | case 0x0B: |
| 1118 | 8ecc7913 | j_mayer | ret = i2c->hsadr; |
| 1119 | 8ecc7913 | j_mayer | break;
|
| 1120 | 8ecc7913 | j_mayer | case 0x0C: |
| 1121 | 8ecc7913 | j_mayer | ret = i2c->clkdiv; |
| 1122 | 8ecc7913 | j_mayer | break;
|
| 1123 | 8ecc7913 | j_mayer | case 0x0D: |
| 1124 | 8ecc7913 | j_mayer | ret = i2c->intrmsk; |
| 1125 | 8ecc7913 | j_mayer | break;
|
| 1126 | 8ecc7913 | j_mayer | case 0x0E: |
| 1127 | 8ecc7913 | j_mayer | ret = i2c->xfrcnt; |
| 1128 | 8ecc7913 | j_mayer | break;
|
| 1129 | 8ecc7913 | j_mayer | case 0x0F: |
| 1130 | 8ecc7913 | j_mayer | ret = i2c->xtcntlss; |
| 1131 | 8ecc7913 | j_mayer | break;
|
| 1132 | 8ecc7913 | j_mayer | case 0x10: |
| 1133 | 8ecc7913 | j_mayer | ret = i2c->directcntl; |
| 1134 | 8ecc7913 | j_mayer | break;
|
| 1135 | 8ecc7913 | j_mayer | default:
|
| 1136 | 8ecc7913 | j_mayer | ret = 0x00;
|
| 1137 | 8ecc7913 | j_mayer | break;
|
| 1138 | 8ecc7913 | j_mayer | } |
| 1139 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
| 1140 | aae9366a | j_mayer | printf("%s: addr " PADDRX " %02" PRIx32 "\n", __func__, addr, ret); |
| 1141 | 8ecc7913 | j_mayer | #endif
|
| 1142 | 8ecc7913 | j_mayer | |
| 1143 | 8ecc7913 | j_mayer | return ret;
|
| 1144 | 8ecc7913 | j_mayer | } |
| 1145 | 8ecc7913 | j_mayer | |
| 1146 | 8ecc7913 | j_mayer | static void ppc4xx_i2c_writeb (void *opaque, |
| 1147 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
| 1148 | 8ecc7913 | j_mayer | {
|
| 1149 | 8ecc7913 | j_mayer | ppc4xx_i2c_t *i2c; |
| 1150 | 8ecc7913 | j_mayer | |
| 1151 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
| 1152 | aae9366a | j_mayer | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 1153 | 8ecc7913 | j_mayer | #endif
|
| 1154 | 8ecc7913 | j_mayer | i2c = opaque; |
| 1155 | 8ecc7913 | j_mayer | switch (addr - i2c->base) {
|
| 1156 | 8ecc7913 | j_mayer | case 0x00: |
| 1157 | 8ecc7913 | j_mayer | i2c->mdata = value; |
| 1158 | 8ecc7913 | j_mayer | // i2c_sendbyte(&i2c->mdata);
|
| 1159 | 8ecc7913 | j_mayer | break;
|
| 1160 | 8ecc7913 | j_mayer | case 0x02: |
| 1161 | 8ecc7913 | j_mayer | i2c->sdata = value; |
| 1162 | 8ecc7913 | j_mayer | break;
|
| 1163 | 8ecc7913 | j_mayer | case 0x04: |
| 1164 | 8ecc7913 | j_mayer | i2c->lmadr = value; |
| 1165 | 8ecc7913 | j_mayer | break;
|
| 1166 | 8ecc7913 | j_mayer | case 0x05: |
| 1167 | 8ecc7913 | j_mayer | i2c->hmadr = value; |
| 1168 | 8ecc7913 | j_mayer | break;
|
| 1169 | 8ecc7913 | j_mayer | case 0x06: |
| 1170 | 8ecc7913 | j_mayer | i2c->cntl = value; |
| 1171 | 8ecc7913 | j_mayer | break;
|
| 1172 | 8ecc7913 | j_mayer | case 0x07: |
| 1173 | 8ecc7913 | j_mayer | i2c->mdcntl = value & 0xDF;
|
| 1174 | 8ecc7913 | j_mayer | break;
|
| 1175 | 8ecc7913 | j_mayer | case 0x08: |
| 1176 | 8ecc7913 | j_mayer | i2c->sts &= ~(value & 0x0A);
|
| 1177 | 8ecc7913 | j_mayer | break;
|
| 1178 | 8ecc7913 | j_mayer | case 0x09: |
| 1179 | 8ecc7913 | j_mayer | i2c->extsts &= ~(value & 0x8F);
|
| 1180 | 8ecc7913 | j_mayer | break;
|
| 1181 | 8ecc7913 | j_mayer | case 0x0A: |
| 1182 | 8ecc7913 | j_mayer | i2c->lsadr = value; |
| 1183 | 8ecc7913 | j_mayer | break;
|
| 1184 | 8ecc7913 | j_mayer | case 0x0B: |
| 1185 | 8ecc7913 | j_mayer | i2c->hsadr = value; |
| 1186 | 8ecc7913 | j_mayer | break;
|
| 1187 | 8ecc7913 | j_mayer | case 0x0C: |
| 1188 | 8ecc7913 | j_mayer | i2c->clkdiv = value; |
| 1189 | 8ecc7913 | j_mayer | break;
|
| 1190 | 8ecc7913 | j_mayer | case 0x0D: |
| 1191 | 8ecc7913 | j_mayer | i2c->intrmsk = value; |
| 1192 | 8ecc7913 | j_mayer | break;
|
| 1193 | 8ecc7913 | j_mayer | case 0x0E: |
| 1194 | 8ecc7913 | j_mayer | i2c->xfrcnt = value & 0x77;
|
| 1195 | 8ecc7913 | j_mayer | break;
|
| 1196 | 8ecc7913 | j_mayer | case 0x0F: |
| 1197 | 8ecc7913 | j_mayer | i2c->xtcntlss = value; |
| 1198 | 8ecc7913 | j_mayer | break;
|
| 1199 | 8ecc7913 | j_mayer | case 0x10: |
| 1200 | 8ecc7913 | j_mayer | i2c->directcntl = value & 0x7;
|
| 1201 | 8ecc7913 | j_mayer | break;
|
| 1202 | 8ecc7913 | j_mayer | } |
| 1203 | 8ecc7913 | j_mayer | } |
| 1204 | 8ecc7913 | j_mayer | |
| 1205 | 8ecc7913 | j_mayer | static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr) |
| 1206 | 8ecc7913 | j_mayer | {
|
| 1207 | 8ecc7913 | j_mayer | uint32_t ret; |
| 1208 | 8ecc7913 | j_mayer | |
| 1209 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
| 1210 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
| 1211 | 8ecc7913 | j_mayer | #endif
|
| 1212 | 8ecc7913 | j_mayer | ret = ppc4xx_i2c_readb(opaque, addr) << 8;
|
| 1213 | 8ecc7913 | j_mayer | ret |= ppc4xx_i2c_readb(opaque, addr + 1);
|
| 1214 | 8ecc7913 | j_mayer | |
| 1215 | 8ecc7913 | j_mayer | return ret;
|
| 1216 | 8ecc7913 | j_mayer | } |
| 1217 | 8ecc7913 | j_mayer | |
| 1218 | 8ecc7913 | j_mayer | static void ppc4xx_i2c_writew (void *opaque, |
| 1219 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
| 1220 | 8ecc7913 | j_mayer | {
|
| 1221 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
| 1222 | aae9366a | j_mayer | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 1223 | 8ecc7913 | j_mayer | #endif
|
| 1224 | 8ecc7913 | j_mayer | ppc4xx_i2c_writeb(opaque, addr, value >> 8);
|
| 1225 | 8ecc7913 | j_mayer | ppc4xx_i2c_writeb(opaque, addr + 1, value);
|
| 1226 | 8ecc7913 | j_mayer | } |
| 1227 | 8ecc7913 | j_mayer | |
| 1228 | 8ecc7913 | j_mayer | static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr) |
| 1229 | 8ecc7913 | j_mayer | {
|
| 1230 | 8ecc7913 | j_mayer | uint32_t ret; |
| 1231 | 8ecc7913 | j_mayer | |
| 1232 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
| 1233 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
| 1234 | 8ecc7913 | j_mayer | #endif
|
| 1235 | 8ecc7913 | j_mayer | ret = ppc4xx_i2c_readb(opaque, addr) << 24;
|
| 1236 | 8ecc7913 | j_mayer | ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16; |
| 1237 | 8ecc7913 | j_mayer | ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8; |
| 1238 | 8ecc7913 | j_mayer | ret |= ppc4xx_i2c_readb(opaque, addr + 3);
|
| 1239 | 8ecc7913 | j_mayer | |
| 1240 | 8ecc7913 | j_mayer | return ret;
|
| 1241 | 8ecc7913 | j_mayer | } |
| 1242 | 8ecc7913 | j_mayer | |
| 1243 | 8ecc7913 | j_mayer | static void ppc4xx_i2c_writel (void *opaque, |
| 1244 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
| 1245 | 8ecc7913 | j_mayer | {
|
| 1246 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
| 1247 | aae9366a | j_mayer | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 1248 | 8ecc7913 | j_mayer | #endif
|
| 1249 | 8ecc7913 | j_mayer | ppc4xx_i2c_writeb(opaque, addr, value >> 24);
|
| 1250 | 8ecc7913 | j_mayer | ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16); |
| 1251 | 8ecc7913 | j_mayer | ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8); |
| 1252 | 8ecc7913 | j_mayer | ppc4xx_i2c_writeb(opaque, addr + 3, value);
|
| 1253 | 8ecc7913 | j_mayer | } |
| 1254 | 8ecc7913 | j_mayer | |
| 1255 | 8ecc7913 | j_mayer | static CPUReadMemoryFunc *i2c_read[] = {
|
| 1256 | 8ecc7913 | j_mayer | &ppc4xx_i2c_readb, |
| 1257 | 8ecc7913 | j_mayer | &ppc4xx_i2c_readw, |
| 1258 | 8ecc7913 | j_mayer | &ppc4xx_i2c_readl, |
| 1259 | 8ecc7913 | j_mayer | }; |
| 1260 | 8ecc7913 | j_mayer | |
| 1261 | 8ecc7913 | j_mayer | static CPUWriteMemoryFunc *i2c_write[] = {
|
| 1262 | 8ecc7913 | j_mayer | &ppc4xx_i2c_writeb, |
| 1263 | 8ecc7913 | j_mayer | &ppc4xx_i2c_writew, |
| 1264 | 8ecc7913 | j_mayer | &ppc4xx_i2c_writel, |
| 1265 | 8ecc7913 | j_mayer | }; |
| 1266 | 8ecc7913 | j_mayer | |
| 1267 | 8ecc7913 | j_mayer | static void ppc4xx_i2c_reset (void *opaque) |
| 1268 | 8ecc7913 | j_mayer | {
|
| 1269 | 8ecc7913 | j_mayer | ppc4xx_i2c_t *i2c; |
| 1270 | 8ecc7913 | j_mayer | |
| 1271 | 8ecc7913 | j_mayer | i2c = opaque; |
| 1272 | 8ecc7913 | j_mayer | i2c->mdata = 0x00;
|
| 1273 | 8ecc7913 | j_mayer | i2c->sdata = 0x00;
|
| 1274 | 8ecc7913 | j_mayer | i2c->cntl = 0x00;
|
| 1275 | 8ecc7913 | j_mayer | i2c->mdcntl = 0x00;
|
| 1276 | 8ecc7913 | j_mayer | i2c->sts = 0x00;
|
| 1277 | 8ecc7913 | j_mayer | i2c->extsts = 0x00;
|
| 1278 | 8ecc7913 | j_mayer | i2c->clkdiv = 0x00;
|
| 1279 | 8ecc7913 | j_mayer | i2c->xfrcnt = 0x00;
|
| 1280 | 8ecc7913 | j_mayer | i2c->directcntl = 0x0F;
|
| 1281 | 8ecc7913 | j_mayer | } |
| 1282 | 8ecc7913 | j_mayer | |
| 1283 | 9c02f1a2 | j_mayer | void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
| 1284 | 9c02f1a2 | j_mayer | target_phys_addr_t offset, qemu_irq irq) |
| 1285 | 8ecc7913 | j_mayer | {
|
| 1286 | 8ecc7913 | j_mayer | ppc4xx_i2c_t *i2c; |
| 1287 | 8ecc7913 | j_mayer | |
| 1288 | 8ecc7913 | j_mayer | i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
|
| 1289 | 8ecc7913 | j_mayer | if (i2c != NULL) { |
| 1290 | 9c02f1a2 | j_mayer | i2c->base = offset; |
| 1291 | 9c02f1a2 | j_mayer | i2c->irq = irq; |
| 1292 | 8ecc7913 | j_mayer | ppc4xx_i2c_reset(i2c); |
| 1293 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
| 1294 | aae9366a | j_mayer | printf("%s: offset " PADDRX "\n", __func__, offset); |
| 1295 | 8ecc7913 | j_mayer | #endif
|
| 1296 | 8ecc7913 | j_mayer | ppc4xx_mmio_register(env, mmio, offset, 0x011,
|
| 1297 | 8ecc7913 | j_mayer | i2c_read, i2c_write, i2c); |
| 1298 | 8ecc7913 | j_mayer | qemu_register_reset(ppc4xx_i2c_reset, i2c); |
| 1299 | 8ecc7913 | j_mayer | } |
| 1300 | 8ecc7913 | j_mayer | } |
| 1301 | 8ecc7913 | j_mayer | |
| 1302 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
| 1303 | 9c02f1a2 | j_mayer | /* General purpose timers */
|
| 1304 | 9c02f1a2 | j_mayer | typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; |
| 1305 | 9c02f1a2 | j_mayer | struct ppc4xx_gpt_t {
|
| 1306 | 9c02f1a2 | j_mayer | target_phys_addr_t base; |
| 1307 | 9c02f1a2 | j_mayer | int64_t tb_offset; |
| 1308 | 9c02f1a2 | j_mayer | uint32_t tb_freq; |
| 1309 | 9c02f1a2 | j_mayer | struct QEMUTimer *timer;
|
| 1310 | 9c02f1a2 | j_mayer | qemu_irq irqs[5];
|
| 1311 | 9c02f1a2 | j_mayer | uint32_t oe; |
| 1312 | 9c02f1a2 | j_mayer | uint32_t ol; |
| 1313 | 9c02f1a2 | j_mayer | uint32_t im; |
| 1314 | 9c02f1a2 | j_mayer | uint32_t is; |
| 1315 | 9c02f1a2 | j_mayer | uint32_t ie; |
| 1316 | 9c02f1a2 | j_mayer | uint32_t comp[5];
|
| 1317 | 9c02f1a2 | j_mayer | uint32_t mask[5];
|
| 1318 | 9c02f1a2 | j_mayer | }; |
| 1319 | 9c02f1a2 | j_mayer | |
| 1320 | 9c02f1a2 | j_mayer | static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr) |
| 1321 | 9c02f1a2 | j_mayer | {
|
| 1322 | 9c02f1a2 | j_mayer | #ifdef DEBUG_GPT
|
| 1323 | 9c02f1a2 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
| 1324 | 9c02f1a2 | j_mayer | #endif
|
| 1325 | 9c02f1a2 | j_mayer | /* XXX: generate a bus fault */
|
| 1326 | 9c02f1a2 | j_mayer | return -1; |
| 1327 | 9c02f1a2 | j_mayer | } |
| 1328 | 9c02f1a2 | j_mayer | |
| 1329 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_writeb (void *opaque, |
| 1330 | 9c02f1a2 | j_mayer | target_phys_addr_t addr, uint32_t value) |
| 1331 | 9c02f1a2 | j_mayer | {
|
| 1332 | 9c02f1a2 | j_mayer | #ifdef DEBUG_I2C
|
| 1333 | aae9366a | j_mayer | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 1334 | 9c02f1a2 | j_mayer | #endif
|
| 1335 | 9c02f1a2 | j_mayer | /* XXX: generate a bus fault */
|
| 1336 | 9c02f1a2 | j_mayer | } |
| 1337 | 9c02f1a2 | j_mayer | |
| 1338 | 9c02f1a2 | j_mayer | static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr) |
| 1339 | 9c02f1a2 | j_mayer | {
|
| 1340 | 9c02f1a2 | j_mayer | #ifdef DEBUG_GPT
|
| 1341 | 9c02f1a2 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
| 1342 | 9c02f1a2 | j_mayer | #endif
|
| 1343 | 9c02f1a2 | j_mayer | /* XXX: generate a bus fault */
|
| 1344 | 9c02f1a2 | j_mayer | return -1; |
| 1345 | 9c02f1a2 | j_mayer | } |
| 1346 | 9c02f1a2 | j_mayer | |
| 1347 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_writew (void *opaque, |
| 1348 | 9c02f1a2 | j_mayer | target_phys_addr_t addr, uint32_t value) |
| 1349 | 9c02f1a2 | j_mayer | {
|
| 1350 | 9c02f1a2 | j_mayer | #ifdef DEBUG_I2C
|
| 1351 | aae9366a | j_mayer | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 1352 | 9c02f1a2 | j_mayer | #endif
|
| 1353 | 9c02f1a2 | j_mayer | /* XXX: generate a bus fault */
|
| 1354 | 9c02f1a2 | j_mayer | } |
| 1355 | 9c02f1a2 | j_mayer | |
| 1356 | 9c02f1a2 | j_mayer | static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) |
| 1357 | 9c02f1a2 | j_mayer | {
|
| 1358 | 9c02f1a2 | j_mayer | /* XXX: TODO */
|
| 1359 | 9c02f1a2 | j_mayer | return 0; |
| 1360 | 9c02f1a2 | j_mayer | } |
| 1361 | 9c02f1a2 | j_mayer | |
| 1362 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) |
| 1363 | 9c02f1a2 | j_mayer | {
|
| 1364 | 9c02f1a2 | j_mayer | /* XXX: TODO */
|
| 1365 | 9c02f1a2 | j_mayer | } |
| 1366 | 9c02f1a2 | j_mayer | |
| 1367 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) |
| 1368 | 9c02f1a2 | j_mayer | {
|
| 1369 | 9c02f1a2 | j_mayer | uint32_t mask; |
| 1370 | 9c02f1a2 | j_mayer | int i;
|
| 1371 | 9c02f1a2 | j_mayer | |
| 1372 | 9c02f1a2 | j_mayer | mask = 0x80000000;
|
| 1373 | 9c02f1a2 | j_mayer | for (i = 0; i < 5; i++) { |
| 1374 | 9c02f1a2 | j_mayer | if (gpt->oe & mask) {
|
| 1375 | 9c02f1a2 | j_mayer | /* Output is enabled */
|
| 1376 | 9c02f1a2 | j_mayer | if (ppc4xx_gpt_compare(gpt, i)) {
|
| 1377 | 9c02f1a2 | j_mayer | /* Comparison is OK */
|
| 1378 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); |
| 1379 | 9c02f1a2 | j_mayer | } else {
|
| 1380 | 9c02f1a2 | j_mayer | /* Comparison is KO */
|
| 1381 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); |
| 1382 | 9c02f1a2 | j_mayer | } |
| 1383 | 9c02f1a2 | j_mayer | } |
| 1384 | 9c02f1a2 | j_mayer | mask = mask >> 1;
|
| 1385 | 9c02f1a2 | j_mayer | } |
| 1386 | 9c02f1a2 | j_mayer | } |
| 1387 | 9c02f1a2 | j_mayer | |
| 1388 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) |
| 1389 | 9c02f1a2 | j_mayer | {
|
| 1390 | 9c02f1a2 | j_mayer | uint32_t mask; |
| 1391 | 9c02f1a2 | j_mayer | int i;
|
| 1392 | 9c02f1a2 | j_mayer | |
| 1393 | 9c02f1a2 | j_mayer | mask = 0x00008000;
|
| 1394 | 9c02f1a2 | j_mayer | for (i = 0; i < 5; i++) { |
| 1395 | 9c02f1a2 | j_mayer | if (gpt->is & gpt->im & mask)
|
| 1396 | 9c02f1a2 | j_mayer | qemu_irq_raise(gpt->irqs[i]); |
| 1397 | 9c02f1a2 | j_mayer | else
|
| 1398 | 9c02f1a2 | j_mayer | qemu_irq_lower(gpt->irqs[i]); |
| 1399 | 9c02f1a2 | j_mayer | mask = mask >> 1;
|
| 1400 | 9c02f1a2 | j_mayer | } |
| 1401 | 9c02f1a2 | j_mayer | } |
| 1402 | 9c02f1a2 | j_mayer | |
| 1403 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) |
| 1404 | 9c02f1a2 | j_mayer | {
|
| 1405 | 9c02f1a2 | j_mayer | /* XXX: TODO */
|
| 1406 | 9c02f1a2 | j_mayer | } |
| 1407 | 9c02f1a2 | j_mayer | |
| 1408 | 9c02f1a2 | j_mayer | static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr) |
| 1409 | 9c02f1a2 | j_mayer | {
|
| 1410 | 9c02f1a2 | j_mayer | ppc4xx_gpt_t *gpt; |
| 1411 | 9c02f1a2 | j_mayer | uint32_t ret; |
| 1412 | 9c02f1a2 | j_mayer | int idx;
|
| 1413 | 9c02f1a2 | j_mayer | |
| 1414 | 9c02f1a2 | j_mayer | #ifdef DEBUG_GPT
|
| 1415 | 9c02f1a2 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
| 1416 | 9c02f1a2 | j_mayer | #endif
|
| 1417 | 9c02f1a2 | j_mayer | gpt = opaque; |
| 1418 | 9c02f1a2 | j_mayer | switch (addr - gpt->base) {
|
| 1419 | 9c02f1a2 | j_mayer | case 0x00: |
| 1420 | 9c02f1a2 | j_mayer | /* Time base counter */
|
| 1421 | 9c02f1a2 | j_mayer | ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset, |
| 1422 | 9c02f1a2 | j_mayer | gpt->tb_freq, ticks_per_sec); |
| 1423 | 9c02f1a2 | j_mayer | break;
|
| 1424 | 9c02f1a2 | j_mayer | case 0x10: |
| 1425 | 9c02f1a2 | j_mayer | /* Output enable */
|
| 1426 | 9c02f1a2 | j_mayer | ret = gpt->oe; |
| 1427 | 9c02f1a2 | j_mayer | break;
|
| 1428 | 9c02f1a2 | j_mayer | case 0x14: |
| 1429 | 9c02f1a2 | j_mayer | /* Output level */
|
| 1430 | 9c02f1a2 | j_mayer | ret = gpt->ol; |
| 1431 | 9c02f1a2 | j_mayer | break;
|
| 1432 | 9c02f1a2 | j_mayer | case 0x18: |
| 1433 | 9c02f1a2 | j_mayer | /* Interrupt mask */
|
| 1434 | 9c02f1a2 | j_mayer | ret = gpt->im; |
| 1435 | 9c02f1a2 | j_mayer | break;
|
| 1436 | 9c02f1a2 | j_mayer | case 0x1C: |
| 1437 | 9c02f1a2 | j_mayer | case 0x20: |
| 1438 | 9c02f1a2 | j_mayer | /* Interrupt status */
|
| 1439 | 9c02f1a2 | j_mayer | ret = gpt->is; |
| 1440 | 9c02f1a2 | j_mayer | break;
|
| 1441 | 9c02f1a2 | j_mayer | case 0x24: |
| 1442 | 9c02f1a2 | j_mayer | /* Interrupt enable */
|
| 1443 | 9c02f1a2 | j_mayer | ret = gpt->ie; |
| 1444 | 9c02f1a2 | j_mayer | break;
|
| 1445 | 9c02f1a2 | j_mayer | case 0x80 ... 0x90: |
| 1446 | 9c02f1a2 | j_mayer | /* Compare timer */
|
| 1447 | 9c02f1a2 | j_mayer | idx = ((addr - gpt->base) - 0x80) >> 2; |
| 1448 | 9c02f1a2 | j_mayer | ret = gpt->comp[idx]; |
| 1449 | 9c02f1a2 | j_mayer | break;
|
| 1450 | 9c02f1a2 | j_mayer | case 0xC0 ... 0xD0: |
| 1451 | 9c02f1a2 | j_mayer | /* Compare mask */
|
| 1452 | 9c02f1a2 | j_mayer | idx = ((addr - gpt->base) - 0xC0) >> 2; |
| 1453 | 9c02f1a2 | j_mayer | ret = gpt->mask[idx]; |
| 1454 | 9c02f1a2 | j_mayer | break;
|
| 1455 | 9c02f1a2 | j_mayer | default:
|
| 1456 | 9c02f1a2 | j_mayer | ret = -1;
|
| 1457 | 9c02f1a2 | j_mayer | break;
|
| 1458 | 9c02f1a2 | j_mayer | } |
| 1459 | 9c02f1a2 | j_mayer | |
| 1460 | 9c02f1a2 | j_mayer | return ret;
|
| 1461 | 9c02f1a2 | j_mayer | } |
| 1462 | 9c02f1a2 | j_mayer | |
| 1463 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_writel (void *opaque, |
| 1464 | 9c02f1a2 | j_mayer | target_phys_addr_t addr, uint32_t value) |
| 1465 | 9c02f1a2 | j_mayer | {
|
| 1466 | 9c02f1a2 | j_mayer | ppc4xx_gpt_t *gpt; |
| 1467 | 9c02f1a2 | j_mayer | int idx;
|
| 1468 | 9c02f1a2 | j_mayer | |
| 1469 | 9c02f1a2 | j_mayer | #ifdef DEBUG_I2C
|
| 1470 | aae9366a | j_mayer | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
| 1471 | 9c02f1a2 | j_mayer | #endif
|
| 1472 | 9c02f1a2 | j_mayer | gpt = opaque; |
| 1473 | 9c02f1a2 | j_mayer | switch (addr - gpt->base) {
|
| 1474 | 9c02f1a2 | j_mayer | case 0x00: |
| 1475 | 9c02f1a2 | j_mayer | /* Time base counter */
|
| 1476 | 9c02f1a2 | j_mayer | gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq) |
| 1477 | 9c02f1a2 | j_mayer | - qemu_get_clock(vm_clock); |
| 1478 | 9c02f1a2 | j_mayer | ppc4xx_gpt_compute_timer(gpt); |
| 1479 | 9c02f1a2 | j_mayer | break;
|
| 1480 | 9c02f1a2 | j_mayer | case 0x10: |
| 1481 | 9c02f1a2 | j_mayer | /* Output enable */
|
| 1482 | 9c02f1a2 | j_mayer | gpt->oe = value & 0xF8000000;
|
| 1483 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_outputs(gpt); |
| 1484 | 9c02f1a2 | j_mayer | break;
|
| 1485 | 9c02f1a2 | j_mayer | case 0x14: |
| 1486 | 9c02f1a2 | j_mayer | /* Output level */
|
| 1487 | 9c02f1a2 | j_mayer | gpt->ol = value & 0xF8000000;
|
| 1488 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_outputs(gpt); |
| 1489 | 9c02f1a2 | j_mayer | break;
|
| 1490 | 9c02f1a2 | j_mayer | case 0x18: |
| 1491 | 9c02f1a2 | j_mayer | /* Interrupt mask */
|
| 1492 | 9c02f1a2 | j_mayer | gpt->im = value & 0x0000F800;
|
| 1493 | 9c02f1a2 | j_mayer | break;
|
| 1494 | 9c02f1a2 | j_mayer | case 0x1C: |
| 1495 | 9c02f1a2 | j_mayer | /* Interrupt status set */
|
| 1496 | 9c02f1a2 | j_mayer | gpt->is |= value & 0x0000F800;
|
| 1497 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_irqs(gpt); |
| 1498 | 9c02f1a2 | j_mayer | break;
|
| 1499 | 9c02f1a2 | j_mayer | case 0x20: |
| 1500 | 9c02f1a2 | j_mayer | /* Interrupt status clear */
|
| 1501 | 9c02f1a2 | j_mayer | gpt->is &= ~(value & 0x0000F800);
|
| 1502 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_irqs(gpt); |
| 1503 | 9c02f1a2 | j_mayer | break;
|
| 1504 | 9c02f1a2 | j_mayer | case 0x24: |
| 1505 | 9c02f1a2 | j_mayer | /* Interrupt enable */
|
| 1506 | 9c02f1a2 | j_mayer | gpt->ie = value & 0x0000F800;
|
| 1507 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_irqs(gpt); |
| 1508 | 9c02f1a2 | j_mayer | break;
|
| 1509 | 9c02f1a2 | j_mayer | case 0x80 ... 0x90: |
| 1510 | 9c02f1a2 | j_mayer | /* Compare timer */
|
| 1511 | 9c02f1a2 | j_mayer | idx = ((addr - gpt->base) - 0x80) >> 2; |
| 1512 | 9c02f1a2 | j_mayer | gpt->comp[idx] = value & 0xF8000000;
|
| 1513 | 9c02f1a2 | j_mayer | ppc4xx_gpt_compute_timer(gpt); |
| 1514 | 9c02f1a2 | j_mayer | break;
|
| 1515 | 9c02f1a2 | j_mayer | case 0xC0 ... 0xD0: |
| 1516 | 9c02f1a2 | j_mayer | /* Compare mask */
|
| 1517 | 9c02f1a2 | j_mayer | idx = ((addr - gpt->base) - 0xC0) >> 2; |
| 1518 | 9c02f1a2 | j_mayer | gpt->mask[idx] = value & 0xF8000000;
|
| 1519 | 9c02f1a2 | j_mayer | ppc4xx_gpt_compute_timer(gpt); |
| 1520 | 9c02f1a2 | j_mayer | break;
|
| 1521 | 9c02f1a2 | j_mayer | } |
| 1522 | 9c02f1a2 | j_mayer | } |
| 1523 | 9c02f1a2 | j_mayer | |
| 1524 | 9c02f1a2 | j_mayer | static CPUReadMemoryFunc *gpt_read[] = {
|
| 1525 | 9c02f1a2 | j_mayer | &ppc4xx_gpt_readb, |
| 1526 | 9c02f1a2 | j_mayer | &ppc4xx_gpt_readw, |
| 1527 | 9c02f1a2 | j_mayer | &ppc4xx_gpt_readl, |
| 1528 | 9c02f1a2 | j_mayer | }; |
| 1529 | 9c02f1a2 | j_mayer | |
| 1530 | 9c02f1a2 | j_mayer | static CPUWriteMemoryFunc *gpt_write[] = {
|
| 1531 | 9c02f1a2 | j_mayer | &ppc4xx_gpt_writeb, |
| 1532 | 9c02f1a2 | j_mayer | &ppc4xx_gpt_writew, |
| 1533 | 9c02f1a2 | j_mayer | &ppc4xx_gpt_writel, |
| 1534 | 9c02f1a2 | j_mayer | }; |
| 1535 | 9c02f1a2 | j_mayer | |
| 1536 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_cb (void *opaque) |
| 1537 | 9c02f1a2 | j_mayer | {
|
| 1538 | 9c02f1a2 | j_mayer | ppc4xx_gpt_t *gpt; |
| 1539 | 9c02f1a2 | j_mayer | |
| 1540 | 9c02f1a2 | j_mayer | gpt = opaque; |
| 1541 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_irqs(gpt); |
| 1542 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_outputs(gpt); |
| 1543 | 9c02f1a2 | j_mayer | ppc4xx_gpt_compute_timer(gpt); |
| 1544 | 9c02f1a2 | j_mayer | } |
| 1545 | 9c02f1a2 | j_mayer | |
| 1546 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_reset (void *opaque) |
| 1547 | 9c02f1a2 | j_mayer | {
|
| 1548 | 9c02f1a2 | j_mayer | ppc4xx_gpt_t *gpt; |
| 1549 | 9c02f1a2 | j_mayer | int i;
|
| 1550 | 9c02f1a2 | j_mayer | |
| 1551 | 9c02f1a2 | j_mayer | gpt = opaque; |
| 1552 | 9c02f1a2 | j_mayer | qemu_del_timer(gpt->timer); |
| 1553 | 9c02f1a2 | j_mayer | gpt->oe = 0x00000000;
|
| 1554 | 9c02f1a2 | j_mayer | gpt->ol = 0x00000000;
|
| 1555 | 9c02f1a2 | j_mayer | gpt->im = 0x00000000;
|
| 1556 | 9c02f1a2 | j_mayer | gpt->is = 0x00000000;
|
| 1557 | 9c02f1a2 | j_mayer | gpt->ie = 0x00000000;
|
| 1558 | 9c02f1a2 | j_mayer | for (i = 0; i < 5; i++) { |
| 1559 | 9c02f1a2 | j_mayer | gpt->comp[i] = 0x00000000;
|
| 1560 | 9c02f1a2 | j_mayer | gpt->mask[i] = 0x00000000;
|
| 1561 | 9c02f1a2 | j_mayer | } |
| 1562 | 9c02f1a2 | j_mayer | } |
| 1563 | 9c02f1a2 | j_mayer | |
| 1564 | 9c02f1a2 | j_mayer | void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
| 1565 | 9c02f1a2 | j_mayer | target_phys_addr_t offset, qemu_irq irqs[5])
|
| 1566 | 9c02f1a2 | j_mayer | {
|
| 1567 | 9c02f1a2 | j_mayer | ppc4xx_gpt_t *gpt; |
| 1568 | 9c02f1a2 | j_mayer | int i;
|
| 1569 | 9c02f1a2 | j_mayer | |
| 1570 | 9c02f1a2 | j_mayer | gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
|
| 1571 | 9c02f1a2 | j_mayer | if (gpt != NULL) { |
| 1572 | 9c02f1a2 | j_mayer | gpt->base = offset; |
| 1573 | 9c02f1a2 | j_mayer | for (i = 0; i < 5; i++) |
| 1574 | 9c02f1a2 | j_mayer | gpt->irqs[i] = irqs[i]; |
| 1575 | 9c02f1a2 | j_mayer | gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt); |
| 1576 | 9c02f1a2 | j_mayer | ppc4xx_gpt_reset(gpt); |
| 1577 | 9c02f1a2 | j_mayer | #ifdef DEBUG_GPT
|
| 1578 | aae9366a | j_mayer | printf("%s: offset " PADDRX "\n", __func__, offset); |
| 1579 | 9c02f1a2 | j_mayer | #endif
|
| 1580 | 9c02f1a2 | j_mayer | ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
|
| 1581 | 9c02f1a2 | j_mayer | gpt_read, gpt_write, gpt); |
| 1582 | 9c02f1a2 | j_mayer | qemu_register_reset(ppc4xx_gpt_reset, gpt); |
| 1583 | 9c02f1a2 | j_mayer | } |
| 1584 | 9c02f1a2 | j_mayer | } |
| 1585 | 9c02f1a2 | j_mayer | |
| 1586 | 9c02f1a2 | j_mayer | /*****************************************************************************/
|
| 1587 | 9c02f1a2 | j_mayer | /* MAL */
|
| 1588 | 9c02f1a2 | j_mayer | enum {
|
| 1589 | 9c02f1a2 | j_mayer | MAL0_CFG = 0x180,
|
| 1590 | 9c02f1a2 | j_mayer | MAL0_ESR = 0x181,
|
| 1591 | 9c02f1a2 | j_mayer | MAL0_IER = 0x182,
|
| 1592 | 9c02f1a2 | j_mayer | MAL0_TXCASR = 0x184,
|
| 1593 | 9c02f1a2 | j_mayer | MAL0_TXCARR = 0x185,
|
| 1594 | 9c02f1a2 | j_mayer | MAL0_TXEOBISR = 0x186,
|
| 1595 | 9c02f1a2 | j_mayer | MAL0_TXDEIR = 0x187,
|
| 1596 | 9c02f1a2 | j_mayer | MAL0_RXCASR = 0x190,
|
| 1597 | 9c02f1a2 | j_mayer | MAL0_RXCARR = 0x191,
|
| 1598 | 9c02f1a2 | j_mayer | MAL0_RXEOBISR = 0x192,
|
| 1599 | 9c02f1a2 | j_mayer | MAL0_RXDEIR = 0x193,
|
| 1600 | 9c02f1a2 | j_mayer | MAL0_TXCTP0R = 0x1A0,
|
| 1601 | 9c02f1a2 | j_mayer | MAL0_TXCTP1R = 0x1A1,
|
| 1602 | 9c02f1a2 | j_mayer | MAL0_TXCTP2R = 0x1A2,
|
| 1603 | 9c02f1a2 | j_mayer | MAL0_TXCTP3R = 0x1A3,
|
| 1604 | 9c02f1a2 | j_mayer | MAL0_RXCTP0R = 0x1C0,
|
| 1605 | 9c02f1a2 | j_mayer | MAL0_RXCTP1R = 0x1C1,
|
| 1606 | 9c02f1a2 | j_mayer | MAL0_RCBS0 = 0x1E0,
|
| 1607 | 9c02f1a2 | j_mayer | MAL0_RCBS1 = 0x1E1,
|
| 1608 | 9c02f1a2 | j_mayer | }; |
| 1609 | 9c02f1a2 | j_mayer | |
| 1610 | 9c02f1a2 | j_mayer | typedef struct ppc40x_mal_t ppc40x_mal_t; |
| 1611 | 9c02f1a2 | j_mayer | struct ppc40x_mal_t {
|
| 1612 | 9c02f1a2 | j_mayer | qemu_irq irqs[4];
|
| 1613 | 9c02f1a2 | j_mayer | uint32_t cfg; |
| 1614 | 9c02f1a2 | j_mayer | uint32_t esr; |
| 1615 | 9c02f1a2 | j_mayer | uint32_t ier; |
| 1616 | 9c02f1a2 | j_mayer | uint32_t txcasr; |
| 1617 | 9c02f1a2 | j_mayer | uint32_t txcarr; |
| 1618 | 9c02f1a2 | j_mayer | uint32_t txeobisr; |
| 1619 | 9c02f1a2 | j_mayer | uint32_t txdeir; |
| 1620 | 9c02f1a2 | j_mayer | uint32_t rxcasr; |
| 1621 | 9c02f1a2 | j_mayer | uint32_t rxcarr; |
| 1622 | 9c02f1a2 | j_mayer | uint32_t rxeobisr; |
| 1623 | 9c02f1a2 | j_mayer | uint32_t rxdeir; |
| 1624 | 9c02f1a2 | j_mayer | uint32_t txctpr[4];
|
| 1625 | 9c02f1a2 | j_mayer | uint32_t rxctpr[2];
|
| 1626 | 9c02f1a2 | j_mayer | uint32_t rcbs[2];
|
| 1627 | 9c02f1a2 | j_mayer | }; |
| 1628 | 9c02f1a2 | j_mayer | |
| 1629 | 9c02f1a2 | j_mayer | static void ppc40x_mal_reset (void *opaque); |
| 1630 | 9c02f1a2 | j_mayer | |
| 1631 | 9c02f1a2 | j_mayer | static target_ulong dcr_read_mal (void *opaque, int dcrn) |
| 1632 | 9c02f1a2 | j_mayer | {
|
| 1633 | 9c02f1a2 | j_mayer | ppc40x_mal_t *mal; |
| 1634 | 9c02f1a2 | j_mayer | target_ulong ret; |
| 1635 | 9c02f1a2 | j_mayer | |
| 1636 | 9c02f1a2 | j_mayer | mal = opaque; |
| 1637 | 9c02f1a2 | j_mayer | switch (dcrn) {
|
| 1638 | 9c02f1a2 | j_mayer | case MAL0_CFG:
|
| 1639 | 9c02f1a2 | j_mayer | ret = mal->cfg; |
| 1640 | 9c02f1a2 | j_mayer | break;
|
| 1641 | 9c02f1a2 | j_mayer | case MAL0_ESR:
|
| 1642 | 9c02f1a2 | j_mayer | ret = mal->esr; |
| 1643 | 9c02f1a2 | j_mayer | break;
|
| 1644 | 9c02f1a2 | j_mayer | case MAL0_IER:
|
| 1645 | 9c02f1a2 | j_mayer | ret = mal->ier; |
| 1646 | 9c02f1a2 | j_mayer | break;
|
| 1647 | 9c02f1a2 | j_mayer | case MAL0_TXCASR:
|
| 1648 | 9c02f1a2 | j_mayer | ret = mal->txcasr; |
| 1649 | 9c02f1a2 | j_mayer | break;
|
| 1650 | 9c02f1a2 | j_mayer | case MAL0_TXCARR:
|
| 1651 | 9c02f1a2 | j_mayer | ret = mal->txcarr; |
| 1652 | 9c02f1a2 | j_mayer | break;
|
| 1653 | 9c02f1a2 | j_mayer | case MAL0_TXEOBISR:
|
| 1654 | 9c02f1a2 | j_mayer | ret = mal->txeobisr; |
| 1655 | 9c02f1a2 | j_mayer | break;
|
| 1656 | 9c02f1a2 | j_mayer | case MAL0_TXDEIR:
|
| 1657 | 9c02f1a2 | j_mayer | ret = mal->txdeir; |
| 1658 | 9c02f1a2 | j_mayer | break;
|
| 1659 | 9c02f1a2 | j_mayer | case MAL0_RXCASR:
|
| 1660 | 9c02f1a2 | j_mayer | ret = mal->rxcasr; |
| 1661 | 9c02f1a2 | j_mayer | break;
|
| 1662 | 9c02f1a2 | j_mayer | case MAL0_RXCARR:
|
| 1663 | 9c02f1a2 | j_mayer | ret = mal->rxcarr; |
| 1664 | 9c02f1a2 | j_mayer | break;
|
| 1665 | 9c02f1a2 | j_mayer | case MAL0_RXEOBISR:
|
| 1666 | 9c02f1a2 | j_mayer | ret = mal->rxeobisr; |
| 1667 | 9c02f1a2 | j_mayer | break;
|
| 1668 | 9c02f1a2 | j_mayer | case MAL0_RXDEIR:
|
| 1669 | 9c02f1a2 | j_mayer | ret = mal->rxdeir; |
| 1670 | 9c02f1a2 | j_mayer | break;
|
| 1671 | 9c02f1a2 | j_mayer | case MAL0_TXCTP0R:
|
| 1672 | 9c02f1a2 | j_mayer | ret = mal->txctpr[0];
|
| 1673 | 9c02f1a2 | j_mayer | break;
|
| 1674 | 9c02f1a2 | j_mayer | case MAL0_TXCTP1R:
|
| 1675 | 9c02f1a2 | j_mayer | ret = mal->txctpr[1];
|
| 1676 | 9c02f1a2 | j_mayer | break;
|
| 1677 | 9c02f1a2 | j_mayer | case MAL0_TXCTP2R:
|
| 1678 | 9c02f1a2 | j_mayer | ret = mal->txctpr[2];
|
| 1679 | 9c02f1a2 | j_mayer | break;
|
| 1680 | 9c02f1a2 | j_mayer | case MAL0_TXCTP3R:
|
| 1681 | 9c02f1a2 | j_mayer | ret = mal->txctpr[3];
|
| 1682 | 9c02f1a2 | j_mayer | break;
|
| 1683 | 9c02f1a2 | j_mayer | case MAL0_RXCTP0R:
|
| 1684 | 9c02f1a2 | j_mayer | ret = mal->rxctpr[0];
|
| 1685 | 9c02f1a2 | j_mayer | break;
|
| 1686 | 9c02f1a2 | j_mayer | case MAL0_RXCTP1R:
|
| 1687 | 9c02f1a2 | j_mayer | ret = mal->rxctpr[1];
|
| 1688 | 9c02f1a2 | j_mayer | break;
|
| 1689 | 9c02f1a2 | j_mayer | case MAL0_RCBS0:
|
| 1690 | 9c02f1a2 | j_mayer | ret = mal->rcbs[0];
|
| 1691 | 9c02f1a2 | j_mayer | break;
|
| 1692 | 9c02f1a2 | j_mayer | case MAL0_RCBS1:
|
| 1693 | 9c02f1a2 | j_mayer | ret = mal->rcbs[1];
|
| 1694 | 9c02f1a2 | j_mayer | break;
|
| 1695 | 9c02f1a2 | j_mayer | default:
|
| 1696 | 9c02f1a2 | j_mayer | ret = 0;
|
| 1697 | 9c02f1a2 | j_mayer | break;
|
| 1698 | 9c02f1a2 | j_mayer | } |
| 1699 | 9c02f1a2 | j_mayer | |
| 1700 | 9c02f1a2 | j_mayer | return ret;
|
| 1701 | 9c02f1a2 | j_mayer | } |
| 1702 | 9c02f1a2 | j_mayer | |
| 1703 | 9c02f1a2 | j_mayer | static void dcr_write_mal (void *opaque, int dcrn, target_ulong val) |
| 1704 | 9c02f1a2 | j_mayer | {
|
| 1705 | 9c02f1a2 | j_mayer | ppc40x_mal_t *mal; |
| 1706 | 9c02f1a2 | j_mayer | int idx;
|
| 1707 | 9c02f1a2 | j_mayer | |
| 1708 | 9c02f1a2 | j_mayer | mal = opaque; |
| 1709 | 9c02f1a2 | j_mayer | switch (dcrn) {
|
| 1710 | 9c02f1a2 | j_mayer | case MAL0_CFG:
|
| 1711 | 9c02f1a2 | j_mayer | if (val & 0x80000000) |
| 1712 | 9c02f1a2 | j_mayer | ppc40x_mal_reset(mal); |
| 1713 | 9c02f1a2 | j_mayer | mal->cfg = val & 0x00FFC087;
|
| 1714 | 9c02f1a2 | j_mayer | break;
|
| 1715 | 9c02f1a2 | j_mayer | case MAL0_ESR:
|
| 1716 | 9c02f1a2 | j_mayer | /* Read/clear */
|
| 1717 | 9c02f1a2 | j_mayer | mal->esr &= ~val; |
| 1718 | 9c02f1a2 | j_mayer | break;
|
| 1719 | 9c02f1a2 | j_mayer | case MAL0_IER:
|
| 1720 | 9c02f1a2 | j_mayer | mal->ier = val & 0x0000001F;
|
| 1721 | 9c02f1a2 | j_mayer | break;
|
| 1722 | 9c02f1a2 | j_mayer | case MAL0_TXCASR:
|
| 1723 | 9c02f1a2 | j_mayer | mal->txcasr = val & 0xF0000000;
|
| 1724 | 9c02f1a2 | j_mayer | break;
|
| 1725 | 9c02f1a2 | j_mayer | case MAL0_TXCARR:
|
| 1726 | 9c02f1a2 | j_mayer | mal->txcarr = val & 0xF0000000;
|
| 1727 | 9c02f1a2 | j_mayer | break;
|
| 1728 | 9c02f1a2 | j_mayer | case MAL0_TXEOBISR:
|
| 1729 | 9c02f1a2 | j_mayer | /* Read/clear */
|
| 1730 | 9c02f1a2 | j_mayer | mal->txeobisr &= ~val; |
| 1731 | 9c02f1a2 | j_mayer | break;
|
| 1732 | 9c02f1a2 | j_mayer | case MAL0_TXDEIR:
|
| 1733 | 9c02f1a2 | j_mayer | /* Read/clear */
|
| 1734 | 9c02f1a2 | j_mayer | mal->txdeir &= ~val; |
| 1735 | 9c02f1a2 | j_mayer | break;
|
| 1736 | 9c02f1a2 | j_mayer | case MAL0_RXCASR:
|
| 1737 | 9c02f1a2 | j_mayer | mal->rxcasr = val & 0xC0000000;
|
| 1738 | 9c02f1a2 | j_mayer | break;
|
| 1739 | 9c02f1a2 | j_mayer | case MAL0_RXCARR:
|
| 1740 | 9c02f1a2 | j_mayer | mal->rxcarr = val & 0xC0000000;
|
| 1741 | 9c02f1a2 | j_mayer | break;
|
| 1742 | 9c02f1a2 | j_mayer | case MAL0_RXEOBISR:
|
| 1743 | 9c02f1a2 | j_mayer | /* Read/clear */
|
| 1744 | 9c02f1a2 | j_mayer | mal->rxeobisr &= ~val; |
| 1745 | 9c02f1a2 | j_mayer | break;
|
| 1746 | 9c02f1a2 | j_mayer | case MAL0_RXDEIR:
|
| 1747 | 9c02f1a2 | j_mayer | /* Read/clear */
|
| 1748 | 9c02f1a2 | j_mayer | mal->rxdeir &= ~val; |
| 1749 | 9c02f1a2 | j_mayer | break;
|
| 1750 | 9c02f1a2 | j_mayer | case MAL0_TXCTP0R:
|
| 1751 | 9c02f1a2 | j_mayer | idx = 0;
|
| 1752 | 9c02f1a2 | j_mayer | goto update_tx_ptr;
|
| 1753 | 9c02f1a2 | j_mayer | case MAL0_TXCTP1R:
|
| 1754 | 9c02f1a2 | j_mayer | idx = 1;
|
| 1755 | 9c02f1a2 | j_mayer | goto update_tx_ptr;
|
| 1756 | 9c02f1a2 | j_mayer | case MAL0_TXCTP2R:
|
| 1757 | 9c02f1a2 | j_mayer | idx = 2;
|
| 1758 | 9c02f1a2 | j_mayer | goto update_tx_ptr;
|
| 1759 | 9c02f1a2 | j_mayer | case MAL0_TXCTP3R:
|
| 1760 | 9c02f1a2 | j_mayer | idx = 3;
|
| 1761 | 9c02f1a2 | j_mayer | update_tx_ptr:
|
| 1762 | 9c02f1a2 | j_mayer | mal->txctpr[idx] = val; |
| 1763 | 9c02f1a2 | j_mayer | break;
|
| 1764 | 9c02f1a2 | j_mayer | case MAL0_RXCTP0R:
|
| 1765 | 9c02f1a2 | j_mayer | idx = 0;
|
| 1766 | 9c02f1a2 | j_mayer | goto update_rx_ptr;
|
| 1767 | 9c02f1a2 | j_mayer | case MAL0_RXCTP1R:
|
| 1768 | 9c02f1a2 | j_mayer | idx = 1;
|
| 1769 | 9c02f1a2 | j_mayer | update_rx_ptr:
|
| 1770 | 9c02f1a2 | j_mayer | mal->rxctpr[idx] = val; |
| 1771 | 9c02f1a2 | j_mayer | break;
|
| 1772 | 9c02f1a2 | j_mayer | case MAL0_RCBS0:
|
| 1773 | 9c02f1a2 | j_mayer | idx = 0;
|
| 1774 | 9c02f1a2 | j_mayer | goto update_rx_size;
|
| 1775 | 9c02f1a2 | j_mayer | case MAL0_RCBS1:
|
| 1776 | 9c02f1a2 | j_mayer | idx = 1;
|
| 1777 | 9c02f1a2 | j_mayer | update_rx_size:
|
| 1778 | 9c02f1a2 | j_mayer | mal->rcbs[idx] = val & 0x000000FF;
|
| 1779 | 9c02f1a2 | j_mayer | break;
|
| 1780 | 9c02f1a2 | j_mayer | } |
| 1781 | 9c02f1a2 | j_mayer | } |
| 1782 | 9c02f1a2 | j_mayer | |
| 1783 | 9c02f1a2 | j_mayer | static void ppc40x_mal_reset (void *opaque) |
| 1784 | 9c02f1a2 | j_mayer | {
|
| 1785 | 9c02f1a2 | j_mayer | ppc40x_mal_t *mal; |
| 1786 | 9c02f1a2 | j_mayer | |
| 1787 | 9c02f1a2 | j_mayer | mal = opaque; |
| 1788 | 9c02f1a2 | j_mayer | mal->cfg = 0x0007C000;
|
| 1789 | 9c02f1a2 | j_mayer | mal->esr = 0x00000000;
|
| 1790 | 9c02f1a2 | j_mayer | mal->ier = 0x00000000;
|
| 1791 | 9c02f1a2 | j_mayer | mal->rxcasr = 0x00000000;
|
| 1792 | 9c02f1a2 | j_mayer | mal->rxdeir = 0x00000000;
|
| 1793 | 9c02f1a2 | j_mayer | mal->rxeobisr = 0x00000000;
|
| 1794 | 9c02f1a2 | j_mayer | mal->txcasr = 0x00000000;
|
| 1795 | 9c02f1a2 | j_mayer | mal->txdeir = 0x00000000;
|
| 1796 | 9c02f1a2 | j_mayer | mal->txeobisr = 0x00000000;
|
| 1797 | 9c02f1a2 | j_mayer | } |
| 1798 | 9c02f1a2 | j_mayer | |
| 1799 | 9c02f1a2 | j_mayer | void ppc405_mal_init (CPUState *env, qemu_irq irqs[4]) |
| 1800 | 9c02f1a2 | j_mayer | {
|
| 1801 | 9c02f1a2 | j_mayer | ppc40x_mal_t *mal; |
| 1802 | 9c02f1a2 | j_mayer | int i;
|
| 1803 | 9c02f1a2 | j_mayer | |
| 1804 | 9c02f1a2 | j_mayer | mal = qemu_mallocz(sizeof(ppc40x_mal_t));
|
| 1805 | 9c02f1a2 | j_mayer | if (mal != NULL) { |
| 1806 | 9c02f1a2 | j_mayer | for (i = 0; i < 4; i++) |
| 1807 | 9c02f1a2 | j_mayer | mal->irqs[i] = irqs[i]; |
| 1808 | 9c02f1a2 | j_mayer | ppc40x_mal_reset(mal); |
| 1809 | 9c02f1a2 | j_mayer | qemu_register_reset(&ppc40x_mal_reset, mal); |
| 1810 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_CFG, |
| 1811 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
| 1812 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_ESR, |
| 1813 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
| 1814 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_IER, |
| 1815 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
| 1816 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_TXCASR, |
| 1817 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
| 1818 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_TXCARR, |
| 1819 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
| 1820 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_TXEOBISR, |
| 1821 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
| 1822 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_TXDEIR, |
| 1823 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
| 1824 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_RXCASR, |
| 1825 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
| 1826 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_RXCARR, |
| 1827 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
| 1828 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_RXEOBISR, |
| 1829 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
| 1830 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_RXDEIR, |
| 1831 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
| 1832 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_TXCTP0R, |
| 1833 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
| 1834 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_TXCTP1R, |
| 1835 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
| 1836 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_TXCTP2R, |
| 1837 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
| 1838 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_TXCTP3R, |
| 1839 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
| 1840 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_RXCTP0R, |
| 1841 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
| 1842 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_RXCTP1R, |
| 1843 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
| 1844 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_RCBS0, |
| 1845 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
| 1846 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_RCBS1, |
| 1847 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
| 1848 | 9c02f1a2 | j_mayer | } |
| 1849 | 9c02f1a2 | j_mayer | } |
| 1850 | 9c02f1a2 | j_mayer | |
| 1851 | 9c02f1a2 | j_mayer | /*****************************************************************************/
|
| 1852 | 8ecc7913 | j_mayer | /* SPR */
|
| 1853 | 8ecc7913 | j_mayer | void ppc40x_core_reset (CPUState *env)
|
| 1854 | 8ecc7913 | j_mayer | {
|
| 1855 | 8ecc7913 | j_mayer | target_ulong dbsr; |
| 1856 | 8ecc7913 | j_mayer | |
| 1857 | 8ecc7913 | j_mayer | printf("Reset PowerPC core\n");
|
| 1858 | ef397e88 | j_mayer | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
| 1859 | ef397e88 | j_mayer | /* XXX: TOFIX */
|
| 1860 | ef397e88 | j_mayer | #if 0
|
| 1861 | 8ecc7913 | j_mayer | cpu_ppc_reset(env);
|
| 1862 | ef397e88 | j_mayer | #else
|
| 1863 | ef397e88 | j_mayer | qemu_system_reset_request(); |
| 1864 | ef397e88 | j_mayer | #endif
|
| 1865 | 8ecc7913 | j_mayer | dbsr = env->spr[SPR_40x_DBSR]; |
| 1866 | 8ecc7913 | j_mayer | dbsr &= ~0x00000300;
|
| 1867 | 8ecc7913 | j_mayer | dbsr |= 0x00000100;
|
| 1868 | 8ecc7913 | j_mayer | env->spr[SPR_40x_DBSR] = dbsr; |
| 1869 | 8ecc7913 | j_mayer | } |
| 1870 | 8ecc7913 | j_mayer | |
| 1871 | 8ecc7913 | j_mayer | void ppc40x_chip_reset (CPUState *env)
|
| 1872 | 8ecc7913 | j_mayer | {
|
| 1873 | 8ecc7913 | j_mayer | target_ulong dbsr; |
| 1874 | 8ecc7913 | j_mayer | |
| 1875 | 8ecc7913 | j_mayer | printf("Reset PowerPC chip\n");
|
| 1876 | ef397e88 | j_mayer | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
| 1877 | ef397e88 | j_mayer | /* XXX: TOFIX */
|
| 1878 | ef397e88 | j_mayer | #if 0
|
| 1879 | 8ecc7913 | j_mayer | cpu_ppc_reset(env);
|
| 1880 | ef397e88 | j_mayer | #else
|
| 1881 | ef397e88 | j_mayer | qemu_system_reset_request(); |
| 1882 | ef397e88 | j_mayer | #endif
|
| 1883 | 8ecc7913 | j_mayer | /* XXX: TODO reset all internal peripherals */
|
| 1884 | 8ecc7913 | j_mayer | dbsr = env->spr[SPR_40x_DBSR]; |
| 1885 | 8ecc7913 | j_mayer | dbsr &= ~0x00000300;
|
| 1886 | 04f20795 | j_mayer | dbsr |= 0x00000200;
|
| 1887 | 8ecc7913 | j_mayer | env->spr[SPR_40x_DBSR] = dbsr; |
| 1888 | 8ecc7913 | j_mayer | } |
| 1889 | 8ecc7913 | j_mayer | |
| 1890 | 8ecc7913 | j_mayer | void ppc40x_system_reset (CPUState *env)
|
| 1891 | 8ecc7913 | j_mayer | {
|
| 1892 | 8ecc7913 | j_mayer | printf("Reset PowerPC system\n");
|
| 1893 | 8ecc7913 | j_mayer | qemu_system_reset_request(); |
| 1894 | 8ecc7913 | j_mayer | } |
| 1895 | 8ecc7913 | j_mayer | |
| 1896 | 8ecc7913 | j_mayer | void store_40x_dbcr0 (CPUState *env, uint32_t val)
|
| 1897 | 8ecc7913 | j_mayer | {
|
| 1898 | 8ecc7913 | j_mayer | switch ((val >> 28) & 0x3) { |
| 1899 | 8ecc7913 | j_mayer | case 0x0: |
| 1900 | 8ecc7913 | j_mayer | /* No action */
|
| 1901 | 8ecc7913 | j_mayer | break;
|
| 1902 | 8ecc7913 | j_mayer | case 0x1: |
| 1903 | 8ecc7913 | j_mayer | /* Core reset */
|
| 1904 | 8ecc7913 | j_mayer | ppc40x_core_reset(env); |
| 1905 | 8ecc7913 | j_mayer | break;
|
| 1906 | 8ecc7913 | j_mayer | case 0x2: |
| 1907 | 8ecc7913 | j_mayer | /* Chip reset */
|
| 1908 | 8ecc7913 | j_mayer | ppc40x_chip_reset(env); |
| 1909 | 8ecc7913 | j_mayer | break;
|
| 1910 | 8ecc7913 | j_mayer | case 0x3: |
| 1911 | 8ecc7913 | j_mayer | /* System reset */
|
| 1912 | 8ecc7913 | j_mayer | ppc40x_system_reset(env); |
| 1913 | 8ecc7913 | j_mayer | break;
|
| 1914 | 8ecc7913 | j_mayer | } |
| 1915 | 8ecc7913 | j_mayer | } |
| 1916 | 8ecc7913 | j_mayer | |
| 1917 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
| 1918 | 8ecc7913 | j_mayer | /* PowerPC 405CR */
|
| 1919 | 8ecc7913 | j_mayer | enum {
|
| 1920 | 8ecc7913 | j_mayer | PPC405CR_CPC0_PLLMR = 0x0B0,
|
| 1921 | 8ecc7913 | j_mayer | PPC405CR_CPC0_CR0 = 0x0B1,
|
| 1922 | 8ecc7913 | j_mayer | PPC405CR_CPC0_CR1 = 0x0B2,
|
| 1923 | 8ecc7913 | j_mayer | PPC405CR_CPC0_PSR = 0x0B4,
|
| 1924 | 8ecc7913 | j_mayer | PPC405CR_CPC0_JTAGID = 0x0B5,
|
| 1925 | 8ecc7913 | j_mayer | PPC405CR_CPC0_ER = 0x0B9,
|
| 1926 | 8ecc7913 | j_mayer | PPC405CR_CPC0_FR = 0x0BA,
|
| 1927 | 8ecc7913 | j_mayer | PPC405CR_CPC0_SR = 0x0BB,
|
| 1928 | 8ecc7913 | j_mayer | }; |
| 1929 | 8ecc7913 | j_mayer | |
| 1930 | 04f20795 | j_mayer | enum {
|
| 1931 | 04f20795 | j_mayer | PPC405CR_CPU_CLK = 0,
|
| 1932 | 04f20795 | j_mayer | PPC405CR_TMR_CLK = 1,
|
| 1933 | 04f20795 | j_mayer | PPC405CR_PLB_CLK = 2,
|
| 1934 | 04f20795 | j_mayer | PPC405CR_SDRAM_CLK = 3,
|
| 1935 | 04f20795 | j_mayer | PPC405CR_OPB_CLK = 4,
|
| 1936 | 04f20795 | j_mayer | PPC405CR_EXT_CLK = 5,
|
| 1937 | 04f20795 | j_mayer | PPC405CR_UART_CLK = 6,
|
| 1938 | 04f20795 | j_mayer | PPC405CR_CLK_NB = 7,
|
| 1939 | 04f20795 | j_mayer | }; |
| 1940 | 04f20795 | j_mayer | |
| 1941 | 8ecc7913 | j_mayer | typedef struct ppc405cr_cpc_t ppc405cr_cpc_t; |
| 1942 | 8ecc7913 | j_mayer | struct ppc405cr_cpc_t {
|
| 1943 | 04f20795 | j_mayer | clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
| 1944 | 8ecc7913 | j_mayer | uint32_t sysclk; |
| 1945 | 8ecc7913 | j_mayer | uint32_t psr; |
| 1946 | 8ecc7913 | j_mayer | uint32_t cr0; |
| 1947 | 8ecc7913 | j_mayer | uint32_t cr1; |
| 1948 | 8ecc7913 | j_mayer | uint32_t jtagid; |
| 1949 | 8ecc7913 | j_mayer | uint32_t pllmr; |
| 1950 | 8ecc7913 | j_mayer | uint32_t er; |
| 1951 | 8ecc7913 | j_mayer | uint32_t fr; |
| 1952 | 8ecc7913 | j_mayer | }; |
| 1953 | 8ecc7913 | j_mayer | |
| 1954 | 8ecc7913 | j_mayer | static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) |
| 1955 | 8ecc7913 | j_mayer | {
|
| 1956 | 8ecc7913 | j_mayer | uint64_t VCO_out, PLL_out; |
| 1957 | 8ecc7913 | j_mayer | uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk; |
| 1958 | 8ecc7913 | j_mayer | int M, D0, D1, D2;
|
| 1959 | 8ecc7913 | j_mayer | |
| 1960 | 8ecc7913 | j_mayer | D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */ |
| 1961 | 8ecc7913 | j_mayer | if (cpc->pllmr & 0x80000000) { |
| 1962 | 8ecc7913 | j_mayer | D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */ |
| 1963 | 8ecc7913 | j_mayer | D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */ |
| 1964 | 8ecc7913 | j_mayer | M = D0 * D1 * D2; |
| 1965 | 8ecc7913 | j_mayer | VCO_out = cpc->sysclk * M; |
| 1966 | 8ecc7913 | j_mayer | if (VCO_out < 400000000 || VCO_out > 800000000) { |
| 1967 | 8ecc7913 | j_mayer | /* PLL cannot lock */
|
| 1968 | 8ecc7913 | j_mayer | cpc->pllmr &= ~0x80000000;
|
| 1969 | 8ecc7913 | j_mayer | goto bypass_pll;
|
| 1970 | 8ecc7913 | j_mayer | } |
| 1971 | 8ecc7913 | j_mayer | PLL_out = VCO_out / D2; |
| 1972 | 8ecc7913 | j_mayer | } else {
|
| 1973 | 8ecc7913 | j_mayer | /* Bypass PLL */
|
| 1974 | 8ecc7913 | j_mayer | bypass_pll:
|
| 1975 | 8ecc7913 | j_mayer | M = D0; |
| 1976 | 8ecc7913 | j_mayer | PLL_out = cpc->sysclk * M; |
| 1977 | 8ecc7913 | j_mayer | } |
| 1978 | 8ecc7913 | j_mayer | CPU_clk = PLL_out; |
| 1979 | 8ecc7913 | j_mayer | if (cpc->cr1 & 0x00800000) |
| 1980 | 8ecc7913 | j_mayer | TMR_clk = cpc->sysclk; /* Should have a separate clock */
|
| 1981 | 8ecc7913 | j_mayer | else
|
| 1982 | 8ecc7913 | j_mayer | TMR_clk = CPU_clk; |
| 1983 | 8ecc7913 | j_mayer | PLB_clk = CPU_clk / D0; |
| 1984 | 8ecc7913 | j_mayer | SDRAM_clk = PLB_clk; |
| 1985 | 8ecc7913 | j_mayer | D0 = ((cpc->pllmr >> 10) & 0x3) + 1; |
| 1986 | 8ecc7913 | j_mayer | OPB_clk = PLB_clk / D0; |
| 1987 | 8ecc7913 | j_mayer | D0 = ((cpc->pllmr >> 24) & 0x3) + 2; |
| 1988 | 8ecc7913 | j_mayer | EXT_clk = PLB_clk / D0; |
| 1989 | 8ecc7913 | j_mayer | D0 = ((cpc->cr0 >> 1) & 0x1F) + 1; |
| 1990 | 8ecc7913 | j_mayer | UART_clk = CPU_clk / D0; |
| 1991 | 8ecc7913 | j_mayer | /* Setup CPU clocks */
|
| 1992 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk); |
| 1993 | 8ecc7913 | j_mayer | /* Setup time-base clock */
|
| 1994 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk); |
| 1995 | 8ecc7913 | j_mayer | /* Setup PLB clock */
|
| 1996 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk); |
| 1997 | 8ecc7913 | j_mayer | /* Setup SDRAM clock */
|
| 1998 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk); |
| 1999 | 8ecc7913 | j_mayer | /* Setup OPB clock */
|
| 2000 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk); |
| 2001 | 8ecc7913 | j_mayer | /* Setup external clock */
|
| 2002 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk); |
| 2003 | 8ecc7913 | j_mayer | /* Setup UART clock */
|
| 2004 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk); |
| 2005 | 8ecc7913 | j_mayer | } |
| 2006 | 8ecc7913 | j_mayer | |
| 2007 | 8ecc7913 | j_mayer | static target_ulong dcr_read_crcpc (void *opaque, int dcrn) |
| 2008 | 8ecc7913 | j_mayer | {
|
| 2009 | 8ecc7913 | j_mayer | ppc405cr_cpc_t *cpc; |
| 2010 | 8ecc7913 | j_mayer | target_ulong ret; |
| 2011 | 8ecc7913 | j_mayer | |
| 2012 | 8ecc7913 | j_mayer | cpc = opaque; |
| 2013 | 8ecc7913 | j_mayer | switch (dcrn) {
|
| 2014 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_PLLMR:
|
| 2015 | 8ecc7913 | j_mayer | ret = cpc->pllmr; |
| 2016 | 8ecc7913 | j_mayer | break;
|
| 2017 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_CR0:
|
| 2018 | 8ecc7913 | j_mayer | ret = cpc->cr0; |
| 2019 | 8ecc7913 | j_mayer | break;
|
| 2020 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_CR1:
|
| 2021 | 8ecc7913 | j_mayer | ret = cpc->cr1; |
| 2022 | 8ecc7913 | j_mayer | break;
|
| 2023 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_PSR:
|
| 2024 | 8ecc7913 | j_mayer | ret = cpc->psr; |
| 2025 | 8ecc7913 | j_mayer | break;
|
| 2026 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_JTAGID:
|
| 2027 | 8ecc7913 | j_mayer | ret = cpc->jtagid; |
| 2028 | 8ecc7913 | j_mayer | break;
|
| 2029 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_ER:
|
| 2030 | 8ecc7913 | j_mayer | ret = cpc->er; |
| 2031 | 8ecc7913 | j_mayer | break;
|
| 2032 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_FR:
|
| 2033 | 8ecc7913 | j_mayer | ret = cpc->fr; |
| 2034 | 8ecc7913 | j_mayer | break;
|
| 2035 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_SR:
|
| 2036 | 8ecc7913 | j_mayer | ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
|
| 2037 | 8ecc7913 | j_mayer | break;
|
| 2038 | 8ecc7913 | j_mayer | default:
|
| 2039 | 8ecc7913 | j_mayer | /* Avoid gcc warning */
|
| 2040 | 8ecc7913 | j_mayer | ret = 0;
|
| 2041 | 8ecc7913 | j_mayer | break;
|
| 2042 | 8ecc7913 | j_mayer | } |
| 2043 | 8ecc7913 | j_mayer | |
| 2044 | 8ecc7913 | j_mayer | return ret;
|
| 2045 | 8ecc7913 | j_mayer | } |
| 2046 | 8ecc7913 | j_mayer | |
| 2047 | 8ecc7913 | j_mayer | static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val) |
| 2048 | 8ecc7913 | j_mayer | {
|
| 2049 | 8ecc7913 | j_mayer | ppc405cr_cpc_t *cpc; |
| 2050 | 8ecc7913 | j_mayer | |
| 2051 | 8ecc7913 | j_mayer | cpc = opaque; |
| 2052 | 8ecc7913 | j_mayer | switch (dcrn) {
|
| 2053 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_PLLMR:
|
| 2054 | 8ecc7913 | j_mayer | cpc->pllmr = val & 0xFFF77C3F;
|
| 2055 | 8ecc7913 | j_mayer | break;
|
| 2056 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_CR0:
|
| 2057 | 8ecc7913 | j_mayer | cpc->cr0 = val & 0x0FFFFFFE;
|
| 2058 | 8ecc7913 | j_mayer | break;
|
| 2059 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_CR1:
|
| 2060 | 8ecc7913 | j_mayer | cpc->cr1 = val & 0x00800000;
|
| 2061 | 8ecc7913 | j_mayer | break;
|
| 2062 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_PSR:
|
| 2063 | 8ecc7913 | j_mayer | /* Read-only */
|
| 2064 | 8ecc7913 | j_mayer | break;
|
| 2065 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_JTAGID:
|
| 2066 | 8ecc7913 | j_mayer | /* Read-only */
|
| 2067 | 8ecc7913 | j_mayer | break;
|
| 2068 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_ER:
|
| 2069 | 8ecc7913 | j_mayer | cpc->er = val & 0xBFFC0000;
|
| 2070 | 8ecc7913 | j_mayer | break;
|
| 2071 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_FR:
|
| 2072 | 8ecc7913 | j_mayer | cpc->fr = val & 0xBFFC0000;
|
| 2073 | 8ecc7913 | j_mayer | break;
|
| 2074 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_SR:
|
| 2075 | 8ecc7913 | j_mayer | /* Read-only */
|
| 2076 | 8ecc7913 | j_mayer | break;
|
| 2077 | 8ecc7913 | j_mayer | } |
| 2078 | 8ecc7913 | j_mayer | } |
| 2079 | 8ecc7913 | j_mayer | |
| 2080 | 8ecc7913 | j_mayer | static void ppc405cr_cpc_reset (void *opaque) |
| 2081 | 8ecc7913 | j_mayer | {
|
| 2082 | 8ecc7913 | j_mayer | ppc405cr_cpc_t *cpc; |
| 2083 | 8ecc7913 | j_mayer | int D;
|
| 2084 | 8ecc7913 | j_mayer | |
| 2085 | 8ecc7913 | j_mayer | cpc = opaque; |
| 2086 | 8ecc7913 | j_mayer | /* Compute PLLMR value from PSR settings */
|
| 2087 | 8ecc7913 | j_mayer | cpc->pllmr = 0x80000000;
|
| 2088 | 8ecc7913 | j_mayer | /* PFWD */
|
| 2089 | 8ecc7913 | j_mayer | switch ((cpc->psr >> 30) & 3) { |
| 2090 | 8ecc7913 | j_mayer | case 0: |
| 2091 | 8ecc7913 | j_mayer | /* Bypass */
|
| 2092 | 8ecc7913 | j_mayer | cpc->pllmr &= ~0x80000000;
|
| 2093 | 8ecc7913 | j_mayer | break;
|
| 2094 | 8ecc7913 | j_mayer | case 1: |
| 2095 | 8ecc7913 | j_mayer | /* Divide by 3 */
|
| 2096 | 8ecc7913 | j_mayer | cpc->pllmr |= 5 << 16; |
| 2097 | 8ecc7913 | j_mayer | break;
|
| 2098 | 8ecc7913 | j_mayer | case 2: |
| 2099 | 8ecc7913 | j_mayer | /* Divide by 4 */
|
| 2100 | 8ecc7913 | j_mayer | cpc->pllmr |= 4 << 16; |
| 2101 | 8ecc7913 | j_mayer | break;
|
| 2102 | 8ecc7913 | j_mayer | case 3: |
| 2103 | 8ecc7913 | j_mayer | /* Divide by 6 */
|
| 2104 | 8ecc7913 | j_mayer | cpc->pllmr |= 2 << 16; |
| 2105 | 8ecc7913 | j_mayer | break;
|
| 2106 | 8ecc7913 | j_mayer | } |
| 2107 | 8ecc7913 | j_mayer | /* PFBD */
|
| 2108 | 8ecc7913 | j_mayer | D = (cpc->psr >> 28) & 3; |
| 2109 | 8ecc7913 | j_mayer | cpc->pllmr |= (D + 1) << 20; |
| 2110 | 8ecc7913 | j_mayer | /* PT */
|
| 2111 | 8ecc7913 | j_mayer | D = (cpc->psr >> 25) & 7; |
| 2112 | 8ecc7913 | j_mayer | switch (D) {
|
| 2113 | 8ecc7913 | j_mayer | case 0x2: |
| 2114 | 8ecc7913 | j_mayer | cpc->pllmr |= 0x13;
|
| 2115 | 8ecc7913 | j_mayer | break;
|
| 2116 | 8ecc7913 | j_mayer | case 0x4: |
| 2117 | 8ecc7913 | j_mayer | cpc->pllmr |= 0x15;
|
| 2118 | 8ecc7913 | j_mayer | break;
|
| 2119 | 8ecc7913 | j_mayer | case 0x5: |
| 2120 | 8ecc7913 | j_mayer | cpc->pllmr |= 0x16;
|
| 2121 | 8ecc7913 | j_mayer | break;
|
| 2122 | 8ecc7913 | j_mayer | default:
|
| 2123 | 8ecc7913 | j_mayer | break;
|
| 2124 | 8ecc7913 | j_mayer | } |
| 2125 | 8ecc7913 | j_mayer | /* PDC */
|
| 2126 | 8ecc7913 | j_mayer | D = (cpc->psr >> 23) & 3; |
| 2127 | 8ecc7913 | j_mayer | cpc->pllmr |= D << 26;
|
| 2128 | 8ecc7913 | j_mayer | /* ODP */
|
| 2129 | 8ecc7913 | j_mayer | D = (cpc->psr >> 21) & 3; |
| 2130 | 8ecc7913 | j_mayer | cpc->pllmr |= D << 10;
|
| 2131 | 8ecc7913 | j_mayer | /* EBPD */
|
| 2132 | 8ecc7913 | j_mayer | D = (cpc->psr >> 17) & 3; |
| 2133 | 8ecc7913 | j_mayer | cpc->pllmr |= D << 24;
|
| 2134 | 8ecc7913 | j_mayer | cpc->cr0 = 0x0000003C;
|
| 2135 | 8ecc7913 | j_mayer | cpc->cr1 = 0x2B0D8800;
|
| 2136 | 8ecc7913 | j_mayer | cpc->er = 0x00000000;
|
| 2137 | 8ecc7913 | j_mayer | cpc->fr = 0x00000000;
|
| 2138 | 8ecc7913 | j_mayer | ppc405cr_clk_setup(cpc); |
| 2139 | 8ecc7913 | j_mayer | } |
| 2140 | 8ecc7913 | j_mayer | |
| 2141 | 8ecc7913 | j_mayer | static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) |
| 2142 | 8ecc7913 | j_mayer | {
|
| 2143 | 8ecc7913 | j_mayer | int D;
|
| 2144 | 8ecc7913 | j_mayer | |
| 2145 | 8ecc7913 | j_mayer | /* XXX: this should be read from IO pins */
|
| 2146 | 8ecc7913 | j_mayer | cpc->psr = 0x00000000; /* 8 bits ROM */ |
| 2147 | 8ecc7913 | j_mayer | /* PFWD */
|
| 2148 | 8ecc7913 | j_mayer | D = 0x2; /* Divide by 4 */ |
| 2149 | 8ecc7913 | j_mayer | cpc->psr |= D << 30;
|
| 2150 | 8ecc7913 | j_mayer | /* PFBD */
|
| 2151 | 8ecc7913 | j_mayer | D = 0x1; /* Divide by 2 */ |
| 2152 | 8ecc7913 | j_mayer | cpc->psr |= D << 28;
|
| 2153 | 8ecc7913 | j_mayer | /* PDC */
|
| 2154 | 8ecc7913 | j_mayer | D = 0x1; /* Divide by 2 */ |
| 2155 | 8ecc7913 | j_mayer | cpc->psr |= D << 23;
|
| 2156 | 8ecc7913 | j_mayer | /* PT */
|
| 2157 | 8ecc7913 | j_mayer | D = 0x5; /* M = 16 */ |
| 2158 | 8ecc7913 | j_mayer | cpc->psr |= D << 25;
|
| 2159 | 8ecc7913 | j_mayer | /* ODP */
|
| 2160 | 8ecc7913 | j_mayer | D = 0x1; /* Divide by 2 */ |
| 2161 | 8ecc7913 | j_mayer | cpc->psr |= D << 21;
|
| 2162 | 8ecc7913 | j_mayer | /* EBDP */
|
| 2163 | 8ecc7913 | j_mayer | D = 0x2; /* Divide by 4 */ |
| 2164 | 8ecc7913 | j_mayer | cpc->psr |= D << 17;
|
| 2165 | 8ecc7913 | j_mayer | } |
| 2166 | 8ecc7913 | j_mayer | |
| 2167 | 8ecc7913 | j_mayer | static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], |
| 2168 | 8ecc7913 | j_mayer | uint32_t sysclk) |
| 2169 | 8ecc7913 | j_mayer | {
|
| 2170 | 8ecc7913 | j_mayer | ppc405cr_cpc_t *cpc; |
| 2171 | 8ecc7913 | j_mayer | |
| 2172 | 8ecc7913 | j_mayer | cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
|
| 2173 | 8ecc7913 | j_mayer | if (cpc != NULL) { |
| 2174 | 04f20795 | j_mayer | memcpy(cpc->clk_setup, clk_setup, |
| 2175 | 04f20795 | j_mayer | PPC405CR_CLK_NB * sizeof(clk_setup_t));
|
| 2176 | 8ecc7913 | j_mayer | cpc->sysclk = sysclk; |
| 2177 | 8ecc7913 | j_mayer | cpc->jtagid = 0x42051049;
|
| 2178 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, |
| 2179 | 8ecc7913 | j_mayer | &dcr_read_crcpc, &dcr_write_crcpc); |
| 2180 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc, |
| 2181 | 8ecc7913 | j_mayer | &dcr_read_crcpc, &dcr_write_crcpc); |
| 2182 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc, |
| 2183 | 8ecc7913 | j_mayer | &dcr_read_crcpc, &dcr_write_crcpc); |
| 2184 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc, |
| 2185 | 8ecc7913 | j_mayer | &dcr_read_crcpc, &dcr_write_crcpc); |
| 2186 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc, |
| 2187 | 8ecc7913 | j_mayer | &dcr_read_crcpc, &dcr_write_crcpc); |
| 2188 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc, |
| 2189 | 8ecc7913 | j_mayer | &dcr_read_crcpc, &dcr_write_crcpc); |
| 2190 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc, |
| 2191 | 8ecc7913 | j_mayer | &dcr_read_crcpc, &dcr_write_crcpc); |
| 2192 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, |
| 2193 | 8ecc7913 | j_mayer | &dcr_read_crcpc, &dcr_write_crcpc); |
| 2194 | 8ecc7913 | j_mayer | ppc405cr_clk_init(cpc); |
| 2195 | 8ecc7913 | j_mayer | qemu_register_reset(ppc405cr_cpc_reset, cpc); |
| 2196 | 8ecc7913 | j_mayer | ppc405cr_cpc_reset(cpc); |
| 2197 | 8ecc7913 | j_mayer | } |
| 2198 | 8ecc7913 | j_mayer | } |
| 2199 | 8ecc7913 | j_mayer | |
| 2200 | 71db710f | blueswir1 | CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
|
| 2201 | 71db710f | blueswir1 | target_phys_addr_t ram_sizes[4],
|
| 2202 | 8ecc7913 | j_mayer | uint32_t sysclk, qemu_irq **picp, |
| 2203 | 04f20795 | j_mayer | ram_addr_t *offsetp, int do_init)
|
| 2204 | 8ecc7913 | j_mayer | {
|
| 2205 | 04f20795 | j_mayer | clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
| 2206 | 8ecc7913 | j_mayer | qemu_irq dma_irqs[4];
|
| 2207 | 8ecc7913 | j_mayer | CPUState *env; |
| 2208 | 8ecc7913 | j_mayer | ppc4xx_mmio_t *mmio; |
| 2209 | 8ecc7913 | j_mayer | qemu_irq *pic, *irqs; |
| 2210 | 8ecc7913 | j_mayer | ram_addr_t offset; |
| 2211 | 8ecc7913 | j_mayer | int i;
|
| 2212 | 8ecc7913 | j_mayer | |
| 2213 | 8ecc7913 | j_mayer | memset(clk_setup, 0, sizeof(clk_setup)); |
| 2214 | 008ff9d7 | j_mayer | env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
|
| 2215 | 04f20795 | j_mayer | &clk_setup[PPC405CR_TMR_CLK], sysclk); |
| 2216 | 8ecc7913 | j_mayer | /* Memory mapped devices registers */
|
| 2217 | 8ecc7913 | j_mayer | mmio = ppc4xx_mmio_init(env, 0xEF600000);
|
| 2218 | 8ecc7913 | j_mayer | /* PLB arbitrer */
|
| 2219 | 8ecc7913 | j_mayer | ppc4xx_plb_init(env); |
| 2220 | 8ecc7913 | j_mayer | /* PLB to OPB bridge */
|
| 2221 | 8ecc7913 | j_mayer | ppc4xx_pob_init(env); |
| 2222 | 8ecc7913 | j_mayer | /* OBP arbitrer */
|
| 2223 | 8ecc7913 | j_mayer | ppc4xx_opba_init(env, mmio, 0x600);
|
| 2224 | 8ecc7913 | j_mayer | /* Universal interrupt controller */
|
| 2225 | 8ecc7913 | j_mayer | irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
|
| 2226 | 8ecc7913 | j_mayer | irqs[PPCUIC_OUTPUT_INT] = |
| 2227 | b48d7d69 | j_mayer | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
| 2228 | 8ecc7913 | j_mayer | irqs[PPCUIC_OUTPUT_CINT] = |
| 2229 | b48d7d69 | j_mayer | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
| 2230 | 8ecc7913 | j_mayer | pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
| 2231 | 8ecc7913 | j_mayer | *picp = pic; |
| 2232 | 8ecc7913 | j_mayer | /* SDRAM controller */
|
| 2233 | 80e8bd2b | aurel32 | ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); |
| 2234 | 8ecc7913 | j_mayer | offset = 0;
|
| 2235 | 8ecc7913 | j_mayer | for (i = 0; i < 4; i++) |
| 2236 | 8ecc7913 | j_mayer | offset += ram_sizes[i]; |
| 2237 | 8ecc7913 | j_mayer | /* External bus controller */
|
| 2238 | 8ecc7913 | j_mayer | ppc405_ebc_init(env); |
| 2239 | 8ecc7913 | j_mayer | /* DMA controller */
|
| 2240 | 04f20795 | j_mayer | dma_irqs[0] = pic[26]; |
| 2241 | 04f20795 | j_mayer | dma_irqs[1] = pic[25]; |
| 2242 | 04f20795 | j_mayer | dma_irqs[2] = pic[24]; |
| 2243 | 04f20795 | j_mayer | dma_irqs[3] = pic[23]; |
| 2244 | 8ecc7913 | j_mayer | ppc405_dma_init(env, dma_irqs); |
| 2245 | 8ecc7913 | j_mayer | /* Serial ports */
|
| 2246 | 8ecc7913 | j_mayer | if (serial_hds[0] != NULL) { |
| 2247 | 923e5e33 | aurel32 | ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]); |
| 2248 | 8ecc7913 | j_mayer | } |
| 2249 | 8ecc7913 | j_mayer | if (serial_hds[1] != NULL) { |
| 2250 | 923e5e33 | aurel32 | ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]); |
| 2251 | 8ecc7913 | j_mayer | } |
| 2252 | 8ecc7913 | j_mayer | /* IIC controller */
|
| 2253 | 923e5e33 | aurel32 | ppc405_i2c_init(env, mmio, 0x500, pic[2]); |
| 2254 | 8ecc7913 | j_mayer | /* GPIO */
|
| 2255 | 8ecc7913 | j_mayer | ppc405_gpio_init(env, mmio, 0x700);
|
| 2256 | 8ecc7913 | j_mayer | /* CPU control */
|
| 2257 | 8ecc7913 | j_mayer | ppc405cr_cpc_init(env, clk_setup, sysclk); |
| 2258 | 8ecc7913 | j_mayer | *offsetp = offset; |
| 2259 | 8ecc7913 | j_mayer | |
| 2260 | 8ecc7913 | j_mayer | return env;
|
| 2261 | 8ecc7913 | j_mayer | } |
| 2262 | 8ecc7913 | j_mayer | |
| 2263 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
| 2264 | 8ecc7913 | j_mayer | /* PowerPC 405EP */
|
| 2265 | 8ecc7913 | j_mayer | /* CPU control */
|
| 2266 | 8ecc7913 | j_mayer | enum {
|
| 2267 | 8ecc7913 | j_mayer | PPC405EP_CPC0_PLLMR0 = 0x0F0,
|
| 2268 | 8ecc7913 | j_mayer | PPC405EP_CPC0_BOOT = 0x0F1,
|
| 2269 | 8ecc7913 | j_mayer | PPC405EP_CPC0_EPCTL = 0x0F3,
|
| 2270 | 8ecc7913 | j_mayer | PPC405EP_CPC0_PLLMR1 = 0x0F4,
|
| 2271 | 8ecc7913 | j_mayer | PPC405EP_CPC0_UCR = 0x0F5,
|
| 2272 | 8ecc7913 | j_mayer | PPC405EP_CPC0_SRR = 0x0F6,
|
| 2273 | 8ecc7913 | j_mayer | PPC405EP_CPC0_JTAGID = 0x0F7,
|
| 2274 | 8ecc7913 | j_mayer | PPC405EP_CPC0_PCI = 0x0F9,
|
| 2275 | 9c02f1a2 | j_mayer | #if 0
|
| 2276 | 9c02f1a2 | j_mayer | PPC405EP_CPC0_ER = xxx,
|
| 2277 | 9c02f1a2 | j_mayer | PPC405EP_CPC0_FR = xxx,
|
| 2278 | 9c02f1a2 | j_mayer | PPC405EP_CPC0_SR = xxx,
|
| 2279 | 9c02f1a2 | j_mayer | #endif
|
| 2280 | 8ecc7913 | j_mayer | }; |
| 2281 | 8ecc7913 | j_mayer | |
| 2282 | 04f20795 | j_mayer | enum {
|
| 2283 | 04f20795 | j_mayer | PPC405EP_CPU_CLK = 0,
|
| 2284 | 04f20795 | j_mayer | PPC405EP_PLB_CLK = 1,
|
| 2285 | 04f20795 | j_mayer | PPC405EP_OPB_CLK = 2,
|
| 2286 | 04f20795 | j_mayer | PPC405EP_EBC_CLK = 3,
|
| 2287 | 04f20795 | j_mayer | PPC405EP_MAL_CLK = 4,
|
| 2288 | 04f20795 | j_mayer | PPC405EP_PCI_CLK = 5,
|
| 2289 | 04f20795 | j_mayer | PPC405EP_UART0_CLK = 6,
|
| 2290 | 04f20795 | j_mayer | PPC405EP_UART1_CLK = 7,
|
| 2291 | 04f20795 | j_mayer | PPC405EP_CLK_NB = 8,
|
| 2292 | 04f20795 | j_mayer | }; |
| 2293 | 04f20795 | j_mayer | |
| 2294 | 8ecc7913 | j_mayer | typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; |
| 2295 | 8ecc7913 | j_mayer | struct ppc405ep_cpc_t {
|
| 2296 | 8ecc7913 | j_mayer | uint32_t sysclk; |
| 2297 | 04f20795 | j_mayer | clk_setup_t clk_setup[PPC405EP_CLK_NB]; |
| 2298 | 8ecc7913 | j_mayer | uint32_t boot; |
| 2299 | 8ecc7913 | j_mayer | uint32_t epctl; |
| 2300 | 8ecc7913 | j_mayer | uint32_t pllmr[2];
|
| 2301 | 8ecc7913 | j_mayer | uint32_t ucr; |
| 2302 | 8ecc7913 | j_mayer | uint32_t srr; |
| 2303 | 8ecc7913 | j_mayer | uint32_t jtagid; |
| 2304 | 8ecc7913 | j_mayer | uint32_t pci; |
| 2305 | 9c02f1a2 | j_mayer | /* Clock and power management */
|
| 2306 | 9c02f1a2 | j_mayer | uint32_t er; |
| 2307 | 9c02f1a2 | j_mayer | uint32_t fr; |
| 2308 | 9c02f1a2 | j_mayer | uint32_t sr; |
| 2309 | 8ecc7913 | j_mayer | }; |
| 2310 | 8ecc7913 | j_mayer | |
| 2311 | 8ecc7913 | j_mayer | static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) |
| 2312 | 8ecc7913 | j_mayer | {
|
| 2313 | 8ecc7913 | j_mayer | uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; |
| 2314 | 8ecc7913 | j_mayer | uint32_t UART0_clk, UART1_clk; |
| 2315 | 8ecc7913 | j_mayer | uint64_t VCO_out, PLL_out; |
| 2316 | 8ecc7913 | j_mayer | int M, D;
|
| 2317 | 8ecc7913 | j_mayer | |
| 2318 | 8ecc7913 | j_mayer | VCO_out = 0;
|
| 2319 | 8ecc7913 | j_mayer | if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { |
| 2320 | 8ecc7913 | j_mayer | M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ |
| 2321 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
| 2322 | aae9366a | j_mayer | printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); |
| 2323 | aae9366a | j_mayer | #endif
|
| 2324 | 8ecc7913 | j_mayer | D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ |
| 2325 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
| 2326 | aae9366a | j_mayer | printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); |
| 2327 | aae9366a | j_mayer | #endif
|
| 2328 | 8ecc7913 | j_mayer | VCO_out = cpc->sysclk * M * D; |
| 2329 | 8ecc7913 | j_mayer | if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { |
| 2330 | 8ecc7913 | j_mayer | /* Error - unlock the PLL */
|
| 2331 | 8ecc7913 | j_mayer | printf("VCO out of range %" PRIu64 "\n", VCO_out); |
| 2332 | 8ecc7913 | j_mayer | #if 0
|
| 2333 | 8ecc7913 | j_mayer | cpc->pllmr[1] &= ~0x80000000;
|
| 2334 | 8ecc7913 | j_mayer | goto pll_bypass;
|
| 2335 | 8ecc7913 | j_mayer | #endif
|
| 2336 | 8ecc7913 | j_mayer | } |
| 2337 | 8ecc7913 | j_mayer | PLL_out = VCO_out / D; |
| 2338 | 9c02f1a2 | j_mayer | /* Pretend the PLL is locked */
|
| 2339 | 9c02f1a2 | j_mayer | cpc->boot |= 0x00000001;
|
| 2340 | 8ecc7913 | j_mayer | } else {
|
| 2341 | 8ecc7913 | j_mayer | #if 0
|
| 2342 | 8ecc7913 | j_mayer | pll_bypass:
|
| 2343 | 8ecc7913 | j_mayer | #endif
|
| 2344 | 8ecc7913 | j_mayer | PLL_out = cpc->sysclk; |
| 2345 | 9c02f1a2 | j_mayer | if (cpc->pllmr[1] & 0x40000000) { |
| 2346 | 9c02f1a2 | j_mayer | /* Pretend the PLL is not locked */
|
| 2347 | 9c02f1a2 | j_mayer | cpc->boot &= ~0x00000001;
|
| 2348 | 9c02f1a2 | j_mayer | } |
| 2349 | 8ecc7913 | j_mayer | } |
| 2350 | 8ecc7913 | j_mayer | /* Now, compute all other clocks */
|
| 2351 | 8ecc7913 | j_mayer | D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ |
| 2352 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
| 2353 | aae9366a | j_mayer | printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); |
| 2354 | 8ecc7913 | j_mayer | #endif
|
| 2355 | 8ecc7913 | j_mayer | CPU_clk = PLL_out / D; |
| 2356 | 8ecc7913 | j_mayer | D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ |
| 2357 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
| 2358 | aae9366a | j_mayer | printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); |
| 2359 | 8ecc7913 | j_mayer | #endif
|
| 2360 | 8ecc7913 | j_mayer | PLB_clk = CPU_clk / D; |
| 2361 | 8ecc7913 | j_mayer | D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ |
| 2362 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
| 2363 | aae9366a | j_mayer | printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); |
| 2364 | 8ecc7913 | j_mayer | #endif
|
| 2365 | 8ecc7913 | j_mayer | OPB_clk = PLB_clk / D; |
| 2366 | 8ecc7913 | j_mayer | D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ |
| 2367 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
| 2368 | aae9366a | j_mayer | printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); |
| 2369 | 8ecc7913 | j_mayer | #endif
|
| 2370 | 8ecc7913 | j_mayer | EBC_clk = PLB_clk / D; |
| 2371 | 8ecc7913 | j_mayer | D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ |
| 2372 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
| 2373 | aae9366a | j_mayer | printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); |
| 2374 | 8ecc7913 | j_mayer | #endif
|
| 2375 | 8ecc7913 | j_mayer | MAL_clk = PLB_clk / D; |
| 2376 | 8ecc7913 | j_mayer | D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ |
| 2377 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
| 2378 | aae9366a | j_mayer | printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D); |
| 2379 | 8ecc7913 | j_mayer | #endif
|
| 2380 | 8ecc7913 | j_mayer | PCI_clk = PLB_clk / D; |
| 2381 | 8ecc7913 | j_mayer | D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ |
| 2382 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
| 2383 | aae9366a | j_mayer | printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D); |
| 2384 | 8ecc7913 | j_mayer | #endif
|
| 2385 | 8ecc7913 | j_mayer | UART0_clk = PLL_out / D; |
| 2386 | 8ecc7913 | j_mayer | D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ |
| 2387 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
| 2388 | aae9366a | j_mayer | printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D); |
| 2389 | 8ecc7913 | j_mayer | #endif
|
| 2390 | 8ecc7913 | j_mayer | UART1_clk = PLL_out / D; |
| 2391 | 8ecc7913 | j_mayer | #ifdef DEBUG_CLOCKS
|
| 2392 | aae9366a | j_mayer | printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 |
| 2393 | 8ecc7913 | j_mayer | " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); |
| 2394 | aae9366a | j_mayer | printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 |
| 2395 | aae9366a | j_mayer | " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 |
| 2396 | aae9366a | j_mayer | " UART1 %" PRIu32 "\n", |
| 2397 | 8ecc7913 | j_mayer | CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, |
| 2398 | 8ecc7913 | j_mayer | UART0_clk, UART1_clk); |
| 2399 | 8ecc7913 | j_mayer | #endif
|
| 2400 | 8ecc7913 | j_mayer | /* Setup CPU clocks */
|
| 2401 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); |
| 2402 | 8ecc7913 | j_mayer | /* Setup PLB clock */
|
| 2403 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); |
| 2404 | 8ecc7913 | j_mayer | /* Setup OPB clock */
|
| 2405 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); |
| 2406 | 8ecc7913 | j_mayer | /* Setup external clock */
|
| 2407 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); |
| 2408 | 8ecc7913 | j_mayer | /* Setup MAL clock */
|
| 2409 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); |
| 2410 | 8ecc7913 | j_mayer | /* Setup PCI clock */
|
| 2411 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); |
| 2412 | 8ecc7913 | j_mayer | /* Setup UART0 clock */
|
| 2413 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); |
| 2414 | 8ecc7913 | j_mayer | /* Setup UART1 clock */
|
| 2415 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); |
| 2416 | 8ecc7913 | j_mayer | } |
| 2417 | 8ecc7913 | j_mayer | |
| 2418 | 8ecc7913 | j_mayer | static target_ulong dcr_read_epcpc (void *opaque, int dcrn) |
| 2419 | 8ecc7913 | j_mayer | {
|
| 2420 | 8ecc7913 | j_mayer | ppc405ep_cpc_t *cpc; |
| 2421 | 8ecc7913 | j_mayer | target_ulong ret; |
| 2422 | 8ecc7913 | j_mayer | |
| 2423 | 8ecc7913 | j_mayer | cpc = opaque; |
| 2424 | 8ecc7913 | j_mayer | switch (dcrn) {
|
| 2425 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_BOOT:
|
| 2426 | 8ecc7913 | j_mayer | ret = cpc->boot; |
| 2427 | 8ecc7913 | j_mayer | break;
|
| 2428 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_EPCTL:
|
| 2429 | 8ecc7913 | j_mayer | ret = cpc->epctl; |
| 2430 | 8ecc7913 | j_mayer | break;
|
| 2431 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_PLLMR0:
|
| 2432 | 8ecc7913 | j_mayer | ret = cpc->pllmr[0];
|
| 2433 | 8ecc7913 | j_mayer | break;
|
| 2434 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_PLLMR1:
|
| 2435 | 8ecc7913 | j_mayer | ret = cpc->pllmr[1];
|
| 2436 | 8ecc7913 | j_mayer | break;
|
| 2437 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_UCR:
|
| 2438 | 8ecc7913 | j_mayer | ret = cpc->ucr; |
| 2439 | 8ecc7913 | j_mayer | break;
|
| 2440 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_SRR:
|
| 2441 | 8ecc7913 | j_mayer | ret = cpc->srr; |
| 2442 | 8ecc7913 | j_mayer | break;
|
| 2443 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_JTAGID:
|
| 2444 | 8ecc7913 | j_mayer | ret = cpc->jtagid; |
| 2445 | 8ecc7913 | j_mayer | break;
|
| 2446 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_PCI:
|
| 2447 | 8ecc7913 | j_mayer | ret = cpc->pci; |
| 2448 | 8ecc7913 | j_mayer | break;
|
| 2449 | 8ecc7913 | j_mayer | default:
|
| 2450 | 8ecc7913 | j_mayer | /* Avoid gcc warning */
|
| 2451 | 8ecc7913 | j_mayer | ret = 0;
|
| 2452 | 8ecc7913 | j_mayer | break;
|
| 2453 | 8ecc7913 | j_mayer | } |
| 2454 | 8ecc7913 | j_mayer | |
| 2455 | 8ecc7913 | j_mayer | return ret;
|
| 2456 | 8ecc7913 | j_mayer | } |
| 2457 | 8ecc7913 | j_mayer | |
| 2458 | 8ecc7913 | j_mayer | static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val) |
| 2459 | 8ecc7913 | j_mayer | {
|
| 2460 | 8ecc7913 | j_mayer | ppc405ep_cpc_t *cpc; |
| 2461 | 8ecc7913 | j_mayer | |
| 2462 | 8ecc7913 | j_mayer | cpc = opaque; |
| 2463 | 8ecc7913 | j_mayer | switch (dcrn) {
|
| 2464 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_BOOT:
|
| 2465 | 8ecc7913 | j_mayer | /* Read-only register */
|
| 2466 | 8ecc7913 | j_mayer | break;
|
| 2467 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_EPCTL:
|
| 2468 | 8ecc7913 | j_mayer | /* Don't care for now */
|
| 2469 | 8ecc7913 | j_mayer | cpc->epctl = val & 0xC00000F3;
|
| 2470 | 8ecc7913 | j_mayer | break;
|
| 2471 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_PLLMR0:
|
| 2472 | 8ecc7913 | j_mayer | cpc->pllmr[0] = val & 0x00633333; |
| 2473 | 8ecc7913 | j_mayer | ppc405ep_compute_clocks(cpc); |
| 2474 | 8ecc7913 | j_mayer | break;
|
| 2475 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_PLLMR1:
|
| 2476 | 8ecc7913 | j_mayer | cpc->pllmr[1] = val & 0xC0F73FFF; |
| 2477 | 8ecc7913 | j_mayer | ppc405ep_compute_clocks(cpc); |
| 2478 | 8ecc7913 | j_mayer | break;
|
| 2479 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_UCR:
|
| 2480 | 8ecc7913 | j_mayer | /* UART control - don't care for now */
|
| 2481 | 8ecc7913 | j_mayer | cpc->ucr = val & 0x003F7F7F;
|
| 2482 | 8ecc7913 | j_mayer | break;
|
| 2483 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_SRR:
|
| 2484 | 8ecc7913 | j_mayer | cpc->srr = val; |
| 2485 | 8ecc7913 | j_mayer | break;
|
| 2486 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_JTAGID:
|
| 2487 | 8ecc7913 | j_mayer | /* Read-only */
|
| 2488 | 8ecc7913 | j_mayer | break;
|
| 2489 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_PCI:
|
| 2490 | 8ecc7913 | j_mayer | cpc->pci = val; |
| 2491 | 8ecc7913 | j_mayer | break;
|
| 2492 | 8ecc7913 | j_mayer | } |
| 2493 | 8ecc7913 | j_mayer | } |
| 2494 | 8ecc7913 | j_mayer | |
| 2495 | 8ecc7913 | j_mayer | static void ppc405ep_cpc_reset (void *opaque) |
| 2496 | 8ecc7913 | j_mayer | {
|
| 2497 | 8ecc7913 | j_mayer | ppc405ep_cpc_t *cpc = opaque; |
| 2498 | 8ecc7913 | j_mayer | |
| 2499 | 8ecc7913 | j_mayer | cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ |
| 2500 | 8ecc7913 | j_mayer | cpc->epctl = 0x00000000;
|
| 2501 | 8ecc7913 | j_mayer | cpc->pllmr[0] = 0x00011010; |
| 2502 | 8ecc7913 | j_mayer | cpc->pllmr[1] = 0x40000000; |
| 2503 | 8ecc7913 | j_mayer | cpc->ucr = 0x00000000;
|
| 2504 | 8ecc7913 | j_mayer | cpc->srr = 0x00040000;
|
| 2505 | 8ecc7913 | j_mayer | cpc->pci = 0x00000000;
|
| 2506 | 9c02f1a2 | j_mayer | cpc->er = 0x00000000;
|
| 2507 | 9c02f1a2 | j_mayer | cpc->fr = 0x00000000;
|
| 2508 | 9c02f1a2 | j_mayer | cpc->sr = 0x00000000;
|
| 2509 | 8ecc7913 | j_mayer | ppc405ep_compute_clocks(cpc); |
| 2510 | 8ecc7913 | j_mayer | } |
| 2511 | 8ecc7913 | j_mayer | |
| 2512 | 8ecc7913 | j_mayer | /* XXX: sysclk should be between 25 and 100 MHz */
|
| 2513 | 8ecc7913 | j_mayer | static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], |
| 2514 | 8ecc7913 | j_mayer | uint32_t sysclk) |
| 2515 | 8ecc7913 | j_mayer | {
|
| 2516 | 8ecc7913 | j_mayer | ppc405ep_cpc_t *cpc; |
| 2517 | 8ecc7913 | j_mayer | |
| 2518 | 8ecc7913 | j_mayer | cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
|
| 2519 | 8ecc7913 | j_mayer | if (cpc != NULL) { |
| 2520 | 04f20795 | j_mayer | memcpy(cpc->clk_setup, clk_setup, |
| 2521 | 04f20795 | j_mayer | PPC405EP_CLK_NB * sizeof(clk_setup_t));
|
| 2522 | 8ecc7913 | j_mayer | cpc->jtagid = 0x20267049;
|
| 2523 | 8ecc7913 | j_mayer | cpc->sysclk = sysclk; |
| 2524 | 8ecc7913 | j_mayer | ppc405ep_cpc_reset(cpc); |
| 2525 | 8ecc7913 | j_mayer | qemu_register_reset(&ppc405ep_cpc_reset, cpc); |
| 2526 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, |
| 2527 | 8ecc7913 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc); |
| 2528 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, |
| 2529 | 8ecc7913 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc); |
| 2530 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, |
| 2531 | 8ecc7913 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc); |
| 2532 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, |
| 2533 | 8ecc7913 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc); |
| 2534 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, |
| 2535 | 8ecc7913 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc); |
| 2536 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, |
| 2537 | 8ecc7913 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc); |
| 2538 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, |
| 2539 | 8ecc7913 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc); |
| 2540 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, |
| 2541 | 8ecc7913 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc); |
| 2542 | 9c02f1a2 | j_mayer | #if 0
|
| 2543 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
|
| 2544 | 9c02f1a2 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc);
|
| 2545 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
|
| 2546 | 9c02f1a2 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc);
|
| 2547 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
|
| 2548 | 9c02f1a2 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc);
|
| 2549 | 9c02f1a2 | j_mayer | #endif
|
| 2550 | 8ecc7913 | j_mayer | } |
| 2551 | 8ecc7913 | j_mayer | } |
| 2552 | 8ecc7913 | j_mayer | |
| 2553 | 71db710f | blueswir1 | CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
|
| 2554 | 71db710f | blueswir1 | target_phys_addr_t ram_sizes[2],
|
| 2555 | 8ecc7913 | j_mayer | uint32_t sysclk, qemu_irq **picp, |
| 2556 | 04f20795 | j_mayer | ram_addr_t *offsetp, int do_init)
|
| 2557 | 8ecc7913 | j_mayer | {
|
| 2558 | 9c02f1a2 | j_mayer | clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; |
| 2559 | 9c02f1a2 | j_mayer | qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; |
| 2560 | 8ecc7913 | j_mayer | CPUState *env; |
| 2561 | 8ecc7913 | j_mayer | ppc4xx_mmio_t *mmio; |
| 2562 | 8ecc7913 | j_mayer | qemu_irq *pic, *irqs; |
| 2563 | 8ecc7913 | j_mayer | ram_addr_t offset; |
| 2564 | 8ecc7913 | j_mayer | int i;
|
| 2565 | 8ecc7913 | j_mayer | |
| 2566 | 8ecc7913 | j_mayer | memset(clk_setup, 0, sizeof(clk_setup)); |
| 2567 | 8ecc7913 | j_mayer | /* init CPUs */
|
| 2568 | 008ff9d7 | j_mayer | env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
|
| 2569 | 9c02f1a2 | j_mayer | &tlb_clk_setup, sysclk); |
| 2570 | 9c02f1a2 | j_mayer | clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; |
| 2571 | 9c02f1a2 | j_mayer | clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; |
| 2572 | 8ecc7913 | j_mayer | /* Internal devices init */
|
| 2573 | 8ecc7913 | j_mayer | /* Memory mapped devices registers */
|
| 2574 | 8ecc7913 | j_mayer | mmio = ppc4xx_mmio_init(env, 0xEF600000);
|
| 2575 | 8ecc7913 | j_mayer | /* PLB arbitrer */
|
| 2576 | 8ecc7913 | j_mayer | ppc4xx_plb_init(env); |
| 2577 | 8ecc7913 | j_mayer | /* PLB to OPB bridge */
|
| 2578 | 8ecc7913 | j_mayer | ppc4xx_pob_init(env); |
| 2579 | 8ecc7913 | j_mayer | /* OBP arbitrer */
|
| 2580 | 8ecc7913 | j_mayer | ppc4xx_opba_init(env, mmio, 0x600);
|
| 2581 | 8ecc7913 | j_mayer | /* Universal interrupt controller */
|
| 2582 | 8ecc7913 | j_mayer | irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
|
| 2583 | 8ecc7913 | j_mayer | irqs[PPCUIC_OUTPUT_INT] = |
| 2584 | b48d7d69 | j_mayer | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
| 2585 | 8ecc7913 | j_mayer | irqs[PPCUIC_OUTPUT_CINT] = |
| 2586 | b48d7d69 | j_mayer | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
| 2587 | 8ecc7913 | j_mayer | pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
| 2588 | 8ecc7913 | j_mayer | *picp = pic; |
| 2589 | 8ecc7913 | j_mayer | /* SDRAM controller */
|
| 2590 | 923e5e33 | aurel32 | /* XXX 405EP has no ECC interrupt */
|
| 2591 | 80e8bd2b | aurel32 | ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); |
| 2592 | 8ecc7913 | j_mayer | offset = 0;
|
| 2593 | 8ecc7913 | j_mayer | for (i = 0; i < 2; i++) |
| 2594 | 8ecc7913 | j_mayer | offset += ram_sizes[i]; |
| 2595 | 8ecc7913 | j_mayer | /* External bus controller */
|
| 2596 | 8ecc7913 | j_mayer | ppc405_ebc_init(env); |
| 2597 | 8ecc7913 | j_mayer | /* DMA controller */
|
| 2598 | 923e5e33 | aurel32 | dma_irqs[0] = pic[5]; |
| 2599 | 923e5e33 | aurel32 | dma_irqs[1] = pic[6]; |
| 2600 | 923e5e33 | aurel32 | dma_irqs[2] = pic[7]; |
| 2601 | 923e5e33 | aurel32 | dma_irqs[3] = pic[8]; |
| 2602 | 8ecc7913 | j_mayer | ppc405_dma_init(env, dma_irqs); |
| 2603 | 8ecc7913 | j_mayer | /* IIC controller */
|
| 2604 | 923e5e33 | aurel32 | ppc405_i2c_init(env, mmio, 0x500, pic[2]); |
| 2605 | 8ecc7913 | j_mayer | /* GPIO */
|
| 2606 | 8ecc7913 | j_mayer | ppc405_gpio_init(env, mmio, 0x700);
|
| 2607 | 8ecc7913 | j_mayer | /* Serial ports */
|
| 2608 | 8ecc7913 | j_mayer | if (serial_hds[0] != NULL) { |
| 2609 | 923e5e33 | aurel32 | ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]); |
| 2610 | 8ecc7913 | j_mayer | } |
| 2611 | 8ecc7913 | j_mayer | if (serial_hds[1] != NULL) { |
| 2612 | 923e5e33 | aurel32 | ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]); |
| 2613 | 8ecc7913 | j_mayer | } |
| 2614 | 8ecc7913 | j_mayer | /* OCM */
|
| 2615 | 8ecc7913 | j_mayer | ppc405_ocm_init(env, ram_sizes[0] + ram_sizes[1]); |
| 2616 | 8ecc7913 | j_mayer | offset += 4096;
|
| 2617 | 9c02f1a2 | j_mayer | /* GPT */
|
| 2618 | 923e5e33 | aurel32 | gpt_irqs[0] = pic[19]; |
| 2619 | 923e5e33 | aurel32 | gpt_irqs[1] = pic[20]; |
| 2620 | 923e5e33 | aurel32 | gpt_irqs[2] = pic[21]; |
| 2621 | 923e5e33 | aurel32 | gpt_irqs[3] = pic[22]; |
| 2622 | 923e5e33 | aurel32 | gpt_irqs[4] = pic[23]; |
| 2623 | 9c02f1a2 | j_mayer | ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs);
|
| 2624 | 8ecc7913 | j_mayer | /* PCI */
|
| 2625 | 923e5e33 | aurel32 | /* Uses pic[3], pic[16], pic[18] */
|
| 2626 | 9c02f1a2 | j_mayer | /* MAL */
|
| 2627 | 923e5e33 | aurel32 | mal_irqs[0] = pic[11]; |
| 2628 | 923e5e33 | aurel32 | mal_irqs[1] = pic[12]; |
| 2629 | 923e5e33 | aurel32 | mal_irqs[2] = pic[13]; |
| 2630 | 923e5e33 | aurel32 | mal_irqs[3] = pic[14]; |
| 2631 | 9c02f1a2 | j_mayer | ppc405_mal_init(env, mal_irqs); |
| 2632 | 9c02f1a2 | j_mayer | /* Ethernet */
|
| 2633 | 923e5e33 | aurel32 | /* Uses pic[9], pic[15], pic[17] */
|
| 2634 | 8ecc7913 | j_mayer | /* CPU control */
|
| 2635 | 8ecc7913 | j_mayer | ppc405ep_cpc_init(env, clk_setup, sysclk); |
| 2636 | 8ecc7913 | j_mayer | *offsetp = offset; |
| 2637 | 8ecc7913 | j_mayer | |
| 2638 | 8ecc7913 | j_mayer | return env;
|
| 2639 | 8ecc7913 | j_mayer | } |