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/*

 *  PowerPC emulation cpu definitions for qemu.

 *

 *  Copyright (c) 2003-2007 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, see <http://www.gnu.org/licenses/>.

 */

#if !defined (__CPU_PPC_H__)

#define __CPU_PPC_H__

#include "config.h"

#include "qemu-common.h"

//#define PPC_EMULATE_32BITS_HYPV

#if defined (TARGET_PPC64)

/* PowerPC 64 definitions */

#define TARGET_LONG_BITS 64

#define TARGET_PAGE_BITS 12

/* Note that the official physical address space bits is 62-M where M

   is implementation dependent.  I've not looked up M for the set of

   cpus we emulate at the system level.  */

#define TARGET_PHYS_ADDR_SPACE_BITS 62

/* Note that the PPC environment architecture talks about 80 bit virtual

   addresses, with segmentation.  Obviously that's not all visible to a

   single process, which is all we're concerned with here.  */

#ifdef TARGET_ABI32

# define TARGET_VIRT_ADDR_SPACE_BITS 32

#else

# define TARGET_VIRT_ADDR_SPACE_BITS 64

#endif

#define TARGET_PAGE_BITS_16M 24

#else /* defined (TARGET_PPC64) */

/* PowerPC 32 definitions */

#define TARGET_LONG_BITS 32

#if defined(TARGET_PPCEMB)

/* Specific definitions for PowerPC embedded */

/* BookE have 36 bits physical address space */

#if defined(CONFIG_USER_ONLY)

/* It looks like a lot of Linux programs assume page size

 * is 4kB long. This is evil, but we have to deal with it...

 */

#define TARGET_PAGE_BITS 12

#else /* defined(CONFIG_USER_ONLY) */

/* Pages can be 1 kB small */

#define TARGET_PAGE_BITS 10

#endif /* defined(CONFIG_USER_ONLY) */

#else /* defined(TARGET_PPCEMB) */

/* "standard" PowerPC 32 definitions */

#define TARGET_PAGE_BITS 12

#endif /* defined(TARGET_PPCEMB) */

#define TARGET_PHYS_ADDR_SPACE_BITS 36

#define TARGET_VIRT_ADDR_SPACE_BITS 32

#endif /* defined (TARGET_PPC64) */

#define CPUArchState struct CPUPPCState

#include "cpu-defs.h"

#include "softfloat.h"

#define TARGET_HAS_ICE 1

#if defined (TARGET_PPC64)

#define ELF_MACHINE     EM_PPC64

#else

#define ELF_MACHINE     EM_PPC

#endif

/*****************************************************************************/

/* MMU model                                                                 */

typedef enum powerpc_mmu_t powerpc_mmu_t;

enum powerpc_mmu_t {

    POWERPC_MMU_UNKNOWN    = 0x00000000,

    /* Standard 32 bits PowerPC MMU                            */

    POWERPC_MMU_32B        = 0x00000001,

    /* PowerPC 6xx MMU with software TLB                       */

    POWERPC_MMU_SOFT_6xx   = 0x00000002,

    /* PowerPC 74xx MMU with software TLB                      */

    POWERPC_MMU_SOFT_74xx  = 0x00000003,

    /* PowerPC 4xx MMU with software TLB                       */

    POWERPC_MMU_SOFT_4xx   = 0x00000004,

    /* PowerPC 4xx MMU with software TLB and zones protections */

    POWERPC_MMU_SOFT_4xx_Z = 0x00000005,

    /* PowerPC MMU in real mode only                           */

    POWERPC_MMU_REAL       = 0x00000006,

    /* Freescale MPC8xx MMU model                              */

    POWERPC_MMU_MPC8xx     = 0x00000007,

    /* BookE MMU model                                         */

    POWERPC_MMU_BOOKE      = 0x00000008,

    /* BookE 2.06 MMU model                                    */

    POWERPC_MMU_BOOKE206   = 0x00000009,

    /* PowerPC 601 MMU model (specific BATs format)            */

    POWERPC_MMU_601        = 0x0000000A,

#if defined(TARGET_PPC64)

#define POWERPC_MMU_64       0x00010000

#define POWERPC_MMU_1TSEG    0x00020000

    /* 64 bits PowerPC MMU                                     */

    POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,

    /* 620 variant (no segment exceptions)                     */

    POWERPC_MMU_620        = POWERPC_MMU_64 | 0x00000002,

    /* Architecture 2.06 variant                               */

    POWERPC_MMU_2_06       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003,

#endif /* defined(TARGET_PPC64) */

};

/*****************************************************************************/

/* Exception model                                                           */

typedef enum powerpc_excp_t powerpc_excp_t;

enum powerpc_excp_t {

    POWERPC_EXCP_UNKNOWN   = 0,

    /* Standard PowerPC exception model */

    POWERPC_EXCP_STD,

    /* PowerPC 40x exception model      */

    POWERPC_EXCP_40x,

    /* PowerPC 601 exception model      */

    POWERPC_EXCP_601,

    /* PowerPC 602 exception model      */

    POWERPC_EXCP_602,

    /* PowerPC 603 exception model      */

    POWERPC_EXCP_603,

    /* PowerPC 603e exception model     */

    POWERPC_EXCP_603E,

    /* PowerPC G2 exception model       */

    POWERPC_EXCP_G2,

    /* PowerPC 604 exception model      */

    POWERPC_EXCP_604,

    /* PowerPC 7x0 exception model      */

    POWERPC_EXCP_7x0,

    /* PowerPC 7x5 exception model      */

    POWERPC_EXCP_7x5,

    /* PowerPC 74xx exception model     */

    POWERPC_EXCP_74xx,

    /* BookE exception model            */

    POWERPC_EXCP_BOOKE,

#if defined(TARGET_PPC64)

    /* PowerPC 970 exception model      */

    POWERPC_EXCP_970,

    /* POWER7 exception model           */

    POWERPC_EXCP_POWER7,

#endif /* defined(TARGET_PPC64) */

};

/*****************************************************************************/

/* Exception vectors definitions                                             */

enum {

    POWERPC_EXCP_NONE    = -1,

    /* The 64 first entries are used by the PowerPC embedded specification   */

    POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */

    POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */

    POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */

    POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */

    POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */

    POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */

    POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */

    POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */

    POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */

    POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */

    POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */

    POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */

    POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */

    POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */

    POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */

    POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */

    /* Vectors 16 to 31 are reserved                                         */

    POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */

    POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */

    POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */

    POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */

    POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */

    POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */

    POWERPC_EXCP_GDOORI   = 38, /* Embedded guest doorbell interrupt         */

    POWERPC_EXCP_GDOORCI  = 39, /* Embedded guest doorbell critical interrupt*/

    POWERPC_EXCP_HYPPRIV  = 41, /* Embedded hypervisor priv instruction      */

    /* Vectors 42 to 63 are reserved                                         */

    /* Exceptions defined in the PowerPC server specification                */

    POWERPC_EXCP_RESET    = 64, /* System reset exception                    */

    POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */

    POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */

    POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */

    POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */

    POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */

    POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */

    POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */

    POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */

    POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */

    /* 40x specific exceptions                                               */

    POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */

    /* 601 specific exceptions                                               */

    POWERPC_EXCP_IO       = 75, /* IO error exception                        */

    POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */

    /* 602 specific exceptions                                               */

    POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */

    /* 602/603 specific exceptions                                           */

    POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */

    POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */

    POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */

    /* Exceptions available on most PowerPC                                  */

    POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */

    POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */

    POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */

    POWERPC_EXCP_SMI      = 84, /* System management interrupt               */

    POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */

    /* 7xx/74xx specific exceptions                                          */

    POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */

    /* 74xx specific exceptions                                              */

    POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */

    /* 970FX specific exceptions                                             */

    POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */

    POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */

    /* Freescale embedded cores specific exceptions                          */

    POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */

    POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */

    POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */

    POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */

    /* EOL                                                                   */

    POWERPC_EXCP_NB       = 96,

    /* QEMU exceptions: used internally during code translation              */

    POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */

    POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */

    /* QEMU exceptions: special cases we want to stop translation            */

    POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */

    POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */

    POWERPC_EXCP_STCX         = 0x204 /* Conditional stores in user mode     */

};

/* Exceptions error codes                                                    */

enum {

    /* Exception subtypes for POWERPC_EXCP_ALIGN                             */

    POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */

    POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */

    POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */

    POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */

    POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */

    POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */

    /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */

    /* FP exceptions                                                         */

    POWERPC_EXCP_FP            = 0x10,

    POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */

    POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */

    POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */

    POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */

    POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */

    POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */

    POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */

    POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */

    POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */

    POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */

    POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */

    POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */

    POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */

    /* Invalid instruction                                                   */

    POWERPC_EXCP_INVAL         = 0x20,

    POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */

    POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */

    POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */

    POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */

    /* Privileged instruction                                                */

    POWERPC_EXCP_PRIV          = 0x30,

    POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */

    POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */

    /* Trap                                                                  */

    POWERPC_EXCP_TRAP          = 0x40,

};

/*****************************************************************************/

/* Input pins model                                                          */

typedef enum powerpc_input_t powerpc_input_t;

enum powerpc_input_t {

    PPC_FLAGS_INPUT_UNKNOWN = 0,

    /* PowerPC 6xx bus                  */

    PPC_FLAGS_INPUT_6xx,

    /* BookE bus                        */

    PPC_FLAGS_INPUT_BookE,

    /* PowerPC 405 bus                  */

    PPC_FLAGS_INPUT_405,

    /* PowerPC 970 bus                  */

    PPC_FLAGS_INPUT_970,

    /* PowerPC POWER7 bus               */

    PPC_FLAGS_INPUT_POWER7,

    /* PowerPC 401 bus                  */

    PPC_FLAGS_INPUT_401,

    /* Freescale RCPU bus               */

    PPC_FLAGS_INPUT_RCPU,

};

#define PPC_INPUT(env) (env->bus_model)

/*****************************************************************************/

typedef struct ppc_def_t ppc_def_t;

typedef struct opc_handler_t opc_handler_t;

/*****************************************************************************/

/* Types used to describe some PowerPC registers */

typedef struct CPUPPCState CPUPPCState;

typedef struct ppc_tb_t ppc_tb_t;

typedef struct ppc_spr_t ppc_spr_t;

typedef struct ppc_dcr_t ppc_dcr_t;

typedef union ppc_avr_t ppc_avr_t;

typedef union ppc_tlb_t ppc_tlb_t;

/* SPR access micro-ops generations callbacks */

struct ppc_spr_t {

    void (*uea_read)(void *opaque, int gpr_num, int spr_num);

    void (*uea_write)(void *opaque, int spr_num, int gpr_num);

#if !defined(CONFIG_USER_ONLY)

    void (*oea_read)(void *opaque, int gpr_num, int spr_num);

    void (*oea_write)(void *opaque, int spr_num, int gpr_num);

    void (*hea_read)(void *opaque, int gpr_num, int spr_num);

    void (*hea_write)(void *opaque, int spr_num, int gpr_num);

#endif

    const char *name;

};

/* Altivec registers (128 bits) */

union ppc_avr_t {

    float32 f[4];

    uint8_t u8[16];

    uint16_t u16[8];

    uint32_t u32[4];

    int8_t s8[16];

    int16_t s16[8];

    int32_t s32[4];

    uint64_t u64[2];

};

#if !defined(CONFIG_USER_ONLY)

/* Software TLB cache */

typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;

struct ppc6xx_tlb_t {

    target_ulong pte0;

    target_ulong pte1;

    target_ulong EPN;

};

typedef struct ppcemb_tlb_t ppcemb_tlb_t;

struct ppcemb_tlb_t {

    target_phys_addr_t RPN;

    target_ulong EPN;

    target_ulong PID;

    target_ulong size;

    uint32_t prot;

    uint32_t attr; /* Storage attributes */

};

typedef struct ppcmas_tlb_t {

     uint32_t mas8;

     uint32_t mas1;

     uint64_t mas2;

     uint64_t mas7_3;

} ppcmas_tlb_t;

union ppc_tlb_t {

    ppc6xx_tlb_t *tlb6;

    ppcemb_tlb_t *tlbe;

    ppcmas_tlb_t *tlbm;

};

/* possible TLB variants */

#define TLB_NONE               0

#define TLB_6XX                1

#define TLB_EMB                2

#define TLB_MAS                3

#endif

#define SDR_32_HTABORG         0xFFFF0000UL

#define SDR_32_HTABMASK        0x000001FFUL

#if defined(TARGET_PPC64)

#define SDR_64_HTABORG         0xFFFFFFFFFFFC0000ULL

#define SDR_64_HTABSIZE        0x000000000000001FULL

#endif /* defined(TARGET_PPC64 */

#define HASH_PTE_SIZE_32       8

#define HASH_PTE_SIZE_64       16

typedef struct ppc_slb_t ppc_slb_t;

struct ppc_slb_t {

    uint64_t esid;

    uint64_t vsid;

};

/* Bits in the SLB ESID word */

#define SLB_ESID_ESID           0xFFFFFFFFF0000000ULL

#define SLB_ESID_V              0x0000000008000000ULL /* valid */

/* Bits in the SLB VSID word */

#define SLB_VSID_SHIFT          12

#define SLB_VSID_SHIFT_1T       24

#define SLB_VSID_SSIZE_SHIFT    62

#define SLB_VSID_B              0xc000000000000000ULL

#define SLB_VSID_B_256M         0x0000000000000000ULL

#define SLB_VSID_B_1T           0x4000000000000000ULL

#define SLB_VSID_VSID           0x3FFFFFFFFFFFF000ULL

#define SLB_VSID_PTEM           (SLB_VSID_B | SLB_VSID_VSID)

#define SLB_VSID_KS             0x0000000000000800ULL

#define SLB_VSID_KP             0x0000000000000400ULL

#define SLB_VSID_N              0x0000000000000200ULL /* no-execute */

#define SLB_VSID_L              0x0000000000000100ULL

#define SLB_VSID_C              0x0000000000000080ULL /* class */

#define SLB_VSID_LP             0x0000000000000030ULL

#define SLB_VSID_ATTR           0x0000000000000FFFULL

#define SEGMENT_SHIFT_256M      28

#define SEGMENT_MASK_256M       (~((1ULL << SEGMENT_SHIFT_256M) - 1))

#define SEGMENT_SHIFT_1T        40

#define SEGMENT_MASK_1T         (~((1ULL << SEGMENT_SHIFT_1T) - 1))

/*****************************************************************************/

/* Machine state register bits definition                                    */

#define MSR_SF   63 /* Sixty-four-bit mode                            hflags */

#define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */

#define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */

#define MSR_SHV  60 /* hypervisor state                               hflags */

#define MSR_CM   31 /* Computation mode for BookE                     hflags */

#define MSR_ICM  30 /* Interrupt computation mode for BookE                  */

#define MSR_THV  29 /* hypervisor state for 32 bits PowerPC           hflags */

#define MSR_GS   28 /* guest state for BookE                                 */

#define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */

#define MSR_VR   25 /* altivec available                            x hflags */

#define MSR_SPE  25 /* SPE enable for BookE                         x hflags */

#define MSR_AP   23 /* Access privilege state on 602                  hflags */

#define MSR_SA   22 /* Supervisor access mode on 602                  hflags */

#define MSR_KEY  19 /* key bit on 603e                                       */

#define MSR_POW  18 /* Power management                                      */

#define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */

#define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */

#define MSR_ILE  16 /* Interrupt little-endian mode                          */

#define MSR_EE   15 /* External interrupt enable                             */

#define MSR_PR   14 /* Problem state                                  hflags */

#define MSR_FP   13 /* Floating point available                       hflags */

#define MSR_ME   12 /* Machine check interrupt enable                        */

#define MSR_FE0  11 /* Floating point exception mode 0                hflags */

#define MSR_SE   10 /* Single-step trace enable                     x hflags */

#define MSR_DWE  10 /* Debug wait enable on 405                     x        */

#define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */

#define MSR_BE   9  /* Branch trace enable                          x hflags */

#define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */

#define MSR_FE1  8  /* Floating point exception mode 1                hflags */

#define MSR_AL   7  /* AL bit on POWER                                       */

#define MSR_EP   6  /* Exception prefix on 601                               */

#define MSR_IR   5  /* Instruction relocate                                  */

#define MSR_DR   4  /* Data relocate                                         */

#define MSR_PE   3  /* Protection enable on 403                              */

#define MSR_PX   2  /* Protection exclusive on 403                  x        */

#define MSR_PMM  2  /* Performance monitor mark on POWER            x        */

#define MSR_RI   1  /* Recoverable interrupt                        1        */

#define MSR_LE   0  /* Little-endian mode                           1 hflags */

#define msr_sf   ((env->msr >> MSR_SF)   & 1)

#define msr_isf  ((env->msr >> MSR_ISF)  & 1)

#define msr_shv  ((env->msr >> MSR_SHV)  & 1)

#define msr_cm   ((env->msr >> MSR_CM)   & 1)

#define msr_icm  ((env->msr >> MSR_ICM)  & 1)

#define msr_thv  ((env->msr >> MSR_THV)  & 1)

#define msr_gs   ((env->msr >> MSR_GS)   & 1)

#define msr_ucle ((env->msr >> MSR_UCLE) & 1)

#define msr_vr   ((env->msr >> MSR_VR)   & 1)

#define msr_spe  ((env->msr >> MSR_SPE)  & 1)

#define msr_ap   ((env->msr >> MSR_AP)   & 1)

#define msr_sa   ((env->msr >> MSR_SA)   & 1)

#define msr_key  ((env->msr >> MSR_KEY)  & 1)

#define msr_pow  ((env->msr >> MSR_POW)  & 1)

#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)

#define msr_ce   ((env->msr >> MSR_CE)   & 1)

#define msr_ile  ((env->msr >> MSR_ILE)  & 1)

#define msr_ee   ((env->msr >> MSR_EE)   & 1)

#define msr_pr   ((env->msr >> MSR_PR)   & 1)

#define msr_fp   ((env->msr >> MSR_FP)   & 1)

#define msr_me   ((env->msr >> MSR_ME)   & 1)

#define msr_fe0  ((env->msr >> MSR_FE0)  & 1)

#define msr_se   ((env->msr >> MSR_SE)   & 1)

#define msr_dwe  ((env->msr >> MSR_DWE)  & 1)

#define msr_uble ((env->msr >> MSR_UBLE) & 1)

#define msr_be   ((env->msr >> MSR_BE)   & 1)

#define msr_de   ((env->msr >> MSR_DE)   & 1)

#define msr_fe1  ((env->msr >> MSR_FE1)  & 1)

#define msr_al   ((env->msr >> MSR_AL)   & 1)

#define msr_ep   ((env->msr >> MSR_EP)   & 1)

#define msr_ir   ((env->msr >> MSR_IR)   & 1)

#define msr_dr   ((env->msr >> MSR_DR)   & 1)

#define msr_pe   ((env->msr >> MSR_PE)   & 1)

#define msr_px   ((env->msr >> MSR_PX)   & 1)

#define msr_pmm  ((env->msr >> MSR_PMM)  & 1)

#define msr_ri   ((env->msr >> MSR_RI)   & 1)

#define msr_le   ((env->msr >> MSR_LE)   & 1)

/* Hypervisor bit is more specific */

#if defined(TARGET_PPC64)

#define MSR_HVB (1ULL << MSR_SHV)

#define msr_hv  msr_shv

#else

#if defined(PPC_EMULATE_32BITS_HYPV)

#define MSR_HVB (1ULL << MSR_THV)

#define msr_hv  msr_thv

#else

#define MSR_HVB (0ULL)

#define msr_hv  (0)

#endif

#endif

/* Exception state register bits definition                                  */

#define ESR_PIL   (1 << (63 - 36)) /* Illegal Instruction                    */

#define ESR_PPR   (1 << (63 - 37)) /* Privileged Instruction                 */

#define ESR_PTR   (1 << (63 - 38)) /* Trap                                   */

#define ESR_FP    (1 << (63 - 39)) /* Floating-Point Operation               */

#define ESR_ST    (1 << (63 - 40)) /* Store Operation                        */

#define ESR_AP    (1 << (63 - 44)) /* Auxiliary Processor Operation          */

#define ESR_PUO   (1 << (63 - 45)) /* Unimplemented Operation                */

#define ESR_BO    (1 << (63 - 46)) /* Byte Ordering                          */

#define ESR_PIE   (1 << (63 - 47)) /* Imprecise exception                    */

#define ESR_DATA  (1 << (63 - 53)) /* Data Access (Embedded page table)      */

#define ESR_TLBI  (1 << (63 - 54)) /* TLB Ineligible (Embedded page table)   */

#define ESR_PT    (1 << (63 - 55)) /* Page Table (Embedded page table)       */

#define ESR_SPV   (1 << (63 - 56)) /* SPE/VMX operation                      */

#define ESR_EPID  (1 << (63 - 57)) /* External Process ID operation          */

#define ESR_VLEMI (1 << (63 - 58)) /* VLE operation                          */

#define ESR_MIF   (1 << (63 - 62)) /* Misaligned instruction (VLE)           */

enum {

    POWERPC_FLAG_NONE     = 0x00000000,

    /* Flag for MSR bit 25 signification (VRE/SPE)                           */

    POWERPC_FLAG_SPE      = 0x00000001,

    POWERPC_FLAG_VRE      = 0x00000002,

    /* Flag for MSR bit 17 signification (TGPR/CE)                           */

    POWERPC_FLAG_TGPR     = 0x00000004,

    POWERPC_FLAG_CE       = 0x00000008,

    /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */

    POWERPC_FLAG_SE       = 0x00000010,

    POWERPC_FLAG_DWE      = 0x00000020,

    POWERPC_FLAG_UBLE     = 0x00000040,

    /* Flag for MSR bit 9 signification (BE/DE)                              */

    POWERPC_FLAG_BE       = 0x00000080,

    POWERPC_FLAG_DE       = 0x00000100,

    /* Flag for MSR bit 2 signification (PX/PMM)                             */

    POWERPC_FLAG_PX       = 0x00000200,

    POWERPC_FLAG_PMM      = 0x00000400,

    /* Flag for special features                                             */

    /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */

    POWERPC_FLAG_RTC_CLK  = 0x00010000,

    POWERPC_FLAG_BUS_CLK  = 0x00020000,

    /* Has CFAR                                                              */

    POWERPC_FLAG_CFAR     = 0x00040000,

};

/*****************************************************************************/

/* Floating point status and control register                                */

#define FPSCR_FX     31 /* Floating-point exception summary                  */

#define FPSCR_FEX    30 /* Floating-point enabled exception summary          */

#define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */

#define FPSCR_OX     28 /* Floating-point overflow exception                 */

#define FPSCR_UX     27 /* Floating-point underflow exception                */

#define FPSCR_ZX     26 /* Floating-point zero divide exception              */

#define FPSCR_XX     25 /* Floating-point inexact exception                  */

#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */

#define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */

#define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */

#define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */

#define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */

#define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */

#define FPSCR_FR     18 /* Floating-point fraction rounded                   */

#define FPSCR_FI     17 /* Floating-point fraction inexact                   */

#define FPSCR_C      16 /* Floating-point result class descriptor            */

#define FPSCR_FL     15 /* Floating-point less than or negative              */

#define FPSCR_FG     14 /* Floating-point greater than or negative           */

#define FPSCR_FE     13 /* Floating-point equal or zero                      */

#define FPSCR_FU     12 /* Floating-point unordered or NaN                   */

#define FPSCR_FPCC   12 /* Floating-point condition code                     */

#define FPSCR_FPRF   12 /* Floating-point result flags                       */

#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */

#define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */

#define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */

#define FPSCR_VE     7  /* Floating-point invalid operation exception enable */

#define FPSCR_OE     6  /* Floating-point overflow exception enable          */

#define FPSCR_UE     5  /* Floating-point undeflow exception enable          */

#define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */

#define FPSCR_XE     3  /* Floating-point inexact exception enable           */

#define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */

#define FPSCR_RN1    1

#define FPSCR_RN     0  /* Floating-point rounding control                   */

#define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)

#define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)

#define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)

#define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)

#define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)

#define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)

#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)

#define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)

#define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)

#define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)

#define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)

#define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)

#define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)

#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)

#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)

#define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)

#define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)

#define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)

#define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)

#define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)

#define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)

#define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)

#define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)

/* Invalid operation exception summary */

#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \

                                  (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \

                                  (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \

                                  (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \

                                  (1 << FPSCR_VXCVI)))

/* exception summary */

#define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)

/* enabled exception summary */

#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \

                   0x1F)

/*****************************************************************************/

/* Vector status and control register */

#define VSCR_NJ                16 /* Vector non-java */

#define VSCR_SAT        0 /* Vector saturation */

#define vscr_nj                (((env->vscr) >> VSCR_NJ)        & 0x1)

#define vscr_sat        (((env->vscr) >> VSCR_SAT)        & 0x1)

/*****************************************************************************/

/* BookE e500 MMU registers */

#define MAS0_NV_SHIFT      0

#define MAS0_NV_MASK       (0xfff << MAS0_NV_SHIFT)

#define MAS0_WQ_SHIFT      12

#define MAS0_WQ_MASK       (3 << MAS0_WQ_SHIFT)

/* Write TLB entry regardless of reservation */

#define MAS0_WQ_ALWAYS     (0 << MAS0_WQ_SHIFT)

/* Write TLB entry only already in use */

#define MAS0_WQ_COND       (1 << MAS0_WQ_SHIFT)

/* Clear TLB entry */

#define MAS0_WQ_CLR_RSRV   (2 << MAS0_WQ_SHIFT)

#define MAS0_HES_SHIFT     14

#define MAS0_HES           (1 << MAS0_HES_SHIFT)

#define MAS0_ESEL_SHIFT    16

#define MAS0_ESEL_MASK     (0xfff << MAS0_ESEL_SHIFT)

#define MAS0_TLBSEL_SHIFT  28

#define MAS0_TLBSEL_MASK   (3 << MAS0_TLBSEL_SHIFT)

#define MAS0_TLBSEL_TLB0   (0 << MAS0_TLBSEL_SHIFT)

#define MAS0_TLBSEL_TLB1   (1 << MAS0_TLBSEL_SHIFT)

#define MAS0_TLBSEL_TLB2   (2 << MAS0_TLBSEL_SHIFT)

#define MAS0_TLBSEL_TLB3   (3 << MAS0_TLBSEL_SHIFT)

#define MAS0_ATSEL_SHIFT   31

#define MAS0_ATSEL         (1 << MAS0_ATSEL_SHIFT)

#define MAS0_ATSEL_TLB     0

#define MAS0_ATSEL_LRAT    MAS0_ATSEL

#define MAS1_TSIZE_SHIFT   7

#define MAS1_TSIZE_MASK    (0x1f << MAS1_TSIZE_SHIFT)

#define MAS1_TS_SHIFT      12

#define MAS1_TS            (1 << MAS1_TS_SHIFT)

#define MAS1_IND_SHIFT     13

#define MAS1_IND           (1 << MAS1_IND_SHIFT)

#define MAS1_TID_SHIFT     16

#define MAS1_TID_MASK      (0x3fff << MAS1_TID_SHIFT)

#define MAS1_IPROT_SHIFT   30

#define MAS1_IPROT         (1 << MAS1_IPROT_SHIFT)

#define MAS1_VALID_SHIFT   31

#define MAS1_VALID         0x80000000

#define MAS2_EPN_SHIFT     12

#define MAS2_EPN_MASK      (0xfffff << MAS2_EPN_SHIFT)

#define MAS2_ACM_SHIFT     6

#define MAS2_ACM           (1 << MAS2_ACM_SHIFT)

#define MAS2_VLE_SHIFT     5

#define MAS2_VLE           (1 << MAS2_VLE_SHIFT)

#define MAS2_W_SHIFT       4

#define MAS2_W             (1 << MAS2_W_SHIFT)

#define MAS2_I_SHIFT       3

#define MAS2_I             (1 << MAS2_I_SHIFT)

#define MAS2_M_SHIFT       2

#define MAS2_M             (1 << MAS2_M_SHIFT)

#define MAS2_G_SHIFT       1

#define MAS2_G             (1 << MAS2_G_SHIFT)

#define MAS2_E_SHIFT       0

#define MAS2_E             (1 << MAS2_E_SHIFT)

#define MAS3_RPN_SHIFT     12

#define MAS3_RPN_MASK      (0xfffff << MAS3_RPN_SHIFT)

#define MAS3_U0                 0x00000200

#define MAS3_U1                 0x00000100

#define MAS3_U2                 0x00000080

#define MAS3_U3                 0x00000040

#define MAS3_UX                 0x00000020

#define MAS3_SX                 0x00000010

#define MAS3_UW                 0x00000008

#define MAS3_SW                 0x00000004

#define MAS3_UR                 0x00000002

#define MAS3_SR                 0x00000001

#define MAS3_SPSIZE_SHIFT       1

#define MAS3_SPSIZE_MASK        (0x3e << MAS3_SPSIZE_SHIFT)

#define MAS4_TLBSELD_SHIFT      MAS0_TLBSEL_SHIFT

#define MAS4_TLBSELD_MASK       MAS0_TLBSEL_MASK

#define MAS4_TIDSELD_MASK       0x00030000

#define MAS4_TIDSELD_PID0       0x00000000

#define MAS4_TIDSELD_PID1       0x00010000

#define MAS4_TIDSELD_PID2       0x00020000

#define MAS4_TIDSELD_PIDZ       0x00030000

#define MAS4_INDD               0x00008000      /* Default IND */

#define MAS4_TSIZED_SHIFT       MAS1_TSIZE_SHIFT

#define MAS4_TSIZED_MASK        MAS1_TSIZE_MASK

#define MAS4_ACMD               0x00000040

#define MAS4_VLED               0x00000020

#define MAS4_WD                 0x00000010

#define MAS4_ID                 0x00000008

#define MAS4_MD                 0x00000004

#define MAS4_GD                 0x00000002

#define MAS4_ED                 0x00000001

#define MAS4_WIMGED_MASK        0x0000001f      /* Default WIMGE */

#define MAS4_WIMGED_SHIFT       0

#define MAS5_SGS                0x80000000

#define MAS5_SLPID_MASK         0x00000fff

#define MAS6_SPID0              0x3fff0000

#define MAS6_SPID1              0x00007ffe

#define MAS6_ISIZE(x)           MAS1_TSIZE(x)

#define MAS6_SAS                0x00000001

#define MAS6_SPID               MAS6_SPID0

#define MAS6_SIND               0x00000002      /* Indirect page */

#define MAS6_SIND_SHIFT         1

#define MAS6_SPID_MASK          0x3fff0000

#define MAS6_SPID_SHIFT         16

#define MAS6_ISIZE_MASK         0x00000f80

#define MAS6_ISIZE_SHIFT        7

#define MAS7_RPN                0xffffffff

#define MAS8_TGS                0x80000000

#define MAS8_VF                 0x40000000

#define MAS8_TLBPID             0x00000fff

/* Bit definitions for MMUCFG */

#define MMUCFG_MAVN     0x00000003      /* MMU Architecture Version Number */

#define MMUCFG_MAVN_V1  0x00000000      /* v1.0 */

#define MMUCFG_MAVN_V2  0x00000001      /* v2.0 */

#define MMUCFG_NTLBS    0x0000000c      /* Number of TLBs */

#define MMUCFG_PIDSIZE  0x000007c0      /* PID Reg Size */

#define MMUCFG_TWC      0x00008000      /* TLB Write Conditional (v2.0) */

#define MMUCFG_LRAT     0x00010000      /* LRAT Supported (v2.0) */

#define MMUCFG_RASIZE   0x00fe0000      /* Real Addr Size */

#define MMUCFG_LPIDSIZE 0x0f000000      /* LPID Reg Size */

/* Bit definitions for MMUCSR0 */

#define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */

#define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */

#define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */

#define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */

#define MMUCSR0_TLBFI   (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \

                         MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)

#define MMUCSR0_TLB0PS  0x00000780      /* TLB0 Page Size */

#define MMUCSR0_TLB1PS  0x00007800      /* TLB1 Page Size */

#define MMUCSR0_TLB2PS  0x00078000      /* TLB2 Page Size */

#define MMUCSR0_TLB3PS  0x00780000      /* TLB3 Page Size */

/* TLBnCFG encoding */

#define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */

#define TLBnCFG_HES             0x00002000      /* HW select supported */

#define TLBnCFG_AVAIL           0x00004000      /* variable page size */

#define TLBnCFG_IPROT           0x00008000      /* IPROT supported */

#define TLBnCFG_GTWE            0x00010000      /* Guest can write */

#define TLBnCFG_IND             0x00020000      /* IND entries supported */

#define TLBnCFG_PT              0x00040000      /* Can load from page table */

#define TLBnCFG_MINSIZE         0x00f00000      /* Minimum Page Size (v1.0) */

#define TLBnCFG_MINSIZE_SHIFT   20

#define TLBnCFG_MAXSIZE         0x000f0000      /* Maximum Page Size (v1.0) */

#define TLBnCFG_MAXSIZE_SHIFT   16

#define TLBnCFG_ASSOC           0xff000000      /* Associativity */

#define TLBnCFG_ASSOC_SHIFT     24

/* TLBnPS encoding */

#define TLBnPS_4K               0x00000004

#define TLBnPS_8K               0x00000008

#define TLBnPS_16K              0x00000010

#define TLBnPS_32K              0x00000020

#define TLBnPS_64K              0x00000040

#define TLBnPS_128K             0x00000080

#define TLBnPS_256K             0x00000100

#define TLBnPS_512K             0x00000200

#define TLBnPS_1M               0x00000400

#define TLBnPS_2M               0x00000800

#define TLBnPS_4M               0x00001000

#define TLBnPS_8M               0x00002000

#define TLBnPS_16M              0x00004000

#define TLBnPS_32M              0x00008000

#define TLBnPS_64M              0x00010000

#define TLBnPS_128M             0x00020000

#define TLBnPS_256M             0x00040000

#define TLBnPS_512M             0x00080000

#define TLBnPS_1G               0x00100000

#define TLBnPS_2G               0x00200000

#define TLBnPS_4G               0x00400000

#define TLBnPS_8G               0x00800000

#define TLBnPS_16G              0x01000000

#define TLBnPS_32G              0x02000000

#define TLBnPS_64G              0x04000000

#define TLBnPS_128G             0x08000000

#define TLBnPS_256G             0x10000000

/* tlbilx action encoding */

#define TLBILX_T_ALL                    0

#define TLBILX_T_TID                    1

#define TLBILX_T_FULLMATCH              3

#define TLBILX_T_CLASS0                 4

#define TLBILX_T_CLASS1                 5

#define TLBILX_T_CLASS2                 6

#define TLBILX_T_CLASS3                 7

/* BookE 2.06 helper defines */

#define BOOKE206_FLUSH_TLB0    (1 << 0)

#define BOOKE206_FLUSH_TLB1    (1 << 1)

#define BOOKE206_FLUSH_TLB2    (1 << 2)

#define BOOKE206_FLUSH_TLB3    (1 << 3)

/* number of possible TLBs */

#define BOOKE206_MAX_TLBN      4

/*****************************************************************************/

/* Embedded.Processor Control */

#define DBELL_TYPE_SHIFT               27

#define DBELL_TYPE_MASK                (0x1f << DBELL_TYPE_SHIFT)

#define DBELL_TYPE_DBELL               (0x00 << DBELL_TYPE_SHIFT)

#define DBELL_TYPE_DBELL_CRIT          (0x01 << DBELL_TYPE_SHIFT)

#define DBELL_TYPE_G_DBELL             (0x02 << DBELL_TYPE_SHIFT)

#define DBELL_TYPE_G_DBELL_CRIT        (0x03 << DBELL_TYPE_SHIFT)

#define DBELL_TYPE_G_DBELL_MC          (0x04 << DBELL_TYPE_SHIFT)

#define DBELL_BRDCAST                  (1 << 26)

#define DBELL_LPIDTAG_SHIFT            14

#define DBELL_LPIDTAG_MASK             (0xfff << DBELL_LPIDTAG_SHIFT)

#define DBELL_PIRTAG_MASK              0x3fff

/*****************************************************************************/

/* The whole PowerPC CPU context */

#define NB_MMU_MODES 3

struct ppc_def_t {

    const char *name;

    uint32_t pvr;

    uint32_t svr;

    uint64_t insns_flags;

    uint64_t insns_flags2;

    uint64_t msr_mask;

    powerpc_mmu_t   mmu_model;

    powerpc_excp_t  excp_model;

    powerpc_input_t bus_model;

    uint32_t flags;

    int bfd_mach;

    void (*init_proc)(CPUPPCState *env);

    int  (*check_pow)(CPUPPCState *env);

};

struct CPUPPCState {

    /* First are the most commonly used resources

     * during translated code execution

     */

    /* general purpose registers */

    target_ulong gpr[32];

#if !defined(TARGET_PPC64)

    /* Storage for GPR MSB, used by the SPE extension */

    target_ulong gprh[32];

#endif

    /* LR */

    target_ulong lr;

    /* CTR */

    target_ulong ctr;

    /* condition register */

    uint32_t crf[8];

#if defined(TARGET_PPC64)

    /* CFAR */

    target_ulong cfar;

#endif

    /* XER */

    target_ulong xer;

    /* Reservation address */

    target_ulong reserve_addr;

    /* Reservation value */

    target_ulong reserve_val;

    /* Reservation store address */

    target_ulong reserve_ea;

    /* Reserved store source register and size */

    target_ulong reserve_info;

    /* Those ones are used in supervisor mode only */

    /* machine state register */

    target_ulong msr;

    /* temporary general purpose registers */

    target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */

    /* Floating point execution context */

    float_status fp_status;

    /* floating point registers */

    float64 fpr[32];

    /* floating point status and control register */

    uint32_t fpscr;

    /* Next instruction pointer */

    target_ulong nip;

    int access_type; /* when a memory exception occurs, the access

                        type is stored here */

    CPU_COMMON

    /* MMU context - only relevant for full system emulation */

#if !defined(CONFIG_USER_ONLY)

#if defined(TARGET_PPC64)

    /* Address space register */

    target_ulong asr;

    /* PowerPC 64 SLB area */

    ppc_slb_t slb[64];

    int slb_nr;

#endif

    /* segment registers */

    target_phys_addr_t htab_base;

    target_phys_addr_t htab_mask;

    target_ulong sr[32];

    /* externally stored hash table */

    uint8_t *external_htab;

    /* BATs */

    int nb_BATs;

    target_ulong DBAT[2][8];

    target_ulong IBAT[2][8];

    /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */

    int nb_tlb;      /* Total number of TLB                                  */

    int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */

    int nb_ways;     /* Number of ways in the TLB set                        */

    int last_way;    /* Last used way used to allocate TLB in a LRU way      */

    int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */

    int nb_pids;     /* Number of available PID registers                    */

    int tlb_type;    /* Type of TLB we're dealing with                       */

    ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed        */

    /* 403 dedicated access protection registers */

    target_ulong pb[4];

    bool tlb_dirty;   /* Set to non-zero when modifying TLB                  */

    bool kvm_sw_tlb;  /* non-zero if KVM SW TLB API is active                */

#endif

    /* Other registers */

    /* Special purpose registers */

    target_ulong spr[1024];

    ppc_spr_t spr_cb[1024];

    /* Altivec registers */

    ppc_avr_t avr[32];

    uint32_t vscr;

    /* SPE registers */

    uint64_t spe_acc;

    uint32_t spe_fscr;

    /* SPE and Altivec can share a status since they will never be used

     * simultaneously */

    float_status vec_status;

    /* Internal devices resources */

    /* Time base and decrementer */

    ppc_tb_t *tb_env;

    /* Device control registers */

    ppc_dcr_t *dcr_env;

    int dcache_line_size;

    int icache_line_size;

    /* Those resources are used during exception processing */

    /* CPU model definition */

    target_ulong msr_mask;

    powerpc_mmu_t mmu_model;

    powerpc_excp_t excp_model;

    powerpc_input_t bus_model;

    int bfd_mach;

    uint32_t flags;

    uint64_t insns_flags;

    uint64_t insns_flags2;

#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)

    target_phys_addr_t vpa;

    target_phys_addr_t slb_shadow;

    target_phys_addr_t dispatch_trace_log;

    uint32_t dtl_size;

#endif /* TARGET_PPC64 */

    int error_code;

    uint32_t pending_interrupts;

#if !defined(CONFIG_USER_ONLY)

    /* This is the IRQ controller, which is implementation dependent

     * and only relevant when emulating a complete machine.

     */

    uint32_t irq_input_state;

    void **irq_inputs;

    /* Exception vectors */

    target_ulong excp_vectors[POWERPC_EXCP_NB];

    target_ulong excp_prefix;

    target_ulong hreset_excp_prefix;

    target_ulong ivor_mask;

    target_ulong ivpr_mask;

    target_ulong hreset_vector;

#endif

    /* Those resources are used only during code translation */

    /* opcode handlers */

    opc_handler_t *opcodes[0x40];

    /* Those resources are used only in QEMU core */

    target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */

    target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */

    int mmu_idx;         /* precomputed MMU index to speed up mem accesses */

    /* Power management */

    int power_mode;

    int (*check_pow)(CPUPPCState *env);

#if !defined(CONFIG_USER_ONLY)

    void *load_info;    /* Holds boot loading state.  */

#endif

    /* booke timers */

    /* Specifies bit locations of the Time Base used to signal a fixed timer

     * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)

     *

     * 0 selects the least significant bit.

     * 63 selects the most significant bit.

     */

    uint8_t fit_period[4];

    uint8_t wdt_period[4];

};

#define SET_FIT_PERIOD(a_, b_, c_, d_)          \

do {                                            \

    env->fit_period[0] = (a_);                  \

    env->fit_period[1] = (b_);                  \

    env->fit_period[2] = (c_);                  \

    env->fit_period[3] = (d_);                  \

 } while (0)

#define SET_WDT_PERIOD(a_, b_, c_, d_)          \

do {                                            \

    env->wdt_period[0] = (a_);                  \

    env->wdt_period[1] = (b_);                  \

    env->wdt_period[2] = (c_);                  \

    env->wdt_period[3] = (d_);                  \

 } while (0)

#if !defined(CONFIG_USER_ONLY)

/* Context used internally during MMU translations */

typedef struct mmu_ctx_t mmu_ctx_t;

struct mmu_ctx_t {

    target_phys_addr_t raddr;      /* Real address              */

    target_phys_addr_t eaddr;      /* Effective address         */

    int prot;                      /* Protection bits           */

    target_phys_addr_t hash[2];    /* Pagetable hash values     */

    target_ulong ptem;             /* Virtual segment ID | API  */

    int key;                       /* Access key                */

    int nx;                        /* Non-execute area          */

};

#endif

#include "cpu-qom.h"

/*****************************************************************************/

PowerPCCPU *cpu_ppc_init(const char *cpu_model);

void ppc_translate_init(void);

int cpu_ppc_exec (CPUPPCState *s);

/* you can call this signal handler from your SIGBUS and SIGSEGV

   signal handlers to inform the virtual CPU of exceptions. non zero

   is returned if the signal was handled by the virtual CPU.  */

int cpu_ppc_signal_handler (int host_signum, void *pinfo,

                            void *puc);

int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,

                              int mmu_idx);

#define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault

#if !defined(CONFIG_USER_ONLY)

int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,

                          int rw, int access_type);

#endif

void do_interrupt (CPUPPCState *env);

void ppc_hw_interrupt (CPUPPCState *env);

#if !defined(CONFIG_USER_ONLY)

void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code,

                       target_ulong pte0, target_ulong pte1);

void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value);

void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value);

void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value);

void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value);

void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);

void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);

void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);

#if defined(TARGET_PPC64)

void ppc_store_asr (CPUPPCState *env, target_ulong value);

target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);

target_ulong ppc_load_sr (CPUPPCState *env, int sr_nr);

int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);

int ppc_load_slb_esid (CPUPPCState *env, target_ulong rb, target_ulong *rt);

int ppc_load_slb_vsid (CPUPPCState *env, target_ulong rb, target_ulong *rt);

#endif /* defined(TARGET_PPC64) */

void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value);

#endif /* !defined(CONFIG_USER_ONLY) */

void ppc_store_msr (CPUPPCState *env, target_ulong value);

void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);

const ppc_def_t *ppc_find_by_pvr(uint32_t pvr);

const ppc_def_t *cpu_ppc_find_by_name (const char *name);

int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);

/* Time-base and decrementer management */

#ifndef NO_CPU_IO_DEFS

uint64_t cpu_ppc_load_tbl (CPUPPCState *env);

uint32_t cpu_ppc_load_tbu (CPUPPCState *env);

void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);

void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);

uint64_t cpu_ppc_load_atbl (CPUPPCState *env);

uint32_t cpu_ppc_load_atbu (CPUPPCState *env);

void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);

void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);

uint32_t cpu_ppc_load_decr (CPUPPCState *env);

void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);

uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);

void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);

uint64_t cpu_ppc_load_purr (CPUPPCState *env);

void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);

uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);

uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);

#if !defined(CONFIG_USER_ONLY)

void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);

void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);

target_ulong load_40x_pit (CPUPPCState *env);

void store_40x_pit (CPUPPCState *env, target_ulong val);

void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);

void store_40x_sler (CPUPPCState *env, uint32_t val);

void store_booke_tcr (CPUPPCState *env, target_ulong val);

void store_booke_tsr (CPUPPCState *env, target_ulong val);

void booke206_flush_tlb(CPUPPCState *env, int flags, const int check_iprot);

target_phys_addr_t booke206_tlb_to_page_size(CPUPPCState *env, ppcmas_tlb_t *tlb);

int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb,

                     target_phys_addr_t *raddrp, target_ulong address,

                     uint32_t pid, int ext, int i);

int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,

                     target_phys_addr_t *raddrp, target_ulong address,

                     uint32_t pid);

void ppc_tlb_invalidate_all (CPUPPCState *env);

void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);

#if defined(TARGET_PPC64)

void ppc_slb_invalidate_all (CPUPPCState *env);

void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);

#endif

int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);

#endif

#endif

static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)

{

    uint64_t gprv;

    gprv = env->gpr[gprn];

#if !defined(TARGET_PPC64)

    if (env->flags & POWERPC_FLAG_SPE) {

        /* If the CPU implements the SPE extension, we have to get the

         * high bits of the GPR from the gprh storage area

         */

        gprv &= 0xFFFFFFFFULL;

        gprv |= (uint64_t)env->gprh[gprn] << 32;

    }

#endif

    return gprv;

}

/* Device control registers */

int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);

int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);

static inline CPUPPCState *cpu_init(const char *cpu_model)

{

    PowerPCCPU *cpu = cpu_ppc_init(cpu_model);

    if (cpu == NULL) {

        return NULL;

    }

    return &cpu->env;

}

#define cpu_exec cpu_ppc_exec

#define cpu_gen_code cpu_ppc_gen_code

#define cpu_signal_handler cpu_ppc_signal_handler

#define cpu_list ppc_cpu_list

#define CPU_SAVE_VERSION 4

/* MMU modes definitions */

#define MMU_MODE0_SUFFIX _user

#define MMU_MODE1_SUFFIX _kernel

#define MMU_MODE2_SUFFIX _hypv

#define MMU_USER_IDX 0

static inline int cpu_mmu_index (CPUPPCState *env)

{

    return env->mmu_idx;

}

#if defined(CONFIG_USER_ONLY)

static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp)