Revision c832e3de
| b/target-i386/translate.c | ||
|---|---|---|
| 274 | 274 |
|
| 275 | 275 |
static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0) |
| 276 | 276 |
{
|
| 277 |
TCGv tmp; |
|
| 278 |
|
|
| 279 | 277 |
switch(ot) {
|
| 280 | 278 |
case OT_BYTE: |
| 281 |
tmp = tcg_temp_new(); |
|
| 282 |
tcg_gen_ext8u_tl(tmp, t0); |
|
| 283 | 279 |
if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
|
| 284 |
tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xff); |
|
| 285 |
tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp); |
|
| 280 |
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8); |
|
| 286 | 281 |
} else {
|
| 287 |
tcg_gen_shli_tl(tmp, tmp, 8); |
|
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tcg_gen_andi_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], ~0xff00); |
|
| 289 |
tcg_gen_or_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], tmp); |
|
| 282 |
tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8); |
|
| 290 | 283 |
} |
| 291 |
tcg_temp_free(tmp); |
|
| 292 | 284 |
break; |
| 293 | 285 |
case OT_WORD: |
| 294 |
tmp = tcg_temp_new(); |
|
| 295 |
tcg_gen_ext16u_tl(tmp, t0); |
|
| 296 |
tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff); |
|
| 297 |
tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp); |
|
| 298 |
tcg_temp_free(tmp); |
|
| 286 |
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16); |
|
| 299 | 287 |
break; |
| 300 | 288 |
default: /* XXX this shouldn't be reached; abort? */ |
| 301 | 289 |
case OT_LONG: |
| ... | ... | |
| 323 | 311 |
|
| 324 | 312 |
static inline void gen_op_mov_reg_A0(int size, int reg) |
| 325 | 313 |
{
|
| 326 |
TCGv tmp; |
|
| 327 |
|
|
| 328 | 314 |
switch(size) {
|
| 329 | 315 |
case 0: |
| 330 |
tmp = tcg_temp_new(); |
|
| 331 |
tcg_gen_ext16u_tl(tmp, cpu_A0); |
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| 332 |
tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff); |
|
| 333 |
tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp); |
|
| 334 |
tcg_temp_free(tmp); |
|
| 316 |
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16); |
|
| 335 | 317 |
break; |
| 336 | 318 |
default: /* XXX this shouldn't be reached; abort? */ |
| 337 | 319 |
case 1: |
| ... | ... | |
| 415 | 397 |
switch(size) {
|
| 416 | 398 |
case 0: |
| 417 | 399 |
tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val); |
| 418 |
tcg_gen_ext16u_tl(cpu_tmp0, cpu_tmp0); |
|
| 419 |
tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff); |
|
| 420 |
tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0); |
|
| 400 |
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16); |
|
| 421 | 401 |
break; |
| 422 | 402 |
case 1: |
| 423 | 403 |
tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val); |
| ... | ... | |
| 439 | 419 |
switch(size) {
|
| 440 | 420 |
case 0: |
| 441 | 421 |
tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]); |
| 442 |
tcg_gen_ext16u_tl(cpu_tmp0, cpu_tmp0); |
|
| 443 |
tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff); |
|
| 444 |
tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0); |
|
| 422 |
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16); |
|
| 445 | 423 |
break; |
| 446 | 424 |
case 1: |
| 447 | 425 |
tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]); |
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