Revision c90daa1c hw/usb/hcd-xhci.c
| b/hw/usb/hcd-xhci.c | ||
|---|---|---|
| 1187 | 1187 |
static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, |
| 1188 | 1188 |
XHCIStreamContext *sctx, uint32_t state) |
| 1189 | 1189 |
{
|
| 1190 |
XHCIRing *ring = NULL; |
|
| 1190 | 1191 |
uint32_t ctx[5]; |
| 1191 | 1192 |
uint32_t ctx2[2]; |
| 1192 | 1193 |
|
| ... | ... | |
| 1197 | 1198 |
/* update ring dequeue ptr */ |
| 1198 | 1199 |
if (epctx->nr_pstreams) {
|
| 1199 | 1200 |
if (sctx != NULL) {
|
| 1201 |
ring = &sctx->ring; |
|
| 1200 | 1202 |
xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); |
| 1201 | 1203 |
ctx2[0] &= 0xe; |
| 1202 | 1204 |
ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs; |
| ... | ... | |
| 1204 | 1206 |
xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); |
| 1205 | 1207 |
} |
| 1206 | 1208 |
} else {
|
| 1207 |
ctx[2] = epctx->ring.dequeue | epctx->ring.ccs; |
|
| 1208 |
ctx[3] = (epctx->ring.dequeue >> 16) >> 16; |
|
| 1209 |
ring = &epctx->ring; |
|
| 1210 |
} |
|
| 1211 |
if (ring) {
|
|
| 1212 |
ctx[2] = ring->dequeue | ring->ccs; |
|
| 1213 |
ctx[3] = (ring->dequeue >> 16) >> 16; |
|
| 1214 |
|
|
| 1209 | 1215 |
DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",
|
| 1210 | 1216 |
epctx->pctx, state, ctx[3], ctx[2]); |
| 1211 | 1217 |
} |
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