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1 | c3d2689d | balrog | /*
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2 | c3d2689d | balrog | * TI OMAP processors emulation.
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3 | c3d2689d | balrog | *
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4 | b4e3104b | balrog | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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5 | c3d2689d | balrog | *
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6 | c3d2689d | balrog | * This program is free software; you can redistribute it and/or
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7 | c3d2689d | balrog | * modify it under the terms of the GNU General Public License as
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8 | 827df9f3 | balrog | * published by the Free Software Foundation; either version 2 or
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9 | 827df9f3 | balrog | * (at your option) version 3 of the License.
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10 | c3d2689d | balrog | *
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11 | c3d2689d | balrog | * This program is distributed in the hope that it will be useful,
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12 | c3d2689d | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | c3d2689d | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 | c3d2689d | balrog | * GNU General Public License for more details.
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15 | c3d2689d | balrog | *
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16 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
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17 | 8167ee88 | Blue Swirl | * with this program; if not, see <http://www.gnu.org/licenses/>.
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18 | c3d2689d | balrog | */
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19 | 87ecb68b | pbrook | #include "hw.h" |
20 | 87ecb68b | pbrook | #include "arm-misc.h" |
21 | 87ecb68b | pbrook | #include "omap.h" |
22 | 87ecb68b | pbrook | #include "sysemu.h" |
23 | afbb5194 | balrog | #include "soc_dma.h" |
24 | 2446333c | Blue Swirl | #include "blockdev.h" |
25 | 45416789 | Blue Swirl | #include "range.h" |
26 | 77831c20 | Juha Riihimäki | #include "sysbus.h" |
27 | c3d2689d | balrog | |
28 | 827df9f3 | balrog | /* Should signal the TCMI/GPMC */
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29 | c227f099 | Anthony Liguori | uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
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30 | 66450b15 | balrog | { |
31 | 02645926 | balrog | uint8_t ret; |
32 | 02645926 | balrog | |
33 | 66450b15 | balrog | OMAP_8B_REG(addr); |
34 | b854bc19 | balrog | cpu_physical_memory_read(addr, (void *) &ret, 1); |
35 | 02645926 | balrog | return ret;
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36 | 66450b15 | balrog | } |
37 | 66450b15 | balrog | |
38 | c227f099 | Anthony Liguori | void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, |
39 | 66450b15 | balrog | uint32_t value) |
40 | 66450b15 | balrog | { |
41 | b854bc19 | balrog | uint8_t val8 = value; |
42 | b854bc19 | balrog | |
43 | 66450b15 | balrog | OMAP_8B_REG(addr); |
44 | b854bc19 | balrog | cpu_physical_memory_write(addr, (void *) &val8, 1); |
45 | 66450b15 | balrog | } |
46 | 66450b15 | balrog | |
47 | c227f099 | Anthony Liguori | uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
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48 | c3d2689d | balrog | { |
49 | b854bc19 | balrog | uint16_t ret; |
50 | b854bc19 | balrog | |
51 | c3d2689d | balrog | OMAP_16B_REG(addr); |
52 | b854bc19 | balrog | cpu_physical_memory_read(addr, (void *) &ret, 2); |
53 | b854bc19 | balrog | return ret;
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54 | c3d2689d | balrog | } |
55 | c3d2689d | balrog | |
56 | c227f099 | Anthony Liguori | void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, |
57 | c3d2689d | balrog | uint32_t value) |
58 | c3d2689d | balrog | { |
59 | b854bc19 | balrog | uint16_t val16 = value; |
60 | b854bc19 | balrog | |
61 | c3d2689d | balrog | OMAP_16B_REG(addr); |
62 | b854bc19 | balrog | cpu_physical_memory_write(addr, (void *) &val16, 2); |
63 | c3d2689d | balrog | } |
64 | c3d2689d | balrog | |
65 | c227f099 | Anthony Liguori | uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
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66 | c3d2689d | balrog | { |
67 | b854bc19 | balrog | uint32_t ret; |
68 | b854bc19 | balrog | |
69 | c3d2689d | balrog | OMAP_32B_REG(addr); |
70 | b854bc19 | balrog | cpu_physical_memory_read(addr, (void *) &ret, 4); |
71 | b854bc19 | balrog | return ret;
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72 | c3d2689d | balrog | } |
73 | c3d2689d | balrog | |
74 | c227f099 | Anthony Liguori | void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, |
75 | c3d2689d | balrog | uint32_t value) |
76 | c3d2689d | balrog | { |
77 | c3d2689d | balrog | OMAP_32B_REG(addr); |
78 | b854bc19 | balrog | cpu_physical_memory_write(addr, (void *) &value, 4); |
79 | c3d2689d | balrog | } |
80 | c3d2689d | balrog | |
81 | c3d2689d | balrog | /* MPU OS timers */
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82 | c3d2689d | balrog | struct omap_mpu_timer_s {
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83 | 4b3fedf3 | Avi Kivity | MemoryRegion iomem; |
84 | c3d2689d | balrog | qemu_irq irq; |
85 | c3d2689d | balrog | omap_clk clk; |
86 | c3d2689d | balrog | uint32_t val; |
87 | c3d2689d | balrog | int64_t time; |
88 | c3d2689d | balrog | QEMUTimer *timer; |
89 | e856f2ad | balrog | QEMUBH *tick; |
90 | c3d2689d | balrog | int64_t rate; |
91 | c3d2689d | balrog | int it_ena;
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92 | c3d2689d | balrog | |
93 | c3d2689d | balrog | int enable;
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94 | c3d2689d | balrog | int ptv;
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95 | c3d2689d | balrog | int ar;
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96 | c3d2689d | balrog | int st;
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97 | c3d2689d | balrog | uint32_t reset_val; |
98 | c3d2689d | balrog | }; |
99 | c3d2689d | balrog | |
100 | c3d2689d | balrog | static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) |
101 | c3d2689d | balrog | { |
102 | 74475455 | Paolo Bonzini | uint64_t distance = qemu_get_clock_ns(vm_clock) - timer->time; |
103 | c3d2689d | balrog | |
104 | c3d2689d | balrog | if (timer->st && timer->enable && timer->rate)
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105 | c3d2689d | balrog | return timer->val - muldiv64(distance >> (timer->ptv + 1), |
106 | 6ee093c9 | Juan Quintela | timer->rate, get_ticks_per_sec()); |
107 | c3d2689d | balrog | else
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108 | c3d2689d | balrog | return timer->val;
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109 | c3d2689d | balrog | } |
110 | c3d2689d | balrog | |
111 | c3d2689d | balrog | static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) |
112 | c3d2689d | balrog | { |
113 | c3d2689d | balrog | timer->val = omap_timer_read(timer); |
114 | 74475455 | Paolo Bonzini | timer->time = qemu_get_clock_ns(vm_clock); |
115 | c3d2689d | balrog | } |
116 | c3d2689d | balrog | |
117 | c3d2689d | balrog | static inline void omap_timer_update(struct omap_mpu_timer_s *timer) |
118 | c3d2689d | balrog | { |
119 | c3d2689d | balrog | int64_t expires; |
120 | c3d2689d | balrog | |
121 | c3d2689d | balrog | if (timer->enable && timer->st && timer->rate) {
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122 | c3d2689d | balrog | timer->val = timer->reset_val; /* Should skip this on clk enable */
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123 | b8b137d6 | balrog | expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1),
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124 | 6ee093c9 | Juan Quintela | get_ticks_per_sec(), timer->rate); |
125 | b854bc19 | balrog | |
126 | b854bc19 | balrog | /* If timer expiry would be sooner than in about 1 ms and
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127 | b854bc19 | balrog | * auto-reload isn't set, then fire immediately. This is a hack
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128 | b854bc19 | balrog | * to make systems like PalmOS run in acceptable time. PalmOS
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129 | b854bc19 | balrog | * sets the interval to a very low value and polls the status bit
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130 | b854bc19 | balrog | * in a busy loop when it wants to sleep just a couple of CPU
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131 | b854bc19 | balrog | * ticks. */
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132 | 6ee093c9 | Juan Quintela | if (expires > (get_ticks_per_sec() >> 10) || timer->ar) |
133 | b854bc19 | balrog | qemu_mod_timer(timer->timer, timer->time + expires); |
134 | e856f2ad | balrog | else
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135 | e856f2ad | balrog | qemu_bh_schedule(timer->tick); |
136 | c3d2689d | balrog | } else
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137 | c3d2689d | balrog | qemu_del_timer(timer->timer); |
138 | c3d2689d | balrog | } |
139 | c3d2689d | balrog | |
140 | e856f2ad | balrog | static void omap_timer_fire(void *opaque) |
141 | c3d2689d | balrog | { |
142 | e856f2ad | balrog | struct omap_mpu_timer_s *timer = opaque;
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143 | c3d2689d | balrog | |
144 | c3d2689d | balrog | if (!timer->ar) {
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145 | c3d2689d | balrog | timer->val = 0;
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146 | c3d2689d | balrog | timer->st = 0;
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147 | c3d2689d | balrog | } |
148 | c3d2689d | balrog | |
149 | c3d2689d | balrog | if (timer->it_ena)
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150 | 106627d0 | balrog | /* Edge-triggered irq */
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151 | 106627d0 | balrog | qemu_irq_pulse(timer->irq); |
152 | e856f2ad | balrog | } |
153 | e856f2ad | balrog | |
154 | e856f2ad | balrog | static void omap_timer_tick(void *opaque) |
155 | e856f2ad | balrog | { |
156 | e856f2ad | balrog | struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; |
157 | e856f2ad | balrog | |
158 | e856f2ad | balrog | omap_timer_sync(timer); |
159 | e856f2ad | balrog | omap_timer_fire(timer); |
160 | c3d2689d | balrog | omap_timer_update(timer); |
161 | c3d2689d | balrog | } |
162 | c3d2689d | balrog | |
163 | c3d2689d | balrog | static void omap_timer_clk_update(void *opaque, int line, int on) |
164 | c3d2689d | balrog | { |
165 | c3d2689d | balrog | struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; |
166 | c3d2689d | balrog | |
167 | c3d2689d | balrog | omap_timer_sync(timer); |
168 | c3d2689d | balrog | timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
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169 | c3d2689d | balrog | omap_timer_update(timer); |
170 | c3d2689d | balrog | } |
171 | c3d2689d | balrog | |
172 | c3d2689d | balrog | static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) |
173 | c3d2689d | balrog | { |
174 | c3d2689d | balrog | omap_clk_adduser(timer->clk, |
175 | c3d2689d | balrog | qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]); |
176 | c3d2689d | balrog | timer->rate = omap_clk_getrate(timer->clk); |
177 | c3d2689d | balrog | } |
178 | c3d2689d | balrog | |
179 | 4b3fedf3 | Avi Kivity | static uint64_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr, |
180 | 4b3fedf3 | Avi Kivity | unsigned size)
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181 | c3d2689d | balrog | { |
182 | c3d2689d | balrog | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
183 | c3d2689d | balrog | |
184 | 4b3fedf3 | Avi Kivity | if (size != 4) { |
185 | 4b3fedf3 | Avi Kivity | return omap_badwidth_read32(opaque, addr);
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186 | 4b3fedf3 | Avi Kivity | } |
187 | 4b3fedf3 | Avi Kivity | |
188 | 8da3ff18 | pbrook | switch (addr) {
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189 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
190 | c3d2689d | balrog | return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; |
191 | c3d2689d | balrog | |
192 | c3d2689d | balrog | case 0x04: /* LOAD_TIM */ |
193 | c3d2689d | balrog | break;
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194 | c3d2689d | balrog | |
195 | c3d2689d | balrog | case 0x08: /* READ_TIM */ |
196 | c3d2689d | balrog | return omap_timer_read(s);
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197 | c3d2689d | balrog | } |
198 | c3d2689d | balrog | |
199 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
200 | c3d2689d | balrog | return 0; |
201 | c3d2689d | balrog | } |
202 | c3d2689d | balrog | |
203 | c227f099 | Anthony Liguori | static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr, |
204 | 4b3fedf3 | Avi Kivity | uint64_t value, unsigned size)
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205 | c3d2689d | balrog | { |
206 | c3d2689d | balrog | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
207 | c3d2689d | balrog | |
208 | 4b3fedf3 | Avi Kivity | if (size != 4) { |
209 | 4b3fedf3 | Avi Kivity | return omap_badwidth_write32(opaque, addr, value);
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210 | 4b3fedf3 | Avi Kivity | } |
211 | 4b3fedf3 | Avi Kivity | |
212 | 8da3ff18 | pbrook | switch (addr) {
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213 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
214 | c3d2689d | balrog | omap_timer_sync(s); |
215 | c3d2689d | balrog | s->enable = (value >> 5) & 1; |
216 | c3d2689d | balrog | s->ptv = (value >> 2) & 7; |
217 | c3d2689d | balrog | s->ar = (value >> 1) & 1; |
218 | c3d2689d | balrog | s->st = value & 1;
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219 | c3d2689d | balrog | omap_timer_update(s); |
220 | c3d2689d | balrog | return;
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221 | c3d2689d | balrog | |
222 | c3d2689d | balrog | case 0x04: /* LOAD_TIM */ |
223 | c3d2689d | balrog | s->reset_val = value; |
224 | c3d2689d | balrog | return;
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225 | c3d2689d | balrog | |
226 | c3d2689d | balrog | case 0x08: /* READ_TIM */ |
227 | c3d2689d | balrog | OMAP_RO_REG(addr); |
228 | c3d2689d | balrog | break;
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229 | c3d2689d | balrog | |
230 | c3d2689d | balrog | default:
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231 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
232 | c3d2689d | balrog | } |
233 | c3d2689d | balrog | } |
234 | c3d2689d | balrog | |
235 | 4b3fedf3 | Avi Kivity | static const MemoryRegionOps omap_mpu_timer_ops = { |
236 | 4b3fedf3 | Avi Kivity | .read = omap_mpu_timer_read, |
237 | 4b3fedf3 | Avi Kivity | .write = omap_mpu_timer_write, |
238 | 4b3fedf3 | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
239 | c3d2689d | balrog | }; |
240 | c3d2689d | balrog | |
241 | c3d2689d | balrog | static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) |
242 | c3d2689d | balrog | { |
243 | c3d2689d | balrog | qemu_del_timer(s->timer); |
244 | c3d2689d | balrog | s->enable = 0;
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245 | c3d2689d | balrog | s->reset_val = 31337;
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246 | c3d2689d | balrog | s->val = 0;
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247 | c3d2689d | balrog | s->ptv = 0;
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248 | c3d2689d | balrog | s->ar = 0;
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249 | c3d2689d | balrog | s->st = 0;
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250 | c3d2689d | balrog | s->it_ena = 1;
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251 | c3d2689d | balrog | } |
252 | c3d2689d | balrog | |
253 | 4b3fedf3 | Avi Kivity | static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory, |
254 | 4b3fedf3 | Avi Kivity | target_phys_addr_t base, |
255 | c3d2689d | balrog | qemu_irq irq, omap_clk clk) |
256 | c3d2689d | balrog | { |
257 | c3d2689d | balrog | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) |
258 | 7267c094 | Anthony Liguori | g_malloc0(sizeof(struct omap_mpu_timer_s)); |
259 | c3d2689d | balrog | |
260 | c3d2689d | balrog | s->irq = irq; |
261 | c3d2689d | balrog | s->clk = clk; |
262 | 74475455 | Paolo Bonzini | s->timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, s); |
263 | e856f2ad | balrog | s->tick = qemu_bh_new(omap_timer_fire, s); |
264 | c3d2689d | balrog | omap_mpu_timer_reset(s); |
265 | c3d2689d | balrog | omap_timer_clk_setup(s); |
266 | c3d2689d | balrog | |
267 | 4b3fedf3 | Avi Kivity | memory_region_init_io(&s->iomem, &omap_mpu_timer_ops, s, |
268 | 4b3fedf3 | Avi Kivity | "omap-mpu-timer", 0x100); |
269 | 4b3fedf3 | Avi Kivity | |
270 | 4b3fedf3 | Avi Kivity | memory_region_add_subregion(system_memory, base, &s->iomem); |
271 | c3d2689d | balrog | |
272 | c3d2689d | balrog | return s;
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273 | c3d2689d | balrog | } |
274 | c3d2689d | balrog | |
275 | c3d2689d | balrog | /* Watchdog timer */
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276 | c3d2689d | balrog | struct omap_watchdog_timer_s {
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277 | c3d2689d | balrog | struct omap_mpu_timer_s timer;
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278 | 4b3fedf3 | Avi Kivity | MemoryRegion iomem; |
279 | c3d2689d | balrog | uint8_t last_wr; |
280 | c3d2689d | balrog | int mode;
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281 | c3d2689d | balrog | int free;
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282 | c3d2689d | balrog | int reset;
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283 | c3d2689d | balrog | }; |
284 | c3d2689d | balrog | |
285 | 4b3fedf3 | Avi Kivity | static uint64_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr, |
286 | 4b3fedf3 | Avi Kivity | unsigned size)
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287 | c3d2689d | balrog | { |
288 | c3d2689d | balrog | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
289 | c3d2689d | balrog | |
290 | 4b3fedf3 | Avi Kivity | if (size != 2) { |
291 | 4b3fedf3 | Avi Kivity | return omap_badwidth_read16(opaque, addr);
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292 | 4b3fedf3 | Avi Kivity | } |
293 | 4b3fedf3 | Avi Kivity | |
294 | 8da3ff18 | pbrook | switch (addr) {
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295 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
296 | c3d2689d | balrog | return (s->timer.ptv << 9) | (s->timer.ar << 8) | |
297 | c3d2689d | balrog | (s->timer.st << 7) | (s->free << 1); |
298 | c3d2689d | balrog | |
299 | c3d2689d | balrog | case 0x04: /* READ_TIMER */ |
300 | c3d2689d | balrog | return omap_timer_read(&s->timer);
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301 | c3d2689d | balrog | |
302 | c3d2689d | balrog | case 0x08: /* TIMER_MODE */ |
303 | c3d2689d | balrog | return s->mode << 15; |
304 | c3d2689d | balrog | } |
305 | c3d2689d | balrog | |
306 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
307 | c3d2689d | balrog | return 0; |
308 | c3d2689d | balrog | } |
309 | c3d2689d | balrog | |
310 | c227f099 | Anthony Liguori | static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr, |
311 | 4b3fedf3 | Avi Kivity | uint64_t value, unsigned size)
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312 | c3d2689d | balrog | { |
313 | c3d2689d | balrog | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
314 | c3d2689d | balrog | |
315 | 4b3fedf3 | Avi Kivity | if (size != 2) { |
316 | 4b3fedf3 | Avi Kivity | return omap_badwidth_write16(opaque, addr, value);
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317 | 4b3fedf3 | Avi Kivity | } |
318 | 4b3fedf3 | Avi Kivity | |
319 | 8da3ff18 | pbrook | switch (addr) {
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320 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
321 | c3d2689d | balrog | omap_timer_sync(&s->timer); |
322 | c3d2689d | balrog | s->timer.ptv = (value >> 9) & 7; |
323 | c3d2689d | balrog | s->timer.ar = (value >> 8) & 1; |
324 | c3d2689d | balrog | s->timer.st = (value >> 7) & 1; |
325 | c3d2689d | balrog | s->free = (value >> 1) & 1; |
326 | c3d2689d | balrog | omap_timer_update(&s->timer); |
327 | c3d2689d | balrog | break;
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328 | c3d2689d | balrog | |
329 | c3d2689d | balrog | case 0x04: /* LOAD_TIMER */ |
330 | c3d2689d | balrog | s->timer.reset_val = value & 0xffff;
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331 | c3d2689d | balrog | break;
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332 | c3d2689d | balrog | |
333 | c3d2689d | balrog | case 0x08: /* TIMER_MODE */ |
334 | c3d2689d | balrog | if (!s->mode && ((value >> 15) & 1)) |
335 | c3d2689d | balrog | omap_clk_get(s->timer.clk); |
336 | c3d2689d | balrog | s->mode |= (value >> 15) & 1; |
337 | c3d2689d | balrog | if (s->last_wr == 0xf5) { |
338 | c3d2689d | balrog | if ((value & 0xff) == 0xa0) { |
339 | d8f699cb | balrog | if (s->mode) {
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340 | d8f699cb | balrog | s->mode = 0;
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341 | d8f699cb | balrog | omap_clk_put(s->timer.clk); |
342 | d8f699cb | balrog | } |
343 | c3d2689d | balrog | } else {
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344 | c3d2689d | balrog | /* XXX: on T|E hardware somehow this has no effect,
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345 | c3d2689d | balrog | * on Zire 71 it works as specified. */
|
346 | c3d2689d | balrog | s->reset = 1;
|
347 | c3d2689d | balrog | qemu_system_reset_request(); |
348 | c3d2689d | balrog | } |
349 | c3d2689d | balrog | } |
350 | c3d2689d | balrog | s->last_wr = value & 0xff;
|
351 | c3d2689d | balrog | break;
|
352 | c3d2689d | balrog | |
353 | c3d2689d | balrog | default:
|
354 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
355 | c3d2689d | balrog | } |
356 | c3d2689d | balrog | } |
357 | c3d2689d | balrog | |
358 | 4b3fedf3 | Avi Kivity | static const MemoryRegionOps omap_wd_timer_ops = { |
359 | 4b3fedf3 | Avi Kivity | .read = omap_wd_timer_read, |
360 | 4b3fedf3 | Avi Kivity | .write = omap_wd_timer_write, |
361 | 4b3fedf3 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
362 | c3d2689d | balrog | }; |
363 | c3d2689d | balrog | |
364 | c3d2689d | balrog | static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) |
365 | c3d2689d | balrog | { |
366 | c3d2689d | balrog | qemu_del_timer(s->timer.timer); |
367 | c3d2689d | balrog | if (!s->mode)
|
368 | c3d2689d | balrog | omap_clk_get(s->timer.clk); |
369 | c3d2689d | balrog | s->mode = 1;
|
370 | c3d2689d | balrog | s->free = 1;
|
371 | c3d2689d | balrog | s->reset = 0;
|
372 | c3d2689d | balrog | s->timer.enable = 1;
|
373 | c3d2689d | balrog | s->timer.it_ena = 1;
|
374 | c3d2689d | balrog | s->timer.reset_val = 0xffff;
|
375 | c3d2689d | balrog | s->timer.val = 0;
|
376 | c3d2689d | balrog | s->timer.st = 0;
|
377 | c3d2689d | balrog | s->timer.ptv = 0;
|
378 | c3d2689d | balrog | s->timer.ar = 0;
|
379 | c3d2689d | balrog | omap_timer_update(&s->timer); |
380 | c3d2689d | balrog | } |
381 | c3d2689d | balrog | |
382 | 4b3fedf3 | Avi Kivity | static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory, |
383 | 4b3fedf3 | Avi Kivity | target_phys_addr_t base, |
384 | c3d2689d | balrog | qemu_irq irq, omap_clk clk) |
385 | c3d2689d | balrog | { |
386 | c3d2689d | balrog | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) |
387 | 7267c094 | Anthony Liguori | g_malloc0(sizeof(struct omap_watchdog_timer_s)); |
388 | c3d2689d | balrog | |
389 | c3d2689d | balrog | s->timer.irq = irq; |
390 | c3d2689d | balrog | s->timer.clk = clk; |
391 | 74475455 | Paolo Bonzini | s->timer.timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, &s->timer); |
392 | c3d2689d | balrog | omap_wd_timer_reset(s); |
393 | c3d2689d | balrog | omap_timer_clk_setup(&s->timer); |
394 | c3d2689d | balrog | |
395 | 4b3fedf3 | Avi Kivity | memory_region_init_io(&s->iomem, &omap_wd_timer_ops, s, |
396 | 4b3fedf3 | Avi Kivity | "omap-wd-timer", 0x100); |
397 | 4b3fedf3 | Avi Kivity | memory_region_add_subregion(memory, base, &s->iomem); |
398 | c3d2689d | balrog | |
399 | c3d2689d | balrog | return s;
|
400 | c3d2689d | balrog | } |
401 | c3d2689d | balrog | |
402 | c3d2689d | balrog | /* 32-kHz timer */
|
403 | c3d2689d | balrog | struct omap_32khz_timer_s {
|
404 | c3d2689d | balrog | struct omap_mpu_timer_s timer;
|
405 | 4b3fedf3 | Avi Kivity | MemoryRegion iomem; |
406 | c3d2689d | balrog | }; |
407 | c3d2689d | balrog | |
408 | 4b3fedf3 | Avi Kivity | static uint64_t omap_os_timer_read(void *opaque, target_phys_addr_t addr, |
409 | 4b3fedf3 | Avi Kivity | unsigned size)
|
410 | c3d2689d | balrog | { |
411 | c3d2689d | balrog | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; |
412 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
413 | c3d2689d | balrog | |
414 | 4b3fedf3 | Avi Kivity | if (size != 4) { |
415 | 4b3fedf3 | Avi Kivity | return omap_badwidth_read32(opaque, addr);
|
416 | 4b3fedf3 | Avi Kivity | } |
417 | 4b3fedf3 | Avi Kivity | |
418 | c3d2689d | balrog | switch (offset) {
|
419 | c3d2689d | balrog | case 0x00: /* TVR */ |
420 | c3d2689d | balrog | return s->timer.reset_val;
|
421 | c3d2689d | balrog | |
422 | c3d2689d | balrog | case 0x04: /* TCR */ |
423 | c3d2689d | balrog | return omap_timer_read(&s->timer);
|
424 | c3d2689d | balrog | |
425 | c3d2689d | balrog | case 0x08: /* CR */ |
426 | c3d2689d | balrog | return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; |
427 | c3d2689d | balrog | |
428 | c3d2689d | balrog | default:
|
429 | c3d2689d | balrog | break;
|
430 | c3d2689d | balrog | } |
431 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
432 | c3d2689d | balrog | return 0; |
433 | c3d2689d | balrog | } |
434 | c3d2689d | balrog | |
435 | c227f099 | Anthony Liguori | static void omap_os_timer_write(void *opaque, target_phys_addr_t addr, |
436 | 4b3fedf3 | Avi Kivity | uint64_t value, unsigned size)
|
437 | c3d2689d | balrog | { |
438 | c3d2689d | balrog | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; |
439 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
440 | c3d2689d | balrog | |
441 | 4b3fedf3 | Avi Kivity | if (size != 4) { |
442 | 4b3fedf3 | Avi Kivity | return omap_badwidth_write32(opaque, addr, value);
|
443 | 4b3fedf3 | Avi Kivity | } |
444 | 4b3fedf3 | Avi Kivity | |
445 | c3d2689d | balrog | switch (offset) {
|
446 | c3d2689d | balrog | case 0x00: /* TVR */ |
447 | c3d2689d | balrog | s->timer.reset_val = value & 0x00ffffff;
|
448 | c3d2689d | balrog | break;
|
449 | c3d2689d | balrog | |
450 | c3d2689d | balrog | case 0x04: /* TCR */ |
451 | c3d2689d | balrog | OMAP_RO_REG(addr); |
452 | c3d2689d | balrog | break;
|
453 | c3d2689d | balrog | |
454 | c3d2689d | balrog | case 0x08: /* CR */ |
455 | c3d2689d | balrog | s->timer.ar = (value >> 3) & 1; |
456 | c3d2689d | balrog | s->timer.it_ena = (value >> 2) & 1; |
457 | c3d2689d | balrog | if (s->timer.st != (value & 1) || (value & 2)) { |
458 | c3d2689d | balrog | omap_timer_sync(&s->timer); |
459 | c3d2689d | balrog | s->timer.enable = value & 1;
|
460 | c3d2689d | balrog | s->timer.st = value & 1;
|
461 | c3d2689d | balrog | omap_timer_update(&s->timer); |
462 | c3d2689d | balrog | } |
463 | c3d2689d | balrog | break;
|
464 | c3d2689d | balrog | |
465 | c3d2689d | balrog | default:
|
466 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
467 | c3d2689d | balrog | } |
468 | c3d2689d | balrog | } |
469 | c3d2689d | balrog | |
470 | 4b3fedf3 | Avi Kivity | static const MemoryRegionOps omap_os_timer_ops = { |
471 | 4b3fedf3 | Avi Kivity | .read = omap_os_timer_read, |
472 | 4b3fedf3 | Avi Kivity | .write = omap_os_timer_write, |
473 | 4b3fedf3 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
474 | c3d2689d | balrog | }; |
475 | c3d2689d | balrog | |
476 | c3d2689d | balrog | static void omap_os_timer_reset(struct omap_32khz_timer_s *s) |
477 | c3d2689d | balrog | { |
478 | c3d2689d | balrog | qemu_del_timer(s->timer.timer); |
479 | c3d2689d | balrog | s->timer.enable = 0;
|
480 | c3d2689d | balrog | s->timer.it_ena = 0;
|
481 | c3d2689d | balrog | s->timer.reset_val = 0x00ffffff;
|
482 | c3d2689d | balrog | s->timer.val = 0;
|
483 | c3d2689d | balrog | s->timer.st = 0;
|
484 | c3d2689d | balrog | s->timer.ptv = 0;
|
485 | c3d2689d | balrog | s->timer.ar = 1;
|
486 | c3d2689d | balrog | } |
487 | c3d2689d | balrog | |
488 | 4b3fedf3 | Avi Kivity | static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory, |
489 | 4b3fedf3 | Avi Kivity | target_phys_addr_t base, |
490 | c3d2689d | balrog | qemu_irq irq, omap_clk clk) |
491 | c3d2689d | balrog | { |
492 | c3d2689d | balrog | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) |
493 | 7267c094 | Anthony Liguori | g_malloc0(sizeof(struct omap_32khz_timer_s)); |
494 | c3d2689d | balrog | |
495 | c3d2689d | balrog | s->timer.irq = irq; |
496 | c3d2689d | balrog | s->timer.clk = clk; |
497 | 74475455 | Paolo Bonzini | s->timer.timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, &s->timer); |
498 | c3d2689d | balrog | omap_os_timer_reset(s); |
499 | c3d2689d | balrog | omap_timer_clk_setup(&s->timer); |
500 | c3d2689d | balrog | |
501 | 4b3fedf3 | Avi Kivity | memory_region_init_io(&s->iomem, &omap_os_timer_ops, s, |
502 | 4b3fedf3 | Avi Kivity | "omap-os-timer", 0x800); |
503 | 4b3fedf3 | Avi Kivity | memory_region_add_subregion(memory, base, &s->iomem); |
504 | c3d2689d | balrog | |
505 | c3d2689d | balrog | return s;
|
506 | c3d2689d | balrog | } |
507 | c3d2689d | balrog | |
508 | c3d2689d | balrog | /* Ultra Low-Power Device Module */
|
509 | 4b3fedf3 | Avi Kivity | static uint64_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr, |
510 | 4b3fedf3 | Avi Kivity | unsigned size)
|
511 | c3d2689d | balrog | { |
512 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
513 | c3d2689d | balrog | uint16_t ret; |
514 | c3d2689d | balrog | |
515 | 4b3fedf3 | Avi Kivity | if (size != 2) { |
516 | 4b3fedf3 | Avi Kivity | return omap_badwidth_read16(opaque, addr);
|
517 | 4b3fedf3 | Avi Kivity | } |
518 | 4b3fedf3 | Avi Kivity | |
519 | 8da3ff18 | pbrook | switch (addr) {
|
520 | c3d2689d | balrog | case 0x14: /* IT_STATUS */ |
521 | 8da3ff18 | pbrook | ret = s->ulpd_pm_regs[addr >> 2];
|
522 | 8da3ff18 | pbrook | s->ulpd_pm_regs[addr >> 2] = 0; |
523 | 0919ac78 | Peter Maydell | qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
|
524 | c3d2689d | balrog | return ret;
|
525 | c3d2689d | balrog | |
526 | c3d2689d | balrog | case 0x18: /* Reserved */ |
527 | c3d2689d | balrog | case 0x1c: /* Reserved */ |
528 | c3d2689d | balrog | case 0x20: /* Reserved */ |
529 | c3d2689d | balrog | case 0x28: /* Reserved */ |
530 | c3d2689d | balrog | case 0x2c: /* Reserved */ |
531 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
532 | c3d2689d | balrog | case 0x00: /* COUNTER_32_LSB */ |
533 | c3d2689d | balrog | case 0x04: /* COUNTER_32_MSB */ |
534 | c3d2689d | balrog | case 0x08: /* COUNTER_HIGH_FREQ_LSB */ |
535 | c3d2689d | balrog | case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ |
536 | c3d2689d | balrog | case 0x10: /* GAUGING_CTRL */ |
537 | c3d2689d | balrog | case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
538 | c3d2689d | balrog | case 0x30: /* CLOCK_CTRL */ |
539 | c3d2689d | balrog | case 0x34: /* SOFT_REQ */ |
540 | c3d2689d | balrog | case 0x38: /* COUNTER_32_FIQ */ |
541 | c3d2689d | balrog | case 0x3c: /* DPLL_CTRL */ |
542 | c3d2689d | balrog | case 0x40: /* STATUS_REQ */ |
543 | c3d2689d | balrog | /* XXX: check clk::usecount state for every clock */
|
544 | c3d2689d | balrog | case 0x48: /* LOCL_TIME */ |
545 | c3d2689d | balrog | case 0x4c: /* APLL_CTRL */ |
546 | c3d2689d | balrog | case 0x50: /* POWER_CTRL */ |
547 | 8da3ff18 | pbrook | return s->ulpd_pm_regs[addr >> 2]; |
548 | c3d2689d | balrog | } |
549 | c3d2689d | balrog | |
550 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
551 | c3d2689d | balrog | return 0; |
552 | c3d2689d | balrog | } |
553 | c3d2689d | balrog | |
554 | c3d2689d | balrog | static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, |
555 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
556 | c3d2689d | balrog | { |
557 | c3d2689d | balrog | if (diff & (1 << 4)) /* USB_MCLK_EN */ |
558 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); |
559 | c3d2689d | balrog | if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ |
560 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); |
561 | c3d2689d | balrog | } |
562 | c3d2689d | balrog | |
563 | c3d2689d | balrog | static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, |
564 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
565 | c3d2689d | balrog | { |
566 | c3d2689d | balrog | if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ |
567 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); |
568 | c3d2689d | balrog | if (diff & (1 << 1)) /* SOFT_COM_REQ */ |
569 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); |
570 | c3d2689d | balrog | if (diff & (1 << 2)) /* SOFT_SDW_REQ */ |
571 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); |
572 | c3d2689d | balrog | if (diff & (1 << 3)) /* SOFT_USB_REQ */ |
573 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); |
574 | c3d2689d | balrog | } |
575 | c3d2689d | balrog | |
576 | c227f099 | Anthony Liguori | static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr, |
577 | 4b3fedf3 | Avi Kivity | uint64_t value, unsigned size)
|
578 | c3d2689d | balrog | { |
579 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
580 | c3d2689d | balrog | int64_t now, ticks; |
581 | c3d2689d | balrog | int div, mult;
|
582 | c3d2689d | balrog | static const int bypass_div[4] = { 1, 2, 4, 4 }; |
583 | c3d2689d | balrog | uint16_t diff; |
584 | c3d2689d | balrog | |
585 | 4b3fedf3 | Avi Kivity | if (size != 2) { |
586 | 4b3fedf3 | Avi Kivity | return omap_badwidth_write16(opaque, addr, value);
|
587 | 4b3fedf3 | Avi Kivity | } |
588 | 4b3fedf3 | Avi Kivity | |
589 | 8da3ff18 | pbrook | switch (addr) {
|
590 | c3d2689d | balrog | case 0x00: /* COUNTER_32_LSB */ |
591 | c3d2689d | balrog | case 0x04: /* COUNTER_32_MSB */ |
592 | c3d2689d | balrog | case 0x08: /* COUNTER_HIGH_FREQ_LSB */ |
593 | c3d2689d | balrog | case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ |
594 | c3d2689d | balrog | case 0x14: /* IT_STATUS */ |
595 | c3d2689d | balrog | case 0x40: /* STATUS_REQ */ |
596 | c3d2689d | balrog | OMAP_RO_REG(addr); |
597 | c3d2689d | balrog | break;
|
598 | c3d2689d | balrog | |
599 | c3d2689d | balrog | case 0x10: /* GAUGING_CTRL */ |
600 | c3d2689d | balrog | /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
|
601 | 8da3ff18 | pbrook | if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) { |
602 | 74475455 | Paolo Bonzini | now = qemu_get_clock_ns(vm_clock); |
603 | c3d2689d | balrog | |
604 | c3d2689d | balrog | if (value & 1) |
605 | c3d2689d | balrog | s->ulpd_gauge_start = now; |
606 | c3d2689d | balrog | else {
|
607 | c3d2689d | balrog | now -= s->ulpd_gauge_start; |
608 | c3d2689d | balrog | |
609 | c3d2689d | balrog | /* 32-kHz ticks */
|
610 | 6ee093c9 | Juan Quintela | ticks = muldiv64(now, 32768, get_ticks_per_sec());
|
611 | c3d2689d | balrog | s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; |
612 | c3d2689d | balrog | s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; |
613 | c3d2689d | balrog | if (ticks >> 32) /* OVERFLOW_32K */ |
614 | c3d2689d | balrog | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; |
615 | c3d2689d | balrog | |
616 | c3d2689d | balrog | /* High frequency ticks */
|
617 | 6ee093c9 | Juan Quintela | ticks = muldiv64(now, 12000000, get_ticks_per_sec());
|
618 | c3d2689d | balrog | s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; |
619 | c3d2689d | balrog | s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; |
620 | c3d2689d | balrog | if (ticks >> 32) /* OVERFLOW_HI_FREQ */ |
621 | c3d2689d | balrog | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; |
622 | c3d2689d | balrog | |
623 | c3d2689d | balrog | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ |
624 | 0919ac78 | Peter Maydell | qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
|
625 | c3d2689d | balrog | } |
626 | c3d2689d | balrog | } |
627 | 8da3ff18 | pbrook | s->ulpd_pm_regs[addr >> 2] = value;
|
628 | c3d2689d | balrog | break;
|
629 | c3d2689d | balrog | |
630 | c3d2689d | balrog | case 0x18: /* Reserved */ |
631 | c3d2689d | balrog | case 0x1c: /* Reserved */ |
632 | c3d2689d | balrog | case 0x20: /* Reserved */ |
633 | c3d2689d | balrog | case 0x28: /* Reserved */ |
634 | c3d2689d | balrog | case 0x2c: /* Reserved */ |
635 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
636 | c3d2689d | balrog | case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
637 | c3d2689d | balrog | case 0x38: /* COUNTER_32_FIQ */ |
638 | c3d2689d | balrog | case 0x48: /* LOCL_TIME */ |
639 | c3d2689d | balrog | case 0x50: /* POWER_CTRL */ |
640 | 8da3ff18 | pbrook | s->ulpd_pm_regs[addr >> 2] = value;
|
641 | c3d2689d | balrog | break;
|
642 | c3d2689d | balrog | |
643 | c3d2689d | balrog | case 0x30: /* CLOCK_CTRL */ |
644 | 8da3ff18 | pbrook | diff = s->ulpd_pm_regs[addr >> 2] ^ value;
|
645 | 8da3ff18 | pbrook | s->ulpd_pm_regs[addr >> 2] = value & 0x3f; |
646 | c3d2689d | balrog | omap_ulpd_clk_update(s, diff, value); |
647 | c3d2689d | balrog | break;
|
648 | c3d2689d | balrog | |
649 | c3d2689d | balrog | case 0x34: /* SOFT_REQ */ |
650 | 8da3ff18 | pbrook | diff = s->ulpd_pm_regs[addr >> 2] ^ value;
|
651 | 8da3ff18 | pbrook | s->ulpd_pm_regs[addr >> 2] = value & 0x1f; |
652 | c3d2689d | balrog | omap_ulpd_req_update(s, diff, value); |
653 | c3d2689d | balrog | break;
|
654 | c3d2689d | balrog | |
655 | c3d2689d | balrog | case 0x3c: /* DPLL_CTRL */ |
656 | c3d2689d | balrog | /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
|
657 | c3d2689d | balrog | * omitted altogether, probably a typo. */
|
658 | c3d2689d | balrog | /* This register has identical semantics with DPLL(1:3) control
|
659 | c3d2689d | balrog | * registers, see omap_dpll_write() */
|
660 | 8da3ff18 | pbrook | diff = s->ulpd_pm_regs[addr >> 2] & value;
|
661 | 8da3ff18 | pbrook | s->ulpd_pm_regs[addr >> 2] = value & 0x2fff; |
662 | c3d2689d | balrog | if (diff & (0x3ff << 2)) { |
663 | c3d2689d | balrog | if (value & (1 << 4)) { /* PLL_ENABLE */ |
664 | c3d2689d | balrog | div = ((value >> 5) & 3) + 1; /* PLL_DIV */ |
665 | c3d2689d | balrog | mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ |
666 | c3d2689d | balrog | } else {
|
667 | c3d2689d | balrog | div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ |
668 | c3d2689d | balrog | mult = 1;
|
669 | c3d2689d | balrog | } |
670 | c3d2689d | balrog | omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
|
671 | c3d2689d | balrog | } |
672 | c3d2689d | balrog | |
673 | c3d2689d | balrog | /* Enter the desired mode. */
|
674 | 8da3ff18 | pbrook | s->ulpd_pm_regs[addr >> 2] =
|
675 | 8da3ff18 | pbrook | (s->ulpd_pm_regs[addr >> 2] & 0xfffe) | |
676 | 8da3ff18 | pbrook | ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1); |
677 | c3d2689d | balrog | |
678 | c3d2689d | balrog | /* Act as if the lock is restored. */
|
679 | 8da3ff18 | pbrook | s->ulpd_pm_regs[addr >> 2] |= 2; |
680 | c3d2689d | balrog | break;
|
681 | c3d2689d | balrog | |
682 | c3d2689d | balrog | case 0x4c: /* APLL_CTRL */ |
683 | 8da3ff18 | pbrook | diff = s->ulpd_pm_regs[addr >> 2] & value;
|
684 | 8da3ff18 | pbrook | s->ulpd_pm_regs[addr >> 2] = value & 0xf; |
685 | c3d2689d | balrog | if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ |
686 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
|
687 | c3d2689d | balrog | (value & (1 << 0)) ? "apll" : "dpll4")); |
688 | c3d2689d | balrog | break;
|
689 | c3d2689d | balrog | |
690 | c3d2689d | balrog | default:
|
691 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
692 | c3d2689d | balrog | } |
693 | c3d2689d | balrog | } |
694 | c3d2689d | balrog | |
695 | 4b3fedf3 | Avi Kivity | static const MemoryRegionOps omap_ulpd_pm_ops = { |
696 | 4b3fedf3 | Avi Kivity | .read = omap_ulpd_pm_read, |
697 | 4b3fedf3 | Avi Kivity | .write = omap_ulpd_pm_write, |
698 | 4b3fedf3 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
699 | c3d2689d | balrog | }; |
700 | c3d2689d | balrog | |
701 | c3d2689d | balrog | static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) |
702 | c3d2689d | balrog | { |
703 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; |
704 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; |
705 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; |
706 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; |
707 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; |
708 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; |
709 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; |
710 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; |
711 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; |
712 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; |
713 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; |
714 | c3d2689d | balrog | omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); |
715 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; |
716 | c3d2689d | balrog | omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); |
717 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; |
718 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; |
719 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; |
720 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ |
721 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; |
722 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; |
723 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; |
724 | c3d2689d | balrog | omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4); |
725 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); |
726 | c3d2689d | balrog | } |
727 | c3d2689d | balrog | |
728 | 4b3fedf3 | Avi Kivity | static void omap_ulpd_pm_init(MemoryRegion *system_memory, |
729 | 4b3fedf3 | Avi Kivity | target_phys_addr_t base, |
730 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
731 | c3d2689d | balrog | { |
732 | 4b3fedf3 | Avi Kivity | memory_region_init_io(&mpu->ulpd_pm_iomem, &omap_ulpd_pm_ops, mpu, |
733 | 4b3fedf3 | Avi Kivity | "omap-ulpd-pm", 0x800); |
734 | 4b3fedf3 | Avi Kivity | memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem); |
735 | c3d2689d | balrog | omap_ulpd_pm_reset(mpu); |
736 | c3d2689d | balrog | } |
737 | c3d2689d | balrog | |
738 | c3d2689d | balrog | /* OMAP Pin Configuration */
|
739 | 4b3fedf3 | Avi Kivity | static uint64_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr, |
740 | 4b3fedf3 | Avi Kivity | unsigned size)
|
741 | c3d2689d | balrog | { |
742 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
743 | c3d2689d | balrog | |
744 | 4b3fedf3 | Avi Kivity | if (size != 4) { |
745 | 4b3fedf3 | Avi Kivity | return omap_badwidth_read32(opaque, addr);
|
746 | 4b3fedf3 | Avi Kivity | } |
747 | 4b3fedf3 | Avi Kivity | |
748 | 8da3ff18 | pbrook | switch (addr) {
|
749 | c3d2689d | balrog | case 0x00: /* FUNC_MUX_CTRL_0 */ |
750 | c3d2689d | balrog | case 0x04: /* FUNC_MUX_CTRL_1 */ |
751 | c3d2689d | balrog | case 0x08: /* FUNC_MUX_CTRL_2 */ |
752 | 8da3ff18 | pbrook | return s->func_mux_ctrl[addr >> 2]; |
753 | c3d2689d | balrog | |
754 | c3d2689d | balrog | case 0x0c: /* COMP_MODE_CTRL_0 */ |
755 | c3d2689d | balrog | return s->comp_mode_ctrl[0]; |
756 | c3d2689d | balrog | |
757 | c3d2689d | balrog | case 0x10: /* FUNC_MUX_CTRL_3 */ |
758 | c3d2689d | balrog | case 0x14: /* FUNC_MUX_CTRL_4 */ |
759 | c3d2689d | balrog | case 0x18: /* FUNC_MUX_CTRL_5 */ |
760 | c3d2689d | balrog | case 0x1c: /* FUNC_MUX_CTRL_6 */ |
761 | c3d2689d | balrog | case 0x20: /* FUNC_MUX_CTRL_7 */ |
762 | c3d2689d | balrog | case 0x24: /* FUNC_MUX_CTRL_8 */ |
763 | c3d2689d | balrog | case 0x28: /* FUNC_MUX_CTRL_9 */ |
764 | c3d2689d | balrog | case 0x2c: /* FUNC_MUX_CTRL_A */ |
765 | c3d2689d | balrog | case 0x30: /* FUNC_MUX_CTRL_B */ |
766 | c3d2689d | balrog | case 0x34: /* FUNC_MUX_CTRL_C */ |
767 | c3d2689d | balrog | case 0x38: /* FUNC_MUX_CTRL_D */ |
768 | 8da3ff18 | pbrook | return s->func_mux_ctrl[(addr >> 2) - 1]; |
769 | c3d2689d | balrog | |
770 | c3d2689d | balrog | case 0x40: /* PULL_DWN_CTRL_0 */ |
771 | c3d2689d | balrog | case 0x44: /* PULL_DWN_CTRL_1 */ |
772 | c3d2689d | balrog | case 0x48: /* PULL_DWN_CTRL_2 */ |
773 | c3d2689d | balrog | case 0x4c: /* PULL_DWN_CTRL_3 */ |
774 | 8da3ff18 | pbrook | return s->pull_dwn_ctrl[(addr & 0xf) >> 2]; |
775 | c3d2689d | balrog | |
776 | c3d2689d | balrog | case 0x50: /* GATE_INH_CTRL_0 */ |
777 | c3d2689d | balrog | return s->gate_inh_ctrl[0]; |
778 | c3d2689d | balrog | |
779 | c3d2689d | balrog | case 0x60: /* VOLTAGE_CTRL_0 */ |
780 | c3d2689d | balrog | return s->voltage_ctrl[0]; |
781 | c3d2689d | balrog | |
782 | c3d2689d | balrog | case 0x70: /* TEST_DBG_CTRL_0 */ |
783 | c3d2689d | balrog | return s->test_dbg_ctrl[0]; |
784 | c3d2689d | balrog | |
785 | c3d2689d | balrog | case 0x80: /* MOD_CONF_CTRL_0 */ |
786 | c3d2689d | balrog | return s->mod_conf_ctrl[0]; |
787 | c3d2689d | balrog | } |
788 | c3d2689d | balrog | |
789 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
790 | c3d2689d | balrog | return 0; |
791 | c3d2689d | balrog | } |
792 | c3d2689d | balrog | |
793 | c3d2689d | balrog | static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, |
794 | c3d2689d | balrog | uint32_t diff, uint32_t value) |
795 | c3d2689d | balrog | { |
796 | c3d2689d | balrog | if (s->compat1509) {
|
797 | c3d2689d | balrog | if (diff & (1 << 9)) /* BLUETOOTH */ |
798 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
|
799 | c3d2689d | balrog | (~value >> 9) & 1); |
800 | c3d2689d | balrog | if (diff & (1 << 7)) /* USB.CLKO */ |
801 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb.clko"),
|
802 | c3d2689d | balrog | (value >> 7) & 1); |
803 | c3d2689d | balrog | } |
804 | c3d2689d | balrog | } |
805 | c3d2689d | balrog | |
806 | c3d2689d | balrog | static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, |
807 | c3d2689d | balrog | uint32_t diff, uint32_t value) |
808 | c3d2689d | balrog | { |
809 | c3d2689d | balrog | if (s->compat1509) {
|
810 | c3d2689d | balrog | if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */ |
811 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
|
812 | c3d2689d | balrog | (value >> 31) & 1); |
813 | c3d2689d | balrog | if (diff & (1 << 1)) /* CLK32K */ |
814 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "clk32k_out"),
|
815 | c3d2689d | balrog | (~value >> 1) & 1); |
816 | c3d2689d | balrog | } |
817 | c3d2689d | balrog | } |
818 | c3d2689d | balrog | |
819 | c3d2689d | balrog | static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, |
820 | c3d2689d | balrog | uint32_t diff, uint32_t value) |
821 | c3d2689d | balrog | { |
822 | c3d2689d | balrog | if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */ |
823 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "uart3_ck"),
|
824 | c3d2689d | balrog | omap_findclk(s, ((value >> 31) & 1) ? |
825 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
826 | c3d2689d | balrog | if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ |
827 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "uart2_ck"),
|
828 | c3d2689d | balrog | omap_findclk(s, ((value >> 30) & 1) ? |
829 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
830 | c3d2689d | balrog | if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ |
831 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "uart1_ck"),
|
832 | c3d2689d | balrog | omap_findclk(s, ((value >> 29) & 1) ? |
833 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
834 | c3d2689d | balrog | if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ |
835 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "mmc_ck"),
|
836 | c3d2689d | balrog | omap_findclk(s, ((value >> 23) & 1) ? |
837 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
838 | c3d2689d | balrog | if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ |
839 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
|
840 | c3d2689d | balrog | omap_findclk(s, ((value >> 12) & 1) ? |
841 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
842 | c3d2689d | balrog | if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ |
843 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); |
844 | c3d2689d | balrog | } |
845 | c3d2689d | balrog | |
846 | c227f099 | Anthony Liguori | static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr, |
847 | 4b3fedf3 | Avi Kivity | uint64_t value, unsigned size)
|
848 | c3d2689d | balrog | { |
849 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
850 | c3d2689d | balrog | uint32_t diff; |
851 | c3d2689d | balrog | |
852 | 4b3fedf3 | Avi Kivity | if (size != 4) { |
853 | 4b3fedf3 | Avi Kivity | return omap_badwidth_write32(opaque, addr, value);
|
854 | 4b3fedf3 | Avi Kivity | } |
855 | 4b3fedf3 | Avi Kivity | |
856 | 8da3ff18 | pbrook | switch (addr) {
|
857 | c3d2689d | balrog | case 0x00: /* FUNC_MUX_CTRL_0 */ |
858 | 8da3ff18 | pbrook | diff = s->func_mux_ctrl[addr >> 2] ^ value;
|
859 | 8da3ff18 | pbrook | s->func_mux_ctrl[addr >> 2] = value;
|
860 | c3d2689d | balrog | omap_pin_funcmux0_update(s, diff, value); |
861 | c3d2689d | balrog | return;
|
862 | c3d2689d | balrog | |
863 | c3d2689d | balrog | case 0x04: /* FUNC_MUX_CTRL_1 */ |
864 | 8da3ff18 | pbrook | diff = s->func_mux_ctrl[addr >> 2] ^ value;
|
865 | 8da3ff18 | pbrook | s->func_mux_ctrl[addr >> 2] = value;
|
866 | c3d2689d | balrog | omap_pin_funcmux1_update(s, diff, value); |
867 | c3d2689d | balrog | return;
|
868 | c3d2689d | balrog | |
869 | c3d2689d | balrog | case 0x08: /* FUNC_MUX_CTRL_2 */ |
870 | 8da3ff18 | pbrook | s->func_mux_ctrl[addr >> 2] = value;
|
871 | c3d2689d | balrog | return;
|
872 | c3d2689d | balrog | |
873 | c3d2689d | balrog | case 0x0c: /* COMP_MODE_CTRL_0 */ |
874 | c3d2689d | balrog | s->comp_mode_ctrl[0] = value;
|
875 | c3d2689d | balrog | s->compat1509 = (value != 0x0000eaef);
|
876 | c3d2689d | balrog | omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); |
877 | c3d2689d | balrog | omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); |
878 | c3d2689d | balrog | return;
|
879 | c3d2689d | balrog | |
880 | c3d2689d | balrog | case 0x10: /* FUNC_MUX_CTRL_3 */ |
881 | c3d2689d | balrog | case 0x14: /* FUNC_MUX_CTRL_4 */ |
882 | c3d2689d | balrog | case 0x18: /* FUNC_MUX_CTRL_5 */ |
883 | c3d2689d | balrog | case 0x1c: /* FUNC_MUX_CTRL_6 */ |
884 | c3d2689d | balrog | case 0x20: /* FUNC_MUX_CTRL_7 */ |
885 | c3d2689d | balrog | case 0x24: /* FUNC_MUX_CTRL_8 */ |
886 | c3d2689d | balrog | case 0x28: /* FUNC_MUX_CTRL_9 */ |
887 | c3d2689d | balrog | case 0x2c: /* FUNC_MUX_CTRL_A */ |
888 | c3d2689d | balrog | case 0x30: /* FUNC_MUX_CTRL_B */ |
889 | c3d2689d | balrog | case 0x34: /* FUNC_MUX_CTRL_C */ |
890 | c3d2689d | balrog | case 0x38: /* FUNC_MUX_CTRL_D */ |
891 | 8da3ff18 | pbrook | s->func_mux_ctrl[(addr >> 2) - 1] = value; |
892 | c3d2689d | balrog | return;
|
893 | c3d2689d | balrog | |
894 | c3d2689d | balrog | case 0x40: /* PULL_DWN_CTRL_0 */ |
895 | c3d2689d | balrog | case 0x44: /* PULL_DWN_CTRL_1 */ |
896 | c3d2689d | balrog | case 0x48: /* PULL_DWN_CTRL_2 */ |
897 | c3d2689d | balrog | case 0x4c: /* PULL_DWN_CTRL_3 */ |
898 | 8da3ff18 | pbrook | s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value; |
899 | c3d2689d | balrog | return;
|
900 | c3d2689d | balrog | |
901 | c3d2689d | balrog | case 0x50: /* GATE_INH_CTRL_0 */ |
902 | c3d2689d | balrog | s->gate_inh_ctrl[0] = value;
|
903 | c3d2689d | balrog | return;
|
904 | c3d2689d | balrog | |
905 | c3d2689d | balrog | case 0x60: /* VOLTAGE_CTRL_0 */ |
906 | c3d2689d | balrog | s->voltage_ctrl[0] = value;
|
907 | c3d2689d | balrog | return;
|
908 | c3d2689d | balrog | |
909 | c3d2689d | balrog | case 0x70: /* TEST_DBG_CTRL_0 */ |
910 | c3d2689d | balrog | s->test_dbg_ctrl[0] = value;
|
911 | c3d2689d | balrog | return;
|
912 | c3d2689d | balrog | |
913 | c3d2689d | balrog | case 0x80: /* MOD_CONF_CTRL_0 */ |
914 | c3d2689d | balrog | diff = s->mod_conf_ctrl[0] ^ value;
|
915 | c3d2689d | balrog | s->mod_conf_ctrl[0] = value;
|
916 | c3d2689d | balrog | omap_pin_modconf1_update(s, diff, value); |
917 | c3d2689d | balrog | return;
|
918 | c3d2689d | balrog | |
919 | c3d2689d | balrog | default:
|
920 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
921 | c3d2689d | balrog | } |
922 | c3d2689d | balrog | } |
923 | c3d2689d | balrog | |
924 | 4b3fedf3 | Avi Kivity | static const MemoryRegionOps omap_pin_cfg_ops = { |
925 | 4b3fedf3 | Avi Kivity | .read = omap_pin_cfg_read, |
926 | 4b3fedf3 | Avi Kivity | .write = omap_pin_cfg_write, |
927 | 4b3fedf3 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
928 | c3d2689d | balrog | }; |
929 | c3d2689d | balrog | |
930 | c3d2689d | balrog | static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) |
931 | c3d2689d | balrog | { |
932 | c3d2689d | balrog | /* Start in Compatibility Mode. */
|
933 | c3d2689d | balrog | mpu->compat1509 = 1;
|
934 | c3d2689d | balrog | omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); |
935 | c3d2689d | balrog | omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); |
936 | c3d2689d | balrog | omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); |
937 | c3d2689d | balrog | memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); |
938 | c3d2689d | balrog | memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); |
939 | c3d2689d | balrog | memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); |
940 | c3d2689d | balrog | memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); |
941 | c3d2689d | balrog | memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); |
942 | c3d2689d | balrog | memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); |
943 | c3d2689d | balrog | memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); |
944 | c3d2689d | balrog | } |
945 | c3d2689d | balrog | |
946 | 4b3fedf3 | Avi Kivity | static void omap_pin_cfg_init(MemoryRegion *system_memory, |
947 | 4b3fedf3 | Avi Kivity | target_phys_addr_t base, |
948 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
949 | c3d2689d | balrog | { |
950 | 4b3fedf3 | Avi Kivity | memory_region_init_io(&mpu->pin_cfg_iomem, &omap_pin_cfg_ops, mpu, |
951 | 4b3fedf3 | Avi Kivity | "omap-pin-cfg", 0x800); |
952 | 4b3fedf3 | Avi Kivity | memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem); |
953 | c3d2689d | balrog | omap_pin_cfg_reset(mpu); |
954 | c3d2689d | balrog | } |
955 | c3d2689d | balrog | |
956 | c3d2689d | balrog | /* Device Identification, Die Identification */
|
957 | 4b3fedf3 | Avi Kivity | static uint64_t omap_id_read(void *opaque, target_phys_addr_t addr, |
958 | 4b3fedf3 | Avi Kivity | unsigned size)
|
959 | c3d2689d | balrog | { |
960 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
961 | c3d2689d | balrog | |
962 | 4b3fedf3 | Avi Kivity | if (size != 4) { |
963 | 4b3fedf3 | Avi Kivity | return omap_badwidth_read32(opaque, addr);
|
964 | 4b3fedf3 | Avi Kivity | } |
965 | 4b3fedf3 | Avi Kivity | |
966 | c3d2689d | balrog | switch (addr) {
|
967 | c3d2689d | balrog | case 0xfffe1800: /* DIE_ID_LSB */ |
968 | c3d2689d | balrog | return 0xc9581f0e; |
969 | c3d2689d | balrog | case 0xfffe1804: /* DIE_ID_MSB */ |
970 | c3d2689d | balrog | return 0xa8858bfa; |
971 | c3d2689d | balrog | |
972 | c3d2689d | balrog | case 0xfffe2000: /* PRODUCT_ID_LSB */ |
973 | c3d2689d | balrog | return 0x00aaaafc; |
974 | c3d2689d | balrog | case 0xfffe2004: /* PRODUCT_ID_MSB */ |
975 | c3d2689d | balrog | return 0xcafeb574; |
976 | c3d2689d | balrog | |
977 | c3d2689d | balrog | case 0xfffed400: /* JTAG_ID_LSB */ |
978 | c3d2689d | balrog | switch (s->mpu_model) {
|
979 | c3d2689d | balrog | case omap310:
|
980 | c3d2689d | balrog | return 0x03310315; |
981 | c3d2689d | balrog | case omap1510:
|
982 | c3d2689d | balrog | return 0x03310115; |
983 | 827df9f3 | balrog | default:
|
984 | 2ac71179 | Paul Brook | hw_error("%s: bad mpu model\n", __FUNCTION__);
|
985 | c3d2689d | balrog | } |
986 | c3d2689d | balrog | break;
|
987 | c3d2689d | balrog | |
988 | c3d2689d | balrog | case 0xfffed404: /* JTAG_ID_MSB */ |
989 | c3d2689d | balrog | switch (s->mpu_model) {
|
990 | c3d2689d | balrog | case omap310:
|
991 | c3d2689d | balrog | return 0xfb57402f; |
992 | c3d2689d | balrog | case omap1510:
|
993 | c3d2689d | balrog | return 0xfb47002f; |
994 | 827df9f3 | balrog | default:
|
995 | 2ac71179 | Paul Brook | hw_error("%s: bad mpu model\n", __FUNCTION__);
|
996 | c3d2689d | balrog | } |
997 | c3d2689d | balrog | break;
|
998 | c3d2689d | balrog | } |
999 | c3d2689d | balrog | |
1000 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1001 | c3d2689d | balrog | return 0; |
1002 | c3d2689d | balrog | } |
1003 | c3d2689d | balrog | |
1004 | c227f099 | Anthony Liguori | static void omap_id_write(void *opaque, target_phys_addr_t addr, |
1005 | 4b3fedf3 | Avi Kivity | uint64_t value, unsigned size)
|
1006 | c3d2689d | balrog | { |
1007 | 4b3fedf3 | Avi Kivity | if (size != 4) { |
1008 | 4b3fedf3 | Avi Kivity | return omap_badwidth_write32(opaque, addr, value);
|
1009 | 4b3fedf3 | Avi Kivity | } |
1010 | 4b3fedf3 | Avi Kivity | |
1011 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1012 | c3d2689d | balrog | } |
1013 | c3d2689d | balrog | |
1014 | 4b3fedf3 | Avi Kivity | static const MemoryRegionOps omap_id_ops = { |
1015 | 4b3fedf3 | Avi Kivity | .read = omap_id_read, |
1016 | 4b3fedf3 | Avi Kivity | .write = omap_id_write, |
1017 | 4b3fedf3 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
1018 | c3d2689d | balrog | }; |
1019 | c3d2689d | balrog | |
1020 | 4b3fedf3 | Avi Kivity | static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu) |
1021 | c3d2689d | balrog | { |
1022 | 4b3fedf3 | Avi Kivity | memory_region_init_io(&mpu->id_iomem, &omap_id_ops, mpu, |
1023 | 4b3fedf3 | Avi Kivity | "omap-id", 0x100000000ULL); |
1024 | 4b3fedf3 | Avi Kivity | memory_region_init_alias(&mpu->id_iomem_e18, "omap-id-e18", &mpu->id_iomem,
|
1025 | 4b3fedf3 | Avi Kivity | 0xfffe1800, 0x800); |
1026 | 4b3fedf3 | Avi Kivity | memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18);
|
1027 | 4b3fedf3 | Avi Kivity | memory_region_init_alias(&mpu->id_iomem_ed4, "omap-id-ed4", &mpu->id_iomem,
|
1028 | 4b3fedf3 | Avi Kivity | 0xfffed400, 0x100); |
1029 | 4b3fedf3 | Avi Kivity | memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4);
|
1030 | 4b3fedf3 | Avi Kivity | if (!cpu_is_omap15xx(mpu)) {
|
1031 | 4b3fedf3 | Avi Kivity | memory_region_init_alias(&mpu->id_iomem_ed4, "omap-id-e20",
|
1032 | 4b3fedf3 | Avi Kivity | &mpu->id_iomem, 0xfffe2000, 0x800); |
1033 | 4b3fedf3 | Avi Kivity | memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20);
|
1034 | 4b3fedf3 | Avi Kivity | } |
1035 | c3d2689d | balrog | } |
1036 | c3d2689d | balrog | |
1037 | c3d2689d | balrog | /* MPUI Control (Dummy) */
|
1038 | 4b3fedf3 | Avi Kivity | static uint64_t omap_mpui_read(void *opaque, target_phys_addr_t addr, |
1039 | 4b3fedf3 | Avi Kivity | unsigned size)
|
1040 | c3d2689d | balrog | { |
1041 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1042 | c3d2689d | balrog | |
1043 | 4b3fedf3 | Avi Kivity | if (size != 4) { |
1044 | 4b3fedf3 | Avi Kivity | return omap_badwidth_read32(opaque, addr);
|
1045 | 4b3fedf3 | Avi Kivity | } |
1046 | 4b3fedf3 | Avi Kivity | |
1047 | 8da3ff18 | pbrook | switch (addr) {
|
1048 | c3d2689d | balrog | case 0x00: /* CTRL */ |
1049 | c3d2689d | balrog | return s->mpui_ctrl;
|
1050 | c3d2689d | balrog | case 0x04: /* DEBUG_ADDR */ |
1051 | c3d2689d | balrog | return 0x01ffffff; |
1052 | c3d2689d | balrog | case 0x08: /* DEBUG_DATA */ |
1053 | c3d2689d | balrog | return 0xffffffff; |
1054 | c3d2689d | balrog | case 0x0c: /* DEBUG_FLAG */ |
1055 | c3d2689d | balrog | return 0x00000800; |
1056 | c3d2689d | balrog | case 0x10: /* STATUS */ |
1057 | c3d2689d | balrog | return 0x00000000; |
1058 | c3d2689d | balrog | |
1059 | c3d2689d | balrog | /* Not in OMAP310 */
|
1060 | c3d2689d | balrog | case 0x14: /* DSP_STATUS */ |
1061 | c3d2689d | balrog | case 0x18: /* DSP_BOOT_CONFIG */ |
1062 | c3d2689d | balrog | return 0x00000000; |
1063 | c3d2689d | balrog | case 0x1c: /* DSP_MPUI_CONFIG */ |
1064 | c3d2689d | balrog | return 0x0000ffff; |
1065 | c3d2689d | balrog | } |
1066 | c3d2689d | balrog | |
1067 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1068 | c3d2689d | balrog | return 0; |
1069 | c3d2689d | balrog | } |
1070 | c3d2689d | balrog | |
1071 | c227f099 | Anthony Liguori | static void omap_mpui_write(void *opaque, target_phys_addr_t addr, |
1072 | 4b3fedf3 | Avi Kivity | uint64_t value, unsigned size)
|
1073 | c3d2689d | balrog | { |
1074 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1075 | c3d2689d | balrog | |
1076 | 4b3fedf3 | Avi Kivity | if (size != 4) { |
1077 | 4b3fedf3 | Avi Kivity | return omap_badwidth_write32(opaque, addr, value);
|
1078 | 4b3fedf3 | Avi Kivity | } |
1079 | 4b3fedf3 | Avi Kivity | |
1080 | 8da3ff18 | pbrook | switch (addr) {
|
1081 | c3d2689d | balrog | case 0x00: /* CTRL */ |
1082 | c3d2689d | balrog | s->mpui_ctrl = value & 0x007fffff;
|
1083 | c3d2689d | balrog | break;
|
1084 | c3d2689d | balrog | |
1085 | c3d2689d | balrog | case 0x04: /* DEBUG_ADDR */ |
1086 | c3d2689d | balrog | case 0x08: /* DEBUG_DATA */ |
1087 | c3d2689d | balrog | case 0x0c: /* DEBUG_FLAG */ |
1088 | c3d2689d | balrog | case 0x10: /* STATUS */ |
1089 | c3d2689d | balrog | /* Not in OMAP310 */
|
1090 | c3d2689d | balrog | case 0x14: /* DSP_STATUS */ |
1091 | c3d2689d | balrog | OMAP_RO_REG(addr); |
1092 | c3d2689d | balrog | case 0x18: /* DSP_BOOT_CONFIG */ |
1093 | c3d2689d | balrog | case 0x1c: /* DSP_MPUI_CONFIG */ |
1094 | c3d2689d | balrog | break;
|
1095 | c3d2689d | balrog | |
1096 | c3d2689d | balrog | default:
|
1097 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1098 | c3d2689d | balrog | } |
1099 | c3d2689d | balrog | } |
1100 | c3d2689d | balrog | |
1101 | 4b3fedf3 | Avi Kivity | static const MemoryRegionOps omap_mpui_ops = { |
1102 | 4b3fedf3 | Avi Kivity | .read = omap_mpui_read, |
1103 | 4b3fedf3 | Avi Kivity | .write = omap_mpui_write, |
1104 | 4b3fedf3 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
1105 | c3d2689d | balrog | }; |
1106 | c3d2689d | balrog | |
1107 | c3d2689d | balrog | static void omap_mpui_reset(struct omap_mpu_state_s *s) |
1108 | c3d2689d | balrog | { |
1109 | c3d2689d | balrog | s->mpui_ctrl = 0x0003ff1b;
|
1110 | c3d2689d | balrog | } |
1111 | c3d2689d | balrog | |
1112 | 4b3fedf3 | Avi Kivity | static void omap_mpui_init(MemoryRegion *memory, target_phys_addr_t base, |
1113 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
1114 | c3d2689d | balrog | { |
1115 | 4b3fedf3 | Avi Kivity | memory_region_init_io(&mpu->mpui_iomem, &omap_mpui_ops, mpu, |
1116 | 4b3fedf3 | Avi Kivity | "omap-mpui", 0x100); |
1117 | 4b3fedf3 | Avi Kivity | memory_region_add_subregion(memory, base, &mpu->mpui_iomem); |
1118 | c3d2689d | balrog | |
1119 | c3d2689d | balrog | omap_mpui_reset(mpu); |
1120 | c3d2689d | balrog | } |
1121 | c3d2689d | balrog | |
1122 | c3d2689d | balrog | /* TIPB Bridges */
|
1123 | c3d2689d | balrog | struct omap_tipb_bridge_s {
|
1124 | c3d2689d | balrog | qemu_irq abort; |
1125 | 4b3fedf3 | Avi Kivity | MemoryRegion iomem; |
1126 | c3d2689d | balrog | |
1127 | c3d2689d | balrog | int width_intr;
|
1128 | c3d2689d | balrog | uint16_t control; |
1129 | c3d2689d | balrog | uint16_t alloc; |
1130 | c3d2689d | balrog | uint16_t buffer; |
1131 | c3d2689d | balrog | uint16_t enh_control; |
1132 | c3d2689d | balrog | }; |
1133 | c3d2689d | balrog | |
1134 | 4b3fedf3 | Avi Kivity | static uint64_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr, |
1135 | 4b3fedf3 | Avi Kivity | unsigned size)
|
1136 | c3d2689d | balrog | { |
1137 | c3d2689d | balrog | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
1138 | c3d2689d | balrog | |
1139 | 4b3fedf3 | Avi Kivity | if (size < 2) { |
1140 | 4b3fedf3 | Avi Kivity | return omap_badwidth_read16(opaque, addr);
|
1141 | 4b3fedf3 | Avi Kivity | } |
1142 | 4b3fedf3 | Avi Kivity | |
1143 | 8da3ff18 | pbrook | switch (addr) {
|
1144 | c3d2689d | balrog | case 0x00: /* TIPB_CNTL */ |
1145 | c3d2689d | balrog | return s->control;
|
1146 | c3d2689d | balrog | case 0x04: /* TIPB_BUS_ALLOC */ |
1147 | c3d2689d | balrog | return s->alloc;
|
1148 | c3d2689d | balrog | case 0x08: /* MPU_TIPB_CNTL */ |
1149 | c3d2689d | balrog | return s->buffer;
|
1150 | c3d2689d | balrog | case 0x0c: /* ENHANCED_TIPB_CNTL */ |
1151 | c3d2689d | balrog | return s->enh_control;
|
1152 | c3d2689d | balrog | case 0x10: /* ADDRESS_DBG */ |
1153 | c3d2689d | balrog | case 0x14: /* DATA_DEBUG_LOW */ |
1154 | c3d2689d | balrog | case 0x18: /* DATA_DEBUG_HIGH */ |
1155 | c3d2689d | balrog | return 0xffff; |
1156 | c3d2689d | balrog | case 0x1c: /* DEBUG_CNTR_SIG */ |
1157 | c3d2689d | balrog | return 0x00f8; |
1158 | c3d2689d | balrog | } |
1159 | c3d2689d | balrog | |
1160 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1161 | c3d2689d | balrog | return 0; |
1162 | c3d2689d | balrog | } |
1163 | c3d2689d | balrog | |
1164 | c227f099 | Anthony Liguori | static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr, |
1165 | 4b3fedf3 | Avi Kivity | uint64_t value, unsigned size)
|
1166 | c3d2689d | balrog | { |
1167 | c3d2689d | balrog | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
1168 | c3d2689d | balrog | |
1169 | 4b3fedf3 | Avi Kivity | if (size < 2) { |
1170 | 4b3fedf3 | Avi Kivity | return omap_badwidth_write16(opaque, addr, value);
|
1171 | 4b3fedf3 | Avi Kivity | } |
1172 | 4b3fedf3 | Avi Kivity | |
1173 | 8da3ff18 | pbrook | switch (addr) {
|
1174 | c3d2689d | balrog | case 0x00: /* TIPB_CNTL */ |
1175 | c3d2689d | balrog | s->control = value & 0xffff;
|
1176 | c3d2689d | balrog | break;
|
1177 | c3d2689d | balrog | |
1178 | c3d2689d | balrog | case 0x04: /* TIPB_BUS_ALLOC */ |
1179 | c3d2689d | balrog | s->alloc = value & 0x003f;
|
1180 | c3d2689d | balrog | break;
|
1181 | c3d2689d | balrog | |
1182 | c3d2689d | balrog | case 0x08: /* MPU_TIPB_CNTL */ |
1183 | c3d2689d | balrog | s->buffer = value & 0x0003;
|
1184 | c3d2689d | balrog | break;
|
1185 | c3d2689d | balrog | |
1186 | c3d2689d | balrog | case 0x0c: /* ENHANCED_TIPB_CNTL */ |
1187 | c3d2689d | balrog | s->width_intr = !(value & 2);
|
1188 | c3d2689d | balrog | s->enh_control = value & 0x000f;
|
1189 | c3d2689d | balrog | break;
|
1190 | c3d2689d | balrog | |
1191 | c3d2689d | balrog | case 0x10: /* ADDRESS_DBG */ |
1192 | c3d2689d | balrog | case 0x14: /* DATA_DEBUG_LOW */ |
1193 | c3d2689d | balrog | case 0x18: /* DATA_DEBUG_HIGH */ |
1194 | c3d2689d | balrog | case 0x1c: /* DEBUG_CNTR_SIG */ |
1195 | c3d2689d | balrog | OMAP_RO_REG(addr); |
1196 | c3d2689d | balrog | break;
|
1197 | c3d2689d | balrog | |
1198 | c3d2689d | balrog | default:
|
1199 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1200 | c3d2689d | balrog | } |
1201 | c3d2689d | balrog | } |
1202 | c3d2689d | balrog | |
1203 | 4b3fedf3 | Avi Kivity | static const MemoryRegionOps omap_tipb_bridge_ops = { |
1204 | 4b3fedf3 | Avi Kivity | .read = omap_tipb_bridge_read, |
1205 | 4b3fedf3 | Avi Kivity | .write = omap_tipb_bridge_write, |
1206 | 4b3fedf3 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
1207 | c3d2689d | balrog | }; |
1208 | c3d2689d | balrog | |
1209 | c3d2689d | balrog | static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) |
1210 | c3d2689d | balrog | { |
1211 | c3d2689d | balrog | s->control = 0xffff;
|
1212 | c3d2689d | balrog | s->alloc = 0x0009;
|
1213 | c3d2689d | balrog | s->buffer = 0x0000;
|
1214 | c3d2689d | balrog | s->enh_control = 0x000f;
|
1215 | c3d2689d | balrog | } |
1216 | c3d2689d | balrog | |
1217 | 4b3fedf3 | Avi Kivity | static struct omap_tipb_bridge_s *omap_tipb_bridge_init( |
1218 | 4b3fedf3 | Avi Kivity | MemoryRegion *memory, target_phys_addr_t base, |
1219 | 4b3fedf3 | Avi Kivity | qemu_irq abort_irq, omap_clk clk) |
1220 | c3d2689d | balrog | { |
1221 | c3d2689d | balrog | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) |
1222 | 7267c094 | Anthony Liguori | g_malloc0(sizeof(struct omap_tipb_bridge_s)); |
1223 | c3d2689d | balrog | |
1224 | c3d2689d | balrog | s->abort = abort_irq; |
1225 | c3d2689d | balrog | omap_tipb_bridge_reset(s); |
1226 | c3d2689d | balrog | |
1227 | 4b3fedf3 | Avi Kivity | memory_region_init_io(&s->iomem, &omap_tipb_bridge_ops, s, |
1228 | 4b3fedf3 | Avi Kivity | "omap-tipb-bridge", 0x100); |
1229 | 4b3fedf3 | Avi Kivity | memory_region_add_subregion(memory, base, &s->iomem); |
1230 | c3d2689d | balrog | |
1231 | c3d2689d | balrog | return s;
|
1232 | c3d2689d | balrog | } |
1233 | c3d2689d | balrog | |
1234 | c3d2689d | balrog | /* Dummy Traffic Controller's Memory Interface */
|
1235 | e7aa0ae0 | Avi Kivity | static uint64_t omap_tcmi_read(void *opaque, target_phys_addr_t addr, |
1236 | e7aa0ae0 | Avi Kivity | unsigned size)
|
1237 | c3d2689d | balrog | { |
1238 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1239 | c3d2689d | balrog | uint32_t ret; |
1240 | c3d2689d | balrog | |
1241 | e7aa0ae0 | Avi Kivity | if (size != 4) { |
1242 | e7aa0ae0 | Avi Kivity | return omap_badwidth_read32(opaque, addr);
|
1243 | e7aa0ae0 | Avi Kivity | } |
1244 | e7aa0ae0 | Avi Kivity | |
1245 | 8da3ff18 | pbrook | switch (addr) {
|
1246 | d8f699cb | balrog | case 0x00: /* IMIF_PRIO */ |
1247 | d8f699cb | balrog | case 0x04: /* EMIFS_PRIO */ |
1248 | d8f699cb | balrog | case 0x08: /* EMIFF_PRIO */ |
1249 | d8f699cb | balrog | case 0x0c: /* EMIFS_CONFIG */ |
1250 | d8f699cb | balrog | case 0x10: /* EMIFS_CS0_CONFIG */ |
1251 | d8f699cb | balrog | case 0x14: /* EMIFS_CS1_CONFIG */ |
1252 | d8f699cb | balrog | case 0x18: /* EMIFS_CS2_CONFIG */ |
1253 | d8f699cb | balrog | case 0x1c: /* EMIFS_CS3_CONFIG */ |
1254 | d8f699cb | balrog | case 0x24: /* EMIFF_MRS */ |
1255 | d8f699cb | balrog | case 0x28: /* TIMEOUT1 */ |
1256 | d8f699cb | balrog | case 0x2c: /* TIMEOUT2 */ |
1257 | d8f699cb | balrog | case 0x30: /* TIMEOUT3 */ |
1258 | d8f699cb | balrog | case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ |
1259 | d8f699cb | balrog | case 0x40: /* EMIFS_CFG_DYN_WAIT */ |
1260 | 8da3ff18 | pbrook | return s->tcmi_regs[addr >> 2]; |
1261 | c3d2689d | balrog | |
1262 | d8f699cb | balrog | case 0x20: /* EMIFF_SDRAM_CONFIG */ |
1263 | 8da3ff18 | pbrook | ret = s->tcmi_regs[addr >> 2];
|
1264 | 8da3ff18 | pbrook | s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ |
1265 | c3d2689d | balrog | /* XXX: We can try using the VGA_DIRTY flag for this */
|
1266 | c3d2689d | balrog | return ret;
|
1267 | c3d2689d | balrog | } |
1268 | c3d2689d | balrog | |
1269 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1270 | c3d2689d | balrog | return 0; |
1271 | c3d2689d | balrog | } |
1272 | c3d2689d | balrog | |
1273 | c227f099 | Anthony Liguori | static void omap_tcmi_write(void *opaque, target_phys_addr_t addr, |
1274 | e7aa0ae0 | Avi Kivity | uint64_t value, unsigned size)
|
1275 | c3d2689d | balrog | { |
1276 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1277 | c3d2689d | balrog | |
1278 | e7aa0ae0 | Avi Kivity | if (size != 4) { |
1279 | e7aa0ae0 | Avi Kivity | return omap_badwidth_write32(opaque, addr, value);
|
1280 | e7aa0ae0 | Avi Kivity | } |
1281 | e7aa0ae0 | Avi Kivity | |
1282 | 8da3ff18 | pbrook | switch (addr) {
|
1283 | d8f699cb | balrog | case 0x00: /* IMIF_PRIO */ |
1284 | d8f699cb | balrog | case 0x04: /* EMIFS_PRIO */ |
1285 | d8f699cb | balrog | case 0x08: /* EMIFF_PRIO */ |
1286 | d8f699cb | balrog | case 0x10: /* EMIFS_CS0_CONFIG */ |
1287 | d8f699cb | balrog | case 0x14: /* EMIFS_CS1_CONFIG */ |
1288 | d8f699cb | balrog | case 0x18: /* EMIFS_CS2_CONFIG */ |
1289 | d8f699cb | balrog | case 0x1c: /* EMIFS_CS3_CONFIG */ |
1290 | d8f699cb | balrog | case 0x20: /* EMIFF_SDRAM_CONFIG */ |
1291 | d8f699cb | balrog | case 0x24: /* EMIFF_MRS */ |
1292 | d8f699cb | balrog | case 0x28: /* TIMEOUT1 */ |
1293 | d8f699cb | balrog | case 0x2c: /* TIMEOUT2 */ |
1294 | d8f699cb | balrog | case 0x30: /* TIMEOUT3 */ |
1295 | d8f699cb | balrog | case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ |
1296 | d8f699cb | balrog | case 0x40: /* EMIFS_CFG_DYN_WAIT */ |
1297 | 8da3ff18 | pbrook | s->tcmi_regs[addr >> 2] = value;
|
1298 | c3d2689d | balrog | break;
|
1299 | d8f699cb | balrog | case 0x0c: /* EMIFS_CONFIG */ |
1300 | 8da3ff18 | pbrook | s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4); |
1301 | c3d2689d | balrog | break;
|
1302 | c3d2689d | balrog | |
1303 | c3d2689d | balrog | default:
|
1304 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1305 | c3d2689d | balrog | } |
1306 | c3d2689d | balrog | } |
1307 | c3d2689d | balrog | |
1308 | e7aa0ae0 | Avi Kivity | static const MemoryRegionOps omap_tcmi_ops = { |
1309 | e7aa0ae0 | Avi Kivity | .read = omap_tcmi_read, |
1310 | e7aa0ae0 | Avi Kivity | .write = omap_tcmi_write, |
1311 | e7aa0ae0 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
1312 | c3d2689d | balrog | }; |
1313 | c3d2689d | balrog | |
1314 | c3d2689d | balrog | static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) |
1315 | c3d2689d | balrog | { |
1316 | c3d2689d | balrog | mpu->tcmi_regs[0x00 >> 2] = 0x00000000; |
1317 | c3d2689d | balrog | mpu->tcmi_regs[0x04 >> 2] = 0x00000000; |
1318 | c3d2689d | balrog | mpu->tcmi_regs[0x08 >> 2] = 0x00000000; |
1319 | c3d2689d | balrog | mpu->tcmi_regs[0x0c >> 2] = 0x00000010; |
1320 | c3d2689d | balrog | mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; |
1321 | c3d2689d | balrog | mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; |
1322 | c3d2689d | balrog | mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; |
1323 | c3d2689d | balrog | mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; |
1324 | c3d2689d | balrog | mpu->tcmi_regs[0x20 >> 2] = 0x00618800; |
1325 | c3d2689d | balrog | mpu->tcmi_regs[0x24 >> 2] = 0x00000037; |
1326 | c3d2689d | balrog | mpu->tcmi_regs[0x28 >> 2] = 0x00000000; |
1327 | c3d2689d | balrog | mpu->tcmi_regs[0x2c >> 2] = 0x00000000; |
1328 | c3d2689d | balrog | mpu->tcmi_regs[0x30 >> 2] = 0x00000000; |
1329 | c3d2689d | balrog | mpu->tcmi_regs[0x3c >> 2] = 0x00000003; |
1330 | c3d2689d | balrog | mpu->tcmi_regs[0x40 >> 2] = 0x00000000; |
1331 | c3d2689d | balrog | } |
1332 | c3d2689d | balrog | |
1333 | e7aa0ae0 | Avi Kivity | static void omap_tcmi_init(MemoryRegion *memory, target_phys_addr_t base, |
1334 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
1335 | c3d2689d | balrog | { |
1336 | e7aa0ae0 | Avi Kivity | memory_region_init_io(&mpu->tcmi_iomem, &omap_tcmi_ops, mpu, |
1337 | e7aa0ae0 | Avi Kivity | "omap-tcmi", 0x100); |
1338 | e7aa0ae0 | Avi Kivity | memory_region_add_subregion(memory, base, &mpu->tcmi_iomem); |
1339 | c3d2689d | balrog | omap_tcmi_reset(mpu); |
1340 | c3d2689d | balrog | } |
1341 | c3d2689d | balrog | |
1342 | c3d2689d | balrog | /* Digital phase-locked loops control */
|
1343 | b9f7bc40 | Juha Riihimäki | struct dpll_ctl_s {
|
1344 | b9f7bc40 | Juha Riihimäki | MemoryRegion iomem; |
1345 | b9f7bc40 | Juha Riihimäki | uint16_t mode; |
1346 | b9f7bc40 | Juha Riihimäki | omap_clk dpll; |
1347 | b9f7bc40 | Juha Riihimäki | }; |
1348 | b9f7bc40 | Juha Riihimäki | |
1349 | e7aa0ae0 | Avi Kivity | static uint64_t omap_dpll_read(void *opaque, target_phys_addr_t addr, |
1350 | e7aa0ae0 | Avi Kivity | unsigned size)
|
1351 | c3d2689d | balrog | { |
1352 | c3d2689d | balrog | struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
1353 | c3d2689d | balrog | |
1354 | e7aa0ae0 | Avi Kivity | if (size != 2) { |
1355 | e7aa0ae0 | Avi Kivity | return omap_badwidth_read16(opaque, addr);
|
1356 | e7aa0ae0 | Avi Kivity | } |
1357 | e7aa0ae0 | Avi Kivity | |
1358 | 8da3ff18 | pbrook | if (addr == 0x00) /* CTL_REG */ |
1359 | c3d2689d | balrog | return s->mode;
|
1360 | c3d2689d | balrog | |
1361 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1362 | c3d2689d | balrog | return 0; |
1363 | c3d2689d | balrog | } |
1364 | c3d2689d | balrog | |
1365 | c227f099 | Anthony Liguori | static void omap_dpll_write(void *opaque, target_phys_addr_t addr, |
1366 | e7aa0ae0 | Avi Kivity | uint64_t value, unsigned size)
|
1367 | c3d2689d | balrog | { |
1368 | c3d2689d | balrog | struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
1369 | c3d2689d | balrog | uint16_t diff; |
1370 | c3d2689d | balrog | static const int bypass_div[4] = { 1, 2, 4, 4 }; |
1371 | c3d2689d | balrog | int div, mult;
|
1372 | c3d2689d | balrog | |
1373 | e7aa0ae0 | Avi Kivity | if (size != 2) { |
1374 | e7aa0ae0 | Avi Kivity | return omap_badwidth_write16(opaque, addr, value);
|
1375 | e7aa0ae0 | Avi Kivity | } |
1376 | e7aa0ae0 | Avi Kivity | |
1377 | 8da3ff18 | pbrook | if (addr == 0x00) { /* CTL_REG */ |
1378 | c3d2689d | balrog | /* See omap_ulpd_pm_write() too */
|
1379 | c3d2689d | balrog | diff = s->mode & value; |
1380 | c3d2689d | balrog | s->mode = value & 0x2fff;
|
1381 | c3d2689d | balrog | if (diff & (0x3ff << 2)) { |
1382 | c3d2689d | balrog | if (value & (1 << 4)) { /* PLL_ENABLE */ |
1383 | c3d2689d | balrog | div = ((value >> 5) & 3) + 1; /* PLL_DIV */ |
1384 | c3d2689d | balrog | mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ |
1385 | c3d2689d | balrog | } else {
|
1386 | c3d2689d | balrog | div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ |
1387 | c3d2689d | balrog | mult = 1;
|
1388 | c3d2689d | balrog | } |
1389 | c3d2689d | balrog | omap_clk_setrate(s->dpll, div, mult); |
1390 | c3d2689d | balrog | } |
1391 | c3d2689d | balrog | |
1392 | c3d2689d | balrog | /* Enter the desired mode. */
|
1393 | c3d2689d | balrog | s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); |
1394 | c3d2689d | balrog | |
1395 | c3d2689d | balrog | /* Act as if the lock is restored. */
|
1396 | c3d2689d | balrog | s->mode |= 2;
|
1397 | c3d2689d | balrog | } else {
|
1398 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1399 | c3d2689d | balrog | } |
1400 | c3d2689d | balrog | } |
1401 | c3d2689d | balrog | |
1402 | e7aa0ae0 | Avi Kivity | static const MemoryRegionOps omap_dpll_ops = { |
1403 | e7aa0ae0 | Avi Kivity | .read = omap_dpll_read, |
1404 | e7aa0ae0 | Avi Kivity | .write = omap_dpll_write, |
1405 | e7aa0ae0 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
1406 | c3d2689d | balrog | }; |
1407 | c3d2689d | balrog | |
1408 | c3d2689d | balrog | static void omap_dpll_reset(struct dpll_ctl_s *s) |
1409 | c3d2689d | balrog | { |
1410 | c3d2689d | balrog | s->mode = 0x2002;
|
1411 | c3d2689d | balrog | omap_clk_setrate(s->dpll, 1, 1); |
1412 | c3d2689d | balrog | } |
1413 | c3d2689d | balrog | |
1414 | b9f7bc40 | Juha Riihimäki | static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory, |
1415 | e7aa0ae0 | Avi Kivity | target_phys_addr_t base, omap_clk clk) |
1416 | c3d2689d | balrog | { |
1417 | b9f7bc40 | Juha Riihimäki | struct dpll_ctl_s *s = g_malloc0(sizeof(*s)); |
1418 | e7aa0ae0 | Avi Kivity | memory_region_init_io(&s->iomem, &omap_dpll_ops, s, "omap-dpll", 0x100); |
1419 | c3d2689d | balrog | |
1420 | c3d2689d | balrog | s->dpll = clk; |
1421 | c3d2689d | balrog | omap_dpll_reset(s); |
1422 | c3d2689d | balrog | |
1423 | e7aa0ae0 | Avi Kivity | memory_region_add_subregion(memory, base, &s->iomem); |
1424 | b9f7bc40 | Juha Riihimäki | return s;
|
1425 | c3d2689d | balrog | } |
1426 | c3d2689d | balrog | |
1427 | c3d2689d | balrog | /* MPU Clock/Reset/Power Mode Control */
|
1428 | e7aa0ae0 | Avi Kivity | static uint64_t omap_clkm_read(void *opaque, target_phys_addr_t addr, |
1429 | e7aa0ae0 | Avi Kivity | unsigned size)
|
1430 | c3d2689d | balrog | { |
1431 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1432 | c3d2689d | balrog | |
1433 | e7aa0ae0 | Avi Kivity | if (size != 2) { |
1434 | e7aa0ae0 | Avi Kivity | return omap_badwidth_read16(opaque, addr);
|
1435 | e7aa0ae0 | Avi Kivity | } |
1436 | e7aa0ae0 | Avi Kivity | |
1437 | 8da3ff18 | pbrook | switch (addr) {
|
1438 | c3d2689d | balrog | case 0x00: /* ARM_CKCTL */ |
1439 | c3d2689d | balrog | return s->clkm.arm_ckctl;
|
1440 | c3d2689d | balrog | |
1441 | c3d2689d | balrog | case 0x04: /* ARM_IDLECT1 */ |
1442 | c3d2689d | balrog | return s->clkm.arm_idlect1;
|
1443 | c3d2689d | balrog | |
1444 | c3d2689d | balrog | case 0x08: /* ARM_IDLECT2 */ |
1445 | c3d2689d | balrog | return s->clkm.arm_idlect2;
|
1446 | c3d2689d | balrog | |
1447 | c3d2689d | balrog | case 0x0c: /* ARM_EWUPCT */ |
1448 | c3d2689d | balrog | return s->clkm.arm_ewupct;
|
1449 | c3d2689d | balrog | |
1450 | c3d2689d | balrog | case 0x10: /* ARM_RSTCT1 */ |
1451 | c3d2689d | balrog | return s->clkm.arm_rstct1;
|
1452 | c3d2689d | balrog | |
1453 | c3d2689d | balrog | case 0x14: /* ARM_RSTCT2 */ |
1454 | c3d2689d | balrog | return s->clkm.arm_rstct2;
|
1455 | c3d2689d | balrog | |
1456 | c3d2689d | balrog | case 0x18: /* ARM_SYSST */ |
1457 | d8f699cb | balrog | return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; |
1458 | c3d2689d | balrog | |
1459 | c3d2689d | balrog | case 0x1c: /* ARM_CKOUT1 */ |
1460 | c3d2689d | balrog | return s->clkm.arm_ckout1;
|
1461 | c3d2689d | balrog | |
1462 | c3d2689d | balrog | case 0x20: /* ARM_CKOUT2 */ |
1463 | c3d2689d | balrog | break;
|
1464 | c3d2689d | balrog | } |
1465 | c3d2689d | balrog | |
1466 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1467 | c3d2689d | balrog | return 0; |
1468 | c3d2689d | balrog | } |
1469 | c3d2689d | balrog | |
1470 | c3d2689d | balrog | static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, |
1471 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1472 | c3d2689d | balrog | { |
1473 | c3d2689d | balrog | omap_clk clk; |
1474 | c3d2689d | balrog | |
1475 | c3d2689d | balrog | if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ |
1476 | c3d2689d | balrog | if (value & (1 << 14)) |
1477 | c3d2689d | balrog | /* Reserved */;
|
1478 | c3d2689d | balrog | else {
|
1479 | c3d2689d | balrog | clk = omap_findclk(s, "arminth_ck");
|
1480 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
|
1481 | c3d2689d | balrog | } |
1482 | c3d2689d | balrog | } |
1483 | c3d2689d | balrog | if (diff & (1 << 12)) { /* ARM_TIMXO */ |
1484 | c3d2689d | balrog | clk = omap_findclk(s, "armtim_ck");
|
1485 | c3d2689d | balrog | if (value & (1 << 12)) |
1486 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "clkin"));
|
1487 | c3d2689d | balrog | else
|
1488 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
|
1489 | c3d2689d | balrog | } |
1490 | c3d2689d | balrog | /* XXX: en_dspck */
|
1491 | c3d2689d | balrog | if (diff & (3 << 10)) { /* DSPMMUDIV */ |
1492 | c3d2689d | balrog | clk = omap_findclk(s, "dspmmu_ck");
|
1493 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); |
1494 | c3d2689d | balrog | } |
1495 | c3d2689d | balrog | if (diff & (3 << 8)) { /* TCDIV */ |
1496 | c3d2689d | balrog | clk = omap_findclk(s, "tc_ck");
|
1497 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); |
1498 | c3d2689d | balrog | } |
1499 | c3d2689d | balrog | if (diff & (3 << 6)) { /* DSPDIV */ |
1500 | c3d2689d | balrog | clk = omap_findclk(s, "dsp_ck");
|
1501 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); |
1502 | c3d2689d | balrog | } |
1503 | c3d2689d | balrog | if (diff & (3 << 4)) { /* ARMDIV */ |
1504 | c3d2689d | balrog | clk = omap_findclk(s, "arm_ck");
|
1505 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); |
1506 | c3d2689d | balrog | } |
1507 | c3d2689d | balrog | if (diff & (3 << 2)) { /* LCDDIV */ |
1508 | c3d2689d | balrog | clk = omap_findclk(s, "lcd_ck");
|
1509 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); |
1510 | c3d2689d | balrog | } |
1511 | c3d2689d | balrog | if (diff & (3 << 0)) { /* PERDIV */ |
1512 | c3d2689d | balrog | clk = omap_findclk(s, "armper_ck");
|
1513 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); |
1514 | c3d2689d | balrog | } |
1515 | c3d2689d | balrog | } |
1516 | c3d2689d | balrog | |
1517 | c3d2689d | balrog | static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, |
1518 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1519 | c3d2689d | balrog | { |
1520 | c3d2689d | balrog | omap_clk clk; |
1521 | c3d2689d | balrog | |
1522 | 5f4ef08b | Andreas Färber | if (value & (1 << 11)) { /* SETARM_IDLE */ |
1523 | 5f4ef08b | Andreas Färber | cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT); |
1524 | 5f4ef08b | Andreas Färber | } |
1525 | c3d2689d | balrog | if (!(value & (1 << 10))) /* WKUP_MODE */ |
1526 | c3d2689d | balrog | qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
|
1527 | c3d2689d | balrog | |
1528 | c3d2689d | balrog | #define SET_CANIDLE(clock, bit) \
|
1529 | c3d2689d | balrog | if (diff & (1 << bit)) { \ |
1530 | c3d2689d | balrog | clk = omap_findclk(s, clock); \ |
1531 | c3d2689d | balrog | omap_clk_canidle(clk, (value >> bit) & 1); \
|
1532 | c3d2689d | balrog | } |
1533 | c3d2689d | balrog | SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ |
1534 | c3d2689d | balrog | SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ |
1535 | c3d2689d | balrog | SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ |
1536 | c3d2689d | balrog | SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ |
1537 | c3d2689d | balrog | SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ |
1538 | c3d2689d | balrog | SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ |
1539 | c3d2689d | balrog | SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ |
1540 | c3d2689d | balrog | SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ |
1541 | c3d2689d | balrog | SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ |
1542 | c3d2689d | balrog | SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ |
1543 | c3d2689d | balrog | SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ |
1544 | c3d2689d | balrog | SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ |
1545 | c3d2689d | balrog | SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ |
1546 | c3d2689d | balrog | SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ |
1547 | c3d2689d | balrog | } |
1548 | c3d2689d | balrog | |
1549 | c3d2689d | balrog | static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, |
1550 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1551 | c3d2689d | balrog | { |
1552 | c3d2689d | balrog | omap_clk clk; |
1553 | c3d2689d | balrog | |
1554 | c3d2689d | balrog | #define SET_ONOFF(clock, bit) \
|
1555 | c3d2689d | balrog | if (diff & (1 << bit)) { \ |
1556 | c3d2689d | balrog | clk = omap_findclk(s, clock); \ |
1557 | c3d2689d | balrog | omap_clk_onoff(clk, (value >> bit) & 1); \
|
1558 | c3d2689d | balrog | } |
1559 | c3d2689d | balrog | SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ |
1560 | c3d2689d | balrog | SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ |
1561 | c3d2689d | balrog | SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ |
1562 | c3d2689d | balrog | SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ |
1563 | c3d2689d | balrog | SET_ONOFF("lb_ck", 4) /* EN_LBCK */ |
1564 | c3d2689d | balrog | SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ |
1565 | c3d2689d | balrog | SET_ONOFF("mpui_ck", 6) /* EN_APICK */ |
1566 | c3d2689d | balrog | SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ |
1567 | c3d2689d | balrog | SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ |
1568 | c3d2689d | balrog | SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ |
1569 | c3d2689d | balrog | SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ |
1570 | c3d2689d | balrog | } |
1571 | c3d2689d | balrog | |
1572 | c3d2689d | balrog | static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, |
1573 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1574 | c3d2689d | balrog | { |
1575 | c3d2689d | balrog | omap_clk clk; |
1576 | c3d2689d | balrog | |
1577 | c3d2689d | balrog | if (diff & (3 << 4)) { /* TCLKOUT */ |
1578 | c3d2689d | balrog | clk = omap_findclk(s, "tclk_out");
|
1579 | c3d2689d | balrog | switch ((value >> 4) & 3) { |
1580 | c3d2689d | balrog | case 1: |
1581 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
|
1582 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
1583 | c3d2689d | balrog | break;
|
1584 | c3d2689d | balrog | case 2: |
1585 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
|
1586 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
1587 | c3d2689d | balrog | break;
|
1588 | c3d2689d | balrog | default:
|
1589 | c3d2689d | balrog | omap_clk_onoff(clk, 0);
|
1590 | c3d2689d | balrog | } |
1591 | c3d2689d | balrog | } |
1592 | c3d2689d | balrog | if (diff & (3 << 2)) { /* DCLKOUT */ |
1593 | c3d2689d | balrog | clk = omap_findclk(s, "dclk_out");
|
1594 | c3d2689d | balrog | switch ((value >> 2) & 3) { |
1595 | c3d2689d | balrog | case 0: |
1596 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
|
1597 | c3d2689d | balrog | break;
|
1598 | c3d2689d | balrog | case 1: |
1599 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
|
1600 | c3d2689d | balrog | break;
|
1601 | c3d2689d | balrog | case 2: |
1602 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
|
1603 | c3d2689d | balrog | break;
|
1604 | c3d2689d | balrog | case 3: |
1605 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
|
1606 | c3d2689d | balrog | break;
|
1607 | c3d2689d | balrog | } |
1608 | c3d2689d | balrog | } |
1609 | c3d2689d | balrog | if (diff & (3 << 0)) { /* ACLKOUT */ |
1610 | c3d2689d | balrog | clk = omap_findclk(s, "aclk_out");
|
1611 | c3d2689d | balrog | switch ((value >> 0) & 3) { |
1612 | c3d2689d | balrog | case 1: |
1613 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
|
1614 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
1615 | c3d2689d | balrog | break;
|
1616 | c3d2689d | balrog | case 2: |
1617 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
|
1618 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
1619 | c3d2689d | balrog | break;
|
1620 | c3d2689d | balrog | case 3: |
1621 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
|
1622 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
1623 | c3d2689d | balrog | break;
|
1624 | c3d2689d | balrog | default:
|
1625 | c3d2689d | balrog | omap_clk_onoff(clk, 0);
|
1626 | c3d2689d | balrog | } |
1627 | c3d2689d | balrog | } |
1628 | c3d2689d | balrog | } |
1629 | c3d2689d | balrog | |
1630 | c227f099 | Anthony Liguori | static void omap_clkm_write(void *opaque, target_phys_addr_t addr, |
1631 | e7aa0ae0 | Avi Kivity | uint64_t value, unsigned size)
|
1632 | c3d2689d | balrog | { |
1633 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1634 | c3d2689d | balrog | uint16_t diff; |
1635 | c3d2689d | balrog | omap_clk clk; |
1636 | c3d2689d | balrog | static const char *clkschemename[8] = { |
1637 | c3d2689d | balrog | "fully synchronous", "fully asynchronous", "synchronous scalable", |
1638 | c3d2689d | balrog | "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4", |
1639 | c3d2689d | balrog | }; |
1640 | c3d2689d | balrog | |
1641 | e7aa0ae0 | Avi Kivity | if (size != 2) { |
1642 | e7aa0ae0 | Avi Kivity | return omap_badwidth_write16(opaque, addr, value);
|
1643 | e7aa0ae0 | Avi Kivity | } |
1644 | e7aa0ae0 | Avi Kivity | |
1645 | 8da3ff18 | pbrook | switch (addr) {
|
1646 | c3d2689d | balrog | case 0x00: /* ARM_CKCTL */ |
1647 | c3d2689d | balrog | diff = s->clkm.arm_ckctl ^ value; |
1648 | c3d2689d | balrog | s->clkm.arm_ckctl = value & 0x7fff;
|
1649 | c3d2689d | balrog | omap_clkm_ckctl_update(s, diff, value); |
1650 | c3d2689d | balrog | return;
|
1651 | c3d2689d | balrog | |
1652 | c3d2689d | balrog | case 0x04: /* ARM_IDLECT1 */ |
1653 | c3d2689d | balrog | diff = s->clkm.arm_idlect1 ^ value; |
1654 | c3d2689d | balrog | s->clkm.arm_idlect1 = value & 0x0fff;
|
1655 | c3d2689d | balrog | omap_clkm_idlect1_update(s, diff, value); |
1656 | c3d2689d | balrog | return;
|
1657 | c3d2689d | balrog | |
1658 | c3d2689d | balrog | case 0x08: /* ARM_IDLECT2 */ |
1659 | c3d2689d | balrog | diff = s->clkm.arm_idlect2 ^ value; |
1660 | c3d2689d | balrog | s->clkm.arm_idlect2 = value & 0x07ff;
|
1661 | c3d2689d | balrog | omap_clkm_idlect2_update(s, diff, value); |
1662 | c3d2689d | balrog | return;
|
1663 | c3d2689d | balrog | |
1664 | c3d2689d | balrog | case 0x0c: /* ARM_EWUPCT */ |
1665 | c3d2689d | balrog | s->clkm.arm_ewupct = value & 0x003f;
|
1666 | c3d2689d | balrog | return;
|
1667 | c3d2689d | balrog | |
1668 | c3d2689d | balrog | case 0x10: /* ARM_RSTCT1 */ |
1669 | c3d2689d | balrog | diff = s->clkm.arm_rstct1 ^ value; |
1670 | c3d2689d | balrog | s->clkm.arm_rstct1 = value & 0x0007;
|
1671 | c3d2689d | balrog | if (value & 9) { |
1672 | c3d2689d | balrog | qemu_system_reset_request(); |
1673 | c3d2689d | balrog | s->clkm.cold_start = 0xa;
|
1674 | c3d2689d | balrog | } |
1675 | c3d2689d | balrog | if (diff & ~value & 4) { /* DSP_RST */ |
1676 | c3d2689d | balrog | omap_mpui_reset(s); |
1677 | c3d2689d | balrog | omap_tipb_bridge_reset(s->private_tipb); |
1678 | c3d2689d | balrog | omap_tipb_bridge_reset(s->public_tipb); |
1679 | c3d2689d | balrog | } |
1680 | c3d2689d | balrog | if (diff & 2) { /* DSP_EN */ |
1681 | c3d2689d | balrog | clk = omap_findclk(s, "dsp_ck");
|
1682 | c3d2689d | balrog | omap_clk_canidle(clk, (~value >> 1) & 1); |
1683 | c3d2689d | balrog | } |
1684 | c3d2689d | balrog | return;
|
1685 | c3d2689d | balrog | |
1686 | c3d2689d | balrog | case 0x14: /* ARM_RSTCT2 */ |
1687 | c3d2689d | balrog | s->clkm.arm_rstct2 = value & 0x0001;
|
1688 | c3d2689d | balrog | return;
|
1689 | c3d2689d | balrog | |
1690 | c3d2689d | balrog | case 0x18: /* ARM_SYSST */ |
1691 | c3d2689d | balrog | if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { |
1692 | c3d2689d | balrog | s->clkm.clocking_scheme = (value >> 11) & 7; |
1693 | c3d2689d | balrog | printf("%s: clocking scheme set to %s\n", __FUNCTION__,
|
1694 | c3d2689d | balrog | clkschemename[s->clkm.clocking_scheme]); |
1695 | c3d2689d | balrog | } |
1696 | c3d2689d | balrog | s->clkm.cold_start &= value & 0x3f;
|
1697 | c3d2689d | balrog | return;
|
1698 | c3d2689d | balrog | |
1699 | c3d2689d | balrog | case 0x1c: /* ARM_CKOUT1 */ |
1700 | c3d2689d | balrog | diff = s->clkm.arm_ckout1 ^ value; |
1701 | c3d2689d | balrog | s->clkm.arm_ckout1 = value & 0x003f;
|
1702 | c3d2689d | balrog | omap_clkm_ckout1_update(s, diff, value); |
1703 | c3d2689d | balrog | return;
|
1704 | c3d2689d | balrog | |
1705 | c3d2689d | balrog | case 0x20: /* ARM_CKOUT2 */ |
1706 | c3d2689d | balrog | default:
|
1707 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1708 | c3d2689d | balrog | } |
1709 | c3d2689d | balrog | } |
1710 | c3d2689d | balrog | |
1711 | e7aa0ae0 | Avi Kivity | static const MemoryRegionOps omap_clkm_ops = { |
1712 | e7aa0ae0 | Avi Kivity | .read = omap_clkm_read, |
1713 | e7aa0ae0 | Avi Kivity | .write = omap_clkm_write, |
1714 | e7aa0ae0 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
1715 | c3d2689d | balrog | }; |
1716 | c3d2689d | balrog | |
1717 | e7aa0ae0 | Avi Kivity | static uint64_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr, |
1718 | e7aa0ae0 | Avi Kivity | unsigned size)
|
1719 | c3d2689d | balrog | { |
1720 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1721 | c3d2689d | balrog | |
1722 | e7aa0ae0 | Avi Kivity | if (size != 2) { |
1723 | e7aa0ae0 | Avi Kivity | return omap_badwidth_read16(opaque, addr);
|
1724 | e7aa0ae0 | Avi Kivity | } |
1725 | e7aa0ae0 | Avi Kivity | |
1726 | 8da3ff18 | pbrook | switch (addr) {
|
1727 | c3d2689d | balrog | case 0x04: /* DSP_IDLECT1 */ |
1728 | c3d2689d | balrog | return s->clkm.dsp_idlect1;
|
1729 | c3d2689d | balrog | |
1730 | c3d2689d | balrog | case 0x08: /* DSP_IDLECT2 */ |
1731 | c3d2689d | balrog | return s->clkm.dsp_idlect2;
|
1732 | c3d2689d | balrog | |
1733 | c3d2689d | balrog | case 0x14: /* DSP_RSTCT2 */ |
1734 | c3d2689d | balrog | return s->clkm.dsp_rstct2;
|
1735 | c3d2689d | balrog | |
1736 | c3d2689d | balrog | case 0x18: /* DSP_SYSST */ |
1737 | d8f699cb | balrog | return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | |
1738 | 5f4ef08b | Andreas Färber | (s->cpu->env.halted << 6); /* Quite useless... */ |
1739 | c3d2689d | balrog | } |
1740 | c3d2689d | balrog | |
1741 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1742 | c3d2689d | balrog | return 0; |
1743 | c3d2689d | balrog | } |
1744 | c3d2689d | balrog | |
1745 | c3d2689d | balrog | static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, |
1746 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1747 | c3d2689d | balrog | { |
1748 | c3d2689d | balrog | omap_clk clk; |
1749 | c3d2689d | balrog | |
1750 | c3d2689d | balrog | SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ |
1751 | c3d2689d | balrog | } |
1752 | c3d2689d | balrog | |
1753 | c3d2689d | balrog | static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, |
1754 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1755 | c3d2689d | balrog | { |
1756 | c3d2689d | balrog | omap_clk clk; |
1757 | c3d2689d | balrog | |
1758 | c3d2689d | balrog | SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ |
1759 | c3d2689d | balrog | } |
1760 | c3d2689d | balrog | |
1761 | c227f099 | Anthony Liguori | static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr, |
1762 | e7aa0ae0 | Avi Kivity | uint64_t value, unsigned size)
|
1763 | c3d2689d | balrog | { |
1764 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1765 | c3d2689d | balrog | uint16_t diff; |
1766 | c3d2689d | balrog | |
1767 | e7aa0ae0 | Avi Kivity | if (size != 2) { |
1768 | e7aa0ae0 | Avi Kivity | return omap_badwidth_write16(opaque, addr, value);
|
1769 | e7aa0ae0 | Avi Kivity | } |
1770 | e7aa0ae0 | Avi Kivity | |
1771 | 8da3ff18 | pbrook | switch (addr) {
|
1772 | c3d2689d | balrog | case 0x04: /* DSP_IDLECT1 */ |
1773 | c3d2689d | balrog | diff = s->clkm.dsp_idlect1 ^ value; |
1774 | c3d2689d | balrog | s->clkm.dsp_idlect1 = value & 0x01f7;
|
1775 | c3d2689d | balrog | omap_clkdsp_idlect1_update(s, diff, value); |
1776 | c3d2689d | balrog | break;
|
1777 | c3d2689d | balrog | |
1778 | c3d2689d | balrog | case 0x08: /* DSP_IDLECT2 */ |
1779 | c3d2689d | balrog | s->clkm.dsp_idlect2 = value & 0x0037;
|
1780 | c3d2689d | balrog | diff = s->clkm.dsp_idlect1 ^ value; |
1781 | c3d2689d | balrog | omap_clkdsp_idlect2_update(s, diff, value); |
1782 | c3d2689d | balrog | break;
|
1783 | c3d2689d | balrog | |
1784 | c3d2689d | balrog | case 0x14: /* DSP_RSTCT2 */ |
1785 | c3d2689d | balrog | s->clkm.dsp_rstct2 = value & 0x0001;
|
1786 | c3d2689d | balrog | break;
|
1787 | c3d2689d | balrog | |
1788 | c3d2689d | balrog | case 0x18: /* DSP_SYSST */ |
1789 | c3d2689d | balrog | s->clkm.cold_start &= value & 0x3f;
|
1790 | c3d2689d | balrog | break;
|
1791 | c3d2689d | balrog | |
1792 | c3d2689d | balrog | default:
|
1793 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1794 | c3d2689d | balrog | } |
1795 | c3d2689d | balrog | } |
1796 | c3d2689d | balrog | |
1797 | e7aa0ae0 | Avi Kivity | static const MemoryRegionOps omap_clkdsp_ops = { |
1798 | e7aa0ae0 | Avi Kivity | .read = omap_clkdsp_read, |
1799 | e7aa0ae0 | Avi Kivity | .write = omap_clkdsp_write, |
1800 | e7aa0ae0 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
1801 | c3d2689d | balrog | }; |
1802 | c3d2689d | balrog | |
1803 | c3d2689d | balrog | static void omap_clkm_reset(struct omap_mpu_state_s *s) |
1804 | c3d2689d | balrog | { |
1805 | c3d2689d | balrog | if (s->wdt && s->wdt->reset)
|
1806 | c3d2689d | balrog | s->clkm.cold_start = 0x6;
|
1807 | c3d2689d | balrog | s->clkm.clocking_scheme = 0;
|
1808 | c3d2689d | balrog | omap_clkm_ckctl_update(s, ~0, 0x3000); |
1809 | c3d2689d | balrog | s->clkm.arm_ckctl = 0x3000;
|
1810 | d8f699cb | balrog | omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); |
1811 | c3d2689d | balrog | s->clkm.arm_idlect1 = 0x0400;
|
1812 | d8f699cb | balrog | omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); |
1813 | c3d2689d | balrog | s->clkm.arm_idlect2 = 0x0100;
|
1814 | c3d2689d | balrog | s->clkm.arm_ewupct = 0x003f;
|
1815 | c3d2689d | balrog | s->clkm.arm_rstct1 = 0x0000;
|
1816 | c3d2689d | balrog | s->clkm.arm_rstct2 = 0x0000;
|
1817 | c3d2689d | balrog | s->clkm.arm_ckout1 = 0x0015;
|
1818 | c3d2689d | balrog | s->clkm.dpll1_mode = 0x2002;
|
1819 | c3d2689d | balrog | omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); |
1820 | c3d2689d | balrog | s->clkm.dsp_idlect1 = 0x0040;
|
1821 | c3d2689d | balrog | omap_clkdsp_idlect2_update(s, ~0, 0x0000); |
1822 | c3d2689d | balrog | s->clkm.dsp_idlect2 = 0x0000;
|
1823 | c3d2689d | balrog | s->clkm.dsp_rstct2 = 0x0000;
|
1824 | c3d2689d | balrog | } |
1825 | c3d2689d | balrog | |
1826 | e7aa0ae0 | Avi Kivity | static void omap_clkm_init(MemoryRegion *memory, target_phys_addr_t mpu_base, |
1827 | c227f099 | Anthony Liguori | target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
|
1828 | c3d2689d | balrog | { |
1829 | e7aa0ae0 | Avi Kivity | memory_region_init_io(&s->clkm_iomem, &omap_clkm_ops, s, |
1830 | e7aa0ae0 | Avi Kivity | "omap-clkm", 0x100); |
1831 | e7aa0ae0 | Avi Kivity | memory_region_init_io(&s->clkdsp_iomem, &omap_clkdsp_ops, s, |
1832 | e7aa0ae0 | Avi Kivity | "omap-clkdsp", 0x1000); |
1833 | c3d2689d | balrog | |
1834 | d8f699cb | balrog | s->clkm.arm_idlect1 = 0x03ff;
|
1835 | d8f699cb | balrog | s->clkm.arm_idlect2 = 0x0100;
|
1836 | d8f699cb | balrog | s->clkm.dsp_idlect1 = 0x0002;
|
1837 | c3d2689d | balrog | omap_clkm_reset(s); |
1838 | d8f699cb | balrog | s->clkm.cold_start = 0x3a;
|
1839 | c3d2689d | balrog | |
1840 | e7aa0ae0 | Avi Kivity | memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem); |
1841 | e7aa0ae0 | Avi Kivity | memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem); |
1842 | c3d2689d | balrog | } |
1843 | c3d2689d | balrog | |
1844 | fe71e81a | balrog | /* MPU I/O */
|
1845 | fe71e81a | balrog | struct omap_mpuio_s {
|
1846 | fe71e81a | balrog | qemu_irq irq; |
1847 | fe71e81a | balrog | qemu_irq kbd_irq; |
1848 | fe71e81a | balrog | qemu_irq *in; |
1849 | fe71e81a | balrog | qemu_irq handler[16];
|
1850 | fe71e81a | balrog | qemu_irq wakeup; |
1851 | e7aa0ae0 | Avi Kivity | MemoryRegion iomem; |
1852 | fe71e81a | balrog | |
1853 | fe71e81a | balrog | uint16_t inputs; |
1854 | fe71e81a | balrog | uint16_t outputs; |
1855 | fe71e81a | balrog | uint16_t dir; |
1856 | fe71e81a | balrog | uint16_t edge; |
1857 | fe71e81a | balrog | uint16_t mask; |
1858 | fe71e81a | balrog | uint16_t ints; |
1859 | fe71e81a | balrog | |
1860 | fe71e81a | balrog | uint16_t debounce; |
1861 | fe71e81a | balrog | uint16_t latch; |
1862 | fe71e81a | balrog | uint8_t event; |
1863 | fe71e81a | balrog | |
1864 | fe71e81a | balrog | uint8_t buttons[5];
|
1865 | fe71e81a | balrog | uint8_t row_latch; |
1866 | fe71e81a | balrog | uint8_t cols; |
1867 | fe71e81a | balrog | int kbd_mask;
|
1868 | fe71e81a | balrog | int clk;
|
1869 | fe71e81a | balrog | }; |
1870 | fe71e81a | balrog | |
1871 | fe71e81a | balrog | static void omap_mpuio_set(void *opaque, int line, int level) |
1872 | fe71e81a | balrog | { |
1873 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
1874 | fe71e81a | balrog | uint16_t prev = s->inputs; |
1875 | fe71e81a | balrog | |
1876 | fe71e81a | balrog | if (level)
|
1877 | fe71e81a | balrog | s->inputs |= 1 << line;
|
1878 | fe71e81a | balrog | else
|
1879 | fe71e81a | balrog | s->inputs &= ~(1 << line);
|
1880 | fe71e81a | balrog | |
1881 | fe71e81a | balrog | if (((1 << line) & s->dir & ~s->mask) && s->clk) { |
1882 | fe71e81a | balrog | if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
|
1883 | fe71e81a | balrog | s->ints |= 1 << line;
|
1884 | fe71e81a | balrog | qemu_irq_raise(s->irq); |
1885 | fe71e81a | balrog | /* TODO: wakeup */
|
1886 | fe71e81a | balrog | } |
1887 | fe71e81a | balrog | if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ |
1888 | fe71e81a | balrog | (s->event >> 1) == line) /* PIN_SELECT */ |
1889 | fe71e81a | balrog | s->latch = s->inputs; |
1890 | fe71e81a | balrog | } |
1891 | fe71e81a | balrog | } |
1892 | fe71e81a | balrog | |
1893 | fe71e81a | balrog | static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) |
1894 | fe71e81a | balrog | { |
1895 | fe71e81a | balrog | int i;
|
1896 | fe71e81a | balrog | uint8_t *row, rows = 0, cols = ~s->cols;
|
1897 | fe71e81a | balrog | |
1898 | 38a34e1d | balrog | for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) |
1899 | fe71e81a | balrog | if (*row & cols)
|
1900 | 38a34e1d | balrog | rows |= i; |
1901 | fe71e81a | balrog | |
1902 | cf6d9118 | balrog | qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk); |
1903 | cf6d9118 | balrog | s->row_latch = ~rows; |
1904 | fe71e81a | balrog | } |
1905 | fe71e81a | balrog | |
1906 | e7aa0ae0 | Avi Kivity | static uint64_t omap_mpuio_read(void *opaque, target_phys_addr_t addr, |
1907 | e7aa0ae0 | Avi Kivity | unsigned size)
|
1908 | fe71e81a | balrog | { |
1909 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
1910 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
1911 | fe71e81a | balrog | uint16_t ret; |
1912 | fe71e81a | balrog | |
1913 | e7aa0ae0 | Avi Kivity | if (size != 2) { |
1914 | e7aa0ae0 | Avi Kivity | return omap_badwidth_read16(opaque, addr);
|
1915 | e7aa0ae0 | Avi Kivity | } |
1916 | e7aa0ae0 | Avi Kivity | |
1917 | fe71e81a | balrog | switch (offset) {
|
1918 | fe71e81a | balrog | case 0x00: /* INPUT_LATCH */ |
1919 | fe71e81a | balrog | return s->inputs;
|
1920 | fe71e81a | balrog | |
1921 | fe71e81a | balrog | case 0x04: /* OUTPUT_REG */ |
1922 | fe71e81a | balrog | return s->outputs;
|
1923 | fe71e81a | balrog | |
1924 | fe71e81a | balrog | case 0x08: /* IO_CNTL */ |
1925 | fe71e81a | balrog | return s->dir;
|
1926 | fe71e81a | balrog | |
1927 | fe71e81a | balrog | case 0x10: /* KBR_LATCH */ |
1928 | fe71e81a | balrog | return s->row_latch;
|
1929 | fe71e81a | balrog | |
1930 | fe71e81a | balrog | case 0x14: /* KBC_REG */ |
1931 | fe71e81a | balrog | return s->cols;
|
1932 | fe71e81a | balrog | |
1933 | fe71e81a | balrog | case 0x18: /* GPIO_EVENT_MODE_REG */ |
1934 | fe71e81a | balrog | return s->event;
|
1935 | fe71e81a | balrog | |
1936 | fe71e81a | balrog | case 0x1c: /* GPIO_INT_EDGE_REG */ |
1937 | fe71e81a | balrog | return s->edge;
|
1938 | fe71e81a | balrog | |
1939 | fe71e81a | balrog | case 0x20: /* KBD_INT */ |
1940 | cf6d9118 | balrog | return (~s->row_latch & 0x1f) && !s->kbd_mask; |
1941 | fe71e81a | balrog | |
1942 | fe71e81a | balrog | case 0x24: /* GPIO_INT */ |
1943 | fe71e81a | balrog | ret = s->ints; |
1944 | 8e129e07 | balrog | s->ints &= s->mask; |
1945 | 8e129e07 | balrog | if (ret)
|
1946 | 8e129e07 | balrog | qemu_irq_lower(s->irq); |
1947 | fe71e81a | balrog | return ret;
|
1948 | fe71e81a | balrog | |
1949 | fe71e81a | balrog | case 0x28: /* KBD_MASKIT */ |
1950 | fe71e81a | balrog | return s->kbd_mask;
|
1951 | fe71e81a | balrog | |
1952 | fe71e81a | balrog | case 0x2c: /* GPIO_MASKIT */ |
1953 | fe71e81a | balrog | return s->mask;
|
1954 | fe71e81a | balrog | |
1955 | fe71e81a | balrog | case 0x30: /* GPIO_DEBOUNCING_REG */ |
1956 | fe71e81a | balrog | return s->debounce;
|
1957 | fe71e81a | balrog | |
1958 | fe71e81a | balrog | case 0x34: /* GPIO_LATCH_REG */ |
1959 | fe71e81a | balrog | return s->latch;
|
1960 | fe71e81a | balrog | } |
1961 | fe71e81a | balrog | |
1962 | fe71e81a | balrog | OMAP_BAD_REG(addr); |
1963 | fe71e81a | balrog | return 0; |
1964 | fe71e81a | balrog | } |
1965 | fe71e81a | balrog | |
1966 | c227f099 | Anthony Liguori | static void omap_mpuio_write(void *opaque, target_phys_addr_t addr, |
1967 | e7aa0ae0 | Avi Kivity | uint64_t value, unsigned size)
|
1968 | fe71e81a | balrog | { |
1969 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
1970 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
1971 | fe71e81a | balrog | uint16_t diff; |
1972 | fe71e81a | balrog | int ln;
|
1973 | fe71e81a | balrog | |
1974 | e7aa0ae0 | Avi Kivity | if (size != 2) { |
1975 | e7aa0ae0 | Avi Kivity | return omap_badwidth_write16(opaque, addr, value);
|
1976 | e7aa0ae0 | Avi Kivity | } |
1977 | e7aa0ae0 | Avi Kivity | |
1978 | fe71e81a | balrog | switch (offset) {
|
1979 | fe71e81a | balrog | case 0x04: /* OUTPUT_REG */ |
1980 | d8f699cb | balrog | diff = (s->outputs ^ value) & ~s->dir; |
1981 | fe71e81a | balrog | s->outputs = value; |
1982 | fe71e81a | balrog | while ((ln = ffs(diff))) {
|
1983 | fe71e81a | balrog | ln --; |
1984 | fe71e81a | balrog | if (s->handler[ln])
|
1985 | fe71e81a | balrog | qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
1986 | fe71e81a | balrog | diff &= ~(1 << ln);
|
1987 | fe71e81a | balrog | } |
1988 | fe71e81a | balrog | break;
|
1989 | fe71e81a | balrog | |
1990 | fe71e81a | balrog | case 0x08: /* IO_CNTL */ |
1991 | fe71e81a | balrog | diff = s->outputs & (s->dir ^ value); |
1992 | fe71e81a | balrog | s->dir = value; |
1993 | fe71e81a | balrog | |
1994 | fe71e81a | balrog | value = s->outputs & ~s->dir; |
1995 | fe71e81a | balrog | while ((ln = ffs(diff))) {
|
1996 | fe71e81a | balrog | ln --; |
1997 | fe71e81a | balrog | if (s->handler[ln])
|
1998 | fe71e81a | balrog | qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
1999 | fe71e81a | balrog | diff &= ~(1 << ln);
|
2000 | fe71e81a | balrog | } |
2001 | fe71e81a | balrog | break;
|
2002 | fe71e81a | balrog | |
2003 | fe71e81a | balrog | case 0x14: /* KBC_REG */ |
2004 | fe71e81a | balrog | s->cols = value; |
2005 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
2006 | fe71e81a | balrog | break;
|
2007 | fe71e81a | balrog | |
2008 | fe71e81a | balrog | case 0x18: /* GPIO_EVENT_MODE_REG */ |
2009 | fe71e81a | balrog | s->event = value & 0x1f;
|
2010 | fe71e81a | balrog | break;
|
2011 | fe71e81a | balrog | |
2012 | fe71e81a | balrog | case 0x1c: /* GPIO_INT_EDGE_REG */ |
2013 | fe71e81a | balrog | s->edge = value; |
2014 | fe71e81a | balrog | break;
|
2015 | fe71e81a | balrog | |
2016 | fe71e81a | balrog | case 0x28: /* KBD_MASKIT */ |
2017 | fe71e81a | balrog | s->kbd_mask = value & 1;
|
2018 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
2019 | fe71e81a | balrog | break;
|
2020 | fe71e81a | balrog | |
2021 | fe71e81a | balrog | case 0x2c: /* GPIO_MASKIT */ |
2022 | fe71e81a | balrog | s->mask = value; |
2023 | fe71e81a | balrog | break;
|
2024 | fe71e81a | balrog | |
2025 | fe71e81a | balrog | case 0x30: /* GPIO_DEBOUNCING_REG */ |
2026 | fe71e81a | balrog | s->debounce = value & 0x1ff;
|
2027 | fe71e81a | balrog | break;
|
2028 | fe71e81a | balrog | |
2029 | fe71e81a | balrog | case 0x00: /* INPUT_LATCH */ |
2030 | fe71e81a | balrog | case 0x10: /* KBR_LATCH */ |
2031 | fe71e81a | balrog | case 0x20: /* KBD_INT */ |
2032 | fe71e81a | balrog | case 0x24: /* GPIO_INT */ |
2033 | fe71e81a | balrog | case 0x34: /* GPIO_LATCH_REG */ |
2034 | fe71e81a | balrog | OMAP_RO_REG(addr); |
2035 | fe71e81a | balrog | return;
|
2036 | fe71e81a | balrog | |
2037 | fe71e81a | balrog | default:
|
2038 | fe71e81a | balrog | OMAP_BAD_REG(addr); |
2039 | fe71e81a | balrog | return;
|
2040 | fe71e81a | balrog | } |
2041 | fe71e81a | balrog | } |
2042 | fe71e81a | balrog | |
2043 | e7aa0ae0 | Avi Kivity | static const MemoryRegionOps omap_mpuio_ops = { |
2044 | e7aa0ae0 | Avi Kivity | .read = omap_mpuio_read, |
2045 | e7aa0ae0 | Avi Kivity | .write = omap_mpuio_write, |
2046 | e7aa0ae0 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
2047 | fe71e81a | balrog | }; |
2048 | fe71e81a | balrog | |
2049 | 9596ebb7 | pbrook | static void omap_mpuio_reset(struct omap_mpuio_s *s) |
2050 | fe71e81a | balrog | { |
2051 | fe71e81a | balrog | s->inputs = 0;
|
2052 | fe71e81a | balrog | s->outputs = 0;
|
2053 | fe71e81a | balrog | s->dir = ~0;
|
2054 | fe71e81a | balrog | s->event = 0;
|
2055 | fe71e81a | balrog | s->edge = 0;
|
2056 | fe71e81a | balrog | s->kbd_mask = 0;
|
2057 | fe71e81a | balrog | s->mask = 0;
|
2058 | fe71e81a | balrog | s->debounce = 0;
|
2059 | fe71e81a | balrog | s->latch = 0;
|
2060 | fe71e81a | balrog | s->ints = 0;
|
2061 | fe71e81a | balrog | s->row_latch = 0x1f;
|
2062 | 38a34e1d | balrog | s->clk = 1;
|
2063 | fe71e81a | balrog | } |
2064 | fe71e81a | balrog | |
2065 | fe71e81a | balrog | static void omap_mpuio_onoff(void *opaque, int line, int on) |
2066 | fe71e81a | balrog | { |
2067 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
2068 | fe71e81a | balrog | |
2069 | fe71e81a | balrog | s->clk = on; |
2070 | fe71e81a | balrog | if (on)
|
2071 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
2072 | fe71e81a | balrog | } |
2073 | fe71e81a | balrog | |
2074 | 3b204c81 | Peter Maydell | static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory, |
2075 | e7aa0ae0 | Avi Kivity | target_phys_addr_t base, |
2076 | fe71e81a | balrog | qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, |
2077 | fe71e81a | balrog | omap_clk clk) |
2078 | fe71e81a | balrog | { |
2079 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) |
2080 | 7267c094 | Anthony Liguori | g_malloc0(sizeof(struct omap_mpuio_s)); |
2081 | fe71e81a | balrog | |
2082 | fe71e81a | balrog | s->irq = gpio_int; |
2083 | fe71e81a | balrog | s->kbd_irq = kbd_int; |
2084 | fe71e81a | balrog | s->wakeup = wakeup; |
2085 | fe71e81a | balrog | s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
|
2086 | fe71e81a | balrog | omap_mpuio_reset(s); |
2087 | fe71e81a | balrog | |
2088 | e7aa0ae0 | Avi Kivity | memory_region_init_io(&s->iomem, &omap_mpuio_ops, s, |
2089 | e7aa0ae0 | Avi Kivity | "omap-mpuio", 0x800); |
2090 | e7aa0ae0 | Avi Kivity | memory_region_add_subregion(memory, base, &s->iomem); |
2091 | fe71e81a | balrog | |
2092 | fe71e81a | balrog | omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]); |
2093 | fe71e81a | balrog | |
2094 | fe71e81a | balrog | return s;
|
2095 | fe71e81a | balrog | } |
2096 | fe71e81a | balrog | |
2097 | fe71e81a | balrog | qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
|
2098 | fe71e81a | balrog | { |
2099 | fe71e81a | balrog | return s->in;
|
2100 | fe71e81a | balrog | } |
2101 | fe71e81a | balrog | |
2102 | fe71e81a | balrog | void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) |
2103 | fe71e81a | balrog | { |
2104 | fe71e81a | balrog | if (line >= 16 || line < 0) |
2105 | 2ac71179 | Paul Brook | hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
|
2106 | fe71e81a | balrog | s->handler[line] = handler; |
2107 | fe71e81a | balrog | } |
2108 | fe71e81a | balrog | |
2109 | fe71e81a | balrog | void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) |
2110 | fe71e81a | balrog | { |
2111 | fe71e81a | balrog | if (row >= 5 || row < 0) |
2112 | 2ac71179 | Paul Brook | hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row);
|
2113 | fe71e81a | balrog | |
2114 | fe71e81a | balrog | if (down)
|
2115 | 38a34e1d | balrog | s->buttons[row] |= 1 << col;
|
2116 | fe71e81a | balrog | else
|
2117 | 38a34e1d | balrog | s->buttons[row] &= ~(1 << col);
|
2118 | fe71e81a | balrog | |
2119 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
2120 | fe71e81a | balrog | } |
2121 | fe71e81a | balrog | |
2122 | d951f6ff | balrog | /* MicroWire Interface */
|
2123 | d951f6ff | balrog | struct omap_uwire_s {
|
2124 | a4ebbd18 | Avi Kivity | MemoryRegion iomem; |
2125 | d951f6ff | balrog | qemu_irq txirq; |
2126 | d951f6ff | balrog | qemu_irq rxirq; |
2127 | d951f6ff | balrog | qemu_irq txdrq; |
2128 | d951f6ff | balrog | |
2129 | d951f6ff | balrog | uint16_t txbuf; |
2130 | d951f6ff | balrog | uint16_t rxbuf; |
2131 | d951f6ff | balrog | uint16_t control; |
2132 | d951f6ff | balrog | uint16_t setup[5];
|
2133 | d951f6ff | balrog | |
2134 | bc24a225 | Paul Brook | uWireSlave *chip[4];
|
2135 | d951f6ff | balrog | }; |
2136 | d951f6ff | balrog | |
2137 | d951f6ff | balrog | static void omap_uwire_transfer_start(struct omap_uwire_s *s) |
2138 | d951f6ff | balrog | { |
2139 | d951f6ff | balrog | int chipselect = (s->control >> 10) & 3; /* INDEX */ |
2140 | bc24a225 | Paul Brook | uWireSlave *slave = s->chip[chipselect]; |
2141 | d951f6ff | balrog | |
2142 | d951f6ff | balrog | if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ |
2143 | d951f6ff | balrog | if (s->control & (1 << 12)) /* CS_CMD */ |
2144 | d951f6ff | balrog | if (slave && slave->send)
|
2145 | d951f6ff | balrog | slave->send(slave->opaque, |
2146 | d951f6ff | balrog | s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); |
2147 | d951f6ff | balrog | s->control &= ~(1 << 14); /* CSRB */ |
2148 | d951f6ff | balrog | /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
|
2149 | d951f6ff | balrog | * a DRQ. When is the level IRQ supposed to be reset? */
|
2150 | d951f6ff | balrog | } |
2151 | d951f6ff | balrog | |
2152 | d951f6ff | balrog | if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ |
2153 | d951f6ff | balrog | if (s->control & (1 << 12)) /* CS_CMD */ |
2154 | d951f6ff | balrog | if (slave && slave->receive)
|
2155 | d951f6ff | balrog | s->rxbuf = slave->receive(slave->opaque); |
2156 | d951f6ff | balrog | s->control |= 1 << 15; /* RDRB */ |
2157 | d951f6ff | balrog | /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
|
2158 | d951f6ff | balrog | * a DRQ. When is the level IRQ supposed to be reset? */
|
2159 | d951f6ff | balrog | } |
2160 | d951f6ff | balrog | } |
2161 | d951f6ff | balrog | |
2162 | a4ebbd18 | Avi Kivity | static uint64_t omap_uwire_read(void *opaque, target_phys_addr_t addr, |
2163 | a4ebbd18 | Avi Kivity | unsigned size)
|
2164 | d951f6ff | balrog | { |
2165 | d951f6ff | balrog | struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; |
2166 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2167 | d951f6ff | balrog | |
2168 | a4ebbd18 | Avi Kivity | if (size != 2) { |
2169 | a4ebbd18 | Avi Kivity | return omap_badwidth_read16(opaque, addr);
|
2170 | a4ebbd18 | Avi Kivity | } |
2171 | a4ebbd18 | Avi Kivity | |
2172 | d951f6ff | balrog | switch (offset) {
|
2173 | d951f6ff | balrog | case 0x00: /* RDR */ |
2174 | d951f6ff | balrog | s->control &= ~(1 << 15); /* RDRB */ |
2175 | d951f6ff | balrog | return s->rxbuf;
|
2176 | d951f6ff | balrog | |
2177 | d951f6ff | balrog | case 0x04: /* CSR */ |
2178 | d951f6ff | balrog | return s->control;
|
2179 | d951f6ff | balrog | |
2180 | d951f6ff | balrog | case 0x08: /* SR1 */ |
2181 | d951f6ff | balrog | return s->setup[0]; |
2182 | d951f6ff | balrog | case 0x0c: /* SR2 */ |
2183 | d951f6ff | balrog | return s->setup[1]; |
2184 | d951f6ff | balrog | case 0x10: /* SR3 */ |
2185 | d951f6ff | balrog | return s->setup[2]; |
2186 | d951f6ff | balrog | case 0x14: /* SR4 */ |
2187 | d951f6ff | balrog | return s->setup[3]; |
2188 | d951f6ff | balrog | case 0x18: /* SR5 */ |
2189 | d951f6ff | balrog | return s->setup[4]; |
2190 | d951f6ff | balrog | } |
2191 | d951f6ff | balrog | |
2192 | d951f6ff | balrog | OMAP_BAD_REG(addr); |
2193 | d951f6ff | balrog | return 0; |
2194 | d951f6ff | balrog | } |
2195 | d951f6ff | balrog | |
2196 | c227f099 | Anthony Liguori | static void omap_uwire_write(void *opaque, target_phys_addr_t addr, |
2197 | a4ebbd18 | Avi Kivity | uint64_t value, unsigned size)
|
2198 | d951f6ff | balrog | { |
2199 | d951f6ff | balrog | struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; |
2200 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2201 | d951f6ff | balrog | |
2202 | a4ebbd18 | Avi Kivity | if (size != 2) { |
2203 | a4ebbd18 | Avi Kivity | return omap_badwidth_write16(opaque, addr, value);
|
2204 | a4ebbd18 | Avi Kivity | } |
2205 | a4ebbd18 | Avi Kivity | |
2206 | d951f6ff | balrog | switch (offset) {
|
2207 | d951f6ff | balrog | case 0x00: /* TDR */ |
2208 | d951f6ff | balrog | s->txbuf = value; /* TD */
|
2209 | d951f6ff | balrog | if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ |
2210 | d951f6ff | balrog | ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ |
2211 | cf965d24 | balrog | (s->control & (1 << 12)))) { /* CS_CMD */ |
2212 | cf965d24 | balrog | s->control |= 1 << 14; /* CSRB */ |
2213 | d951f6ff | balrog | omap_uwire_transfer_start(s); |
2214 | cf965d24 | balrog | } |
2215 | d951f6ff | balrog | break;
|
2216 | d951f6ff | balrog | |
2217 | d951f6ff | balrog | case 0x04: /* CSR */ |
2218 | d951f6ff | balrog | s->control = value & 0x1fff;
|
2219 | d951f6ff | balrog | if (value & (1 << 13)) /* START */ |
2220 | d951f6ff | balrog | omap_uwire_transfer_start(s); |
2221 | d951f6ff | balrog | break;
|
2222 | d951f6ff | balrog | |
2223 | d951f6ff | balrog | case 0x08: /* SR1 */ |
2224 | d951f6ff | balrog | s->setup[0] = value & 0x003f; |
2225 | d951f6ff | balrog | break;
|
2226 | d951f6ff | balrog | |
2227 | d951f6ff | balrog | case 0x0c: /* SR2 */ |
2228 | d951f6ff | balrog | s->setup[1] = value & 0x0fc0; |
2229 | d951f6ff | balrog | break;
|
2230 | d951f6ff | balrog | |
2231 | d951f6ff | balrog | case 0x10: /* SR3 */ |
2232 | d951f6ff | balrog | s->setup[2] = value & 0x0003; |
2233 | d951f6ff | balrog | break;
|
2234 | d951f6ff | balrog | |
2235 | d951f6ff | balrog | case 0x14: /* SR4 */ |
2236 | d951f6ff | balrog | s->setup[3] = value & 0x0001; |
2237 | d951f6ff | balrog | break;
|
2238 | d951f6ff | balrog | |
2239 | d951f6ff | balrog | case 0x18: /* SR5 */ |
2240 | d951f6ff | balrog | s->setup[4] = value & 0x000f; |
2241 | d951f6ff | balrog | break;
|
2242 | d951f6ff | balrog | |
2243 | d951f6ff | balrog | default:
|
2244 | d951f6ff | balrog | OMAP_BAD_REG(addr); |
2245 | d951f6ff | balrog | return;
|
2246 | d951f6ff | balrog | } |
2247 | d951f6ff | balrog | } |
2248 | d951f6ff | balrog | |
2249 | a4ebbd18 | Avi Kivity | static const MemoryRegionOps omap_uwire_ops = { |
2250 | a4ebbd18 | Avi Kivity | .read = omap_uwire_read, |
2251 | a4ebbd18 | Avi Kivity | .write = omap_uwire_write, |
2252 | a4ebbd18 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
2253 | d951f6ff | balrog | }; |
2254 | d951f6ff | balrog | |
2255 | 9596ebb7 | pbrook | static void omap_uwire_reset(struct omap_uwire_s *s) |
2256 | d951f6ff | balrog | { |
2257 | 66450b15 | balrog | s->control = 0;
|
2258 | d951f6ff | balrog | s->setup[0] = 0; |
2259 | d951f6ff | balrog | s->setup[1] = 0; |
2260 | d951f6ff | balrog | s->setup[2] = 0; |
2261 | d951f6ff | balrog | s->setup[3] = 0; |
2262 | d951f6ff | balrog | s->setup[4] = 0; |
2263 | d951f6ff | balrog | } |
2264 | d951f6ff | balrog | |
2265 | 0919ac78 | Peter Maydell | static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory, |
2266 | 0919ac78 | Peter Maydell | target_phys_addr_t base, |
2267 | 0919ac78 | Peter Maydell | qemu_irq txirq, qemu_irq rxirq, |
2268 | 0919ac78 | Peter Maydell | qemu_irq dma, |
2269 | 0919ac78 | Peter Maydell | omap_clk clk) |
2270 | d951f6ff | balrog | { |
2271 | d951f6ff | balrog | struct omap_uwire_s *s = (struct omap_uwire_s *) |
2272 | 7267c094 | Anthony Liguori | g_malloc0(sizeof(struct omap_uwire_s)); |
2273 | d951f6ff | balrog | |
2274 | 0919ac78 | Peter Maydell | s->txirq = txirq; |
2275 | 0919ac78 | Peter Maydell | s->rxirq = rxirq; |
2276 | d951f6ff | balrog | s->txdrq = dma; |
2277 | d951f6ff | balrog | omap_uwire_reset(s); |
2278 | d951f6ff | balrog | |
2279 | a4ebbd18 | Avi Kivity | memory_region_init_io(&s->iomem, &omap_uwire_ops, s, "omap-uwire", 0x800); |
2280 | a4ebbd18 | Avi Kivity | memory_region_add_subregion(system_memory, base, &s->iomem); |
2281 | d951f6ff | balrog | |
2282 | d951f6ff | balrog | return s;
|
2283 | d951f6ff | balrog | } |
2284 | d951f6ff | balrog | |
2285 | d951f6ff | balrog | void omap_uwire_attach(struct omap_uwire_s *s, |
2286 | bc24a225 | Paul Brook | uWireSlave *slave, int chipselect)
|
2287 | d951f6ff | balrog | { |
2288 | 827df9f3 | balrog | if (chipselect < 0 || chipselect > 3) { |
2289 | 827df9f3 | balrog | fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
|
2290 | 827df9f3 | balrog | exit(-1);
|
2291 | 827df9f3 | balrog | } |
2292 | d951f6ff | balrog | |
2293 | d951f6ff | balrog | s->chip[chipselect] = slave; |
2294 | d951f6ff | balrog | } |
2295 | d951f6ff | balrog | |
2296 | 66450b15 | balrog | /* Pseudonoise Pulse-Width Light Modulator */
|
2297 | 8717d88a | Juha Riihimäki | struct omap_pwl_s {
|
2298 | 8717d88a | Juha Riihimäki | MemoryRegion iomem; |
2299 | 8717d88a | Juha Riihimäki | uint8_t output; |
2300 | 8717d88a | Juha Riihimäki | uint8_t level; |
2301 | 8717d88a | Juha Riihimäki | uint8_t enable; |
2302 | 8717d88a | Juha Riihimäki | int clk;
|
2303 | 8717d88a | Juha Riihimäki | }; |
2304 | 8717d88a | Juha Riihimäki | |
2305 | 8717d88a | Juha Riihimäki | static void omap_pwl_update(struct omap_pwl_s *s) |
2306 | 66450b15 | balrog | { |
2307 | 8717d88a | Juha Riihimäki | int output = (s->clk && s->enable) ? s->level : 0; |
2308 | 66450b15 | balrog | |
2309 | 8717d88a | Juha Riihimäki | if (output != s->output) {
|
2310 | 8717d88a | Juha Riihimäki | s->output = output; |
2311 | 66450b15 | balrog | printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
|
2312 | 66450b15 | balrog | } |
2313 | 66450b15 | balrog | } |
2314 | 66450b15 | balrog | |
2315 | a4ebbd18 | Avi Kivity | static uint64_t omap_pwl_read(void *opaque, target_phys_addr_t addr, |
2316 | a4ebbd18 | Avi Kivity | unsigned size)
|
2317 | 66450b15 | balrog | { |
2318 | 8717d88a | Juha Riihimäki | struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; |
2319 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2320 | 66450b15 | balrog | |
2321 | a4ebbd18 | Avi Kivity | if (size != 1) { |
2322 | a4ebbd18 | Avi Kivity | return omap_badwidth_read8(opaque, addr);
|
2323 | a4ebbd18 | Avi Kivity | } |
2324 | a4ebbd18 | Avi Kivity | |
2325 | 66450b15 | balrog | switch (offset) {
|
2326 | 66450b15 | balrog | case 0x00: /* PWL_LEVEL */ |
2327 | 8717d88a | Juha Riihimäki | return s->level;
|
2328 | 66450b15 | balrog | case 0x04: /* PWL_CTRL */ |
2329 | 8717d88a | Juha Riihimäki | return s->enable;
|
2330 | 66450b15 | balrog | } |
2331 | 66450b15 | balrog | OMAP_BAD_REG(addr); |
2332 | 66450b15 | balrog | return 0; |
2333 | 66450b15 | balrog | } |
2334 | 66450b15 | balrog | |
2335 | c227f099 | Anthony Liguori | static void omap_pwl_write(void *opaque, target_phys_addr_t addr, |
2336 | a4ebbd18 | Avi Kivity | uint64_t value, unsigned size)
|
2337 | 66450b15 | balrog | { |
2338 | 8717d88a | Juha Riihimäki | struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; |
2339 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2340 | 66450b15 | balrog | |
2341 | a4ebbd18 | Avi Kivity | if (size != 1) { |
2342 | a4ebbd18 | Avi Kivity | return omap_badwidth_write8(opaque, addr, value);
|
2343 | a4ebbd18 | Avi Kivity | } |
2344 | a4ebbd18 | Avi Kivity | |
2345 | 66450b15 | balrog | switch (offset) {
|
2346 | 66450b15 | balrog | case 0x00: /* PWL_LEVEL */ |
2347 | 8717d88a | Juha Riihimäki | s->level = value; |
2348 | 66450b15 | balrog | omap_pwl_update(s); |
2349 | 66450b15 | balrog | break;
|
2350 | 66450b15 | balrog | case 0x04: /* PWL_CTRL */ |
2351 | 8717d88a | Juha Riihimäki | s->enable = value & 1;
|
2352 | 66450b15 | balrog | omap_pwl_update(s); |
2353 | 66450b15 | balrog | break;
|
2354 | 66450b15 | balrog | default:
|
2355 | 66450b15 | balrog | OMAP_BAD_REG(addr); |
2356 | 66450b15 | balrog | return;
|
2357 | 66450b15 | balrog | } |
2358 | 66450b15 | balrog | } |
2359 | 66450b15 | balrog | |
2360 | a4ebbd18 | Avi Kivity | static const MemoryRegionOps omap_pwl_ops = { |
2361 | a4ebbd18 | Avi Kivity | .read = omap_pwl_read, |
2362 | a4ebbd18 | Avi Kivity | .write = omap_pwl_write, |
2363 | a4ebbd18 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
2364 | 66450b15 | balrog | }; |
2365 | 66450b15 | balrog | |
2366 | 8717d88a | Juha Riihimäki | static void omap_pwl_reset(struct omap_pwl_s *s) |
2367 | 66450b15 | balrog | { |
2368 | 8717d88a | Juha Riihimäki | s->output = 0;
|
2369 | 8717d88a | Juha Riihimäki | s->level = 0;
|
2370 | 8717d88a | Juha Riihimäki | s->enable = 0;
|
2371 | 8717d88a | Juha Riihimäki | s->clk = 1;
|
2372 | 66450b15 | balrog | omap_pwl_update(s); |
2373 | 66450b15 | balrog | } |
2374 | 66450b15 | balrog | |
2375 | 66450b15 | balrog | static void omap_pwl_clk_update(void *opaque, int line, int on) |
2376 | 66450b15 | balrog | { |
2377 | 8717d88a | Juha Riihimäki | struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; |
2378 | 66450b15 | balrog | |
2379 | 8717d88a | Juha Riihimäki | s->clk = on; |
2380 | 66450b15 | balrog | omap_pwl_update(s); |
2381 | 66450b15 | balrog | } |
2382 | 66450b15 | balrog | |
2383 | 8717d88a | Juha Riihimäki | static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory, |
2384 | 8717d88a | Juha Riihimäki | target_phys_addr_t base, |
2385 | 8717d88a | Juha Riihimäki | omap_clk clk) |
2386 | 66450b15 | balrog | { |
2387 | 8717d88a | Juha Riihimäki | struct omap_pwl_s *s = g_malloc0(sizeof(*s)); |
2388 | 8717d88a | Juha Riihimäki | |
2389 | 66450b15 | balrog | omap_pwl_reset(s); |
2390 | 66450b15 | balrog | |
2391 | 8717d88a | Juha Riihimäki | memory_region_init_io(&s->iomem, &omap_pwl_ops, s, |
2392 | a4ebbd18 | Avi Kivity | "omap-pwl", 0x800); |
2393 | 8717d88a | Juha Riihimäki | memory_region_add_subregion(system_memory, base, &s->iomem); |
2394 | 66450b15 | balrog | |
2395 | 66450b15 | balrog | omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]); |
2396 | 8717d88a | Juha Riihimäki | return s;
|
2397 | 66450b15 | balrog | } |
2398 | 66450b15 | balrog | |
2399 | f34c417b | balrog | /* Pulse-Width Tone module */
|
2400 | 03759534 | Juha Riihimäki | struct omap_pwt_s {
|
2401 | 03759534 | Juha Riihimäki | MemoryRegion iomem; |
2402 | 03759534 | Juha Riihimäki | uint8_t frc; |
2403 | 03759534 | Juha Riihimäki | uint8_t vrc; |
2404 | 03759534 | Juha Riihimäki | uint8_t gcr; |
2405 | 03759534 | Juha Riihimäki | omap_clk clk; |
2406 | 03759534 | Juha Riihimäki | }; |
2407 | 03759534 | Juha Riihimäki | |
2408 | a4ebbd18 | Avi Kivity | static uint64_t omap_pwt_read(void *opaque, target_phys_addr_t addr, |
2409 | a4ebbd18 | Avi Kivity | unsigned size)
|
2410 | f34c417b | balrog | { |
2411 | 03759534 | Juha Riihimäki | struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; |
2412 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2413 | f34c417b | balrog | |
2414 | a4ebbd18 | Avi Kivity | if (size != 1) { |
2415 | a4ebbd18 | Avi Kivity | return omap_badwidth_read8(opaque, addr);
|
2416 | a4ebbd18 | Avi Kivity | } |
2417 | a4ebbd18 | Avi Kivity | |
2418 | f34c417b | balrog | switch (offset) {
|
2419 | f34c417b | balrog | case 0x00: /* FRC */ |
2420 | 03759534 | Juha Riihimäki | return s->frc;
|
2421 | f34c417b | balrog | case 0x04: /* VCR */ |
2422 | 03759534 | Juha Riihimäki | return s->vrc;
|
2423 | f34c417b | balrog | case 0x08: /* GCR */ |
2424 | 03759534 | Juha Riihimäki | return s->gcr;
|
2425 | f34c417b | balrog | } |
2426 | f34c417b | balrog | OMAP_BAD_REG(addr); |
2427 | f34c417b | balrog | return 0; |
2428 | f34c417b | balrog | } |
2429 | f34c417b | balrog | |
2430 | c227f099 | Anthony Liguori | static void omap_pwt_write(void *opaque, target_phys_addr_t addr, |
2431 | a4ebbd18 | Avi Kivity | uint64_t value, unsigned size)
|
2432 | f34c417b | balrog | { |
2433 | 03759534 | Juha Riihimäki | struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; |
2434 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2435 | f34c417b | balrog | |
2436 | a4ebbd18 | Avi Kivity | if (size != 1) { |
2437 | a4ebbd18 | Avi Kivity | return omap_badwidth_write8(opaque, addr, value);
|
2438 | a4ebbd18 | Avi Kivity | } |
2439 | a4ebbd18 | Avi Kivity | |
2440 | f34c417b | balrog | switch (offset) {
|
2441 | f34c417b | balrog | case 0x00: /* FRC */ |
2442 | 03759534 | Juha Riihimäki | s->frc = value & 0x3f;
|
2443 | f34c417b | balrog | break;
|
2444 | f34c417b | balrog | case 0x04: /* VRC */ |
2445 | 03759534 | Juha Riihimäki | if ((value ^ s->vrc) & 1) { |
2446 | f34c417b | balrog | if (value & 1) |
2447 | f34c417b | balrog | printf("%s: %iHz buzz on\n", __FUNCTION__, (int) |
2448 | f34c417b | balrog | /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
|
2449 | 03759534 | Juha Riihimäki | ((omap_clk_getrate(s->clk) >> 3) /
|
2450 | f34c417b | balrog | /* Pre-multiplexer divider */
|
2451 | 03759534 | Juha Riihimäki | ((s->gcr & 2) ? 1 : 154) / |
2452 | f34c417b | balrog | /* Octave multiplexer */
|
2453 | f34c417b | balrog | (2 << (value & 3)) * |
2454 | f34c417b | balrog | /* 101/107 divider */
|
2455 | f34c417b | balrog | ((value & (1 << 2)) ? 101 : 107) * |
2456 | f34c417b | balrog | /* 49/55 divider */
|
2457 | f34c417b | balrog | ((value & (1 << 3)) ? 49 : 55) * |
2458 | f34c417b | balrog | /* 50/63 divider */
|
2459 | f34c417b | balrog | ((value & (1 << 4)) ? 50 : 63) * |
2460 | f34c417b | balrog | /* 80/127 divider */
|
2461 | f34c417b | balrog | ((value & (1 << 5)) ? 80 : 127) / |
2462 | f34c417b | balrog | (107 * 55 * 63 * 127))); |
2463 | f34c417b | balrog | else
|
2464 | f34c417b | balrog | printf("%s: silence!\n", __FUNCTION__);
|
2465 | f34c417b | balrog | } |
2466 | 03759534 | Juha Riihimäki | s->vrc = value & 0x7f;
|
2467 | f34c417b | balrog | break;
|
2468 | f34c417b | balrog | case 0x08: /* GCR */ |
2469 | 03759534 | Juha Riihimäki | s->gcr = value & 3;
|
2470 | f34c417b | balrog | break;
|
2471 | f34c417b | balrog | default:
|
2472 | f34c417b | balrog | OMAP_BAD_REG(addr); |
2473 | f34c417b | balrog | return;
|
2474 | f34c417b | balrog | } |
2475 | f34c417b | balrog | } |
2476 | f34c417b | balrog | |
2477 | a4ebbd18 | Avi Kivity | static const MemoryRegionOps omap_pwt_ops = { |
2478 | a4ebbd18 | Avi Kivity | .read =omap_pwt_read, |
2479 | a4ebbd18 | Avi Kivity | .write = omap_pwt_write, |
2480 | a4ebbd18 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
2481 | f34c417b | balrog | }; |
2482 | f34c417b | balrog | |
2483 | 03759534 | Juha Riihimäki | static void omap_pwt_reset(struct omap_pwt_s *s) |
2484 | f34c417b | balrog | { |
2485 | 03759534 | Juha Riihimäki | s->frc = 0;
|
2486 | 03759534 | Juha Riihimäki | s->vrc = 0;
|
2487 | 03759534 | Juha Riihimäki | s->gcr = 0;
|
2488 | f34c417b | balrog | } |
2489 | f34c417b | balrog | |
2490 | 03759534 | Juha Riihimäki | static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory, |
2491 | 03759534 | Juha Riihimäki | target_phys_addr_t base, |
2492 | 03759534 | Juha Riihimäki | omap_clk clk) |
2493 | f34c417b | balrog | { |
2494 | 03759534 | Juha Riihimäki | struct omap_pwt_s *s = g_malloc0(sizeof(*s)); |
2495 | 03759534 | Juha Riihimäki | s->clk = clk; |
2496 | f34c417b | balrog | omap_pwt_reset(s); |
2497 | f34c417b | balrog | |
2498 | 03759534 | Juha Riihimäki | memory_region_init_io(&s->iomem, &omap_pwt_ops, s, |
2499 | a4ebbd18 | Avi Kivity | "omap-pwt", 0x800); |
2500 | 03759534 | Juha Riihimäki | memory_region_add_subregion(system_memory, base, &s->iomem); |
2501 | 03759534 | Juha Riihimäki | return s;
|
2502 | f34c417b | balrog | } |
2503 | f34c417b | balrog | |
2504 | 5c1c390f | balrog | /* Real-time Clock module */
|
2505 | 5c1c390f | balrog | struct omap_rtc_s {
|
2506 | a4ebbd18 | Avi Kivity | MemoryRegion iomem; |
2507 | 5c1c390f | balrog | qemu_irq irq; |
2508 | 5c1c390f | balrog | qemu_irq alarm; |
2509 | 5c1c390f | balrog | QEMUTimer *clk; |
2510 | 5c1c390f | balrog | |
2511 | 5c1c390f | balrog | uint8_t interrupts; |
2512 | 5c1c390f | balrog | uint8_t status; |
2513 | 5c1c390f | balrog | int16_t comp_reg; |
2514 | 5c1c390f | balrog | int running;
|
2515 | 5c1c390f | balrog | int pm_am;
|
2516 | 5c1c390f | balrog | int auto_comp;
|
2517 | 5c1c390f | balrog | int round;
|
2518 | 5c1c390f | balrog | struct tm alarm_tm;
|
2519 | 5c1c390f | balrog | time_t alarm_ti; |
2520 | 5c1c390f | balrog | |
2521 | 5c1c390f | balrog | struct tm current_tm;
|
2522 | 5c1c390f | balrog | time_t ti; |
2523 | 5c1c390f | balrog | uint64_t tick; |
2524 | 5c1c390f | balrog | }; |
2525 | 5c1c390f | balrog | |
2526 | 5c1c390f | balrog | static void omap_rtc_interrupts_update(struct omap_rtc_s *s) |
2527 | 5c1c390f | balrog | { |
2528 | 106627d0 | balrog | /* s->alarm is level-triggered */
|
2529 | 5c1c390f | balrog | qemu_set_irq(s->alarm, (s->status >> 6) & 1); |
2530 | 5c1c390f | balrog | } |
2531 | 5c1c390f | balrog | |
2532 | 5c1c390f | balrog | static void omap_rtc_alarm_update(struct omap_rtc_s *s) |
2533 | 5c1c390f | balrog | { |
2534 | 0cd2df75 | aurel32 | s->alarm_ti = mktimegm(&s->alarm_tm); |
2535 | 5c1c390f | balrog | if (s->alarm_ti == -1) |
2536 | 5c1c390f | balrog | printf("%s: conversion failed\n", __FUNCTION__);
|
2537 | 5c1c390f | balrog | } |
2538 | 5c1c390f | balrog | |
2539 | a4ebbd18 | Avi Kivity | static uint64_t omap_rtc_read(void *opaque, target_phys_addr_t addr, |
2540 | a4ebbd18 | Avi Kivity | unsigned size)
|
2541 | 5c1c390f | balrog | { |
2542 | 5c1c390f | balrog | struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; |
2543 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2544 | 5c1c390f | balrog | uint8_t i; |
2545 | 5c1c390f | balrog | |
2546 | a4ebbd18 | Avi Kivity | if (size != 1) { |
2547 | a4ebbd18 | Avi Kivity | return omap_badwidth_read8(opaque, addr);
|
2548 | a4ebbd18 | Avi Kivity | } |
2549 | a4ebbd18 | Avi Kivity | |
2550 | 5c1c390f | balrog | switch (offset) {
|
2551 | 5c1c390f | balrog | case 0x00: /* SECONDS_REG */ |
2552 | abd0c6bd | Paul Brook | return to_bcd(s->current_tm.tm_sec);
|
2553 | 5c1c390f | balrog | |
2554 | 5c1c390f | balrog | case 0x04: /* MINUTES_REG */ |
2555 | abd0c6bd | Paul Brook | return to_bcd(s->current_tm.tm_min);
|
2556 | 5c1c390f | balrog | |
2557 | 5c1c390f | balrog | case 0x08: /* HOURS_REG */ |
2558 | 5c1c390f | balrog | if (s->pm_am)
|
2559 | 5c1c390f | balrog | return ((s->current_tm.tm_hour > 11) << 7) | |
2560 | abd0c6bd | Paul Brook | to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); |
2561 | 5c1c390f | balrog | else
|
2562 | abd0c6bd | Paul Brook | return to_bcd(s->current_tm.tm_hour);
|
2563 | 5c1c390f | balrog | |
2564 | 5c1c390f | balrog | case 0x0c: /* DAYS_REG */ |
2565 | abd0c6bd | Paul Brook | return to_bcd(s->current_tm.tm_mday);
|
2566 | 5c1c390f | balrog | |
2567 | 5c1c390f | balrog | case 0x10: /* MONTHS_REG */ |
2568 | abd0c6bd | Paul Brook | return to_bcd(s->current_tm.tm_mon + 1); |
2569 | 5c1c390f | balrog | |
2570 | 5c1c390f | balrog | case 0x14: /* YEARS_REG */ |
2571 | abd0c6bd | Paul Brook | return to_bcd(s->current_tm.tm_year % 100); |
2572 | 5c1c390f | balrog | |
2573 | 5c1c390f | balrog | case 0x18: /* WEEK_REG */ |
2574 | 5c1c390f | balrog | return s->current_tm.tm_wday;
|
2575 | 5c1c390f | balrog | |
2576 | 5c1c390f | balrog | case 0x20: /* ALARM_SECONDS_REG */ |
2577 | abd0c6bd | Paul Brook | return to_bcd(s->alarm_tm.tm_sec);
|
2578 | 5c1c390f | balrog | |
2579 | 5c1c390f | balrog | case 0x24: /* ALARM_MINUTES_REG */ |
2580 | abd0c6bd | Paul Brook | return to_bcd(s->alarm_tm.tm_min);
|
2581 | 5c1c390f | balrog | |
2582 | 5c1c390f | balrog | case 0x28: /* ALARM_HOURS_REG */ |
2583 | 5c1c390f | balrog | if (s->pm_am)
|
2584 | 5c1c390f | balrog | return ((s->alarm_tm.tm_hour > 11) << 7) | |
2585 | abd0c6bd | Paul Brook | to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); |
2586 | 5c1c390f | balrog | else
|
2587 | abd0c6bd | Paul Brook | return to_bcd(s->alarm_tm.tm_hour);
|
2588 | 5c1c390f | balrog | |
2589 | 5c1c390f | balrog | case 0x2c: /* ALARM_DAYS_REG */ |
2590 | abd0c6bd | Paul Brook | return to_bcd(s->alarm_tm.tm_mday);
|
2591 | 5c1c390f | balrog | |
2592 | 5c1c390f | balrog | case 0x30: /* ALARM_MONTHS_REG */ |
2593 | abd0c6bd | Paul Brook | return to_bcd(s->alarm_tm.tm_mon + 1); |
2594 | 5c1c390f | balrog | |
2595 | 5c1c390f | balrog | case 0x34: /* ALARM_YEARS_REG */ |
2596 | abd0c6bd | Paul Brook | return to_bcd(s->alarm_tm.tm_year % 100); |
2597 | 5c1c390f | balrog | |
2598 | 5c1c390f | balrog | case 0x40: /* RTC_CTRL_REG */ |
2599 | 5c1c390f | balrog | return (s->pm_am << 3) | (s->auto_comp << 2) | |
2600 | 5c1c390f | balrog | (s->round << 1) | s->running;
|
2601 | 5c1c390f | balrog | |
2602 | 5c1c390f | balrog | case 0x44: /* RTC_STATUS_REG */ |
2603 | 5c1c390f | balrog | i = s->status; |
2604 | 5c1c390f | balrog | s->status &= ~0x3d;
|
2605 | 5c1c390f | balrog | return i;
|
2606 | 5c1c390f | balrog | |
2607 | 5c1c390f | balrog | case 0x48: /* RTC_INTERRUPTS_REG */ |
2608 | 5c1c390f | balrog | return s->interrupts;
|
2609 | 5c1c390f | balrog | |
2610 | 5c1c390f | balrog | case 0x4c: /* RTC_COMP_LSB_REG */ |
2611 | 5c1c390f | balrog | return ((uint16_t) s->comp_reg) & 0xff; |
2612 | 5c1c390f | balrog | |
2613 | 5c1c390f | balrog | case 0x50: /* RTC_COMP_MSB_REG */ |
2614 | 5c1c390f | balrog | return ((uint16_t) s->comp_reg) >> 8; |
2615 | 5c1c390f | balrog | } |
2616 | 5c1c390f | balrog | |
2617 | 5c1c390f | balrog | OMAP_BAD_REG(addr); |
2618 | 5c1c390f | balrog | return 0; |
2619 | 5c1c390f | balrog | } |
2620 | 5c1c390f | balrog | |
2621 | c227f099 | Anthony Liguori | static void omap_rtc_write(void *opaque, target_phys_addr_t addr, |
2622 | a4ebbd18 | Avi Kivity | uint64_t value, unsigned size)
|
2623 | 5c1c390f | balrog | { |
2624 | 5c1c390f | balrog | struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; |
2625 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2626 | 5c1c390f | balrog | struct tm new_tm;
|
2627 | 5c1c390f | balrog | time_t ti[2];
|
2628 | 5c1c390f | balrog | |
2629 | a4ebbd18 | Avi Kivity | if (size != 1) { |
2630 | a4ebbd18 | Avi Kivity | return omap_badwidth_write8(opaque, addr, value);
|
2631 | a4ebbd18 | Avi Kivity | } |
2632 | a4ebbd18 | Avi Kivity | |
2633 | 5c1c390f | balrog | switch (offset) {
|
2634 | 5c1c390f | balrog | case 0x00: /* SECONDS_REG */ |
2635 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2636 | 5c1c390f | balrog | printf("RTC SEC_REG <-- %02x\n", value);
|
2637 | 5c1c390f | balrog | #endif
|
2638 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_sec; |
2639 | abd0c6bd | Paul Brook | s->ti += from_bcd(value); |
2640 | 5c1c390f | balrog | return;
|
2641 | 5c1c390f | balrog | |
2642 | 5c1c390f | balrog | case 0x04: /* MINUTES_REG */ |
2643 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2644 | 5c1c390f | balrog | printf("RTC MIN_REG <-- %02x\n", value);
|
2645 | 5c1c390f | balrog | #endif
|
2646 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_min * 60;
|
2647 | abd0c6bd | Paul Brook | s->ti += from_bcd(value) * 60;
|
2648 | 5c1c390f | balrog | return;
|
2649 | 5c1c390f | balrog | |
2650 | 5c1c390f | balrog | case 0x08: /* HOURS_REG */ |
2651 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2652 | 5c1c390f | balrog | printf("RTC HRS_REG <-- %02x\n", value);
|
2653 | 5c1c390f | balrog | #endif
|
2654 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_hour * 3600;
|
2655 | 5c1c390f | balrog | if (s->pm_am) {
|
2656 | abd0c6bd | Paul Brook | s->ti += (from_bcd(value & 0x3f) & 12) * 3600; |
2657 | 5c1c390f | balrog | s->ti += ((value >> 7) & 1) * 43200; |
2658 | 5c1c390f | balrog | } else
|
2659 | abd0c6bd | Paul Brook | s->ti += from_bcd(value & 0x3f) * 3600; |
2660 | 5c1c390f | balrog | return;
|
2661 | 5c1c390f | balrog | |
2662 | 5c1c390f | balrog | case 0x0c: /* DAYS_REG */ |
2663 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2664 | 5c1c390f | balrog | printf("RTC DAY_REG <-- %02x\n", value);
|
2665 | 5c1c390f | balrog | #endif
|
2666 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_mday * 86400;
|
2667 | abd0c6bd | Paul Brook | s->ti += from_bcd(value) * 86400;
|
2668 | 5c1c390f | balrog | return;
|
2669 | 5c1c390f | balrog | |
2670 | 5c1c390f | balrog | case 0x10: /* MONTHS_REG */ |
2671 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2672 | 5c1c390f | balrog | printf("RTC MTH_REG <-- %02x\n", value);
|
2673 | 5c1c390f | balrog | #endif
|
2674 | 5c1c390f | balrog | memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
|
2675 | abd0c6bd | Paul Brook | new_tm.tm_mon = from_bcd(value); |
2676 | 0cd2df75 | aurel32 | ti[0] = mktimegm(&s->current_tm);
|
2677 | 0cd2df75 | aurel32 | ti[1] = mktimegm(&new_tm);
|
2678 | 5c1c390f | balrog | |
2679 | 5c1c390f | balrog | if (ti[0] != -1 && ti[1] != -1) { |
2680 | 5c1c390f | balrog | s->ti -= ti[0];
|
2681 | 5c1c390f | balrog | s->ti += ti[1];
|
2682 | 5c1c390f | balrog | } else {
|
2683 | 5c1c390f | balrog | /* A less accurate version */
|
2684 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_mon * 2592000;
|
2685 | abd0c6bd | Paul Brook | s->ti += from_bcd(value) * 2592000;
|
2686 | 5c1c390f | balrog | } |
2687 | 5c1c390f | balrog | return;
|
2688 | 5c1c390f | balrog | |
2689 | 5c1c390f | balrog | case 0x14: /* YEARS_REG */ |
2690 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2691 | 5c1c390f | balrog | printf("RTC YRS_REG <-- %02x\n", value);
|
2692 | 5c1c390f | balrog | #endif
|
2693 | 5c1c390f | balrog | memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
|
2694 | abd0c6bd | Paul Brook | new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100);
|
2695 | 0cd2df75 | aurel32 | ti[0] = mktimegm(&s->current_tm);
|
2696 | 0cd2df75 | aurel32 | ti[1] = mktimegm(&new_tm);
|
2697 | 5c1c390f | balrog | |
2698 | 5c1c390f | balrog | if (ti[0] != -1 && ti[1] != -1) { |
2699 | 5c1c390f | balrog | s->ti -= ti[0];
|
2700 | 5c1c390f | balrog | s->ti += ti[1];
|
2701 | 5c1c390f | balrog | } else {
|
2702 | 5c1c390f | balrog | /* A less accurate version */
|
2703 | 5c1c390f | balrog | s->ti -= (s->current_tm.tm_year % 100) * 31536000; |
2704 | abd0c6bd | Paul Brook | s->ti += from_bcd(value) * 31536000;
|
2705 | 5c1c390f | balrog | } |
2706 | 5c1c390f | balrog | return;
|
2707 | 5c1c390f | balrog | |
2708 | 5c1c390f | balrog | case 0x18: /* WEEK_REG */ |
2709 | 5c1c390f | balrog | return; /* Ignored */ |
2710 | 5c1c390f | balrog | |
2711 | 5c1c390f | balrog | case 0x20: /* ALARM_SECONDS_REG */ |
2712 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2713 | 5c1c390f | balrog | printf("ALM SEC_REG <-- %02x\n", value);
|
2714 | 5c1c390f | balrog | #endif
|
2715 | abd0c6bd | Paul Brook | s->alarm_tm.tm_sec = from_bcd(value); |
2716 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
2717 | 5c1c390f | balrog | return;
|
2718 | 5c1c390f | balrog | |
2719 | 5c1c390f | balrog | case 0x24: /* ALARM_MINUTES_REG */ |
2720 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2721 | 5c1c390f | balrog | printf("ALM MIN_REG <-- %02x\n", value);
|
2722 | 5c1c390f | balrog | #endif
|
2723 | abd0c6bd | Paul Brook | s->alarm_tm.tm_min = from_bcd(value); |
2724 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
2725 | 5c1c390f | balrog | return;
|
2726 | 5c1c390f | balrog | |
2727 | 5c1c390f | balrog | case 0x28: /* ALARM_HOURS_REG */ |
2728 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2729 | 5c1c390f | balrog | printf("ALM HRS_REG <-- %02x\n", value);
|
2730 | 5c1c390f | balrog | #endif
|
2731 | 5c1c390f | balrog | if (s->pm_am)
|
2732 | 5c1c390f | balrog | s->alarm_tm.tm_hour = |
2733 | abd0c6bd | Paul Brook | ((from_bcd(value & 0x3f)) % 12) + |
2734 | 5c1c390f | balrog | ((value >> 7) & 1) * 12; |
2735 | 5c1c390f | balrog | else
|
2736 | abd0c6bd | Paul Brook | s->alarm_tm.tm_hour = from_bcd(value); |
2737 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
2738 | 5c1c390f | balrog | return;
|
2739 | 5c1c390f | balrog | |
2740 | 5c1c390f | balrog | case 0x2c: /* ALARM_DAYS_REG */ |
2741 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2742 | 5c1c390f | balrog | printf("ALM DAY_REG <-- %02x\n", value);
|
2743 | 5c1c390f | balrog | #endif
|
2744 | abd0c6bd | Paul Brook | s->alarm_tm.tm_mday = from_bcd(value); |
2745 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
2746 | 5c1c390f | balrog | return;
|
2747 | 5c1c390f | balrog | |
2748 | 5c1c390f | balrog | case 0x30: /* ALARM_MONTHS_REG */ |
2749 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2750 | 5c1c390f | balrog | printf("ALM MON_REG <-- %02x\n", value);
|
2751 | 5c1c390f | balrog | #endif
|
2752 | abd0c6bd | Paul Brook | s->alarm_tm.tm_mon = from_bcd(value); |
2753 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
2754 | 5c1c390f | balrog | return;
|
2755 | 5c1c390f | balrog | |
2756 | 5c1c390f | balrog | case 0x34: /* ALARM_YEARS_REG */ |
2757 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2758 | 5c1c390f | balrog | printf("ALM YRS_REG <-- %02x\n", value);
|
2759 | 5c1c390f | balrog | #endif
|
2760 | abd0c6bd | Paul Brook | s->alarm_tm.tm_year = from_bcd(value); |
2761 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
2762 | 5c1c390f | balrog | return;
|
2763 | 5c1c390f | balrog | |
2764 | 5c1c390f | balrog | case 0x40: /* RTC_CTRL_REG */ |
2765 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2766 | 5c1c390f | balrog | printf("RTC CONTROL <-- %02x\n", value);
|
2767 | 5c1c390f | balrog | #endif
|
2768 | 5c1c390f | balrog | s->pm_am = (value >> 3) & 1; |
2769 | 5c1c390f | balrog | s->auto_comp = (value >> 2) & 1; |
2770 | 5c1c390f | balrog | s->round = (value >> 1) & 1; |
2771 | 5c1c390f | balrog | s->running = value & 1;
|
2772 | 5c1c390f | balrog | s->status &= 0xfd;
|
2773 | 5c1c390f | balrog | s->status |= s->running << 1;
|
2774 | 5c1c390f | balrog | return;
|
2775 | 5c1c390f | balrog | |
2776 | 5c1c390f | balrog | case 0x44: /* RTC_STATUS_REG */ |
2777 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2778 | 5c1c390f | balrog | printf("RTC STATUSL <-- %02x\n", value);
|
2779 | 5c1c390f | balrog | #endif
|
2780 | 5c1c390f | balrog | s->status &= ~((value & 0xc0) ^ 0x80); |
2781 | 5c1c390f | balrog | omap_rtc_interrupts_update(s); |
2782 | 5c1c390f | balrog | return;
|
2783 | 5c1c390f | balrog | |
2784 | 5c1c390f | balrog | case 0x48: /* RTC_INTERRUPTS_REG */ |
2785 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2786 | 5c1c390f | balrog | printf("RTC INTRS <-- %02x\n", value);
|
2787 | 5c1c390f | balrog | #endif
|
2788 | 5c1c390f | balrog | s->interrupts = value; |
2789 | 5c1c390f | balrog | return;
|
2790 | 5c1c390f | balrog | |
2791 | 5c1c390f | balrog | case 0x4c: /* RTC_COMP_LSB_REG */ |
2792 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2793 | 5c1c390f | balrog | printf("RTC COMPLSB <-- %02x\n", value);
|
2794 | 5c1c390f | balrog | #endif
|
2795 | 5c1c390f | balrog | s->comp_reg &= 0xff00;
|
2796 | 5c1c390f | balrog | s->comp_reg |= 0x00ff & value;
|
2797 | 5c1c390f | balrog | return;
|
2798 | 5c1c390f | balrog | |
2799 | 5c1c390f | balrog | case 0x50: /* RTC_COMP_MSB_REG */ |
2800 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2801 | 5c1c390f | balrog | printf("RTC COMPMSB <-- %02x\n", value);
|
2802 | 5c1c390f | balrog | #endif
|
2803 | 5c1c390f | balrog | s->comp_reg &= 0x00ff;
|
2804 | 5c1c390f | balrog | s->comp_reg |= 0xff00 & (value << 8); |
2805 | 5c1c390f | balrog | return;
|
2806 | 5c1c390f | balrog | |
2807 | 5c1c390f | balrog | default:
|
2808 | 5c1c390f | balrog | OMAP_BAD_REG(addr); |
2809 | 5c1c390f | balrog | return;
|
2810 | 5c1c390f | balrog | } |
2811 | 5c1c390f | balrog | } |
2812 | 5c1c390f | balrog | |
2813 | a4ebbd18 | Avi Kivity | static const MemoryRegionOps omap_rtc_ops = { |
2814 | a4ebbd18 | Avi Kivity | .read = omap_rtc_read, |
2815 | a4ebbd18 | Avi Kivity | .write = omap_rtc_write, |
2816 | a4ebbd18 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
2817 | 5c1c390f | balrog | }; |
2818 | 5c1c390f | balrog | |
2819 | 5c1c390f | balrog | static void omap_rtc_tick(void *opaque) |
2820 | 5c1c390f | balrog | { |
2821 | 5c1c390f | balrog | struct omap_rtc_s *s = opaque;
|
2822 | 5c1c390f | balrog | |
2823 | 5c1c390f | balrog | if (s->round) {
|
2824 | 5c1c390f | balrog | /* Round to nearest full minute. */
|
2825 | 5c1c390f | balrog | if (s->current_tm.tm_sec < 30) |
2826 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_sec; |
2827 | 5c1c390f | balrog | else
|
2828 | 5c1c390f | balrog | s->ti += 60 - s->current_tm.tm_sec;
|
2829 | 5c1c390f | balrog | |
2830 | 5c1c390f | balrog | s->round = 0;
|
2831 | 5c1c390f | balrog | } |
2832 | 5c1c390f | balrog | |
2833 | f6503059 | balrog | memcpy(&s->current_tm, localtime(&s->ti), sizeof(s->current_tm));
|
2834 | 5c1c390f | balrog | |
2835 | 5c1c390f | balrog | if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { |
2836 | 5c1c390f | balrog | s->status |= 0x40;
|
2837 | 5c1c390f | balrog | omap_rtc_interrupts_update(s); |
2838 | 5c1c390f | balrog | } |
2839 | 5c1c390f | balrog | |
2840 | 5c1c390f | balrog | if (s->interrupts & 0x04) |
2841 | 5c1c390f | balrog | switch (s->interrupts & 3) { |
2842 | 5c1c390f | balrog | case 0: |
2843 | 5c1c390f | balrog | s->status |= 0x04;
|
2844 | 106627d0 | balrog | qemu_irq_pulse(s->irq); |
2845 | 5c1c390f | balrog | break;
|
2846 | 5c1c390f | balrog | case 1: |
2847 | 5c1c390f | balrog | if (s->current_tm.tm_sec)
|
2848 | 5c1c390f | balrog | break;
|
2849 | 5c1c390f | balrog | s->status |= 0x08;
|
2850 | 106627d0 | balrog | qemu_irq_pulse(s->irq); |
2851 | 5c1c390f | balrog | break;
|
2852 | 5c1c390f | balrog | case 2: |
2853 | 5c1c390f | balrog | if (s->current_tm.tm_sec || s->current_tm.tm_min)
|
2854 | 5c1c390f | balrog | break;
|
2855 | 5c1c390f | balrog | s->status |= 0x10;
|
2856 | 106627d0 | balrog | qemu_irq_pulse(s->irq); |
2857 | 5c1c390f | balrog | break;
|
2858 | 5c1c390f | balrog | case 3: |
2859 | 5c1c390f | balrog | if (s->current_tm.tm_sec ||
|
2860 | 5c1c390f | balrog | s->current_tm.tm_min || s->current_tm.tm_hour) |
2861 | 5c1c390f | balrog | break;
|
2862 | 5c1c390f | balrog | s->status |= 0x20;
|
2863 | 106627d0 | balrog | qemu_irq_pulse(s->irq); |
2864 | 5c1c390f | balrog | break;
|
2865 | 5c1c390f | balrog | } |
2866 | 5c1c390f | balrog | |
2867 | 5c1c390f | balrog | /* Move on */
|
2868 | 5c1c390f | balrog | if (s->running)
|
2869 | 5c1c390f | balrog | s->ti ++; |
2870 | 5c1c390f | balrog | s->tick += 1000;
|
2871 | 5c1c390f | balrog | |
2872 | 5c1c390f | balrog | /*
|
2873 | 5c1c390f | balrog | * Every full hour add a rough approximation of the compensation
|
2874 | 5c1c390f | balrog | * register to the 32kHz Timer (which drives the RTC) value.
|
2875 | 5c1c390f | balrog | */
|
2876 | 5c1c390f | balrog | if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
|
2877 | 5c1c390f | balrog | s->tick += s->comp_reg * 1000 / 32768; |
2878 | 5c1c390f | balrog | |
2879 | 5c1c390f | balrog | qemu_mod_timer(s->clk, s->tick); |
2880 | 5c1c390f | balrog | } |
2881 | 5c1c390f | balrog | |
2882 | 9596ebb7 | pbrook | static void omap_rtc_reset(struct omap_rtc_s *s) |
2883 | 5c1c390f | balrog | { |
2884 | f6503059 | balrog | struct tm tm;
|
2885 | f6503059 | balrog | |
2886 | 5c1c390f | balrog | s->interrupts = 0;
|
2887 | 5c1c390f | balrog | s->comp_reg = 0;
|
2888 | 5c1c390f | balrog | s->running = 0;
|
2889 | 5c1c390f | balrog | s->pm_am = 0;
|
2890 | 5c1c390f | balrog | s->auto_comp = 0;
|
2891 | 5c1c390f | balrog | s->round = 0;
|
2892 | 348abc86 | Paolo Bonzini | s->tick = qemu_get_clock_ms(rtc_clock); |
2893 | 5c1c390f | balrog | memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); |
2894 | 5c1c390f | balrog | s->alarm_tm.tm_mday = 0x01;
|
2895 | 5c1c390f | balrog | s->status = 1 << 7; |
2896 | f6503059 | balrog | qemu_get_timedate(&tm, 0);
|
2897 | 0cd2df75 | aurel32 | s->ti = mktimegm(&tm); |
2898 | 5c1c390f | balrog | |
2899 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
2900 | 5c1c390f | balrog | omap_rtc_tick(s); |
2901 | 5c1c390f | balrog | } |
2902 | 5c1c390f | balrog | |
2903 | a4ebbd18 | Avi Kivity | static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory, |
2904 | 0919ac78 | Peter Maydell | target_phys_addr_t base, |
2905 | 0919ac78 | Peter Maydell | qemu_irq timerirq, qemu_irq alarmirq, |
2906 | 0919ac78 | Peter Maydell | omap_clk clk) |
2907 | 5c1c390f | balrog | { |
2908 | 5c1c390f | balrog | struct omap_rtc_s *s = (struct omap_rtc_s *) |
2909 | 7267c094 | Anthony Liguori | g_malloc0(sizeof(struct omap_rtc_s)); |
2910 | 5c1c390f | balrog | |
2911 | 0919ac78 | Peter Maydell | s->irq = timerirq; |
2912 | 0919ac78 | Peter Maydell | s->alarm = alarmirq; |
2913 | 348abc86 | Paolo Bonzini | s->clk = qemu_new_timer_ms(rtc_clock, omap_rtc_tick, s); |
2914 | 5c1c390f | balrog | |
2915 | 5c1c390f | balrog | omap_rtc_reset(s); |
2916 | 5c1c390f | balrog | |
2917 | a4ebbd18 | Avi Kivity | memory_region_init_io(&s->iomem, &omap_rtc_ops, s, |
2918 | a4ebbd18 | Avi Kivity | "omap-rtc", 0x800); |
2919 | a4ebbd18 | Avi Kivity | memory_region_add_subregion(system_memory, base, &s->iomem); |
2920 | 5c1c390f | balrog | |
2921 | 5c1c390f | balrog | return s;
|
2922 | 5c1c390f | balrog | } |
2923 | 5c1c390f | balrog | |
2924 | d8f699cb | balrog | /* Multi-channel Buffered Serial Port interfaces */
|
2925 | d8f699cb | balrog | struct omap_mcbsp_s {
|
2926 | a4ebbd18 | Avi Kivity | MemoryRegion iomem; |
2927 | d8f699cb | balrog | qemu_irq txirq; |
2928 | d8f699cb | balrog | qemu_irq rxirq; |
2929 | d8f699cb | balrog | qemu_irq txdrq; |
2930 | d8f699cb | balrog | qemu_irq rxdrq; |
2931 | d8f699cb | balrog | |
2932 | d8f699cb | balrog | uint16_t spcr[2];
|
2933 | d8f699cb | balrog | uint16_t rcr[2];
|
2934 | d8f699cb | balrog | uint16_t xcr[2];
|
2935 | d8f699cb | balrog | uint16_t srgr[2];
|
2936 | d8f699cb | balrog | uint16_t mcr[2];
|
2937 | d8f699cb | balrog | uint16_t pcr; |
2938 | d8f699cb | balrog | uint16_t rcer[8];
|
2939 | d8f699cb | balrog | uint16_t xcer[8];
|
2940 | d8f699cb | balrog | int tx_rate;
|
2941 | d8f699cb | balrog | int rx_rate;
|
2942 | d8f699cb | balrog | int tx_req;
|
2943 | 73560bc8 | balrog | int rx_req;
|
2944 | d8f699cb | balrog | |
2945 | bc24a225 | Paul Brook | I2SCodec *codec; |
2946 | 73560bc8 | balrog | QEMUTimer *source_timer; |
2947 | 73560bc8 | balrog | QEMUTimer *sink_timer; |
2948 | d8f699cb | balrog | }; |
2949 | d8f699cb | balrog | |
2950 | d8f699cb | balrog | static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s) |
2951 | d8f699cb | balrog | { |
2952 | d8f699cb | balrog | int irq;
|
2953 | d8f699cb | balrog | |
2954 | d8f699cb | balrog | switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ |
2955 | d8f699cb | balrog | case 0: |
2956 | d8f699cb | balrog | irq = (s->spcr[0] >> 1) & 1; /* RRDY */ |
2957 | d8f699cb | balrog | break;
|
2958 | d8f699cb | balrog | case 3: |
2959 | d8f699cb | balrog | irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */ |
2960 | d8f699cb | balrog | break;
|
2961 | d8f699cb | balrog | default:
|
2962 | d8f699cb | balrog | irq = 0;
|
2963 | d8f699cb | balrog | break;
|
2964 | d8f699cb | balrog | } |
2965 | d8f699cb | balrog | |
2966 | 106627d0 | balrog | if (irq)
|
2967 | 106627d0 | balrog | qemu_irq_pulse(s->rxirq); |
2968 | d8f699cb | balrog | |
2969 | d8f699cb | balrog | switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ |
2970 | d8f699cb | balrog | case 0: |
2971 | d8f699cb | balrog | irq = (s->spcr[1] >> 1) & 1; /* XRDY */ |
2972 | d8f699cb | balrog | break;
|
2973 | d8f699cb | balrog | case 3: |
2974 | d8f699cb | balrog | irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */ |
2975 | d8f699cb | balrog | break;
|
2976 | d8f699cb | balrog | default:
|
2977 | d8f699cb | balrog | irq = 0;
|
2978 | d8f699cb | balrog | break;
|
2979 | d8f699cb | balrog | } |
2980 | d8f699cb | balrog | |
2981 | 106627d0 | balrog | if (irq)
|
2982 | 106627d0 | balrog | qemu_irq_pulse(s->txirq); |
2983 | d8f699cb | balrog | } |
2984 | d8f699cb | balrog | |
2985 | 73560bc8 | balrog | static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s) |
2986 | d8f699cb | balrog | { |
2987 | 73560bc8 | balrog | if ((s->spcr[0] >> 1) & 1) /* RRDY */ |
2988 | 73560bc8 | balrog | s->spcr[0] |= 1 << 2; /* RFULL */ |
2989 | 73560bc8 | balrog | s->spcr[0] |= 1 << 1; /* RRDY */ |
2990 | 73560bc8 | balrog | qemu_irq_raise(s->rxdrq); |
2991 | 73560bc8 | balrog | omap_mcbsp_intr_update(s); |
2992 | d8f699cb | balrog | } |
2993 | d8f699cb | balrog | |
2994 | 73560bc8 | balrog | static void omap_mcbsp_source_tick(void *opaque) |
2995 | d8f699cb | balrog | { |
2996 | 73560bc8 | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
2997 | 73560bc8 | balrog | static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; |
2998 | 73560bc8 | balrog | |
2999 | 73560bc8 | balrog | if (!s->rx_rate)
|
3000 | d8f699cb | balrog | return;
|
3001 | 73560bc8 | balrog | if (s->rx_req)
|
3002 | 73560bc8 | balrog | printf("%s: Rx FIFO overrun\n", __FUNCTION__);
|
3003 | d8f699cb | balrog | |
3004 | 73560bc8 | balrog | s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; |
3005 | d8f699cb | balrog | |
3006 | 73560bc8 | balrog | omap_mcbsp_rx_newdata(s); |
3007 | 74475455 | Paolo Bonzini | qemu_mod_timer(s->source_timer, qemu_get_clock_ns(vm_clock) + |
3008 | 6ee093c9 | Juan Quintela | get_ticks_per_sec()); |
3009 | d8f699cb | balrog | } |
3010 | d8f699cb | balrog | |
3011 | d8f699cb | balrog | static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s) |
3012 | d8f699cb | balrog | { |
3013 | 73560bc8 | balrog | if (!s->codec || !s->codec->rts)
|
3014 | 73560bc8 | balrog | omap_mcbsp_source_tick(s); |
3015 | 73560bc8 | balrog | else if (s->codec->in.len) { |
3016 | 73560bc8 | balrog | s->rx_req = s->codec->in.len; |
3017 | 73560bc8 | balrog | omap_mcbsp_rx_newdata(s); |
3018 | d8f699cb | balrog | } |
3019 | d8f699cb | balrog | } |
3020 | d8f699cb | balrog | |
3021 | d8f699cb | balrog | static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s) |
3022 | d8f699cb | balrog | { |
3023 | 73560bc8 | balrog | qemu_del_timer(s->source_timer); |
3024 | 73560bc8 | balrog | } |
3025 | 73560bc8 | balrog | |
3026 | 73560bc8 | balrog | static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s) |
3027 | 73560bc8 | balrog | { |
3028 | d8f699cb | balrog | s->spcr[0] &= ~(1 << 1); /* RRDY */ |
3029 | d8f699cb | balrog | qemu_irq_lower(s->rxdrq); |
3030 | d8f699cb | balrog | omap_mcbsp_intr_update(s); |
3031 | d8f699cb | balrog | } |
3032 | d8f699cb | balrog | |
3033 | 73560bc8 | balrog | static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s) |
3034 | 73560bc8 | balrog | { |
3035 | 73560bc8 | balrog | s->spcr[1] |= 1 << 1; /* XRDY */ |
3036 | 73560bc8 | balrog | qemu_irq_raise(s->txdrq); |
3037 | 73560bc8 | balrog | omap_mcbsp_intr_update(s); |
3038 | 73560bc8 | balrog | } |
3039 | 73560bc8 | balrog | |
3040 | 73560bc8 | balrog | static void omap_mcbsp_sink_tick(void *opaque) |
3041 | d8f699cb | balrog | { |
3042 | 73560bc8 | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3043 | 73560bc8 | balrog | static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; |
3044 | 73560bc8 | balrog | |
3045 | 73560bc8 | balrog | if (!s->tx_rate)
|
3046 | d8f699cb | balrog | return;
|
3047 | 73560bc8 | balrog | if (s->tx_req)
|
3048 | 73560bc8 | balrog | printf("%s: Tx FIFO underrun\n", __FUNCTION__);
|
3049 | 73560bc8 | balrog | |
3050 | 73560bc8 | balrog | s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; |
3051 | 73560bc8 | balrog | |
3052 | 73560bc8 | balrog | omap_mcbsp_tx_newdata(s); |
3053 | 74475455 | Paolo Bonzini | qemu_mod_timer(s->sink_timer, qemu_get_clock_ns(vm_clock) + |
3054 | 6ee093c9 | Juan Quintela | get_ticks_per_sec()); |
3055 | 73560bc8 | balrog | } |
3056 | 73560bc8 | balrog | |
3057 | 73560bc8 | balrog | static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s) |
3058 | 73560bc8 | balrog | { |
3059 | 73560bc8 | balrog | if (!s->codec || !s->codec->cts)
|
3060 | 73560bc8 | balrog | omap_mcbsp_sink_tick(s); |
3061 | 73560bc8 | balrog | else if (s->codec->out.size) { |
3062 | 73560bc8 | balrog | s->tx_req = s->codec->out.size; |
3063 | 73560bc8 | balrog | omap_mcbsp_tx_newdata(s); |
3064 | 73560bc8 | balrog | } |
3065 | 73560bc8 | balrog | } |
3066 | 73560bc8 | balrog | |
3067 | 73560bc8 | balrog | static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s) |
3068 | 73560bc8 | balrog | { |
3069 | 73560bc8 | balrog | s->spcr[1] &= ~(1 << 1); /* XRDY */ |
3070 | 73560bc8 | balrog | qemu_irq_lower(s->txdrq); |
3071 | 73560bc8 | balrog | omap_mcbsp_intr_update(s); |
3072 | 73560bc8 | balrog | if (s->codec && s->codec->cts)
|
3073 | 73560bc8 | balrog | s->codec->tx_swallow(s->codec->opaque); |
3074 | d8f699cb | balrog | } |
3075 | d8f699cb | balrog | |
3076 | d8f699cb | balrog | static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s) |
3077 | d8f699cb | balrog | { |
3078 | 73560bc8 | balrog | s->tx_req = 0;
|
3079 | 73560bc8 | balrog | omap_mcbsp_tx_done(s); |
3080 | 73560bc8 | balrog | qemu_del_timer(s->sink_timer); |
3081 | 73560bc8 | balrog | } |
3082 | 73560bc8 | balrog | |
3083 | 73560bc8 | balrog | static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) |
3084 | 73560bc8 | balrog | { |
3085 | 73560bc8 | balrog | int prev_rx_rate, prev_tx_rate;
|
3086 | 73560bc8 | balrog | int rx_rate = 0, tx_rate = 0; |
3087 | 73560bc8 | balrog | int cpu_rate = 1500000; /* XXX */ |
3088 | 73560bc8 | balrog | |
3089 | 73560bc8 | balrog | /* TODO: check CLKSTP bit */
|
3090 | 73560bc8 | balrog | if (s->spcr[1] & (1 << 6)) { /* GRST */ |
3091 | 73560bc8 | balrog | if (s->spcr[0] & (1 << 0)) { /* RRST */ |
3092 | 73560bc8 | balrog | if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ |
3093 | 73560bc8 | balrog | (s->pcr & (1 << 8))) { /* CLKRM */ |
3094 | 73560bc8 | balrog | if (~s->pcr & (1 << 7)) /* SCLKME */ |
3095 | 73560bc8 | balrog | rx_rate = cpu_rate / |
3096 | 73560bc8 | balrog | ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ |
3097 | 73560bc8 | balrog | } else
|
3098 | 73560bc8 | balrog | if (s->codec)
|
3099 | 73560bc8 | balrog | rx_rate = s->codec->rx_rate; |
3100 | 73560bc8 | balrog | } |
3101 | 73560bc8 | balrog | |
3102 | 73560bc8 | balrog | if (s->spcr[1] & (1 << 0)) { /* XRST */ |
3103 | 73560bc8 | balrog | if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ |
3104 | 73560bc8 | balrog | (s->pcr & (1 << 9))) { /* CLKXM */ |
3105 | 73560bc8 | balrog | if (~s->pcr & (1 << 7)) /* SCLKME */ |
3106 | 73560bc8 | balrog | tx_rate = cpu_rate / |
3107 | 73560bc8 | balrog | ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ |
3108 | 73560bc8 | balrog | } else
|
3109 | 73560bc8 | balrog | if (s->codec)
|
3110 | 73560bc8 | balrog | tx_rate = s->codec->tx_rate; |
3111 | 73560bc8 | balrog | } |
3112 | 73560bc8 | balrog | } |
3113 | 73560bc8 | balrog | prev_tx_rate = s->tx_rate; |
3114 | 73560bc8 | balrog | prev_rx_rate = s->rx_rate; |
3115 | 73560bc8 | balrog | s->tx_rate = tx_rate; |
3116 | 73560bc8 | balrog | s->rx_rate = rx_rate; |
3117 | 73560bc8 | balrog | |
3118 | 73560bc8 | balrog | if (s->codec)
|
3119 | 73560bc8 | balrog | s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate); |
3120 | 73560bc8 | balrog | |
3121 | 73560bc8 | balrog | if (!prev_tx_rate && tx_rate)
|
3122 | 73560bc8 | balrog | omap_mcbsp_tx_start(s); |
3123 | 73560bc8 | balrog | else if (s->tx_rate && !tx_rate) |
3124 | 73560bc8 | balrog | omap_mcbsp_tx_stop(s); |
3125 | 73560bc8 | balrog | |
3126 | 73560bc8 | balrog | if (!prev_rx_rate && rx_rate)
|
3127 | 73560bc8 | balrog | omap_mcbsp_rx_start(s); |
3128 | 73560bc8 | balrog | else if (prev_tx_rate && !tx_rate) |
3129 | 73560bc8 | balrog | omap_mcbsp_rx_stop(s); |
3130 | d8f699cb | balrog | } |
3131 | d8f699cb | balrog | |
3132 | a4ebbd18 | Avi Kivity | static uint64_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr, |
3133 | a4ebbd18 | Avi Kivity | unsigned size)
|
3134 | d8f699cb | balrog | { |
3135 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3136 | d8f699cb | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3137 | d8f699cb | balrog | uint16_t ret; |
3138 | d8f699cb | balrog | |
3139 | a4ebbd18 | Avi Kivity | if (size != 2) { |
3140 | a4ebbd18 | Avi Kivity | return omap_badwidth_read16(opaque, addr);
|
3141 | a4ebbd18 | Avi Kivity | } |
3142 | a4ebbd18 | Avi Kivity | |
3143 | d8f699cb | balrog | switch (offset) {
|
3144 | d8f699cb | balrog | case 0x00: /* DRR2 */ |
3145 | d8f699cb | balrog | if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ |
3146 | d8f699cb | balrog | return 0x0000; |
3147 | d8f699cb | balrog | /* Fall through. */
|
3148 | d8f699cb | balrog | case 0x02: /* DRR1 */ |
3149 | 73560bc8 | balrog | if (s->rx_req < 2) { |
3150 | d8f699cb | balrog | printf("%s: Rx FIFO underrun\n", __FUNCTION__);
|
3151 | 73560bc8 | balrog | omap_mcbsp_rx_done(s); |
3152 | d8f699cb | balrog | } else {
|
3153 | 73560bc8 | balrog | s->tx_req -= 2;
|
3154 | 73560bc8 | balrog | if (s->codec && s->codec->in.len >= 2) { |
3155 | 73560bc8 | balrog | ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
|
3156 | 73560bc8 | balrog | ret |= s->codec->in.fifo[s->codec->in.start ++]; |
3157 | 73560bc8 | balrog | s->codec->in.len -= 2;
|
3158 | 73560bc8 | balrog | } else
|
3159 | 73560bc8 | balrog | ret = 0x0000;
|
3160 | 73560bc8 | balrog | if (!s->tx_req)
|
3161 | 73560bc8 | balrog | omap_mcbsp_rx_done(s); |
3162 | d8f699cb | balrog | return ret;
|
3163 | d8f699cb | balrog | } |
3164 | d8f699cb | balrog | return 0x0000; |
3165 | d8f699cb | balrog | |
3166 | d8f699cb | balrog | case 0x04: /* DXR2 */ |
3167 | d8f699cb | balrog | case 0x06: /* DXR1 */ |
3168 | d8f699cb | balrog | return 0x0000; |
3169 | d8f699cb | balrog | |
3170 | d8f699cb | balrog | case 0x08: /* SPCR2 */ |
3171 | d8f699cb | balrog | return s->spcr[1]; |
3172 | d8f699cb | balrog | case 0x0a: /* SPCR1 */ |
3173 | d8f699cb | balrog | return s->spcr[0]; |
3174 | d8f699cb | balrog | case 0x0c: /* RCR2 */ |
3175 | d8f699cb | balrog | return s->rcr[1]; |
3176 | d8f699cb | balrog | case 0x0e: /* RCR1 */ |
3177 | d8f699cb | balrog | return s->rcr[0]; |
3178 | d8f699cb | balrog | case 0x10: /* XCR2 */ |
3179 | d8f699cb | balrog | return s->xcr[1]; |
3180 | d8f699cb | balrog | case 0x12: /* XCR1 */ |
3181 | d8f699cb | balrog | return s->xcr[0]; |
3182 | d8f699cb | balrog | case 0x14: /* SRGR2 */ |
3183 | d8f699cb | balrog | return s->srgr[1]; |
3184 | d8f699cb | balrog | case 0x16: /* SRGR1 */ |
3185 | d8f699cb | balrog | return s->srgr[0]; |
3186 | d8f699cb | balrog | case 0x18: /* MCR2 */ |
3187 | d8f699cb | balrog | return s->mcr[1]; |
3188 | d8f699cb | balrog | case 0x1a: /* MCR1 */ |
3189 | d8f699cb | balrog | return s->mcr[0]; |
3190 | d8f699cb | balrog | case 0x1c: /* RCERA */ |
3191 | d8f699cb | balrog | return s->rcer[0]; |
3192 | d8f699cb | balrog | case 0x1e: /* RCERB */ |
3193 | d8f699cb | balrog | return s->rcer[1]; |
3194 | d8f699cb | balrog | case 0x20: /* XCERA */ |
3195 | d8f699cb | balrog | return s->xcer[0]; |
3196 | d8f699cb | balrog | case 0x22: /* XCERB */ |
3197 | d8f699cb | balrog | return s->xcer[1]; |
3198 | d8f699cb | balrog | case 0x24: /* PCR0 */ |
3199 | d8f699cb | balrog | return s->pcr;
|
3200 | d8f699cb | balrog | case 0x26: /* RCERC */ |
3201 | d8f699cb | balrog | return s->rcer[2]; |
3202 | d8f699cb | balrog | case 0x28: /* RCERD */ |
3203 | d8f699cb | balrog | return s->rcer[3]; |
3204 | d8f699cb | balrog | case 0x2a: /* XCERC */ |
3205 | d8f699cb | balrog | return s->xcer[2]; |
3206 | d8f699cb | balrog | case 0x2c: /* XCERD */ |
3207 | d8f699cb | balrog | return s->xcer[3]; |
3208 | d8f699cb | balrog | case 0x2e: /* RCERE */ |
3209 | d8f699cb | balrog | return s->rcer[4]; |
3210 | d8f699cb | balrog | case 0x30: /* RCERF */ |
3211 | d8f699cb | balrog | return s->rcer[5]; |
3212 | d8f699cb | balrog | case 0x32: /* XCERE */ |
3213 | d8f699cb | balrog | return s->xcer[4]; |
3214 | d8f699cb | balrog | case 0x34: /* XCERF */ |
3215 | d8f699cb | balrog | return s->xcer[5]; |
3216 | d8f699cb | balrog | case 0x36: /* RCERG */ |
3217 | d8f699cb | balrog | return s->rcer[6]; |
3218 | d8f699cb | balrog | case 0x38: /* RCERH */ |
3219 | d8f699cb | balrog | return s->rcer[7]; |
3220 | d8f699cb | balrog | case 0x3a: /* XCERG */ |
3221 | d8f699cb | balrog | return s->xcer[6]; |
3222 | d8f699cb | balrog | case 0x3c: /* XCERH */ |
3223 | d8f699cb | balrog | return s->xcer[7]; |
3224 | d8f699cb | balrog | } |
3225 | d8f699cb | balrog | |
3226 | d8f699cb | balrog | OMAP_BAD_REG(addr); |
3227 | d8f699cb | balrog | return 0; |
3228 | d8f699cb | balrog | } |
3229 | d8f699cb | balrog | |
3230 | c227f099 | Anthony Liguori | static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr, |
3231 | d8f699cb | balrog | uint32_t value) |
3232 | d8f699cb | balrog | { |
3233 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3234 | d8f699cb | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3235 | d8f699cb | balrog | |
3236 | d8f699cb | balrog | switch (offset) {
|
3237 | d8f699cb | balrog | case 0x00: /* DRR2 */ |
3238 | d8f699cb | balrog | case 0x02: /* DRR1 */ |
3239 | d8f699cb | balrog | OMAP_RO_REG(addr); |
3240 | d8f699cb | balrog | return;
|
3241 | d8f699cb | balrog | |
3242 | d8f699cb | balrog | case 0x04: /* DXR2 */ |
3243 | d8f699cb | balrog | if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ |
3244 | d8f699cb | balrog | return;
|
3245 | d8f699cb | balrog | /* Fall through. */
|
3246 | d8f699cb | balrog | case 0x06: /* DXR1 */ |
3247 | 73560bc8 | balrog | if (s->tx_req > 1) { |
3248 | 73560bc8 | balrog | s->tx_req -= 2;
|
3249 | 73560bc8 | balrog | if (s->codec && s->codec->cts) {
|
3250 | d8f699cb | balrog | s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; |
3251 | d8f699cb | balrog | s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; |
3252 | d8f699cb | balrog | } |
3253 | 73560bc8 | balrog | if (s->tx_req < 2) |
3254 | 73560bc8 | balrog | omap_mcbsp_tx_done(s); |
3255 | d8f699cb | balrog | } else
|
3256 | d8f699cb | balrog | printf("%s: Tx FIFO overrun\n", __FUNCTION__);
|
3257 | d8f699cb | balrog | return;
|
3258 | d8f699cb | balrog | |
3259 | d8f699cb | balrog | case 0x08: /* SPCR2 */ |
3260 | d8f699cb | balrog | s->spcr[1] &= 0x0002; |
3261 | d8f699cb | balrog | s->spcr[1] |= 0x03f9 & value; |
3262 | d8f699cb | balrog | s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ |
3263 | 73560bc8 | balrog | if (~value & 1) /* XRST */ |
3264 | d8f699cb | balrog | s->spcr[1] &= ~6; |
3265 | d8f699cb | balrog | omap_mcbsp_req_update(s); |
3266 | d8f699cb | balrog | return;
|
3267 | d8f699cb | balrog | case 0x0a: /* SPCR1 */ |
3268 | d8f699cb | balrog | s->spcr[0] &= 0x0006; |
3269 | d8f699cb | balrog | s->spcr[0] |= 0xf8f9 & value; |
3270 | d8f699cb | balrog | if (value & (1 << 15)) /* DLB */ |
3271 | d8f699cb | balrog | printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__);
|
3272 | d8f699cb | balrog | if (~value & 1) { /* RRST */ |
3273 | d8f699cb | balrog | s->spcr[0] &= ~6; |
3274 | 73560bc8 | balrog | s->rx_req = 0;
|
3275 | 73560bc8 | balrog | omap_mcbsp_rx_done(s); |
3276 | d8f699cb | balrog | } |
3277 | d8f699cb | balrog | omap_mcbsp_req_update(s); |
3278 | d8f699cb | balrog | return;
|
3279 | d8f699cb | balrog | |
3280 | d8f699cb | balrog | case 0x0c: /* RCR2 */ |
3281 | d8f699cb | balrog | s->rcr[1] = value & 0xffff; |
3282 | d8f699cb | balrog | return;
|
3283 | d8f699cb | balrog | case 0x0e: /* RCR1 */ |
3284 | d8f699cb | balrog | s->rcr[0] = value & 0x7fe0; |
3285 | d8f699cb | balrog | return;
|
3286 | d8f699cb | balrog | case 0x10: /* XCR2 */ |
3287 | d8f699cb | balrog | s->xcr[1] = value & 0xffff; |
3288 | d8f699cb | balrog | return;
|
3289 | d8f699cb | balrog | case 0x12: /* XCR1 */ |
3290 | d8f699cb | balrog | s->xcr[0] = value & 0x7fe0; |
3291 | d8f699cb | balrog | return;
|
3292 | d8f699cb | balrog | case 0x14: /* SRGR2 */ |
3293 | d8f699cb | balrog | s->srgr[1] = value & 0xffff; |
3294 | 73560bc8 | balrog | omap_mcbsp_req_update(s); |
3295 | d8f699cb | balrog | return;
|
3296 | d8f699cb | balrog | case 0x16: /* SRGR1 */ |
3297 | d8f699cb | balrog | s->srgr[0] = value & 0xffff; |
3298 | 73560bc8 | balrog | omap_mcbsp_req_update(s); |
3299 | d8f699cb | balrog | return;
|
3300 | d8f699cb | balrog | case 0x18: /* MCR2 */ |
3301 | d8f699cb | balrog | s->mcr[1] = value & 0x03e3; |
3302 | d8f699cb | balrog | if (value & 3) /* XMCM */ |
3303 | d8f699cb | balrog | printf("%s: Tx channel selection mode enable attempt\n",
|
3304 | d8f699cb | balrog | __FUNCTION__); |
3305 | d8f699cb | balrog | return;
|
3306 | d8f699cb | balrog | case 0x1a: /* MCR1 */ |
3307 | d8f699cb | balrog | s->mcr[0] = value & 0x03e1; |
3308 | d8f699cb | balrog | if (value & 1) /* RMCM */ |
3309 | d8f699cb | balrog | printf("%s: Rx channel selection mode enable attempt\n",
|
3310 | d8f699cb | balrog | __FUNCTION__); |
3311 | d8f699cb | balrog | return;
|
3312 | d8f699cb | balrog | case 0x1c: /* RCERA */ |
3313 | d8f699cb | balrog | s->rcer[0] = value & 0xffff; |
3314 | d8f699cb | balrog | return;
|
3315 | d8f699cb | balrog | case 0x1e: /* RCERB */ |
3316 | d8f699cb | balrog | s->rcer[1] = value & 0xffff; |
3317 | d8f699cb | balrog | return;
|
3318 | d8f699cb | balrog | case 0x20: /* XCERA */ |
3319 | d8f699cb | balrog | s->xcer[0] = value & 0xffff; |
3320 | d8f699cb | balrog | return;
|
3321 | d8f699cb | balrog | case 0x22: /* XCERB */ |
3322 | d8f699cb | balrog | s->xcer[1] = value & 0xffff; |
3323 | d8f699cb | balrog | return;
|
3324 | d8f699cb | balrog | case 0x24: /* PCR0 */ |
3325 | d8f699cb | balrog | s->pcr = value & 0x7faf;
|
3326 | d8f699cb | balrog | return;
|
3327 | d8f699cb | balrog | case 0x26: /* RCERC */ |
3328 | d8f699cb | balrog | s->rcer[2] = value & 0xffff; |
3329 | d8f699cb | balrog | return;
|
3330 | d8f699cb | balrog | case 0x28: /* RCERD */ |
3331 | d8f699cb | balrog | s->rcer[3] = value & 0xffff; |
3332 | d8f699cb | balrog | return;
|
3333 | d8f699cb | balrog | case 0x2a: /* XCERC */ |
3334 | d8f699cb | balrog | s->xcer[2] = value & 0xffff; |
3335 | d8f699cb | balrog | return;
|
3336 | d8f699cb | balrog | case 0x2c: /* XCERD */ |
3337 | d8f699cb | balrog | s->xcer[3] = value & 0xffff; |
3338 | d8f699cb | balrog | return;
|
3339 | d8f699cb | balrog | case 0x2e: /* RCERE */ |
3340 | d8f699cb | balrog | s->rcer[4] = value & 0xffff; |
3341 | d8f699cb | balrog | return;
|
3342 | d8f699cb | balrog | case 0x30: /* RCERF */ |
3343 | d8f699cb | balrog | s->rcer[5] = value & 0xffff; |
3344 | d8f699cb | balrog | return;
|
3345 | d8f699cb | balrog | case 0x32: /* XCERE */ |
3346 | d8f699cb | balrog | s->xcer[4] = value & 0xffff; |
3347 | d8f699cb | balrog | return;
|
3348 | d8f699cb | balrog | case 0x34: /* XCERF */ |
3349 | d8f699cb | balrog | s->xcer[5] = value & 0xffff; |
3350 | d8f699cb | balrog | return;
|
3351 | d8f699cb | balrog | case 0x36: /* RCERG */ |
3352 | d8f699cb | balrog | s->rcer[6] = value & 0xffff; |
3353 | d8f699cb | balrog | return;
|
3354 | d8f699cb | balrog | case 0x38: /* RCERH */ |
3355 | d8f699cb | balrog | s->rcer[7] = value & 0xffff; |
3356 | d8f699cb | balrog | return;
|
3357 | d8f699cb | balrog | case 0x3a: /* XCERG */ |
3358 | d8f699cb | balrog | s->xcer[6] = value & 0xffff; |
3359 | d8f699cb | balrog | return;
|
3360 | d8f699cb | balrog | case 0x3c: /* XCERH */ |
3361 | d8f699cb | balrog | s->xcer[7] = value & 0xffff; |
3362 | d8f699cb | balrog | return;
|
3363 | d8f699cb | balrog | } |
3364 | d8f699cb | balrog | |
3365 | d8f699cb | balrog | OMAP_BAD_REG(addr); |
3366 | d8f699cb | balrog | } |
3367 | d8f699cb | balrog | |
3368 | c227f099 | Anthony Liguori | static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr, |
3369 | 73560bc8 | balrog | uint32_t value) |
3370 | 73560bc8 | balrog | { |
3371 | 73560bc8 | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3372 | 73560bc8 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3373 | 73560bc8 | balrog | |
3374 | 73560bc8 | balrog | if (offset == 0x04) { /* DXR */ |
3375 | 73560bc8 | balrog | if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ |
3376 | 73560bc8 | balrog | return;
|
3377 | 73560bc8 | balrog | if (s->tx_req > 3) { |
3378 | 73560bc8 | balrog | s->tx_req -= 4;
|
3379 | 73560bc8 | balrog | if (s->codec && s->codec->cts) {
|
3380 | 73560bc8 | balrog | s->codec->out.fifo[s->codec->out.len ++] = |
3381 | 73560bc8 | balrog | (value >> 24) & 0xff; |
3382 | 73560bc8 | balrog | s->codec->out.fifo[s->codec->out.len ++] = |
3383 | 73560bc8 | balrog | (value >> 16) & 0xff; |
3384 | 73560bc8 | balrog | s->codec->out.fifo[s->codec->out.len ++] = |
3385 | 73560bc8 | balrog | (value >> 8) & 0xff; |
3386 | 73560bc8 | balrog | s->codec->out.fifo[s->codec->out.len ++] = |
3387 | 73560bc8 | balrog | (value >> 0) & 0xff; |
3388 | 73560bc8 | balrog | } |
3389 | 73560bc8 | balrog | if (s->tx_req < 4) |
3390 | 73560bc8 | balrog | omap_mcbsp_tx_done(s); |
3391 | 73560bc8 | balrog | } else
|
3392 | 73560bc8 | balrog | printf("%s: Tx FIFO overrun\n", __FUNCTION__);
|
3393 | 73560bc8 | balrog | return;
|
3394 | 73560bc8 | balrog | } |
3395 | 73560bc8 | balrog | |
3396 | 73560bc8 | balrog | omap_badwidth_write16(opaque, addr, value); |
3397 | 73560bc8 | balrog | } |
3398 | 73560bc8 | balrog | |
3399 | a4ebbd18 | Avi Kivity | static void omap_mcbsp_write(void *opaque, target_phys_addr_t addr, |
3400 | a4ebbd18 | Avi Kivity | uint64_t value, unsigned size)
|
3401 | a4ebbd18 | Avi Kivity | { |
3402 | a4ebbd18 | Avi Kivity | switch (size) {
|
3403 | a4ebbd18 | Avi Kivity | case 2: return omap_mcbsp_writeh(opaque, addr, value); |
3404 | a4ebbd18 | Avi Kivity | case 4: return omap_mcbsp_writew(opaque, addr, value); |
3405 | a4ebbd18 | Avi Kivity | default: return omap_badwidth_write16(opaque, addr, value); |
3406 | a4ebbd18 | Avi Kivity | } |
3407 | a4ebbd18 | Avi Kivity | } |
3408 | d8f699cb | balrog | |
3409 | a4ebbd18 | Avi Kivity | static const MemoryRegionOps omap_mcbsp_ops = { |
3410 | a4ebbd18 | Avi Kivity | .read = omap_mcbsp_read, |
3411 | a4ebbd18 | Avi Kivity | .write = omap_mcbsp_write, |
3412 | a4ebbd18 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
3413 | d8f699cb | balrog | }; |
3414 | d8f699cb | balrog | |
3415 | d8f699cb | balrog | static void omap_mcbsp_reset(struct omap_mcbsp_s *s) |
3416 | d8f699cb | balrog | { |
3417 | d8f699cb | balrog | memset(&s->spcr, 0, sizeof(s->spcr)); |
3418 | d8f699cb | balrog | memset(&s->rcr, 0, sizeof(s->rcr)); |
3419 | d8f699cb | balrog | memset(&s->xcr, 0, sizeof(s->xcr)); |
3420 | d8f699cb | balrog | s->srgr[0] = 0x0001; |
3421 | d8f699cb | balrog | s->srgr[1] = 0x2000; |
3422 | d8f699cb | balrog | memset(&s->mcr, 0, sizeof(s->mcr)); |
3423 | d8f699cb | balrog | memset(&s->pcr, 0, sizeof(s->pcr)); |
3424 | d8f699cb | balrog | memset(&s->rcer, 0, sizeof(s->rcer)); |
3425 | d8f699cb | balrog | memset(&s->xcer, 0, sizeof(s->xcer)); |
3426 | d8f699cb | balrog | s->tx_req = 0;
|
3427 | 73560bc8 | balrog | s->rx_req = 0;
|
3428 | d8f699cb | balrog | s->tx_rate = 0;
|
3429 | d8f699cb | balrog | s->rx_rate = 0;
|
3430 | 73560bc8 | balrog | qemu_del_timer(s->source_timer); |
3431 | 73560bc8 | balrog | qemu_del_timer(s->sink_timer); |
3432 | d8f699cb | balrog | } |
3433 | d8f699cb | balrog | |
3434 | 0919ac78 | Peter Maydell | static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory, |
3435 | 0919ac78 | Peter Maydell | target_phys_addr_t base, |
3436 | 0919ac78 | Peter Maydell | qemu_irq txirq, qemu_irq rxirq, |
3437 | 0919ac78 | Peter Maydell | qemu_irq *dma, omap_clk clk) |
3438 | d8f699cb | balrog | { |
3439 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) |
3440 | 7267c094 | Anthony Liguori | g_malloc0(sizeof(struct omap_mcbsp_s)); |
3441 | d8f699cb | balrog | |
3442 | 0919ac78 | Peter Maydell | s->txirq = txirq; |
3443 | 0919ac78 | Peter Maydell | s->rxirq = rxirq; |
3444 | d8f699cb | balrog | s->txdrq = dma[0];
|
3445 | d8f699cb | balrog | s->rxdrq = dma[1];
|
3446 | 74475455 | Paolo Bonzini | s->sink_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_sink_tick, s); |
3447 | 74475455 | Paolo Bonzini | s->source_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_source_tick, s); |
3448 | d8f699cb | balrog | omap_mcbsp_reset(s); |
3449 | d8f699cb | balrog | |
3450 | a4ebbd18 | Avi Kivity | memory_region_init_io(&s->iomem, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800); |
3451 | a4ebbd18 | Avi Kivity | memory_region_add_subregion(system_memory, base, &s->iomem); |
3452 | d8f699cb | balrog | |
3453 | d8f699cb | balrog | return s;
|
3454 | d8f699cb | balrog | } |
3455 | d8f699cb | balrog | |
3456 | 9596ebb7 | pbrook | static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level) |
3457 | d8f699cb | balrog | { |
3458 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3459 | d8f699cb | balrog | |
3460 | 73560bc8 | balrog | if (s->rx_rate) {
|
3461 | 73560bc8 | balrog | s->rx_req = s->codec->in.len; |
3462 | 73560bc8 | balrog | omap_mcbsp_rx_newdata(s); |
3463 | 73560bc8 | balrog | } |
3464 | d8f699cb | balrog | } |
3465 | d8f699cb | balrog | |
3466 | 9596ebb7 | pbrook | static void omap_mcbsp_i2s_start(void *opaque, int line, int level) |
3467 | d8f699cb | balrog | { |
3468 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3469 | d8f699cb | balrog | |
3470 | 73560bc8 | balrog | if (s->tx_rate) {
|
3471 | 73560bc8 | balrog | s->tx_req = s->codec->out.size; |
3472 | 73560bc8 | balrog | omap_mcbsp_tx_newdata(s); |
3473 | 73560bc8 | balrog | } |
3474 | d8f699cb | balrog | } |
3475 | d8f699cb | balrog | |
3476 | bc24a225 | Paul Brook | void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave) |
3477 | d8f699cb | balrog | { |
3478 | d8f699cb | balrog | s->codec = slave; |
3479 | d8f699cb | balrog | slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0]; |
3480 | d8f699cb | balrog | slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0]; |
3481 | d8f699cb | balrog | } |
3482 | d8f699cb | balrog | |
3483 | f9d43072 | balrog | /* LED Pulse Generators */
|
3484 | f9d43072 | balrog | struct omap_lpg_s {
|
3485 | 60fe76e3 | Avi Kivity | MemoryRegion iomem; |
3486 | f9d43072 | balrog | QEMUTimer *tm; |
3487 | f9d43072 | balrog | |
3488 | f9d43072 | balrog | uint8_t control; |
3489 | f9d43072 | balrog | uint8_t power; |
3490 | f9d43072 | balrog | int64_t on; |
3491 | f9d43072 | balrog | int64_t period; |
3492 | f9d43072 | balrog | int clk;
|
3493 | f9d43072 | balrog | int cycle;
|
3494 | f9d43072 | balrog | }; |
3495 | f9d43072 | balrog | |
3496 | f9d43072 | balrog | static void omap_lpg_tick(void *opaque) |
3497 | f9d43072 | balrog | { |
3498 | f9d43072 | balrog | struct omap_lpg_s *s = opaque;
|
3499 | f9d43072 | balrog | |
3500 | f9d43072 | balrog | if (s->cycle)
|
3501 | e230d4e8 | Paolo Bonzini | qemu_mod_timer(s->tm, qemu_get_clock_ms(vm_clock) + s->period - s->on); |
3502 | f9d43072 | balrog | else
|
3503 | e230d4e8 | Paolo Bonzini | qemu_mod_timer(s->tm, qemu_get_clock_ms(vm_clock) + s->on); |
3504 | f9d43072 | balrog | |
3505 | f9d43072 | balrog | s->cycle = !s->cycle; |
3506 | f9d43072 | balrog | printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off"); |
3507 | f9d43072 | balrog | } |
3508 | f9d43072 | balrog | |
3509 | f9d43072 | balrog | static void omap_lpg_update(struct omap_lpg_s *s) |
3510 | f9d43072 | balrog | { |
3511 | f9d43072 | balrog | int64_t on, period = 1, ticks = 1000; |
3512 | f9d43072 | balrog | static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 }; |
3513 | f9d43072 | balrog | |
3514 | f9d43072 | balrog | if (~s->control & (1 << 6)) /* LPGRES */ |
3515 | f9d43072 | balrog | on = 0;
|
3516 | f9d43072 | balrog | else if (s->control & (1 << 7)) /* PERM_ON */ |
3517 | f9d43072 | balrog | on = period; |
3518 | f9d43072 | balrog | else {
|
3519 | f9d43072 | balrog | period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */ |
3520 | f9d43072 | balrog | 256 / 32); |
3521 | f9d43072 | balrog | on = (s->clk && s->power) ? muldiv64(ticks, |
3522 | f9d43072 | balrog | per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */ |
3523 | f9d43072 | balrog | } |
3524 | f9d43072 | balrog | |
3525 | f9d43072 | balrog | qemu_del_timer(s->tm); |
3526 | f9d43072 | balrog | if (on == period && s->on < s->period)
|
3527 | f9d43072 | balrog | printf("%s: LED is on\n", __FUNCTION__);
|
3528 | f9d43072 | balrog | else if (on == 0 && s->on) |
3529 | f9d43072 | balrog | printf("%s: LED is off\n", __FUNCTION__);
|
3530 | f9d43072 | balrog | else if (on && (on != s->on || period != s->period)) { |
3531 | f9d43072 | balrog | s->cycle = 0;
|
3532 | f9d43072 | balrog | s->on = on; |
3533 | f9d43072 | balrog | s->period = period; |
3534 | f9d43072 | balrog | omap_lpg_tick(s); |
3535 | f9d43072 | balrog | return;
|
3536 | f9d43072 | balrog | } |
3537 | f9d43072 | balrog | |
3538 | f9d43072 | balrog | s->on = on; |
3539 | f9d43072 | balrog | s->period = period; |
3540 | f9d43072 | balrog | } |
3541 | f9d43072 | balrog | |
3542 | f9d43072 | balrog | static void omap_lpg_reset(struct omap_lpg_s *s) |
3543 | f9d43072 | balrog | { |
3544 | f9d43072 | balrog | s->control = 0x00;
|
3545 | f9d43072 | balrog | s->power = 0x00;
|
3546 | f9d43072 | balrog | s->clk = 1;
|
3547 | f9d43072 | balrog | omap_lpg_update(s); |
3548 | f9d43072 | balrog | } |
3549 | f9d43072 | balrog | |
3550 | 60fe76e3 | Avi Kivity | static uint64_t omap_lpg_read(void *opaque, target_phys_addr_t addr, |
3551 | 60fe76e3 | Avi Kivity | unsigned size)
|
3552 | f9d43072 | balrog | { |
3553 | f9d43072 | balrog | struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; |
3554 | f9d43072 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3555 | f9d43072 | balrog | |
3556 | 60fe76e3 | Avi Kivity | if (size != 1) { |
3557 | 60fe76e3 | Avi Kivity | return omap_badwidth_read8(opaque, addr);
|
3558 | 60fe76e3 | Avi Kivity | } |
3559 | 60fe76e3 | Avi Kivity | |
3560 | f9d43072 | balrog | switch (offset) {
|
3561 | f9d43072 | balrog | case 0x00: /* LCR */ |
3562 | f9d43072 | balrog | return s->control;
|
3563 | f9d43072 | balrog | |
3564 | f9d43072 | balrog | case 0x04: /* PMR */ |
3565 | f9d43072 | balrog | return s->power;
|
3566 | f9d43072 | balrog | } |
3567 | f9d43072 | balrog | |
3568 | f9d43072 | balrog | OMAP_BAD_REG(addr); |
3569 | f9d43072 | balrog | return 0; |
3570 | f9d43072 | balrog | } |
3571 | f9d43072 | balrog | |
3572 | c227f099 | Anthony Liguori | static void omap_lpg_write(void *opaque, target_phys_addr_t addr, |
3573 | 60fe76e3 | Avi Kivity | uint64_t value, unsigned size)
|
3574 | f9d43072 | balrog | { |
3575 | f9d43072 | balrog | struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; |
3576 | f9d43072 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3577 | f9d43072 | balrog | |
3578 | 60fe76e3 | Avi Kivity | if (size != 1) { |
3579 | 60fe76e3 | Avi Kivity | return omap_badwidth_write8(opaque, addr, value);
|
3580 | 60fe76e3 | Avi Kivity | } |
3581 | 60fe76e3 | Avi Kivity | |
3582 | f9d43072 | balrog | switch (offset) {
|
3583 | f9d43072 | balrog | case 0x00: /* LCR */ |
3584 | f9d43072 | balrog | if (~value & (1 << 6)) /* LPGRES */ |
3585 | f9d43072 | balrog | omap_lpg_reset(s); |
3586 | f9d43072 | balrog | s->control = value & 0xff;
|
3587 | f9d43072 | balrog | omap_lpg_update(s); |
3588 | f9d43072 | balrog | return;
|
3589 | f9d43072 | balrog | |
3590 | f9d43072 | balrog | case 0x04: /* PMR */ |
3591 | f9d43072 | balrog | s->power = value & 0x01;
|
3592 | f9d43072 | balrog | omap_lpg_update(s); |
3593 | f9d43072 | balrog | return;
|
3594 | f9d43072 | balrog | |
3595 | f9d43072 | balrog | default:
|
3596 | f9d43072 | balrog | OMAP_BAD_REG(addr); |
3597 | f9d43072 | balrog | return;
|
3598 | f9d43072 | balrog | } |
3599 | f9d43072 | balrog | } |
3600 | f9d43072 | balrog | |
3601 | 60fe76e3 | Avi Kivity | static const MemoryRegionOps omap_lpg_ops = { |
3602 | 60fe76e3 | Avi Kivity | .read = omap_lpg_read, |
3603 | 60fe76e3 | Avi Kivity | .write = omap_lpg_write, |
3604 | 60fe76e3 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
3605 | f9d43072 | balrog | }; |
3606 | f9d43072 | balrog | |
3607 | f9d43072 | balrog | static void omap_lpg_clk_update(void *opaque, int line, int on) |
3608 | f9d43072 | balrog | { |
3609 | f9d43072 | balrog | struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; |
3610 | f9d43072 | balrog | |
3611 | f9d43072 | balrog | s->clk = on; |
3612 | f9d43072 | balrog | omap_lpg_update(s); |
3613 | f9d43072 | balrog | } |
3614 | f9d43072 | balrog | |
3615 | 60fe76e3 | Avi Kivity | static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory, |
3616 | 60fe76e3 | Avi Kivity | target_phys_addr_t base, omap_clk clk) |
3617 | f9d43072 | balrog | { |
3618 | f9d43072 | balrog | struct omap_lpg_s *s = (struct omap_lpg_s *) |
3619 | 7267c094 | Anthony Liguori | g_malloc0(sizeof(struct omap_lpg_s)); |
3620 | f9d43072 | balrog | |
3621 | e230d4e8 | Paolo Bonzini | s->tm = qemu_new_timer_ms(vm_clock, omap_lpg_tick, s); |
3622 | f9d43072 | balrog | |
3623 | f9d43072 | balrog | omap_lpg_reset(s); |
3624 | f9d43072 | balrog | |
3625 | 60fe76e3 | Avi Kivity | memory_region_init_io(&s->iomem, &omap_lpg_ops, s, "omap-lpg", 0x800); |
3626 | 60fe76e3 | Avi Kivity | memory_region_add_subregion(system_memory, base, &s->iomem); |
3627 | f9d43072 | balrog | |
3628 | f9d43072 | balrog | omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]); |
3629 | f9d43072 | balrog | |
3630 | f9d43072 | balrog | return s;
|
3631 | f9d43072 | balrog | } |
3632 | f9d43072 | balrog | |
3633 | f9d43072 | balrog | /* MPUI Peripheral Bridge configuration */
|
3634 | 60fe76e3 | Avi Kivity | static uint64_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr, |
3635 | 60fe76e3 | Avi Kivity | unsigned size)
|
3636 | f9d43072 | balrog | { |
3637 | 60fe76e3 | Avi Kivity | if (size != 2) { |
3638 | 60fe76e3 | Avi Kivity | return omap_badwidth_read16(opaque, addr);
|
3639 | 60fe76e3 | Avi Kivity | } |
3640 | 60fe76e3 | Avi Kivity | |
3641 | f9d43072 | balrog | if (addr == OMAP_MPUI_BASE) /* CMR */ |
3642 | f9d43072 | balrog | return 0xfe4d; |
3643 | f9d43072 | balrog | |
3644 | f9d43072 | balrog | OMAP_BAD_REG(addr); |
3645 | f9d43072 | balrog | return 0; |
3646 | f9d43072 | balrog | } |
3647 | f9d43072 | balrog | |
3648 | 60fe76e3 | Avi Kivity | static void omap_mpui_io_write(void *opaque, target_phys_addr_t addr, |
3649 | 60fe76e3 | Avi Kivity | uint64_t value, unsigned size)
|
3650 | 60fe76e3 | Avi Kivity | { |
3651 | 60fe76e3 | Avi Kivity | /* FIXME: infinite loop */
|
3652 | 60fe76e3 | Avi Kivity | omap_badwidth_write16(opaque, addr, value); |
3653 | 60fe76e3 | Avi Kivity | } |
3654 | f9d43072 | balrog | |
3655 | 60fe76e3 | Avi Kivity | static const MemoryRegionOps omap_mpui_io_ops = { |
3656 | 60fe76e3 | Avi Kivity | .read = omap_mpui_io_read, |
3657 | 60fe76e3 | Avi Kivity | .write = omap_mpui_io_write, |
3658 | 60fe76e3 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
3659 | f9d43072 | balrog | }; |
3660 | f9d43072 | balrog | |
3661 | 60fe76e3 | Avi Kivity | static void omap_setup_mpui_io(MemoryRegion *system_memory, |
3662 | 60fe76e3 | Avi Kivity | struct omap_mpu_state_s *mpu)
|
3663 | f9d43072 | balrog | { |
3664 | 60fe76e3 | Avi Kivity | memory_region_init_io(&mpu->mpui_io_iomem, &omap_mpui_io_ops, mpu, |
3665 | 60fe76e3 | Avi Kivity | "omap-mpui-io", 0x7fff); |
3666 | 60fe76e3 | Avi Kivity | memory_region_add_subregion(system_memory, OMAP_MPUI_BASE, |
3667 | 60fe76e3 | Avi Kivity | &mpu->mpui_io_iomem); |
3668 | f9d43072 | balrog | } |
3669 | f9d43072 | balrog | |
3670 | c3d2689d | balrog | /* General chip reset */
|
3671 | 827df9f3 | balrog | static void omap1_mpu_reset(void *opaque) |
3672 | c3d2689d | balrog | { |
3673 | c3d2689d | balrog | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
3674 | c3d2689d | balrog | |
3675 | c3d2689d | balrog | omap_dma_reset(mpu->dma); |
3676 | c3d2689d | balrog | omap_mpu_timer_reset(mpu->timer[0]);
|
3677 | c3d2689d | balrog | omap_mpu_timer_reset(mpu->timer[1]);
|
3678 | c3d2689d | balrog | omap_mpu_timer_reset(mpu->timer[2]);
|
3679 | c3d2689d | balrog | omap_wd_timer_reset(mpu->wdt); |
3680 | c3d2689d | balrog | omap_os_timer_reset(mpu->os_timer); |
3681 | c3d2689d | balrog | omap_lcdc_reset(mpu->lcd); |
3682 | c3d2689d | balrog | omap_ulpd_pm_reset(mpu); |
3683 | c3d2689d | balrog | omap_pin_cfg_reset(mpu); |
3684 | c3d2689d | balrog | omap_mpui_reset(mpu); |
3685 | c3d2689d | balrog | omap_tipb_bridge_reset(mpu->private_tipb); |
3686 | c3d2689d | balrog | omap_tipb_bridge_reset(mpu->public_tipb); |
3687 | b9f7bc40 | Juha Riihimäki | omap_dpll_reset(mpu->dpll[0]);
|
3688 | b9f7bc40 | Juha Riihimäki | omap_dpll_reset(mpu->dpll[1]);
|
3689 | b9f7bc40 | Juha Riihimäki | omap_dpll_reset(mpu->dpll[2]);
|
3690 | d951f6ff | balrog | omap_uart_reset(mpu->uart[0]);
|
3691 | d951f6ff | balrog | omap_uart_reset(mpu->uart[1]);
|
3692 | d951f6ff | balrog | omap_uart_reset(mpu->uart[2]);
|
3693 | b30bb3a2 | balrog | omap_mmc_reset(mpu->mmc); |
3694 | fe71e81a | balrog | omap_mpuio_reset(mpu->mpuio); |
3695 | d951f6ff | balrog | omap_uwire_reset(mpu->microwire); |
3696 | 8717d88a | Juha Riihimäki | omap_pwl_reset(mpu->pwl); |
3697 | 03759534 | Juha Riihimäki | omap_pwt_reset(mpu->pwt); |
3698 | 5c1c390f | balrog | omap_rtc_reset(mpu->rtc); |
3699 | d8f699cb | balrog | omap_mcbsp_reset(mpu->mcbsp1); |
3700 | d8f699cb | balrog | omap_mcbsp_reset(mpu->mcbsp2); |
3701 | d8f699cb | balrog | omap_mcbsp_reset(mpu->mcbsp3); |
3702 | f9d43072 | balrog | omap_lpg_reset(mpu->led[0]);
|
3703 | f9d43072 | balrog | omap_lpg_reset(mpu->led[1]);
|
3704 | 8ef6367e | balrog | omap_clkm_reset(mpu); |
3705 | 5f4ef08b | Andreas Färber | cpu_reset(CPU(mpu->cpu)); |
3706 | c3d2689d | balrog | } |
3707 | c3d2689d | balrog | |
3708 | cf965d24 | balrog | static const struct omap_map_s { |
3709 | c227f099 | Anthony Liguori | target_phys_addr_t phys_dsp; |
3710 | c227f099 | Anthony Liguori | target_phys_addr_t phys_mpu; |
3711 | cf965d24 | balrog | uint32_t size; |
3712 | cf965d24 | balrog | const char *name; |
3713 | cf965d24 | balrog | } omap15xx_dsp_mm[] = { |
3714 | cf965d24 | balrog | /* Strobe 0 */
|
3715 | cf965d24 | balrog | { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */ |
3716 | cf965d24 | balrog | { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */ |
3717 | cf965d24 | balrog | { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */ |
3718 | cf965d24 | balrog | { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */ |
3719 | cf965d24 | balrog | { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */ |
3720 | cf965d24 | balrog | { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */ |
3721 | cf965d24 | balrog | { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */ |
3722 | cf965d24 | balrog | { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */ |
3723 | cf965d24 | balrog | { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */ |
3724 | cf965d24 | balrog | { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */ |
3725 | cf965d24 | balrog | { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */ |
3726 | cf965d24 | balrog | { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */ |
3727 | cf965d24 | balrog | { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */ |
3728 | cf965d24 | balrog | { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */ |
3729 | cf965d24 | balrog | { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */ |
3730 | cf965d24 | balrog | { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */ |
3731 | cf965d24 | balrog | { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */ |
3732 | cf965d24 | balrog | /* Strobe 1 */
|
3733 | cf965d24 | balrog | { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */ |
3734 | cf965d24 | balrog | |
3735 | cf965d24 | balrog | { 0 }
|
3736 | cf965d24 | balrog | }; |
3737 | cf965d24 | balrog | |
3738 | 763b946c | Avi Kivity | static void omap_setup_dsp_mapping(MemoryRegion *system_memory, |
3739 | 763b946c | Avi Kivity | const struct omap_map_s *map) |
3740 | cf965d24 | balrog | { |
3741 | 763b946c | Avi Kivity | MemoryRegion *io; |
3742 | cf965d24 | balrog | |
3743 | cf965d24 | balrog | for (; map->phys_dsp; map ++) {
|
3744 | 763b946c | Avi Kivity | io = g_new(MemoryRegion, 1);
|
3745 | 763b946c | Avi Kivity | memory_region_init_alias(io, map->name, |
3746 | 763b946c | Avi Kivity | system_memory, map->phys_mpu, map->size); |
3747 | 763b946c | Avi Kivity | memory_region_add_subregion(system_memory, map->phys_dsp, io); |
3748 | cf965d24 | balrog | } |
3749 | cf965d24 | balrog | } |
3750 | cf965d24 | balrog | |
3751 | 827df9f3 | balrog | void omap_mpu_wakeup(void *opaque, int irq, int req) |
3752 | c3d2689d | balrog | { |
3753 | c3d2689d | balrog | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
3754 | c3d2689d | balrog | |
3755 | 5f4ef08b | Andreas Färber | if (mpu->cpu->env.halted) {
|
3756 | 5f4ef08b | Andreas Färber | cpu_interrupt(&mpu->cpu->env, CPU_INTERRUPT_EXITTB); |
3757 | 5f4ef08b | Andreas Färber | } |
3758 | c3d2689d | balrog | } |
3759 | c3d2689d | balrog | |
3760 | 827df9f3 | balrog | static const struct dma_irq_map omap1_dma_irq_map[] = { |
3761 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH0_6 },
|
3762 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH1_7 },
|
3763 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH2_8 },
|
3764 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH3 },
|
3765 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH4 },
|
3766 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH5 },
|
3767 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH6 },
|
3768 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH7 },
|
3769 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH8 },
|
3770 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH9 },
|
3771 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH10 },
|
3772 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH11 },
|
3773 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH12 },
|
3774 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH13 },
|
3775 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH14 },
|
3776 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH15 }
|
3777 | 089b7c0a | balrog | }; |
3778 | 089b7c0a | balrog | |
3779 | b4e3104b | balrog | /* DMA ports for OMAP1 */
|
3780 | b4e3104b | balrog | static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, |
3781 | c227f099 | Anthony Liguori | target_phys_addr_t addr) |
3782 | b4e3104b | balrog | { |
3783 | 45416789 | Blue Swirl | return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr);
|
3784 | b4e3104b | balrog | } |
3785 | b4e3104b | balrog | |
3786 | b4e3104b | balrog | static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, |
3787 | c227f099 | Anthony Liguori | target_phys_addr_t addr) |
3788 | b4e3104b | balrog | { |
3789 | 45416789 | Blue Swirl | return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE,
|
3790 | 45416789 | Blue Swirl | addr); |
3791 | b4e3104b | balrog | } |
3792 | b4e3104b | balrog | |
3793 | b4e3104b | balrog | static int omap_validate_imif_addr(struct omap_mpu_state_s *s, |
3794 | c227f099 | Anthony Liguori | target_phys_addr_t addr) |
3795 | b4e3104b | balrog | { |
3796 | 45416789 | Blue Swirl | return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr);
|
3797 | b4e3104b | balrog | } |
3798 | b4e3104b | balrog | |
3799 | b4e3104b | balrog | static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, |
3800 | c227f099 | Anthony Liguori | target_phys_addr_t addr) |
3801 | b4e3104b | balrog | { |
3802 | 45416789 | Blue Swirl | return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr); |
3803 | b4e3104b | balrog | } |
3804 | b4e3104b | balrog | |
3805 | b4e3104b | balrog | static int omap_validate_local_addr(struct omap_mpu_state_s *s, |
3806 | c227f099 | Anthony Liguori | target_phys_addr_t addr) |
3807 | b4e3104b | balrog | { |
3808 | 45416789 | Blue Swirl | return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr); |
3809 | b4e3104b | balrog | } |
3810 | b4e3104b | balrog | |
3811 | b4e3104b | balrog | static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, |
3812 | c227f099 | Anthony Liguori | target_phys_addr_t addr) |
3813 | b4e3104b | balrog | { |
3814 | 45416789 | Blue Swirl | return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr); |
3815 | b4e3104b | balrog | } |
3816 | b4e3104b | balrog | |
3817 | 4b3fedf3 | Avi Kivity | struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
|
3818 | 4b3fedf3 | Avi Kivity | unsigned long sdram_size, |
3819 | 3023f332 | aliguori | const char *core) |
3820 | c3d2689d | balrog | { |
3821 | 089b7c0a | balrog | int i;
|
3822 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) |
3823 | 7267c094 | Anthony Liguori | g_malloc0(sizeof(struct omap_mpu_state_s)); |
3824 | 106627d0 | balrog | qemu_irq *cpu_irq; |
3825 | 089b7c0a | balrog | qemu_irq dma_irqs[6];
|
3826 | 751c6a17 | Gerd Hoffmann | DriveInfo *dinfo; |
3827 | 0919ac78 | Peter Maydell | SysBusDevice *busdev; |
3828 | 106627d0 | balrog | |
3829 | aaed909a | bellard | if (!core)
|
3830 | aaed909a | bellard | core = "ti925t";
|
3831 | c3d2689d | balrog | |
3832 | c3d2689d | balrog | /* Core */
|
3833 | c3d2689d | balrog | s->mpu_model = omap310; |
3834 | 5f4ef08b | Andreas Färber | s->cpu = cpu_arm_init(core); |
3835 | 5f4ef08b | Andreas Färber | if (s->cpu == NULL) { |
3836 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
|
3837 | aaed909a | bellard | exit(1);
|
3838 | aaed909a | bellard | } |
3839 | c3d2689d | balrog | s->sdram_size = sdram_size; |
3840 | c3d2689d | balrog | s->sram_size = OMAP15XX_SRAM_SIZE; |
3841 | c3d2689d | balrog | |
3842 | fe71e81a | balrog | s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0]; |
3843 | fe71e81a | balrog | |
3844 | c3d2689d | balrog | /* Clocks */
|
3845 | c3d2689d | balrog | omap_clk_init(s); |
3846 | c3d2689d | balrog | |
3847 | c3d2689d | balrog | /* Memory-mapped stuff */
|
3848 | c5705a77 | Avi Kivity | memory_region_init_ram(&s->emiff_ram, "omap1.dram", s->sdram_size);
|
3849 | c5705a77 | Avi Kivity | vmstate_register_ram_global(&s->emiff_ram); |
3850 | 2654c962 | Avi Kivity | memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram); |
3851 | c5705a77 | Avi Kivity | memory_region_init_ram(&s->imif_ram, "omap1.sram", s->sram_size);
|
3852 | c5705a77 | Avi Kivity | vmstate_register_ram_global(&s->imif_ram); |
3853 | 2654c962 | Avi Kivity | memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram); |
3854 | c3d2689d | balrog | |
3855 | e7aa0ae0 | Avi Kivity | omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s); |
3856 | c3d2689d | balrog | |
3857 | 4bd74661 | Andreas Färber | cpu_irq = arm_pic_init_cpu(s->cpu); |
3858 | 0919ac78 | Peter Maydell | s->ih[0] = qdev_create(NULL, "omap-intc"); |
3859 | 0919ac78 | Peter Maydell | qdev_prop_set_uint32(s->ih[0], "size", 0x100); |
3860 | 0919ac78 | Peter Maydell | qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck")); |
3861 | 0919ac78 | Peter Maydell | qdev_init_nofail(s->ih[0]);
|
3862 | 0919ac78 | Peter Maydell | busdev = sysbus_from_qdev(s->ih[0]);
|
3863 | 0919ac78 | Peter Maydell | sysbus_connect_irq(busdev, 0, cpu_irq[ARM_PIC_CPU_IRQ]);
|
3864 | 0919ac78 | Peter Maydell | sysbus_connect_irq(busdev, 1, cpu_irq[ARM_PIC_CPU_FIQ]);
|
3865 | 0919ac78 | Peter Maydell | sysbus_mmio_map(busdev, 0, 0xfffecb00); |
3866 | 0919ac78 | Peter Maydell | s->ih[1] = qdev_create(NULL, "omap-intc"); |
3867 | 0919ac78 | Peter Maydell | qdev_prop_set_uint32(s->ih[1], "size", 0x800); |
3868 | 0919ac78 | Peter Maydell | qdev_prop_set_ptr(s->ih[1], "clk", omap_findclk(s, "arminth_ck")); |
3869 | 0919ac78 | Peter Maydell | qdev_init_nofail(s->ih[1]);
|
3870 | 0919ac78 | Peter Maydell | busdev = sysbus_from_qdev(s->ih[1]);
|
3871 | 0919ac78 | Peter Maydell | sysbus_connect_irq(busdev, 0,
|
3872 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ));
|
3873 | 0919ac78 | Peter Maydell | /* The second interrupt controller's FIQ output is not wired up */
|
3874 | 0919ac78 | Peter Maydell | sysbus_mmio_map(busdev, 0, 0xfffe0000); |
3875 | 0919ac78 | Peter Maydell | |
3876 | 0919ac78 | Peter Maydell | for (i = 0; i < 6; i++) { |
3877 | 0919ac78 | Peter Maydell | dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih], |
3878 | 0919ac78 | Peter Maydell | omap1_dma_irq_map[i].intr); |
3879 | 0919ac78 | Peter Maydell | } |
3880 | 7405165e | Avi Kivity | s->dma = omap_dma_init(0xfffed800, dma_irqs, system_memory,
|
3881 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD),
|
3882 | 089b7c0a | balrog | s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
|
3883 | 089b7c0a | balrog | |
3884 | c3d2689d | balrog | s->port[emiff ].addr_valid = omap_validate_emiff_addr; |
3885 | c3d2689d | balrog | s->port[emifs ].addr_valid = omap_validate_emifs_addr; |
3886 | c3d2689d | balrog | s->port[imif ].addr_valid = omap_validate_imif_addr; |
3887 | c3d2689d | balrog | s->port[tipb ].addr_valid = omap_validate_tipb_addr; |
3888 | c3d2689d | balrog | s->port[local ].addr_valid = omap_validate_local_addr; |
3889 | c3d2689d | balrog | s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; |
3890 | c3d2689d | balrog | |
3891 | afbb5194 | balrog | /* Register SDRAM and SRAM DMA ports for fast transfers. */
|
3892 | 2654c962 | Avi Kivity | soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->emiff_ram), |
3893 | 2654c962 | Avi Kivity | OMAP_EMIFF_BASE, s->sdram_size); |
3894 | 2654c962 | Avi Kivity | soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram), |
3895 | 90aeba9d | Avi Kivity | OMAP_IMIF_BASE, s->sram_size); |
3896 | afbb5194 | balrog | |
3897 | 4b3fedf3 | Avi Kivity | s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500, |
3898 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1),
|
3899 | c3d2689d | balrog | omap_findclk(s, "mputim_ck"));
|
3900 | 4b3fedf3 | Avi Kivity | s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600, |
3901 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2),
|
3902 | c3d2689d | balrog | omap_findclk(s, "mputim_ck"));
|
3903 | 4b3fedf3 | Avi Kivity | s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700, |
3904 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3),
|
3905 | c3d2689d | balrog | omap_findclk(s, "mputim_ck"));
|
3906 | c3d2689d | balrog | |
3907 | 4b3fedf3 | Avi Kivity | s->wdt = omap_wd_timer_init(system_memory, 0xfffec800,
|
3908 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER),
|
3909 | c3d2689d | balrog | omap_findclk(s, "armwdt_ck"));
|
3910 | c3d2689d | balrog | |
3911 | 4b3fedf3 | Avi Kivity | s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000,
|
3912 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER),
|
3913 | c3d2689d | balrog | omap_findclk(s, "clk32-kHz"));
|
3914 | c3d2689d | balrog | |
3915 | 30af1ec7 | Benoît Canet | s->lcd = omap_lcdc_init(system_memory, 0xfffec000,
|
3916 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL),
|
3917 | 0919ac78 | Peter Maydell | omap_dma_get_lcdch(s->dma), |
3918 | 0919ac78 | Peter Maydell | omap_findclk(s, "lcd_ck"));
|
3919 | c3d2689d | balrog | |
3920 | 4b3fedf3 | Avi Kivity | omap_ulpd_pm_init(system_memory, 0xfffe0800, s);
|
3921 | 4b3fedf3 | Avi Kivity | omap_pin_cfg_init(system_memory, 0xfffe1000, s);
|
3922 | 4b3fedf3 | Avi Kivity | omap_id_init(system_memory, s); |
3923 | c3d2689d | balrog | |
3924 | 4b3fedf3 | Avi Kivity | omap_mpui_init(system_memory, 0xfffec900, s);
|
3925 | c3d2689d | balrog | |
3926 | 4b3fedf3 | Avi Kivity | s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00,
|
3927 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV),
|
3928 | c3d2689d | balrog | omap_findclk(s, "tipb_ck"));
|
3929 | 4b3fedf3 | Avi Kivity | s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300,
|
3930 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB),
|
3931 | c3d2689d | balrog | omap_findclk(s, "tipb_ck"));
|
3932 | c3d2689d | balrog | |
3933 | e7aa0ae0 | Avi Kivity | omap_tcmi_init(system_memory, 0xfffecc00, s);
|
3934 | c3d2689d | balrog | |
3935 | 0919ac78 | Peter Maydell | s->uart[0] = omap_uart_init(0xfffb0000, |
3936 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1),
|
3937 | c3d2689d | balrog | omap_findclk(s, "uart1_ck"),
|
3938 | 827df9f3 | balrog | omap_findclk(s, "uart1_ck"),
|
3939 | 827df9f3 | balrog | s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX], |
3940 | 6a8aabd3 | Stefan Weil | "uart1",
|
3941 | c3d2689d | balrog | serial_hds[0]);
|
3942 | 0919ac78 | Peter Maydell | s->uart[1] = omap_uart_init(0xfffb0800, |
3943 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2),
|
3944 | c3d2689d | balrog | omap_findclk(s, "uart2_ck"),
|
3945 | 827df9f3 | balrog | omap_findclk(s, "uart2_ck"),
|
3946 | 827df9f3 | balrog | s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX], |
3947 | 6a8aabd3 | Stefan Weil | "uart2",
|
3948 | b9d38e95 | Blue Swirl | serial_hds[0] ? serial_hds[1] : NULL); |
3949 | 0919ac78 | Peter Maydell | s->uart[2] = omap_uart_init(0xfffb9800, |
3950 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3),
|
3951 | c3d2689d | balrog | omap_findclk(s, "uart3_ck"),
|
3952 | 827df9f3 | balrog | omap_findclk(s, "uart3_ck"),
|
3953 | 827df9f3 | balrog | s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX], |
3954 | 6a8aabd3 | Stefan Weil | "uart3",
|
3955 | b9d38e95 | Blue Swirl | serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL); |
3956 | c3d2689d | balrog | |
3957 | b9f7bc40 | Juha Riihimäki | s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00, |
3958 | b9f7bc40 | Juha Riihimäki | omap_findclk(s, "dpll1"));
|
3959 | b9f7bc40 | Juha Riihimäki | s->dpll[1] = omap_dpll_init(system_memory, 0xfffed000, |
3960 | b9f7bc40 | Juha Riihimäki | omap_findclk(s, "dpll2"));
|
3961 | b9f7bc40 | Juha Riihimäki | s->dpll[2] = omap_dpll_init(system_memory, 0xfffed100, |
3962 | b9f7bc40 | Juha Riihimäki | omap_findclk(s, "dpll3"));
|
3963 | c3d2689d | balrog | |
3964 | 751c6a17 | Gerd Hoffmann | dinfo = drive_get(IF_SD, 0, 0); |
3965 | 751c6a17 | Gerd Hoffmann | if (!dinfo) {
|
3966 | e4bcb14c | ths | fprintf(stderr, "qemu: missing SecureDigital device\n");
|
3967 | e4bcb14c | ths | exit(1);
|
3968 | e4bcb14c | ths | } |
3969 | c304fed7 | Avi Kivity | s->mmc = omap_mmc_init(0xfffb7800, system_memory, dinfo->bdrv,
|
3970 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN),
|
3971 | 0919ac78 | Peter Maydell | &s->drq[OMAP_DMA_MMC_TX], |
3972 | 9d413d1d | balrog | omap_findclk(s, "mmc_ck"));
|
3973 | b30bb3a2 | balrog | |
3974 | e7aa0ae0 | Avi Kivity | s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000,
|
3975 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD),
|
3976 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO),
|
3977 | 0919ac78 | Peter Maydell | s->wakeup, omap_findclk(s, "clk32-kHz"));
|
3978 | fe71e81a | balrog | |
3979 | 77831c20 | Juha Riihimäki | s->gpio = qdev_create(NULL, "omap-gpio"); |
3980 | 77831c20 | Juha Riihimäki | qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
|
3981 | bdbc1b3c | Peter Maydell | qdev_prop_set_ptr(s->gpio, "clk", omap_findclk(s, "arm_gpio_ck")); |
3982 | 77831c20 | Juha Riihimäki | qdev_init_nofail(s->gpio); |
3983 | 77831c20 | Juha Riihimäki | sysbus_connect_irq(sysbus_from_qdev(s->gpio), 0,
|
3984 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1));
|
3985 | 77831c20 | Juha Riihimäki | sysbus_mmio_map(sysbus_from_qdev(s->gpio), 0, 0xfffce000); |
3986 | 64330148 | balrog | |
3987 | 0919ac78 | Peter Maydell | s->microwire = omap_uwire_init(system_memory, 0xfffb3000,
|
3988 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX),
|
3989 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX),
|
3990 | d951f6ff | balrog | s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
|
3991 | d951f6ff | balrog | |
3992 | 8717d88a | Juha Riihimäki | s->pwl = omap_pwl_init(system_memory, 0xfffb5800,
|
3993 | 8717d88a | Juha Riihimäki | omap_findclk(s, "armxor_ck"));
|
3994 | 03759534 | Juha Riihimäki | s->pwt = omap_pwt_init(system_memory, 0xfffb6000,
|
3995 | 03759534 | Juha Riihimäki | omap_findclk(s, "armxor_ck"));
|
3996 | 66450b15 | balrog | |
3997 | 54e17933 | Juha Riihimäki | s->i2c[0] = qdev_create(NULL, "omap_i2c"); |
3998 | 54e17933 | Juha Riihimäki | qdev_prop_set_uint8(s->i2c[0], "revision", 0x11); |
3999 | 54e17933 | Juha Riihimäki | qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "mpuper_ck")); |
4000 | 54e17933 | Juha Riihimäki | qdev_init_nofail(s->i2c[0]);
|
4001 | 54e17933 | Juha Riihimäki | busdev = sysbus_from_qdev(s->i2c[0]);
|
4002 | 54e17933 | Juha Riihimäki | sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C)); |
4003 | 54e17933 | Juha Riihimäki | sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]);
|
4004 | 54e17933 | Juha Riihimäki | sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]);
|
4005 | 54e17933 | Juha Riihimäki | sysbus_mmio_map(busdev, 0, 0xfffb3800); |
4006 | 4a2c8ac2 | balrog | |
4007 | a4ebbd18 | Avi Kivity | s->rtc = omap_rtc_init(system_memory, 0xfffb4800,
|
4008 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER),
|
4009 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM),
|
4010 | 5c1c390f | balrog | omap_findclk(s, "clk32-kHz"));
|
4011 | 02645926 | balrog | |
4012 | 0919ac78 | Peter Maydell | s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800,
|
4013 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX),
|
4014 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX),
|
4015 | d8f699cb | balrog | &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
|
4016 | 0919ac78 | Peter Maydell | s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000,
|
4017 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[0],
|
4018 | 0919ac78 | Peter Maydell | OMAP_INT_310_McBSP2_TX), |
4019 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[0],
|
4020 | 0919ac78 | Peter Maydell | OMAP_INT_310_McBSP2_RX), |
4021 | d8f699cb | balrog | &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
|
4022 | 0919ac78 | Peter Maydell | s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000,
|
4023 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX),
|
4024 | 0919ac78 | Peter Maydell | qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX),
|
4025 | d8f699cb | balrog | &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
|
4026 | d8f699cb | balrog | |
4027 | 60fe76e3 | Avi Kivity | s->led[0] = omap_lpg_init(system_memory,
|
4028 | 60fe76e3 | Avi Kivity | 0xfffbd000, omap_findclk(s, "clk32-kHz")); |
4029 | 60fe76e3 | Avi Kivity | s->led[1] = omap_lpg_init(system_memory,
|
4030 | 60fe76e3 | Avi Kivity | 0xfffbd800, omap_findclk(s, "clk32-kHz")); |
4031 | f9d43072 | balrog | |
4032 | 02645926 | balrog | /* Register mappings not currenlty implemented:
|
4033 | 02645926 | balrog | * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
|
4034 | 02645926 | balrog | * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
|
4035 | 02645926 | balrog | * USB W2FC fffb4000 - fffb47ff
|
4036 | 02645926 | balrog | * Camera Interface fffb6800 - fffb6fff
|
4037 | 02645926 | balrog | * USB Host fffba000 - fffba7ff
|
4038 | 02645926 | balrog | * FAC fffba800 - fffbafff
|
4039 | 02645926 | balrog | * HDQ/1-Wire fffbc000 - fffbc7ff
|
4040 | b854bc19 | balrog | * TIPB switches fffbc800 - fffbcfff
|
4041 | 02645926 | balrog | * Mailbox fffcf000 - fffcf7ff
|
4042 | 02645926 | balrog | * Local bus IF fffec100 - fffec1ff
|
4043 | 02645926 | balrog | * Local bus MMU fffec200 - fffec2ff
|
4044 | 02645926 | balrog | * DSP MMU fffed200 - fffed2ff
|
4045 | 02645926 | balrog | */
|
4046 | 02645926 | balrog | |
4047 | 763b946c | Avi Kivity | omap_setup_dsp_mapping(system_memory, omap15xx_dsp_mm); |
4048 | 60fe76e3 | Avi Kivity | omap_setup_mpui_io(system_memory, s); |
4049 | cf965d24 | balrog | |
4050 | a08d4367 | Jan Kiszka | qemu_register_reset(omap1_mpu_reset, s); |
4051 | c3d2689d | balrog | |
4052 | c3d2689d | balrog | return s;
|
4053 | c3d2689d | balrog | } |