root / hw / puv3_pm.c @ c9159fe9
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1 | f716c197 | Guan Xuetao | /*
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2 | f716c197 | Guan Xuetao | * Power Management device simulation in PKUnity SoC
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3 | f716c197 | Guan Xuetao | *
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4 | f716c197 | Guan Xuetao | * Copyright (C) 2010-2012 Guan Xuetao
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5 | f716c197 | Guan Xuetao | *
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6 | f716c197 | Guan Xuetao | * This program is free software; you can redistribute it and/or modify
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7 | f716c197 | Guan Xuetao | * it under the terms of the GNU General Public License version 2 as
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8 | f716c197 | Guan Xuetao | * published by the Free Software Foundation, or any later version.
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9 | f716c197 | Guan Xuetao | * See the COPYING file in the top-level directory.
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10 | f716c197 | Guan Xuetao | */
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11 | f716c197 | Guan Xuetao | #include "hw.h" |
12 | f716c197 | Guan Xuetao | #include "sysbus.h" |
13 | f716c197 | Guan Xuetao | |
14 | f716c197 | Guan Xuetao | #undef DEBUG_PUV3
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15 | f716c197 | Guan Xuetao | #include "puv3.h" |
16 | f716c197 | Guan Xuetao | |
17 | f716c197 | Guan Xuetao | typedef struct { |
18 | f716c197 | Guan Xuetao | SysBusDevice busdev; |
19 | f716c197 | Guan Xuetao | MemoryRegion iomem; |
20 | f716c197 | Guan Xuetao | |
21 | f716c197 | Guan Xuetao | uint32_t reg_PMCR; |
22 | f716c197 | Guan Xuetao | uint32_t reg_PCGR; |
23 | f716c197 | Guan Xuetao | uint32_t reg_PLL_SYS_CFG; |
24 | f716c197 | Guan Xuetao | uint32_t reg_PLL_DDR_CFG; |
25 | f716c197 | Guan Xuetao | uint32_t reg_PLL_VGA_CFG; |
26 | f716c197 | Guan Xuetao | uint32_t reg_DIVCFG; |
27 | f716c197 | Guan Xuetao | } PUV3PMState; |
28 | f716c197 | Guan Xuetao | |
29 | f716c197 | Guan Xuetao | static uint64_t puv3_pm_read(void *opaque, target_phys_addr_t offset, |
30 | f716c197 | Guan Xuetao | unsigned size)
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31 | f716c197 | Guan Xuetao | { |
32 | f716c197 | Guan Xuetao | PUV3PMState *s = opaque; |
33 | f716c197 | Guan Xuetao | uint32_t ret = 0;
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34 | f716c197 | Guan Xuetao | |
35 | f716c197 | Guan Xuetao | switch (offset) {
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36 | f716c197 | Guan Xuetao | case 0x14: |
37 | f716c197 | Guan Xuetao | ret = s->reg_PCGR; |
38 | f716c197 | Guan Xuetao | break;
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39 | f716c197 | Guan Xuetao | case 0x18: |
40 | f716c197 | Guan Xuetao | ret = s->reg_PLL_SYS_CFG; |
41 | f716c197 | Guan Xuetao | break;
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42 | f716c197 | Guan Xuetao | case 0x1c: |
43 | f716c197 | Guan Xuetao | ret = s->reg_PLL_DDR_CFG; |
44 | f716c197 | Guan Xuetao | break;
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45 | f716c197 | Guan Xuetao | case 0x20: |
46 | f716c197 | Guan Xuetao | ret = s->reg_PLL_VGA_CFG; |
47 | f716c197 | Guan Xuetao | break;
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48 | f716c197 | Guan Xuetao | case 0x24: |
49 | f716c197 | Guan Xuetao | ret = s->reg_DIVCFG; |
50 | f716c197 | Guan Xuetao | break;
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51 | f716c197 | Guan Xuetao | case 0x28: /* PLL SYS STATUS */ |
52 | f716c197 | Guan Xuetao | ret = 0x00002401;
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53 | f716c197 | Guan Xuetao | break;
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54 | f716c197 | Guan Xuetao | case 0x2c: /* PLL DDR STATUS */ |
55 | f716c197 | Guan Xuetao | ret = 0x00100c00;
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56 | f716c197 | Guan Xuetao | break;
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57 | f716c197 | Guan Xuetao | case 0x30: /* PLL VGA STATUS */ |
58 | f716c197 | Guan Xuetao | ret = 0x00003801;
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59 | f716c197 | Guan Xuetao | break;
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60 | f716c197 | Guan Xuetao | case 0x34: /* DIV STATUS */ |
61 | f716c197 | Guan Xuetao | ret = 0x22f52015;
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62 | f716c197 | Guan Xuetao | break;
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63 | f716c197 | Guan Xuetao | case 0x38: /* SW RESET */ |
64 | f716c197 | Guan Xuetao | ret = 0x0;
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65 | f716c197 | Guan Xuetao | break;
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66 | f716c197 | Guan Xuetao | case 0x44: /* PLL DFC DONE */ |
67 | f716c197 | Guan Xuetao | ret = 0x7;
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68 | f716c197 | Guan Xuetao | break;
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69 | f716c197 | Guan Xuetao | default:
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70 | f716c197 | Guan Xuetao | DPRINTF("Bad offset 0x%x\n", offset);
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71 | f716c197 | Guan Xuetao | } |
72 | f716c197 | Guan Xuetao | DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
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73 | f716c197 | Guan Xuetao | |
74 | f716c197 | Guan Xuetao | return ret;
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75 | f716c197 | Guan Xuetao | } |
76 | f716c197 | Guan Xuetao | |
77 | f716c197 | Guan Xuetao | static void puv3_pm_write(void *opaque, target_phys_addr_t offset, |
78 | f716c197 | Guan Xuetao | uint64_t value, unsigned size)
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79 | f716c197 | Guan Xuetao | { |
80 | f716c197 | Guan Xuetao | PUV3PMState *s = opaque; |
81 | f716c197 | Guan Xuetao | |
82 | f716c197 | Guan Xuetao | switch (offset) {
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83 | f716c197 | Guan Xuetao | case 0x0: |
84 | f716c197 | Guan Xuetao | s->reg_PMCR = value; |
85 | f716c197 | Guan Xuetao | break;
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86 | f716c197 | Guan Xuetao | case 0x14: |
87 | f716c197 | Guan Xuetao | s->reg_PCGR = value; |
88 | f716c197 | Guan Xuetao | break;
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89 | f716c197 | Guan Xuetao | case 0x18: |
90 | f716c197 | Guan Xuetao | s->reg_PLL_SYS_CFG = value; |
91 | f716c197 | Guan Xuetao | break;
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92 | f716c197 | Guan Xuetao | case 0x1c: |
93 | f716c197 | Guan Xuetao | s->reg_PLL_DDR_CFG = value; |
94 | f716c197 | Guan Xuetao | break;
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95 | f716c197 | Guan Xuetao | case 0x20: |
96 | f716c197 | Guan Xuetao | s->reg_PLL_VGA_CFG = value; |
97 | f716c197 | Guan Xuetao | break;
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98 | f716c197 | Guan Xuetao | case 0x24: |
99 | f716c197 | Guan Xuetao | case 0x38: |
100 | f716c197 | Guan Xuetao | break;
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101 | f716c197 | Guan Xuetao | default:
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102 | f716c197 | Guan Xuetao | DPRINTF("Bad offset 0x%x\n", offset);
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103 | f716c197 | Guan Xuetao | } |
104 | f716c197 | Guan Xuetao | DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
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105 | f716c197 | Guan Xuetao | } |
106 | f716c197 | Guan Xuetao | |
107 | f716c197 | Guan Xuetao | static const MemoryRegionOps puv3_pm_ops = { |
108 | f716c197 | Guan Xuetao | .read = puv3_pm_read, |
109 | f716c197 | Guan Xuetao | .write = puv3_pm_write, |
110 | f716c197 | Guan Xuetao | .impl = { |
111 | f716c197 | Guan Xuetao | .min_access_size = 4,
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112 | f716c197 | Guan Xuetao | .max_access_size = 4,
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113 | f716c197 | Guan Xuetao | }, |
114 | f716c197 | Guan Xuetao | .endianness = DEVICE_NATIVE_ENDIAN, |
115 | f716c197 | Guan Xuetao | }; |
116 | f716c197 | Guan Xuetao | |
117 | f716c197 | Guan Xuetao | static int puv3_pm_init(SysBusDevice *dev) |
118 | f716c197 | Guan Xuetao | { |
119 | f716c197 | Guan Xuetao | PUV3PMState *s = FROM_SYSBUS(PUV3PMState, dev); |
120 | f716c197 | Guan Xuetao | |
121 | f716c197 | Guan Xuetao | s->reg_PCGR = 0x0;
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122 | f716c197 | Guan Xuetao | |
123 | f716c197 | Guan Xuetao | memory_region_init_io(&s->iomem, &puv3_pm_ops, s, "puv3_pm",
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124 | f716c197 | Guan Xuetao | PUV3_REGS_OFFSET); |
125 | f716c197 | Guan Xuetao | sysbus_init_mmio(dev, &s->iomem); |
126 | f716c197 | Guan Xuetao | |
127 | f716c197 | Guan Xuetao | return 0; |
128 | f716c197 | Guan Xuetao | } |
129 | f716c197 | Guan Xuetao | |
130 | f716c197 | Guan Xuetao | static void puv3_pm_class_init(ObjectClass *klass, void *data) |
131 | f716c197 | Guan Xuetao | { |
132 | f716c197 | Guan Xuetao | SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); |
133 | f716c197 | Guan Xuetao | |
134 | f716c197 | Guan Xuetao | sdc->init = puv3_pm_init; |
135 | f716c197 | Guan Xuetao | } |
136 | f716c197 | Guan Xuetao | |
137 | f716c197 | Guan Xuetao | static const TypeInfo puv3_pm_info = { |
138 | f716c197 | Guan Xuetao | .name = "puv3_pm",
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139 | f716c197 | Guan Xuetao | .parent = TYPE_SYS_BUS_DEVICE, |
140 | f716c197 | Guan Xuetao | .instance_size = sizeof(PUV3PMState),
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141 | f716c197 | Guan Xuetao | .class_init = puv3_pm_class_init, |
142 | f716c197 | Guan Xuetao | }; |
143 | f716c197 | Guan Xuetao | |
144 | f716c197 | Guan Xuetao | static void puv3_pm_register_type(void) |
145 | f716c197 | Guan Xuetao | { |
146 | f716c197 | Guan Xuetao | type_register_static(&puv3_pm_info); |
147 | f716c197 | Guan Xuetao | } |
148 | f716c197 | Guan Xuetao | |
149 | f716c197 | Guan Xuetao | type_init(puv3_pm_register_type) |