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1 | 27503323 | bellard | /*
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2 | 27503323 | bellard | * QEMU DMA emulation
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3 | 27503323 | bellard | *
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4 | 27503323 | bellard | * Copyright (c) 2003 Vassili Karpov (malc)
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5 | 27503323 | bellard | *
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6 | 27503323 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 27503323 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 27503323 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 27503323 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 27503323 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 27503323 | bellard | * furnished to do so, subject to the following conditions:
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12 | 27503323 | bellard | *
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13 | 27503323 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 27503323 | bellard | * all copies or substantial portions of the Software.
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15 | 27503323 | bellard | *
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16 | 27503323 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 27503323 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 27503323 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 27503323 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 27503323 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 27503323 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 27503323 | bellard | * THE SOFTWARE.
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23 | 27503323 | bellard | */
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24 | 27503323 | bellard | #include <stdio.h> |
25 | 27503323 | bellard | #include <stdlib.h> |
26 | 27503323 | bellard | #include <inttypes.h> |
27 | 27503323 | bellard | |
28 | 27503323 | bellard | #include "cpu.h" |
29 | 16d17fdb | bellard | #include "vl.h" |
30 | 27503323 | bellard | |
31 | 27503323 | bellard | #define log(...) fprintf (stderr, "dma: " __VA_ARGS__) |
32 | 27503323 | bellard | #ifdef DEBUG_DMA
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33 | 27503323 | bellard | #define lwarn(...) fprintf (stderr, "dma: " __VA_ARGS__) |
34 | 27503323 | bellard | #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__) |
35 | 27503323 | bellard | #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__) |
36 | 27503323 | bellard | #else
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37 | 27503323 | bellard | #define lwarn(...)
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38 | 27503323 | bellard | #define linfo(...)
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39 | 27503323 | bellard | #define ldebug(...)
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40 | 27503323 | bellard | #endif
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41 | 27503323 | bellard | |
42 | 27503323 | bellard | #define MEM_REAL(addr) ((addr)+(uint32_t)(phys_ram_base))
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43 | 27503323 | bellard | #define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0]))) |
44 | 27503323 | bellard | |
45 | 27503323 | bellard | struct dma_regs {
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46 | 27503323 | bellard | int now[2]; |
47 | 27503323 | bellard | uint16_t base[2];
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48 | 27503323 | bellard | uint8_t mode; |
49 | 27503323 | bellard | uint8_t page; |
50 | 27503323 | bellard | uint8_t dack; |
51 | 27503323 | bellard | uint8_t eop; |
52 | 27503323 | bellard | DMA_read_handler read_handler; |
53 | 27503323 | bellard | DMA_misc_handler misc_handler; |
54 | 27503323 | bellard | }; |
55 | 27503323 | bellard | |
56 | 27503323 | bellard | #define ADDR 0 |
57 | 27503323 | bellard | #define COUNT 1 |
58 | 27503323 | bellard | |
59 | 27503323 | bellard | static struct dma_cont { |
60 | 27503323 | bellard | uint8_t status; |
61 | 27503323 | bellard | uint8_t command; |
62 | 27503323 | bellard | uint8_t mask; |
63 | 27503323 | bellard | uint8_t flip_flop; |
64 | 27503323 | bellard | struct dma_regs regs[4]; |
65 | 27503323 | bellard | } dma_controllers[2];
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66 | 27503323 | bellard | |
67 | 27503323 | bellard | enum {
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68 | 27503323 | bellard | CMD_MEMORY_TO_MEMORY = 0x01,
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69 | 27503323 | bellard | CMD_FIXED_ADDRESS = 0x02,
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70 | 27503323 | bellard | CMD_BLOCK_CONTROLLER = 0x04,
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71 | 27503323 | bellard | CMD_COMPRESSED_TIME = 0x08,
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72 | 27503323 | bellard | CMD_CYCLIC_PRIORITY = 0x10,
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73 | 27503323 | bellard | CMD_EXTENDED_WRITE = 0x20,
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74 | 27503323 | bellard | CMD_LOW_DREQ = 0x40,
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75 | 27503323 | bellard | CMD_LOW_DACK = 0x80,
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76 | 27503323 | bellard | CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS |
77 | 27503323 | bellard | | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE |
78 | 27503323 | bellard | | CMD_LOW_DREQ | CMD_LOW_DACK |
79 | 27503323 | bellard | |
80 | 27503323 | bellard | }; |
81 | 27503323 | bellard | |
82 | 16d17fdb | bellard | static void write_page (CPUState *env, uint32_t nport, uint32_t data) |
83 | 27503323 | bellard | { |
84 | 27503323 | bellard | int ichan;
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85 | 27503323 | bellard | int ncont;
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86 | 27503323 | bellard | static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0}; |
87 | 27503323 | bellard | |
88 | 27503323 | bellard | ncont = nport > 0x87;
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89 | 27503323 | bellard | ichan = channels[nport - 0x80 - (ncont << 3)]; |
90 | 27503323 | bellard | |
91 | 27503323 | bellard | if (-1 == ichan) { |
92 | 27503323 | bellard | log ("invalid channel %#x %#x\n", nport, data);
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93 | 27503323 | bellard | return;
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94 | 27503323 | bellard | } |
95 | 27503323 | bellard | |
96 | 27503323 | bellard | dma_controllers[ncont].regs[ichan].page = data; |
97 | 27503323 | bellard | } |
98 | 27503323 | bellard | |
99 | 27503323 | bellard | static void init_chan (int ncont, int ichan) |
100 | 27503323 | bellard | { |
101 | 27503323 | bellard | struct dma_regs *r;
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102 | 27503323 | bellard | |
103 | 27503323 | bellard | r = dma_controllers[ncont].regs + ichan; |
104 | 27503323 | bellard | r->now[ADDR] = r->base[0] << ncont;
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105 | 27503323 | bellard | r->now[COUNT] = 0;
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106 | 27503323 | bellard | } |
107 | 27503323 | bellard | |
108 | 27503323 | bellard | static inline int getff (int ncont) |
109 | 27503323 | bellard | { |
110 | 27503323 | bellard | int ff;
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111 | 27503323 | bellard | |
112 | 27503323 | bellard | ff = dma_controllers[ncont].flip_flop; |
113 | 27503323 | bellard | dma_controllers[ncont].flip_flop = !ff; |
114 | 27503323 | bellard | return ff;
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115 | 27503323 | bellard | } |
116 | 27503323 | bellard | |
117 | 16d17fdb | bellard | static uint32_t read_chan (CPUState *env, uint32_t nport)
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118 | 27503323 | bellard | { |
119 | 27503323 | bellard | int ff;
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120 | 27503323 | bellard | int ncont, ichan, nreg;
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121 | 27503323 | bellard | struct dma_regs *r;
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122 | 27503323 | bellard | int val;
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123 | 27503323 | bellard | |
124 | 27503323 | bellard | ncont = nport > 7;
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125 | 27503323 | bellard | ichan = (nport >> (1 + ncont)) & 3; |
126 | 27503323 | bellard | nreg = (nport >> ncont) & 1;
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127 | 27503323 | bellard | r = dma_controllers[ncont].regs + ichan; |
128 | 27503323 | bellard | |
129 | 27503323 | bellard | ff = getff (ncont); |
130 | 27503323 | bellard | |
131 | 27503323 | bellard | if (nreg)
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132 | 27503323 | bellard | val = (r->base[COUNT] << ncont) - r->now[COUNT]; |
133 | 27503323 | bellard | else
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134 | 27503323 | bellard | val = r->now[ADDR] + r->now[COUNT]; |
135 | 27503323 | bellard | |
136 | 27503323 | bellard | return (val >> (ncont + (ff << 3))) & 0xff; |
137 | 27503323 | bellard | } |
138 | 27503323 | bellard | |
139 | 3504fe17 | bellard | static void write_chan (CPUState *env, uint32_t nport, uint32_t data) |
140 | 27503323 | bellard | { |
141 | 27503323 | bellard | int ncont, ichan, nreg;
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142 | 27503323 | bellard | struct dma_regs *r;
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143 | 27503323 | bellard | |
144 | 27503323 | bellard | ncont = nport > 7;
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145 | 27503323 | bellard | ichan = (nport >> (1 + ncont)) & 3; |
146 | 27503323 | bellard | nreg = (nport >> ncont) & 1;
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147 | 27503323 | bellard | r = dma_controllers[ncont].regs + ichan; |
148 | 27503323 | bellard | |
149 | 3504fe17 | bellard | if (getff (ncont)) {
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150 | 3504fe17 | bellard | r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); |
151 | 27503323 | bellard | init_chan (ncont, ichan); |
152 | 3504fe17 | bellard | } else {
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153 | 3504fe17 | bellard | r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); |
154 | 27503323 | bellard | } |
155 | 27503323 | bellard | } |
156 | 27503323 | bellard | |
157 | 16d17fdb | bellard | static void write_cont (CPUState *env, uint32_t nport, uint32_t data) |
158 | 27503323 | bellard | { |
159 | 27503323 | bellard | int iport, ichan, ncont;
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160 | 27503323 | bellard | struct dma_cont *d;
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161 | 27503323 | bellard | |
162 | 27503323 | bellard | ncont = nport > 0xf;
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163 | 27503323 | bellard | ichan = -1;
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164 | 27503323 | bellard | |
165 | 27503323 | bellard | d = dma_controllers + ncont; |
166 | 27503323 | bellard | if (ncont) {
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167 | 27503323 | bellard | iport = ((nport - 0xd0) >> 1) + 8; |
168 | 27503323 | bellard | } |
169 | 27503323 | bellard | else {
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170 | 27503323 | bellard | iport = nport; |
171 | 27503323 | bellard | } |
172 | 27503323 | bellard | |
173 | 27503323 | bellard | switch (iport) {
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174 | 27503323 | bellard | case 8: /* command */ |
175 | 27503323 | bellard | if (data && (data | CMD_NOT_SUPPORTED)) {
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176 | 27503323 | bellard | log ("command %#x not supported\n", data);
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177 | 27503323 | bellard | goto error;
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178 | 27503323 | bellard | } |
179 | 27503323 | bellard | d->command = data; |
180 | 27503323 | bellard | break;
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181 | 27503323 | bellard | |
182 | 27503323 | bellard | case 9: |
183 | 27503323 | bellard | ichan = data & 3;
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184 | 27503323 | bellard | if (data & 4) { |
185 | 27503323 | bellard | d->status |= 1 << (ichan + 4); |
186 | 27503323 | bellard | } |
187 | 27503323 | bellard | else {
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188 | 27503323 | bellard | d->status &= ~(1 << (ichan + 4)); |
189 | 27503323 | bellard | } |
190 | 27503323 | bellard | d->status &= ~(1 << ichan);
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191 | 27503323 | bellard | break;
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192 | 27503323 | bellard | |
193 | 27503323 | bellard | case 0xa: /* single mask */ |
194 | 27503323 | bellard | if (data & 4) |
195 | 27503323 | bellard | d->mask |= 1 << (data & 3); |
196 | 27503323 | bellard | else
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197 | 27503323 | bellard | d->mask &= ~(1 << (data & 3)); |
198 | 27503323 | bellard | break;
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199 | 27503323 | bellard | |
200 | 27503323 | bellard | case 0xb: /* mode */ |
201 | 27503323 | bellard | { |
202 | 16d17fdb | bellard | ichan = data & 3;
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203 | 16d17fdb | bellard | #ifdef DEBUG_DMA
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204 | 27503323 | bellard | int op;
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205 | 27503323 | bellard | int ai;
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206 | 27503323 | bellard | int dir;
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207 | 27503323 | bellard | int opmode;
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208 | 27503323 | bellard | |
209 | 16d17fdb | bellard | op = (data >> 2) & 3; |
210 | 16d17fdb | bellard | ai = (data >> 4) & 1; |
211 | 16d17fdb | bellard | dir = (data >> 5) & 1; |
212 | 16d17fdb | bellard | opmode = (data >> 6) & 3; |
213 | 27503323 | bellard | |
214 | 27503323 | bellard | linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
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215 | 27503323 | bellard | ichan, op, ai, dir, opmode); |
216 | 27503323 | bellard | #endif
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217 | 27503323 | bellard | |
218 | 27503323 | bellard | d->regs[ichan].mode = data; |
219 | 27503323 | bellard | break;
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220 | 27503323 | bellard | } |
221 | 27503323 | bellard | |
222 | 27503323 | bellard | case 0xc: /* clear flip flop */ |
223 | 27503323 | bellard | d->flip_flop = 0;
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224 | 27503323 | bellard | break;
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225 | 27503323 | bellard | |
226 | 27503323 | bellard | case 0xd: /* reset */ |
227 | 27503323 | bellard | d->flip_flop = 0;
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228 | 27503323 | bellard | d->mask = ~0;
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229 | 27503323 | bellard | d->status = 0;
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230 | 27503323 | bellard | d->command = 0;
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231 | 27503323 | bellard | break;
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232 | 27503323 | bellard | |
233 | 27503323 | bellard | case 0xe: /* clear mask for all channels */ |
234 | 27503323 | bellard | d->mask = 0;
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235 | 27503323 | bellard | break;
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236 | 27503323 | bellard | |
237 | 27503323 | bellard | case 0xf: /* write mask for all channels */ |
238 | 27503323 | bellard | d->mask = data; |
239 | 27503323 | bellard | break;
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240 | 27503323 | bellard | |
241 | 27503323 | bellard | default:
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242 | 27503323 | bellard | log ("dma: unknown iport %#x\n", iport);
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243 | 27503323 | bellard | goto error;
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244 | 27503323 | bellard | } |
245 | 27503323 | bellard | |
246 | 16d17fdb | bellard | #ifdef DEBUG_DMA
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247 | 27503323 | bellard | if (0xc != iport) { |
248 | 27503323 | bellard | linfo ("nport %#06x, ncont %d, ichan % 2d, val %#06x\n",
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249 | 27503323 | bellard | nport, d != dma_controllers, ichan, data); |
250 | 27503323 | bellard | } |
251 | 27503323 | bellard | #endif
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252 | 27503323 | bellard | return;
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253 | 27503323 | bellard | |
254 | 27503323 | bellard | error:
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255 | 27503323 | bellard | abort (); |
256 | 27503323 | bellard | } |
257 | 27503323 | bellard | |
258 | 27503323 | bellard | int DMA_get_channel_mode (int nchan) |
259 | 27503323 | bellard | { |
260 | 27503323 | bellard | return dma_controllers[nchan > 3].regs[nchan & 3].mode; |
261 | 27503323 | bellard | } |
262 | 27503323 | bellard | |
263 | 27503323 | bellard | void DMA_hold_DREQ (int nchan) |
264 | 27503323 | bellard | { |
265 | 27503323 | bellard | int ncont, ichan;
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266 | 27503323 | bellard | |
267 | 27503323 | bellard | ncont = nchan > 3;
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268 | 27503323 | bellard | ichan = nchan & 3;
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269 | 27503323 | bellard | linfo ("held cont=%d chan=%d\n", ncont, ichan);
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270 | 27503323 | bellard | dma_controllers[ncont].status |= 1 << (ichan + 4); |
271 | 27503323 | bellard | } |
272 | 27503323 | bellard | |
273 | 27503323 | bellard | void DMA_release_DREQ (int nchan) |
274 | 27503323 | bellard | { |
275 | 27503323 | bellard | int ncont, ichan;
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276 | 27503323 | bellard | |
277 | 27503323 | bellard | ncont = nchan > 3;
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278 | 27503323 | bellard | ichan = nchan & 3;
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279 | 27503323 | bellard | linfo ("released cont=%d chan=%d\n", ncont, ichan);
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280 | 27503323 | bellard | dma_controllers[ncont].status &= ~(1 << (ichan + 4)); |
281 | 27503323 | bellard | } |
282 | 27503323 | bellard | |
283 | 27503323 | bellard | static void channel_run (int ncont, int ichan) |
284 | 27503323 | bellard | { |
285 | 27503323 | bellard | struct dma_regs *r;
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286 | 27503323 | bellard | int n;
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287 | 27503323 | bellard | int irq;
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288 | 27503323 | bellard | uint32_t addr; |
289 | 27503323 | bellard | /* int ai, dir; */
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290 | 27503323 | bellard | |
291 | 27503323 | bellard | r = dma_controllers[ncont].regs + ichan; |
292 | 27503323 | bellard | /* ai = r->mode & 16; */
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293 | 27503323 | bellard | /* dir = r->mode & 32 ? -1 : 1; */
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294 | 27503323 | bellard | |
295 | 27503323 | bellard | addr = MEM_REAL ((r->page << 16) | r->now[ADDR]);
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296 | 27503323 | bellard | |
297 | 27503323 | bellard | irq = -1;
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298 | 27503323 | bellard | n = r->read_handler (addr, (r->base[COUNT] << ncont) + (1 << ncont), &irq);
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299 | 27503323 | bellard | r->now[COUNT] = n; |
300 | 27503323 | bellard | |
301 | 27503323 | bellard | ldebug ("dma_pos %d irq %d size %d\n",
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302 | 27503323 | bellard | n, irq, (r->base[1] << ncont) + (1 << ncont)); |
303 | 27503323 | bellard | |
304 | 27503323 | bellard | if (-1 != irq) { |
305 | 27503323 | bellard | pic_set_irq (irq, 1);
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306 | 27503323 | bellard | } |
307 | 27503323 | bellard | } |
308 | 27503323 | bellard | |
309 | 27503323 | bellard | void DMA_run (void) |
310 | 27503323 | bellard | { |
311 | 27503323 | bellard | static int in_dma; |
312 | 27503323 | bellard | struct dma_cont *d;
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313 | 27503323 | bellard | int icont, ichan;
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314 | 27503323 | bellard | |
315 | 27503323 | bellard | if (in_dma) {
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316 | 27503323 | bellard | log ("attempt to re-enter dma\n");
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317 | 27503323 | bellard | return;
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318 | 27503323 | bellard | } |
319 | 27503323 | bellard | |
320 | 27503323 | bellard | in_dma = 1;
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321 | 27503323 | bellard | d = dma_controllers; |
322 | 27503323 | bellard | |
323 | 27503323 | bellard | for (icont = 0; icont < 2; icont++, d++) { |
324 | 27503323 | bellard | for (ichan = 0; ichan < 4; ichan++) { |
325 | 27503323 | bellard | int mask;
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326 | 27503323 | bellard | |
327 | 27503323 | bellard | mask = 1 << ichan;
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328 | 27503323 | bellard | |
329 | 27503323 | bellard | if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) |
330 | 27503323 | bellard | channel_run (icont, ichan); |
331 | 27503323 | bellard | } |
332 | 27503323 | bellard | } |
333 | 27503323 | bellard | in_dma = 0;
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334 | 27503323 | bellard | } |
335 | 27503323 | bellard | |
336 | 27503323 | bellard | void DMA_register_channel (int nchan, |
337 | 27503323 | bellard | DMA_read_handler read_handler, |
338 | 27503323 | bellard | DMA_misc_handler misc_handler) |
339 | 27503323 | bellard | { |
340 | 27503323 | bellard | struct dma_regs *r;
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341 | 27503323 | bellard | int ichan, ncont;
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342 | 27503323 | bellard | |
343 | 27503323 | bellard | ncont = nchan > 3;
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344 | 27503323 | bellard | ichan = nchan & 3;
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345 | 27503323 | bellard | |
346 | 27503323 | bellard | r = dma_controllers[ncont].regs + ichan; |
347 | 27503323 | bellard | r->read_handler = read_handler; |
348 | 27503323 | bellard | r->misc_handler = misc_handler; |
349 | 27503323 | bellard | } |
350 | 27503323 | bellard | |
351 | 27503323 | bellard | void DMA_init (void) |
352 | 27503323 | bellard | { |
353 | 27503323 | bellard | int i;
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354 | 27503323 | bellard | int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 }; |
355 | 27503323 | bellard | |
356 | 27503323 | bellard | for (i = 0; i < 8; i++) { |
357 | 3504fe17 | bellard | register_ioport_write (i, 1, write_chan, 1); |
358 | 27503323 | bellard | |
359 | 3504fe17 | bellard | register_ioport_write (0xc0 + (i << 1), 1, write_chan, 1); |
360 | 27503323 | bellard | |
361 | 27503323 | bellard | register_ioport_read (i, 1, read_chan, 1); |
362 | 3504fe17 | bellard | register_ioport_read (0xc0 + (i << 1), 1, read_chan, 1); |
363 | 27503323 | bellard | } |
364 | 27503323 | bellard | |
365 | 27503323 | bellard | for (i = 0; i < LENOFA (page_port_list); i++) { |
366 | 27503323 | bellard | register_ioport_write (page_port_list[i] + 0x80, 1, write_page, 1); |
367 | 27503323 | bellard | register_ioport_write (page_port_list[i] + 0x88, 1, write_page, 1); |
368 | 27503323 | bellard | } |
369 | 27503323 | bellard | |
370 | 27503323 | bellard | for (i = 0; i < 8; i++) { |
371 | 27503323 | bellard | register_ioport_write (i + 8, 1, write_cont, 1); |
372 | 27503323 | bellard | register_ioport_write (0xd0 + (i << 1), 1, write_cont, 1); |
373 | 27503323 | bellard | } |
374 | 27503323 | bellard | |
375 | 3504fe17 | bellard | write_cont (NULL, 0x0d, 0); |
376 | 3504fe17 | bellard | write_cont (NULL, 0xda, 0); |
377 | 27503323 | bellard | } |