Revision c96a29cd hw/mips_r4k.c
b/hw/mips_r4k.c | ||
---|---|---|
72 | 72 |
void cpu_mips_store_compare (CPUState *env, uint32_t value) |
73 | 73 |
{ |
74 | 74 |
cpu_mips_update_count(env, cpu_mips_get_count(env), value); |
75 |
pic_set_irq(5, 0); |
|
75 |
cpu_single_env->CP0_Cause &= ~0x00008000; |
|
76 |
cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); |
|
76 | 77 |
} |
77 | 78 |
|
78 | 79 |
static void mips_timer_cb (void *opaque) |
... | ... | |
86 | 87 |
} |
87 | 88 |
#endif |
88 | 89 |
cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare); |
89 |
pic_set_irq(5, 1); |
|
90 |
cpu_single_env->CP0_Cause |= 0x00008000; |
|
91 |
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); |
|
90 | 92 |
} |
91 | 93 |
|
92 | 94 |
void cpu_mips_clock_init (CPUState *env) |
Also available in: Unified diff