Revision c96a29cd hw/mips_r4k.c

b/hw/mips_r4k.c
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void cpu_mips_store_compare (CPUState *env, uint32_t value)
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{
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    cpu_mips_update_count(env, cpu_mips_get_count(env), value);
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    pic_set_irq(5, 0);
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    cpu_single_env->CP0_Cause &= ~0x00008000;
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    cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
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}
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static void mips_timer_cb (void *opaque)


  		





  ......




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    }


  		





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#endif


  		





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    cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);


  		





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    pic_set_irq(5, 1);


  		





  
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    cpu_single_env->CP0_Cause |= 0x00008000;


  		





  
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    cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);


  		





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}


  		





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void cpu_mips_clock_init (CPUState *env)


  		












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