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1 | 33d68b5f | ths | /*
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2 | 33d68b5f | ths | * MIPS emulation for qemu: CPU initialisation routines.
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3 | 33d68b5f | ths | *
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4 | 33d68b5f | ths | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 33d68b5f | ths | * Copyright (c) 2007 Herve Poussineau
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6 | 33d68b5f | ths | *
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7 | 33d68b5f | ths | * This library is free software; you can redistribute it and/or
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8 | 33d68b5f | ths | * modify it under the terms of the GNU Lesser General Public
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9 | 33d68b5f | ths | * License as published by the Free Software Foundation; either
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10 | 33d68b5f | ths | * version 2 of the License, or (at your option) any later version.
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11 | 33d68b5f | ths | *
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12 | 33d68b5f | ths | * This library is distributed in the hope that it will be useful,
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13 | 33d68b5f | ths | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 33d68b5f | ths | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 33d68b5f | ths | * Lesser General Public License for more details.
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16 | 33d68b5f | ths | *
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17 | 33d68b5f | ths | * You should have received a copy of the GNU Lesser General Public
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18 | 33d68b5f | ths | * License along with this library; if not, write to the Free Software
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19 | 33d68b5f | ths | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 33d68b5f | ths | */
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21 | 33d68b5f | ths | |
22 | 3953d786 | ths | /* CPU / CPU family specific config register values. */
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23 | 3953d786 | ths | |
24 | 3953d786 | ths | /* Have config1, is MIPS32R1, uses TLB, no virtual icache,
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25 | 3953d786 | ths | uncached coherency */
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26 | 3953d786 | ths | #define MIPS_CONFIG0 \
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27 | 3953d786 | ths | ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) | \ |
28 | 3953d786 | ths | (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \ |
29 | 3953d786 | ths | (0x2 << CP0C0_K0))
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30 | 3953d786 | ths | |
31 | fcb4a419 | ths | /* Have config2, 64 sets Icache, 16 bytes Icache line,
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32 | 3953d786 | ths | 2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
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33 | 3953d786 | ths | no coprocessor2 attached, no MDMX support attached,
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34 | 3953d786 | ths | no performance counters, watch registers present,
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35 | 3953d786 | ths | no code compression, EJTAG present, no FPU */
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36 | 3953d786 | ths | #define MIPS_CONFIG1 \
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37 | fcb4a419 | ths | ((1 << CP0C1_M) | \
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38 | 3953d786 | ths | (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) | \ |
39 | 3953d786 | ths | (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) | \ |
40 | 3953d786 | ths | (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ |
41 | 3953d786 | ths | (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ |
42 | 3953d786 | ths | (0 << CP0C1_FP))
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43 | 3953d786 | ths | |
44 | 3953d786 | ths | /* Have config3, no tertiary/secondary caches implemented */
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45 | 3953d786 | ths | #define MIPS_CONFIG2 \
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46 | 3953d786 | ths | ((1 << CP0C2_M))
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47 | 3953d786 | ths | |
48 | 3953d786 | ths | /* No config4, no DSP ASE, no large physaddr,
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49 | 3953d786 | ths | no external interrupt controller, no vectored interupts,
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50 | 3953d786 | ths | no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
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51 | 3953d786 | ths | #define MIPS_CONFIG3 \
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52 | 3953d786 | ths | ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ |
53 | 3953d786 | ths | (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ |
54 | 3953d786 | ths | (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL)) |
55 | 3953d786 | ths | |
56 | 3953d786 | ths | /* Define a implementation number of 1.
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57 | 3953d786 | ths | Define a major version 1, minor version 0. */
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58 | 5a5012ec | ths | #define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV)) |
59 | 3953d786 | ths | |
60 | 3953d786 | ths | |
61 | 33d68b5f | ths | struct mips_def_t {
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62 | 33d68b5f | ths | const unsigned char *name; |
63 | 33d68b5f | ths | int32_t CP0_PRid; |
64 | 33d68b5f | ths | int32_t CP0_Config0; |
65 | 33d68b5f | ths | int32_t CP0_Config1; |
66 | 3953d786 | ths | int32_t CP0_Config2; |
67 | 3953d786 | ths | int32_t CP0_Config3; |
68 | 34ee2ede | ths | int32_t CP0_Config6; |
69 | 34ee2ede | ths | int32_t CP0_Config7; |
70 | 2f644545 | ths | int32_t SYNCI_Step; |
71 | 2f644545 | ths | int32_t CCRes; |
72 | 5a5012ec | ths | int32_t Status_rw_bitmask; |
73 | 3953d786 | ths | int32_t CP1_fcr0; |
74 | 33d68b5f | ths | }; |
75 | 33d68b5f | ths | |
76 | 33d68b5f | ths | /*****************************************************************************/
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77 | 33d68b5f | ths | /* MIPS CPU definitions */
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78 | 33d68b5f | ths | static mips_def_t mips_defs[] =
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79 | 33d68b5f | ths | { |
80 | 60aa19ab | ths | #ifndef TARGET_MIPS64
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81 | 33d68b5f | ths | { |
82 | 33d68b5f | ths | .name = "4Kc",
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83 | 33d68b5f | ths | .CP0_PRid = 0x00018000,
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84 | 33d68b5f | ths | .CP0_Config0 = MIPS_CONFIG0, |
85 | fcb4a419 | ths | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
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86 | 3953d786 | ths | .CP0_Config2 = MIPS_CONFIG2, |
87 | 3953d786 | ths | .CP0_Config3 = MIPS_CONFIG3, |
88 | 2f644545 | ths | .SYNCI_Step = 32,
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89 | 2f644545 | ths | .CCRes = 2,
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90 | 5a5012ec | ths | .Status_rw_bitmask = 0x3278FF17,
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91 | 33d68b5f | ths | }, |
92 | 33d68b5f | ths | { |
93 | 34ee2ede | ths | .name = "4KEcR1",
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94 | 33d68b5f | ths | .CP0_PRid = 0x00018400,
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95 | 34ee2ede | ths | .CP0_Config0 = MIPS_CONFIG0, |
96 | fcb4a419 | ths | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
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97 | 34ee2ede | ths | .CP0_Config2 = MIPS_CONFIG2, |
98 | 34ee2ede | ths | .CP0_Config3 = MIPS_CONFIG3, |
99 | 2f644545 | ths | .SYNCI_Step = 32,
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100 | 2f644545 | ths | .CCRes = 2,
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101 | 4759513b | ths | .Status_rw_bitmask = 0x3278FF17,
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102 | 34ee2ede | ths | }, |
103 | 34ee2ede | ths | { |
104 | 34ee2ede | ths | .name = "4KEc",
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105 | 34ee2ede | ths | .CP0_PRid = 0x00019000,
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106 | 34ee2ede | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
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107 | fcb4a419 | ths | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
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108 | 34ee2ede | ths | .CP0_Config2 = MIPS_CONFIG2, |
109 | 34ee2ede | ths | .CP0_Config3 = MIPS_CONFIG3, |
110 | 2f644545 | ths | .SYNCI_Step = 32,
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111 | 2f644545 | ths | .CCRes = 2,
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112 | 5a5012ec | ths | .Status_rw_bitmask = 0x3278FF17,
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113 | 34ee2ede | ths | }, |
114 | 34ee2ede | ths | { |
115 | 34ee2ede | ths | .name = "24Kc",
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116 | 34ee2ede | ths | .CP0_PRid = 0x00019300,
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117 | 33d68b5f | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
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118 | fcb4a419 | ths | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
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119 | 3953d786 | ths | .CP0_Config2 = MIPS_CONFIG2, |
120 | 3953d786 | ths | .CP0_Config3 = MIPS_CONFIG3, |
121 | 2f644545 | ths | .SYNCI_Step = 32,
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122 | 2f644545 | ths | .CCRes = 2,
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123 | 5a5012ec | ths | .Status_rw_bitmask = 0x3278FF17,
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124 | 33d68b5f | ths | }, |
125 | 33d68b5f | ths | { |
126 | 33d68b5f | ths | .name = "24Kf",
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127 | 33d68b5f | ths | .CP0_PRid = 0x00019300,
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128 | 33d68b5f | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
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129 | fcb4a419 | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU), |
130 | 3953d786 | ths | .CP0_Config2 = MIPS_CONFIG2, |
131 | 3953d786 | ths | .CP0_Config3 = MIPS_CONFIG3, |
132 | 2f644545 | ths | .SYNCI_Step = 32,
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133 | 2f644545 | ths | .CCRes = 2,
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134 | 5a5012ec | ths | .Status_rw_bitmask = 0x3678FF17,
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135 | 5a5012ec | ths | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
136 | 5a5012ec | ths | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |
137 | 33d68b5f | ths | }, |
138 | 33d68b5f | ths | #else
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139 | 33d68b5f | ths | { |
140 | 33d68b5f | ths | .name = "R4000",
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141 | 33d68b5f | ths | .CP0_PRid = 0x00000400,
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142 | 33d68b5f | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
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143 | fcb4a419 | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
144 | 3953d786 | ths | .CP0_Config2 = MIPS_CONFIG2, |
145 | 3953d786 | ths | .CP0_Config3 = MIPS_CONFIG3, |
146 | 2f644545 | ths | .SYNCI_Step = 16,
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147 | 2f644545 | ths | .CCRes = 2,
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148 | 5a5012ec | ths | .Status_rw_bitmask = 0x3678FFFF,
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149 | c9c1a064 | ths | /* XXX: The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */
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150 | c9c1a064 | ths | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), |
151 | c9c1a064 | ths | }, |
152 | c9c1a064 | ths | { |
153 | c9c1a064 | ths | .name = "5Kc",
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154 | c9c1a064 | ths | .CP0_PRid = 0x00018100,
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155 | c9c1a064 | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
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156 | c9c1a064 | ths | .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
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157 | c9c1a064 | ths | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
158 | c9c1a064 | ths | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
159 | c9c1a064 | ths | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
160 | c9c1a064 | ths | .CP0_Config2 = MIPS_CONFIG2, |
161 | c9c1a064 | ths | .CP0_Config3 = MIPS_CONFIG3, |
162 | c9c1a064 | ths | .SYNCI_Step = 32,
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163 | c9c1a064 | ths | .CCRes = 2,
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164 | c9c1a064 | ths | .Status_rw_bitmask = 0x3278FFFF,
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165 | c9c1a064 | ths | }, |
166 | c9c1a064 | ths | { |
167 | c9c1a064 | ths | .name = "5Kf",
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168 | c9c1a064 | ths | .CP0_PRid = 0x00018100,
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169 | c9c1a064 | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
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170 | c9c1a064 | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | |
171 | c9c1a064 | ths | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
172 | c9c1a064 | ths | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
173 | c9c1a064 | ths | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
174 | c9c1a064 | ths | .CP0_Config2 = MIPS_CONFIG2, |
175 | c9c1a064 | ths | .CP0_Config3 = MIPS_CONFIG3, |
176 | c9c1a064 | ths | .SYNCI_Step = 32,
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177 | c9c1a064 | ths | .CCRes = 2,
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178 | c9c1a064 | ths | .Status_rw_bitmask = 0x3678FFFF,
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179 | c9c1a064 | ths | /* XXX: The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
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180 | c9c1a064 | ths | .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | |
181 | c9c1a064 | ths | (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), |
182 | c9c1a064 | ths | }, |
183 | c9c1a064 | ths | { |
184 | c9c1a064 | ths | .name = "20Kc",
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185 | c9c1a064 | ths | .CP0_PRid = 0x00018200,
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186 | c9c1a064 | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (1 << CP0C0_VI), |
187 | c9c1a064 | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | |
188 | c9c1a064 | ths | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
189 | c9c1a064 | ths | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
190 | c9c1a064 | ths | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
191 | c9c1a064 | ths | .CP0_Config2 = MIPS_CONFIG2, |
192 | c9c1a064 | ths | .CP0_Config3 = MIPS_CONFIG3, |
193 | c9c1a064 | ths | .SYNCI_Step = 32,
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194 | c9c1a064 | ths | .CCRes = 2,
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195 | c9c1a064 | ths | .Status_rw_bitmask = 0x36FBFFFF,
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196 | c9c1a064 | ths | /* XXX: The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
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197 | c9c1a064 | ths | .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | |
198 | 5a5012ec | ths | (1 << FCR0_D) | (1 << FCR0_S) | |
199 | c9c1a064 | ths | (0x82 << FCR0_PRID) | (0x0 << FCR0_REV), |
200 | 33d68b5f | ths | }, |
201 | 33d68b5f | ths | #endif
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202 | 33d68b5f | ths | }; |
203 | 33d68b5f | ths | |
204 | 33d68b5f | ths | int mips_find_by_name (const unsigned char *name, mips_def_t **def) |
205 | 33d68b5f | ths | { |
206 | 33d68b5f | ths | int i, ret;
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207 | 33d68b5f | ths | |
208 | 33d68b5f | ths | ret = -1;
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209 | 33d68b5f | ths | *def = NULL;
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210 | 33d68b5f | ths | for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) { |
211 | 33d68b5f | ths | if (strcasecmp(name, mips_defs[i].name) == 0) { |
212 | 33d68b5f | ths | *def = &mips_defs[i]; |
213 | 33d68b5f | ths | ret = 0;
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214 | 33d68b5f | ths | break;
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215 | 33d68b5f | ths | } |
216 | 33d68b5f | ths | } |
217 | 33d68b5f | ths | |
218 | 33d68b5f | ths | return ret;
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219 | 33d68b5f | ths | } |
220 | 33d68b5f | ths | |
221 | 33d68b5f | ths | void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
222 | 33d68b5f | ths | { |
223 | 33d68b5f | ths | int i;
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224 | 33d68b5f | ths | |
225 | 33d68b5f | ths | for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) { |
226 | 33d68b5f | ths | (*cpu_fprintf)(f, "MIPS '%s'\n",
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227 | 33d68b5f | ths | mips_defs[i].name); |
228 | 33d68b5f | ths | } |
229 | 33d68b5f | ths | } |
230 | 33d68b5f | ths | |
231 | 29929e34 | ths | #ifndef CONFIG_USER_ONLY
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232 | 29929e34 | ths | static void no_mmu_init (CPUMIPSState *env, mips_def_t *def) |
233 | 29929e34 | ths | { |
234 | 29929e34 | ths | env->nb_tlb = 1;
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235 | 29929e34 | ths | env->map_address = &no_mmu_map_address; |
236 | 29929e34 | ths | } |
237 | 29929e34 | ths | |
238 | 29929e34 | ths | static void fixed_mmu_init (CPUMIPSState *env, mips_def_t *def) |
239 | 29929e34 | ths | { |
240 | 29929e34 | ths | env->nb_tlb = 1;
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241 | 29929e34 | ths | env->map_address = &fixed_mmu_map_address; |
242 | 29929e34 | ths | } |
243 | 29929e34 | ths | |
244 | 29929e34 | ths | static void r4k_mmu_init (CPUMIPSState *env, mips_def_t *def) |
245 | 29929e34 | ths | { |
246 | 29929e34 | ths | env->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); |
247 | 29929e34 | ths | env->map_address = &r4k_map_address; |
248 | 29929e34 | ths | env->do_tlbwi = r4k_do_tlbwi; |
249 | 29929e34 | ths | env->do_tlbwr = r4k_do_tlbwr; |
250 | 29929e34 | ths | env->do_tlbp = r4k_do_tlbp; |
251 | 29929e34 | ths | env->do_tlbr = r4k_do_tlbr; |
252 | 29929e34 | ths | } |
253 | 29929e34 | ths | #endif /* CONFIG_USER_ONLY */ |
254 | 29929e34 | ths | |
255 | 33d68b5f | ths | int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
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256 | 33d68b5f | ths | { |
257 | 33d68b5f | ths | if (!def)
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258 | 51b2772f | ths | def = env->cpu_model; |
259 | 51b2772f | ths | if (!def)
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260 | 33d68b5f | ths | cpu_abort(env, "Unable to find MIPS CPU definition\n");
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261 | 51b2772f | ths | env->cpu_model = def; |
262 | 33d68b5f | ths | env->CP0_PRid = def->CP0_PRid; |
263 | 33d68b5f | ths | env->CP0_Config0 = def->CP0_Config0; |
264 | 51b2772f | ths | #ifdef TARGET_WORDS_BIGENDIAN
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265 | 51b2772f | ths | env->CP0_Config0 |= (1 << CP0C0_BE);
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266 | 3953d786 | ths | #endif
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267 | 33d68b5f | ths | env->CP0_Config1 = def->CP0_Config1; |
268 | 3953d786 | ths | env->CP0_Config2 = def->CP0_Config2; |
269 | 3953d786 | ths | env->CP0_Config3 = def->CP0_Config3; |
270 | 34ee2ede | ths | env->CP0_Config6 = def->CP0_Config6; |
271 | 34ee2ede | ths | env->CP0_Config7 = def->CP0_Config7; |
272 | 2f644545 | ths | env->SYNCI_Step = def->SYNCI_Step; |
273 | 2f644545 | ths | env->CCRes = def->CCRes; |
274 | 5a5012ec | ths | env->Status_rw_bitmask = def->Status_rw_bitmask; |
275 | 3953d786 | ths | env->fcr0 = def->CP1_fcr0; |
276 | a7037b29 | ths | #ifdef CONFIG_USER_ONLY
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277 | a7037b29 | ths | if (env->CP0_Config1 & (1 << CP0C1_FP)) |
278 | a7037b29 | ths | env->hflags |= MIPS_HFLAG_FPU; |
279 | a7037b29 | ths | if (env->fcr0 & (1 << FCR0_F64)) |
280 | a7037b29 | ths | env->hflags |= MIPS_HFLAG_F64; |
281 | a7037b29 | ths | #else
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282 | 29929e34 | ths | switch ((env->CP0_Config0 >> CP0C0_MT) & 3) { |
283 | 29929e34 | ths | case 0: |
284 | 29929e34 | ths | no_mmu_init(env, def); |
285 | 29929e34 | ths | break;
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286 | 29929e34 | ths | case 1: |
287 | 29929e34 | ths | r4k_mmu_init(env, def); |
288 | 29929e34 | ths | break;
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289 | 29929e34 | ths | case 3: |
290 | 29929e34 | ths | fixed_mmu_init(env, def); |
291 | 29929e34 | ths | break;
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292 | 29929e34 | ths | default:
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293 | 29929e34 | ths | /* Older CPUs like the R3000 may need nonstandard handling here. */
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294 | 29929e34 | ths | cpu_abort(env, "MMU type not supported\n");
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295 | 29929e34 | ths | } |
296 | fcb4a419 | ths | env->CP0_Random = env->nb_tlb - 1;
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297 | fcb4a419 | ths | env->tlb_in_use = env->nb_tlb; |
298 | 29929e34 | ths | #endif /* CONFIG_USER_ONLY */ |
299 | 33d68b5f | ths | return 0; |
300 | 33d68b5f | ths | } |