root / hw / arm11mpcore.c @ c9c3c80a
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1 | f7c70325 | Paul Brook | /*
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2 | f7c70325 | Paul Brook | * ARM11MPCore internal peripheral emulation.
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3 | f7c70325 | Paul Brook | *
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4 | f7c70325 | Paul Brook | * Copyright (c) 2006-2007 CodeSourcery.
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5 | f7c70325 | Paul Brook | * Written by Paul Brook
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6 | f7c70325 | Paul Brook | *
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7 | 8e31bf38 | Matthew Fernandez | * This code is licensed under the GPL.
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8 | f7c70325 | Paul Brook | */
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9 | f7c70325 | Paul Brook | |
10 | 2a6ab1e3 | Peter Maydell | #include "sysbus.h" |
11 | 2a6ab1e3 | Peter Maydell | #include "qemu-timer.h" |
12 | 2a6ab1e3 | Peter Maydell | |
13 | 2a6ab1e3 | Peter Maydell | #define NCPU 4 |
14 | 2a6ab1e3 | Peter Maydell | |
15 | 2a6ab1e3 | Peter Maydell | static inline int |
16 | 2a6ab1e3 | Peter Maydell | gic_get_current_cpu(void)
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17 | 2a6ab1e3 | Peter Maydell | { |
18 | 2a6ab1e3 | Peter Maydell | return cpu_single_env->cpu_index;
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19 | 2a6ab1e3 | Peter Maydell | } |
20 | 2a6ab1e3 | Peter Maydell | |
21 | 2a6ab1e3 | Peter Maydell | #include "arm_gic.c" |
22 | 2a6ab1e3 | Peter Maydell | |
23 | 2a6ab1e3 | Peter Maydell | /* MPCore private memory region. */
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24 | 2a6ab1e3 | Peter Maydell | |
25 | 2a6ab1e3 | Peter Maydell | typedef struct mpcore_priv_state { |
26 | 2a6ab1e3 | Peter Maydell | gic_state gic; |
27 | 2a6ab1e3 | Peter Maydell | uint32_t scu_control; |
28 | 2a6ab1e3 | Peter Maydell | int iomemtype;
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29 | 2a6ab1e3 | Peter Maydell | uint32_t old_timer_status[8];
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30 | 2a6ab1e3 | Peter Maydell | uint32_t num_cpu; |
31 | 2a6ab1e3 | Peter Maydell | qemu_irq *timer_irq; |
32 | 2a6ab1e3 | Peter Maydell | MemoryRegion iomem; |
33 | 2a6ab1e3 | Peter Maydell | MemoryRegion container; |
34 | 2a6ab1e3 | Peter Maydell | DeviceState *mptimer; |
35 | a32134aa | Mark Langsdorf | uint32_t num_irq; |
36 | 2a6ab1e3 | Peter Maydell | } mpcore_priv_state; |
37 | 2a6ab1e3 | Peter Maydell | |
38 | 2a6ab1e3 | Peter Maydell | /* Per-CPU private memory mapped IO. */
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39 | 2a6ab1e3 | Peter Maydell | |
40 | 2a6ab1e3 | Peter Maydell | static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset, |
41 | 2a6ab1e3 | Peter Maydell | unsigned size)
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42 | 2a6ab1e3 | Peter Maydell | { |
43 | 2a6ab1e3 | Peter Maydell | mpcore_priv_state *s = (mpcore_priv_state *)opaque; |
44 | 2a6ab1e3 | Peter Maydell | int id;
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45 | 2a6ab1e3 | Peter Maydell | offset &= 0xff;
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46 | 2a6ab1e3 | Peter Maydell | /* SCU */
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47 | 2a6ab1e3 | Peter Maydell | switch (offset) {
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48 | 2a6ab1e3 | Peter Maydell | case 0x00: /* Control. */ |
49 | 2a6ab1e3 | Peter Maydell | return s->scu_control;
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50 | 2a6ab1e3 | Peter Maydell | case 0x04: /* Configuration. */ |
51 | 2a6ab1e3 | Peter Maydell | id = ((1 << s->num_cpu) - 1) << 4; |
52 | 2a6ab1e3 | Peter Maydell | return id | (s->num_cpu - 1); |
53 | 2a6ab1e3 | Peter Maydell | case 0x08: /* CPU status. */ |
54 | 2a6ab1e3 | Peter Maydell | return 0; |
55 | 2a6ab1e3 | Peter Maydell | case 0x0c: /* Invalidate all. */ |
56 | 2a6ab1e3 | Peter Maydell | return 0; |
57 | 2a6ab1e3 | Peter Maydell | default:
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58 | 2a6ab1e3 | Peter Maydell | hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset); |
59 | 2a6ab1e3 | Peter Maydell | } |
60 | 2a6ab1e3 | Peter Maydell | } |
61 | 2a6ab1e3 | Peter Maydell | |
62 | 2a6ab1e3 | Peter Maydell | static void mpcore_scu_write(void *opaque, target_phys_addr_t offset, |
63 | 2a6ab1e3 | Peter Maydell | uint64_t value, unsigned size)
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64 | 2a6ab1e3 | Peter Maydell | { |
65 | 2a6ab1e3 | Peter Maydell | mpcore_priv_state *s = (mpcore_priv_state *)opaque; |
66 | 2a6ab1e3 | Peter Maydell | offset &= 0xff;
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67 | 2a6ab1e3 | Peter Maydell | /* SCU */
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68 | 2a6ab1e3 | Peter Maydell | switch (offset) {
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69 | 2a6ab1e3 | Peter Maydell | case 0: /* Control register. */ |
70 | 2a6ab1e3 | Peter Maydell | s->scu_control = value & 1;
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71 | 2a6ab1e3 | Peter Maydell | break;
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72 | 2a6ab1e3 | Peter Maydell | case 0x0c: /* Invalidate all. */ |
73 | 2a6ab1e3 | Peter Maydell | /* This is a no-op as cache is not emulated. */
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74 | 2a6ab1e3 | Peter Maydell | break;
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75 | 2a6ab1e3 | Peter Maydell | default:
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76 | 2a6ab1e3 | Peter Maydell | hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset); |
77 | 2a6ab1e3 | Peter Maydell | } |
78 | 2a6ab1e3 | Peter Maydell | } |
79 | 2a6ab1e3 | Peter Maydell | |
80 | 2a6ab1e3 | Peter Maydell | static const MemoryRegionOps mpcore_scu_ops = { |
81 | 2a6ab1e3 | Peter Maydell | .read = mpcore_scu_read, |
82 | 2a6ab1e3 | Peter Maydell | .write = mpcore_scu_write, |
83 | 2a6ab1e3 | Peter Maydell | .endianness = DEVICE_NATIVE_ENDIAN, |
84 | 2a6ab1e3 | Peter Maydell | }; |
85 | 2a6ab1e3 | Peter Maydell | |
86 | 2a6ab1e3 | Peter Maydell | static void mpcore_timer_irq_handler(void *opaque, int irq, int level) |
87 | 2a6ab1e3 | Peter Maydell | { |
88 | 2a6ab1e3 | Peter Maydell | mpcore_priv_state *s = (mpcore_priv_state *)opaque; |
89 | 2a6ab1e3 | Peter Maydell | if (level && !s->old_timer_status[irq]) {
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90 | 2a6ab1e3 | Peter Maydell | gic_set_pending_private(&s->gic, irq >> 1, 29 + (irq & 1)); |
91 | 2a6ab1e3 | Peter Maydell | } |
92 | 2a6ab1e3 | Peter Maydell | s->old_timer_status[irq] = level; |
93 | 2a6ab1e3 | Peter Maydell | } |
94 | 2a6ab1e3 | Peter Maydell | |
95 | 2a6ab1e3 | Peter Maydell | static void mpcore_priv_map_setup(mpcore_priv_state *s) |
96 | 2a6ab1e3 | Peter Maydell | { |
97 | 2a6ab1e3 | Peter Maydell | int i;
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98 | 2a6ab1e3 | Peter Maydell | SysBusDevice *busdev = sysbus_from_qdev(s->mptimer); |
99 | 2a6ab1e3 | Peter Maydell | memory_region_init(&s->container, "mpcode-priv-container", 0x2000); |
100 | 2a6ab1e3 | Peter Maydell | memory_region_init_io(&s->iomem, &mpcore_scu_ops, s, "mpcore-scu", 0x100); |
101 | 2a6ab1e3 | Peter Maydell | memory_region_add_subregion(&s->container, 0, &s->iomem);
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102 | 2a6ab1e3 | Peter Maydell | /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
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103 | 2a6ab1e3 | Peter Maydell | * at 0x200, 0x300...
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104 | 2a6ab1e3 | Peter Maydell | */
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105 | 2a6ab1e3 | Peter Maydell | for (i = 0; i < (s->num_cpu + 1); i++) { |
106 | 2a6ab1e3 | Peter Maydell | target_phys_addr_t offset = 0x100 + (i * 0x100); |
107 | 2a6ab1e3 | Peter Maydell | memory_region_add_subregion(&s->container, offset, &s->gic.cpuiomem[i]); |
108 | 2a6ab1e3 | Peter Maydell | } |
109 | 2a6ab1e3 | Peter Maydell | /* Add the regions for timer and watchdog for "current CPU" and
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110 | 2a6ab1e3 | Peter Maydell | * for each specific CPU.
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111 | 2a6ab1e3 | Peter Maydell | */
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112 | 2a6ab1e3 | Peter Maydell | s->timer_irq = qemu_allocate_irqs(mpcore_timer_irq_handler, |
113 | 2a6ab1e3 | Peter Maydell | s, (s->num_cpu + 1) * 2); |
114 | 2a6ab1e3 | Peter Maydell | for (i = 0; i < (s->num_cpu + 1) * 2; i++) { |
115 | 2a6ab1e3 | Peter Maydell | /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
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116 | 2a6ab1e3 | Peter Maydell | target_phys_addr_t offset = 0x600 + (i >> 1) * 0x100 + (i & 1) * 0x20; |
117 | 2a6ab1e3 | Peter Maydell | memory_region_add_subregion(&s->container, offset, |
118 | 2a6ab1e3 | Peter Maydell | sysbus_mmio_get_region(busdev, i)); |
119 | 2a6ab1e3 | Peter Maydell | } |
120 | 2a6ab1e3 | Peter Maydell | memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
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121 | 2a6ab1e3 | Peter Maydell | /* Wire up the interrupt from each watchdog and timer. */
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122 | 2a6ab1e3 | Peter Maydell | for (i = 0; i < s->num_cpu * 2; i++) { |
123 | 2a6ab1e3 | Peter Maydell | sysbus_connect_irq(busdev, i, s->timer_irq[i]); |
124 | 2a6ab1e3 | Peter Maydell | } |
125 | 2a6ab1e3 | Peter Maydell | } |
126 | 2a6ab1e3 | Peter Maydell | |
127 | 2a6ab1e3 | Peter Maydell | static int mpcore_priv_init(SysBusDevice *dev) |
128 | 2a6ab1e3 | Peter Maydell | { |
129 | 2a6ab1e3 | Peter Maydell | mpcore_priv_state *s = FROM_SYSBUSGIC(mpcore_priv_state, dev); |
130 | 2a6ab1e3 | Peter Maydell | |
131 | a32134aa | Mark Langsdorf | gic_init(&s->gic, s->num_cpu, s->num_irq); |
132 | 2a6ab1e3 | Peter Maydell | s->mptimer = qdev_create(NULL, "arm_mptimer"); |
133 | 2a6ab1e3 | Peter Maydell | qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
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134 | 2a6ab1e3 | Peter Maydell | qdev_init_nofail(s->mptimer); |
135 | 2a6ab1e3 | Peter Maydell | mpcore_priv_map_setup(s); |
136 | 2a6ab1e3 | Peter Maydell | sysbus_init_mmio(dev, &s->container); |
137 | 2a6ab1e3 | Peter Maydell | return 0; |
138 | 2a6ab1e3 | Peter Maydell | } |
139 | f7c70325 | Paul Brook | |
140 | f7c70325 | Paul Brook | /* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ
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141 | f7c70325 | Paul Brook | controllers. The output of these, plus some of the raw input lines
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142 | f7c70325 | Paul Brook | are fed into a single SMP-aware interrupt controller on the CPU. */
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143 | f7c70325 | Paul Brook | typedef struct { |
144 | f7c70325 | Paul Brook | SysBusDevice busdev; |
145 | f7c70325 | Paul Brook | SysBusDevice *priv; |
146 | f7c70325 | Paul Brook | qemu_irq cpuic[32];
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147 | f7c70325 | Paul Brook | qemu_irq rvic[4][64]; |
148 | f7c70325 | Paul Brook | uint32_t num_cpu; |
149 | f7c70325 | Paul Brook | } mpcore_rirq_state; |
150 | f7c70325 | Paul Brook | |
151 | f7c70325 | Paul Brook | /* Map baseboard IRQs onto CPU IRQ lines. */
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152 | f7c70325 | Paul Brook | static const int mpcore_irq_map[32] = { |
153 | f7c70325 | Paul Brook | -1, -1, -1, -1, 1, 2, -1, -1, |
154 | f7c70325 | Paul Brook | -1, -1, 6, -1, 4, 5, -1, -1, |
155 | f7c70325 | Paul Brook | -1, 14, 15, 0, 7, 8, -1, -1, |
156 | f7c70325 | Paul Brook | -1, -1, -1, -1, 9, 3, -1, -1, |
157 | f7c70325 | Paul Brook | }; |
158 | f7c70325 | Paul Brook | |
159 | f7c70325 | Paul Brook | static void mpcore_rirq_set_irq(void *opaque, int irq, int level) |
160 | f7c70325 | Paul Brook | { |
161 | f7c70325 | Paul Brook | mpcore_rirq_state *s = (mpcore_rirq_state *)opaque; |
162 | f7c70325 | Paul Brook | int i;
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163 | f7c70325 | Paul Brook | |
164 | f7c70325 | Paul Brook | for (i = 0; i < 4; i++) { |
165 | f7c70325 | Paul Brook | qemu_set_irq(s->rvic[i][irq], level); |
166 | f7c70325 | Paul Brook | } |
167 | f7c70325 | Paul Brook | if (irq < 32) { |
168 | f7c70325 | Paul Brook | irq = mpcore_irq_map[irq]; |
169 | f7c70325 | Paul Brook | if (irq >= 0) { |
170 | f7c70325 | Paul Brook | qemu_set_irq(s->cpuic[irq], level); |
171 | f7c70325 | Paul Brook | } |
172 | f7c70325 | Paul Brook | } |
173 | f7c70325 | Paul Brook | } |
174 | f7c70325 | Paul Brook | |
175 | f7c70325 | Paul Brook | static int realview_mpcore_init(SysBusDevice *dev) |
176 | f7c70325 | Paul Brook | { |
177 | f7c70325 | Paul Brook | mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev); |
178 | f7c70325 | Paul Brook | DeviceState *gic; |
179 | f7c70325 | Paul Brook | DeviceState *priv; |
180 | f7c70325 | Paul Brook | int n;
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181 | f7c70325 | Paul Brook | int i;
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182 | f7c70325 | Paul Brook | |
183 | f7c70325 | Paul Brook | priv = qdev_create(NULL, "arm11mpcore_priv"); |
184 | f7c70325 | Paul Brook | qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
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185 | f7c70325 | Paul Brook | qdev_init_nofail(priv); |
186 | f7c70325 | Paul Brook | s->priv = sysbus_from_qdev(priv); |
187 | f7c70325 | Paul Brook | sysbus_pass_irq(dev, s->priv); |
188 | f7c70325 | Paul Brook | for (i = 0; i < 32; i++) { |
189 | f7c70325 | Paul Brook | s->cpuic[i] = qdev_get_gpio_in(priv, i); |
190 | f7c70325 | Paul Brook | } |
191 | f7c70325 | Paul Brook | /* ??? IRQ routing is hardcoded to "normal" mode. */
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192 | f7c70325 | Paul Brook | for (n = 0; n < 4; n++) { |
193 | f7c70325 | Paul Brook | gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000, |
194 | f7c70325 | Paul Brook | s->cpuic[10 + n]);
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195 | f7c70325 | Paul Brook | for (i = 0; i < 64; i++) { |
196 | f7c70325 | Paul Brook | s->rvic[n][i] = qdev_get_gpio_in(gic, i); |
197 | f7c70325 | Paul Brook | } |
198 | f7c70325 | Paul Brook | } |
199 | f7c70325 | Paul Brook | qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);
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200 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, sysbus_mmio_get_region(s->priv, 0));
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201 | f7c70325 | Paul Brook | return 0; |
202 | f7c70325 | Paul Brook | } |
203 | f7c70325 | Paul Brook | |
204 | f7c70325 | Paul Brook | static SysBusDeviceInfo mpcore_rirq_info = {
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205 | f7c70325 | Paul Brook | .init = realview_mpcore_init, |
206 | f7c70325 | Paul Brook | .qdev.name = "realview_mpcore",
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207 | f7c70325 | Paul Brook | .qdev.size = sizeof(mpcore_rirq_state),
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208 | f7c70325 | Paul Brook | .qdev.props = (Property[]) { |
209 | f7c70325 | Paul Brook | DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), |
210 | f7c70325 | Paul Brook | DEFINE_PROP_END_OF_LIST(), |
211 | f7c70325 | Paul Brook | } |
212 | f7c70325 | Paul Brook | }; |
213 | f7c70325 | Paul Brook | |
214 | f7c70325 | Paul Brook | static SysBusDeviceInfo mpcore_priv_info = {
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215 | f7c70325 | Paul Brook | .init = mpcore_priv_init, |
216 | f7c70325 | Paul Brook | .qdev.name = "arm11mpcore_priv",
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217 | f7c70325 | Paul Brook | .qdev.size = sizeof(mpcore_priv_state),
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218 | f7c70325 | Paul Brook | .qdev.props = (Property[]) { |
219 | f7c70325 | Paul Brook | DEFINE_PROP_UINT32("num-cpu", mpcore_priv_state, num_cpu, 1), |
220 | a32134aa | Mark Langsdorf | /* The ARM11 MPCORE TRM says the on-chip controller may have
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221 | a32134aa | Mark Langsdorf | * anything from 0 to 224 external interrupt IRQ lines (with another
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222 | a32134aa | Mark Langsdorf | * 32 internal). We default to 32+32, which is the number provided by
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223 | a32134aa | Mark Langsdorf | * the ARM11 MPCore test chip in the Realview Versatile Express
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224 | a32134aa | Mark Langsdorf | * coretile. Other boards may differ and should set this property
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225 | a32134aa | Mark Langsdorf | * appropriately. Some Linux kernels may not boot if the hardware
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226 | a32134aa | Mark Langsdorf | * has more IRQ lines than the kernel expects.
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227 | a32134aa | Mark Langsdorf | */
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228 | a32134aa | Mark Langsdorf | DEFINE_PROP_UINT32("num-irq", mpcore_priv_state, num_irq, 64), |
229 | f7c70325 | Paul Brook | DEFINE_PROP_END_OF_LIST(), |
230 | f7c70325 | Paul Brook | } |
231 | f7c70325 | Paul Brook | }; |
232 | f7c70325 | Paul Brook | |
233 | f7c70325 | Paul Brook | static void arm11mpcore_register_devices(void) |
234 | f7c70325 | Paul Brook | { |
235 | f7c70325 | Paul Brook | sysbus_register_withprop(&mpcore_rirq_info); |
236 | f7c70325 | Paul Brook | sysbus_register_withprop(&mpcore_priv_info); |
237 | f7c70325 | Paul Brook | } |
238 | f7c70325 | Paul Brook | |
239 | f7c70325 | Paul Brook | device_init(arm11mpcore_register_devices) |